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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Jonathan Cameron , Ben Widawsky , Ben Widawsky Subject: [PULL 28/55] mem/cxl-type3: Add sn option to provide serial number for PCI ecap Message-ID: <20221010172813.204597-29-mst@redhat.com> References: <20221010172813.204597-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221010172813.204597-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1665426110014100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jonathan Cameron The Device Serial Number Extended Capability PCI r6.0 sec 7.9.3 provides a standard way to provide a device serial number as an IEEE defined 64-bit extended unique identifier EUI-64. CXL 2.0 section 8.1.12.2 Memory Device PCIe Capabilities and Extended Capabilities requires this to be used to uniquely identify CXL memory devices. Signed-off-by: Jonathan Cameron Message-Id: <20220923161835.9805-1-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Ben Widawsky --- include/hw/cxl/cxl_device.h | 1 + hw/mem/cxl_type3.c | 14 +++++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 1e141b6621..e4d221cdb3 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -237,6 +237,7 @@ struct CXLType3Dev { /* Properties */ HostMemoryBackend *hostmem; HostMemoryBackend *lsa; + uint64_t sn; =20 /* State */ AddressSpace hostmem_as; diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index ada2108fac..a71bf1afeb 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -14,6 +14,12 @@ #include "sysemu/hostmem.h" #include "hw/cxl/cxl.h" =20 +/* + * Null value of all Fs suggested by IEEE RA guidelines for use of + * EU, OUI and CID + */ +#define UI64_NULL ~(0ULL) + static void build_dvsecs(CXLType3Dev *ct3d) { CXLComponentState *cxl_cstate =3D &ct3d->cxl_cstate; @@ -149,7 +155,12 @@ static void ct3_realize(PCIDevice *pci_dev, Error **er= rp) pci_config_set_class(pci_conf, PCI_CLASS_MEMORY_CXL); =20 pcie_endpoint_cap_init(pci_dev, 0x80); - cxl_cstate->dvsec_offset =3D 0x100; + if (ct3d->sn !=3D UI64_NULL) { + pcie_dev_ser_num_init(pci_dev, 0x100, ct3d->sn); + cxl_cstate->dvsec_offset =3D 0x100 + 0x0c; + } else { + cxl_cstate->dvsec_offset =3D 0x100; + } =20 ct3d->cxl_cstate.pdev =3D pci_dev; build_dvsecs(ct3d); @@ -275,6 +286,7 @@ static Property ct3_props[] =3D { HostMemoryBackend *), DEFINE_PROP_LINK("lsa", CXLType3Dev, lsa, TYPE_MEMORY_BACKEND, HostMemoryBackend *), + DEFINE_PROP_UINT64("sn", CXLType3Dev, sn, UI64_NULL), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 MST