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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=chejyLWzKm+amytX5VjNlCtg/brdV5o/nVcOeHFnjvk=; b=mbrsbOmU9SkjUpXqqV/47K5N+87SfreWUQFMApH8wqsU5KcYXe09NuXatd4CXZlnTD LJGEALqAFAZcroWcDHXvthPxmDQS8cYkX8U+pXYYe+ZecyT9gG2QdJGpcRSFXpfmKBSm Qny6hwCAGiUhYVCf30qnPXZ5uBdXDAaO1/pM2uWrj49dROSLqeMiHWPIfFmVqq9FhmaV F10osci7CXK0u87QrZjEvknSX3v2ZGdR1x4e+cEPMJTFN17YMH5+ZNoHD/4TkYJP/2MW riGbOJigljRqJ6zQ1uUBWzNqTw5rFVUlTwwNf1RVd0k734wlGHNfNWvWeptyuAA6juVn jFmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=chejyLWzKm+amytX5VjNlCtg/brdV5o/nVcOeHFnjvk=; b=bUr/HDBywjsn9q8IdBKSK0PNhUqdhSXOBheeP4c+yhFddFQk7Mn8Txz0fXf+i38iVD a6nw2KrNl2w1HNOZ8Dv/P330934X9Q6JMhkDub8szcJ3OetMeDm4yPzqsWUBKsXuYf7x odD/PVbt8LBesBSti2UUFpKfVkkLkRvzU6iNeqLm7Z1rNMzeN9DB5C8At3NknwleXfF+ +VVtf10uIowf8u1h/67YyFgt4+odZsQDP/IyamNnb+a8psgYxZhfTHiiz2sIxo3mGbhR JuCaCSPBUj+/1sbmlebL2S0pug2l1ODSyju+KgC7fkF/6LsDIhCf//m8ufdVpHRj4URy TRIQ== X-Gm-Message-State: ACrzQf0aaXLkKUexTll3vMYAMri6MaF1m2yqGEL85CDxHkPlMBNbVcJr 2bqvcLJLaKrr1XahkWTN6963xbau2wodVA== X-Google-Smtp-Source: AMsMyM4EpnsBQW/JY/q+mYBijUFR6vBiC13iMeptjOGxiCZlui/Ka66dO0ilo4lsDZ9/89cC1K+tug== X-Received: by 2002:adf:f407:0:b0:22e:5848:f6b with SMTP id g7-20020adff407000000b0022e58480f6bmr11586883wro.46.1665412061217; Mon, 10 Oct 2022 07:27:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/28] target/arm: Add is_secure parameter to regime_translation_disabled Date: Mon, 10 Oct 2022 15:27:10 +0100 Message-Id: <20221010142730.502083-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665412686099100001 From: Richard Henderson Remove the use of regime_is_secure from regime_translation_disabled, using the new parameter instead. This fixes a bug in S1_ptw_translate and get_phys_addr where we had passed ARMMMUIdx_Stage2 and not ARMMMUIdx_Stage2_S to determine if Stage2 is disabled, affecting FEAT_SEL2. Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20221001162318.153420-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 631d1e25f15..d789807b086 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -131,12 +131,13 @@ static uint64_t regime_ttbr(CPUARMState *env, ARMMMUI= dx mmu_idx, int ttbrn) } =20 /* Return true if the specified stage of address translation is disabled */ -static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_id= x) +static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_id= x, + bool is_secure) { uint64_t hcr_el2; =20 if (arm_feature(env, ARM_FEATURE_M)) { - switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & + switch (env->v7m.mpu_ctrl[is_secure] & (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK= )) { case R_V7M_MPU_CTRL_ENABLE_MASK: /* Enabled, but not for HardFault and NMI */ @@ -163,7 +164,7 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx) =20 if (hcr_el2 & HCR_TGE) { /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ - if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) =3D= =3D 1) { + if (!is_secure && regime_el(env, mmu_idx) =3D=3D 1) { return true; } } @@ -203,7 +204,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, ARMMMUIdx s2_mmu_idx =3D *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_S= tage2; =20 if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, s2_mmu_idx)) { + !regime_translation_disabled(env, s2_mmu_idx, *is_secure)) { GetPhysAddrResult s2 =3D {}; int ret; =20 @@ -1357,7 +1358,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, ui= nt32_t address, uint32_t base; bool is_user =3D regime_is_user(env, mmu_idx); =20 - if (regime_translation_disabled(env, mmu_idx)) { + if (regime_translation_disabled(env, mmu_idx, is_secure)) { /* MPU disabled. */ result->phys =3D address; result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -1521,7 +1522,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, result->page_size =3D TARGET_PAGE_SIZE; result->prot =3D 0; =20 - if (regime_translation_disabled(env, mmu_idx) || + if (regime_translation_disabled(env, mmu_idx, secure) || m_is_ppb_region(env, address)) { /* * MPU disabled or M profile PPB access: use default memory map. @@ -1733,7 +1734,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, * are done in arm_v7m_load_vector(), which always does a direct * read using address_space_ldl(), rather than going via this function. */ - if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ + if (regime_translation_disabled(env, mmu_idx, secure)) { /* MPU disabl= ed */ hit =3D true; } else if (m_is_ppb_region(env, address)) { hit =3D true; @@ -2307,7 +2308,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, result, fi); =20 /* If S1 fails or S2 is disabled, return early. */ - if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2))= { + if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, + is_secure)) { return ret; } =20 @@ -2437,7 +2439,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, =20 /* Definitely a real MMU, not an MPU */ =20 - if (regime_translation_disabled(env, mmu_idx)) { + if (regime_translation_disabled(env, mmu_idx, is_secure)) { uint64_t hcr; uint8_t memattr; =20 --=20 2.25.1