From nobody Thu Dec 18 22:27:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665412989; cv=none; d=zohomail.com; s=zohoarc; b=MfnXqCQV2hwU54XLfpzj9AmtLPWib7MzE1EpZ1IN7nYHg53ik3XgyEfKHNoy58I5SMGQvY6GIc2n2EHGTWZh3JAuqgWmgZaNOF5mKHobNbG/WVB3ztdPzZ8nPePSIeYFomKzIASQoaFr6rw3bT5Utc5FOvWpmR7sBVCm86v/tX0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665412989; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3s+FyWiCaE2Ik3+lgb9MwwUIPvJVHRPhFGnB5s7T1cU=; b=O+k5bnxZl/lkYbcMQaOLFpwJnisfGxNB4wKh7/RxFrot/S5CckzYVscZUIWr1gVevQ7+tHEEP1jy40QYz0M8Nx2MsXacE4zPvhh397uknaRck+AyokGxZgJ6SurXOhe9vjrjMwBUvmzFSTr+lPsKOvM3XhEcvcmmpxCXOIGAP/k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665412989208952.1692278704851; Mon, 10 Oct 2022 07:43:09 -0700 (PDT) Received: from localhost ([::1]:44012 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohtzm-0000iA-BK for importer@patchew.org; Mon, 10 Oct 2022 10:43:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60096) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtlD-0006bz-IG for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:28:03 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:54254) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtl9-0005bp-9V for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:28:03 -0400 Received: by mail-wm1-x32f.google.com with SMTP id e18so6939615wmq.3 for ; Mon, 10 Oct 2022 07:27:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3s+FyWiCaE2Ik3+lgb9MwwUIPvJVHRPhFGnB5s7T1cU=; b=HXCjUijpTqCY55BXOAZGzQPaNyq6BBPhBHJFfO4brSNx9xc4X9RsByeJtNsHkbb1Ld GNzlMWjKbJUukDPd4RG3IRbWre4eerTnt8sx73NyKzn+Iz/WkFK/o2Agf0h4v8Bipxqm meaZf+sBELQHRsmarv+AMGqGwNF6ULlBrDxSohq/TX5RN5v3Qmp+MfmoYrs9dA/PE6iK aeu8RJN+UHuqY75QnHaRk6kwy78MMSnaho+YiolgtzHItpXsU+jXcd4qMybgOLWqIhkl tKnuWZSZ82GCLAccT3jS1BpUChBeEpdj/+VCQ2m1zFgDtPlcSzLl5Emj8YUTNzRAPox3 hz2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3s+FyWiCaE2Ik3+lgb9MwwUIPvJVHRPhFGnB5s7T1cU=; b=zKCO7SXpfKrhdl9+7lVu/7j7AdJ2g4caTg/AskdvVfzglDuO+1WAYEiM0b07z9i1VT YE8E3yQ92FEEtwDTRXcUD+D9Kk48Bois3tE+tcAn4CLFE1E8xJzSoPCbZpF2QcMnuqv2 sDPCU+mIzzOcvz8hEEygZX/T8WscGFFGRPkNyjrGSw0Ig86APKQScwc94ga6mLAAEV1E mVlh5EvUNgAa33AW8CU+GgYUrpixOcN7vNCQ1+UTMm5ZX6vMlDIlApF/R1DFhby3hDE9 7P7G3nR5oydLTx5F4Qul1ZvbRLVGKTlc9CMuDOXjlf9tuIDv+yAAzbGUpImYhqNdG3bN Nm3w== X-Gm-Message-State: ACrzQf1jOYxSMYPjaMDQh1Dl6qlPWLhKQ89KRS3DoNJDWF4oPzPOAq9g mLVG8nJxfwOzovwOwVFjz7/5Ou0FFgXI5Q== X-Google-Smtp-Source: AMsMyM40p194Hwl/Dtjczj3LU2/ADUfQmIw4tfRQPzGVPBO1/wYCZ9gIDMd2YuaIYNOccqSJiCx3lw== X-Received: by 2002:a05:600c:3b8f:b0:3b4:9cdc:dbd8 with SMTP id n15-20020a05600c3b8f00b003b49cdcdbd8mr12763691wms.148.1665412077741; Mon, 10 Oct 2022 07:27:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/28] target/arm: Use tlb_set_page_full Date: Mon, 10 Oct 2022 15:27:26 +0100 Message-Id: <20221010142730.502083-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665412989548100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Adjust GetPhysAddrResult to fill in CPUTLBEntryFull, so that it may be passed directly to tlb_set_page_full. The change is large, but mostly mechanical. The major non-mechanical change is page_size -> lg_page_size. Most of the time this is obvious, and is related to TARGET_PAGE_BITS. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20221001162318.153420-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 5 +- target/arm/helper.c | 12 +-- target/arm/m_helper.c | 20 ++--- target/arm/ptw.c | 179 ++++++++++++++++++++-------------------- target/arm/tlb_helper.c | 9 +- 5 files changed, 111 insertions(+), 114 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index b509d708514..fd17aee4599 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1071,10 +1071,7 @@ typedef struct ARMCacheAttrs { =20 /* Fields that are valid upon success. */ typedef struct GetPhysAddrResult { - hwaddr phys; - target_ulong page_size; - int prot; - MemTxAttrs attrs; + CPUTLBEntryFull f; ARMCacheAttrs cacheattrs; } GetPhysAddrResult; =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index f1266bb1579..e1338ed6e22 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3323,8 +3323,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, /* Create a 64-bit PAR */ par64 =3D (1 << 11); /* LPAE bit always set */ if (!ret) { - par64 |=3D res.phys & ~0xfffULL; - if (!res.attrs.secure) { + par64 |=3D res.f.phys_addr & ~0xfffULL; + if (!res.f.attrs.secure) { par64 |=3D (1 << 9); /* NS */ } par64 |=3D (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */ @@ -3348,13 +3348,13 @@ static uint64_t do_ats_write(CPUARMState *env, uint= 64_t value, */ if (!ret) { /* We do not set any attribute bits in the PAR */ - if (res.page_size =3D=3D (1 << 24) + if (res.f.lg_page_size =3D=3D 24 && arm_feature(env, ARM_FEATURE_V7)) { - par64 =3D (res.phys & 0xff000000) | (1 << 1); + par64 =3D (res.f.phys_addr & 0xff000000) | (1 << 1); } else { - par64 =3D res.phys & 0xfffff000; + par64 =3D res.f.phys_addr & 0xfffff000; } - if (!res.attrs.secure) { + if (!res.f.attrs.secure) { par64 |=3D (1 << 9); /* NS */ } } else { diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 203ba411f64..355cd4d60a7 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -223,8 +223,8 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr,= uint32_t value, } goto pend_fault; } - address_space_stl_le(arm_addressspace(cs, res.attrs), res.phys, value, - res.attrs, &txres); + address_space_stl_le(arm_addressspace(cs, res.f.attrs), res.f.phys_add= r, + value, res.f.attrs, &txres); if (txres !=3D MEMTX_OK) { /* BusFault trying to write the data */ if (mode =3D=3D STACK_LAZYFP) { @@ -298,8 +298,8 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest,= uint32_t addr, goto pend_fault; } =20 - value =3D address_space_ldl(arm_addressspace(cs, res.attrs), res.phys, - res.attrs, &txres); + value =3D address_space_ldl(arm_addressspace(cs, res.f.attrs), + res.f.phys_addr, res.f.attrs, &txres); if (txres !=3D MEMTX_OK) { /* BusFault trying to read the data */ qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n"); @@ -2022,8 +2022,8 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, bool secure, qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL= \n"); return false; } - *insn =3D address_space_lduw_le(arm_addressspace(cs, res.attrs), res.p= hys, - res.attrs, &txres); + *insn =3D address_space_lduw_le(arm_addressspace(cs, res.f.attrs), + res.f.phys_addr, res.f.attrs, &txres); if (txres !=3D MEMTX_OK) { env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_IBUSERR_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); @@ -2069,8 +2069,8 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMM= UIdx mmu_idx, } return false; } - value =3D address_space_ldl(arm_addressspace(cs, res.attrs), res.phys, - res.attrs, &txres); + value =3D address_space_ldl(arm_addressspace(cs, res.f.attrs), + res.f.phys_addr, res.f.attrs, &txres); if (txres !=3D MEMTX_OK) { /* BusFault trying to read the data */ qemu_log_mask(CPU_LOG_INT, @@ -2817,8 +2817,8 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t ad= dr, uint32_t op) } else { mrvalid =3D true; } - r =3D res.prot & PAGE_READ; - rw =3D res.prot & PAGE_WRITE; + r =3D res.f.prot & PAGE_READ; + rw =3D res.f.prot & PAGE_WRITE; } else { r =3D false; rw =3D false; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 15c37b52c97..ddacffa7ee6 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -256,7 +256,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, assert(!is_secure); } =20 - addr =3D s2.phys; + addr =3D s2.f.phys_addr; } return addr; } @@ -476,7 +476,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, /* 1Mb section. */ phys_addr =3D (desc & 0xfff00000) | (address & 0x000fffff); ap =3D (desc >> 10) & 3; - result->page_size =3D 1024 * 1024; + result->f.lg_page_size =3D 20; /* 1MB */ } else { /* Lookup l2 entry. */ if (type =3D=3D 1) { @@ -497,12 +497,12 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32= _t address, case 1: /* 64k page. */ phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); ap =3D (desc >> (4 + ((address >> 13) & 6))) & 3; - result->page_size =3D 0x10000; + result->f.lg_page_size =3D 16; break; case 2: /* 4k page. */ phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); ap =3D (desc >> (4 + ((address >> 9) & 6))) & 3; - result->page_size =3D 0x1000; + result->f.lg_page_size =3D 12; break; case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ if (type =3D=3D 1) { @@ -510,7 +510,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, if (arm_feature(env, ARM_FEATURE_XSCALE) || arm_feature(env, ARM_FEATURE_V6)) { phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); - result->page_size =3D 0x1000; + result->f.lg_page_size =3D 12; } else { /* * UNPREDICTABLE in ARMv5; we choose to take a @@ -521,7 +521,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, } } else { phys_addr =3D (desc & 0xfffffc00) | (address & 0x3ff); - result->page_size =3D 0x400; + result->f.lg_page_size =3D 10; } ap =3D (desc >> 4) & 3; break; @@ -530,14 +530,14 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32= _t address, g_assert_not_reached(); } } - result->prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); - result->prot |=3D result->prot ? PAGE_EXEC : 0; - if (!(result->prot & (1 << access_type))) { + result->f.prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + result->f.prot |=3D result->f.prot ? PAGE_EXEC : 0; + if (!(result->f.prot & (1 << access_type))) { /* Access permission fault. */ fi->type =3D ARMFault_Permission; goto do_fault; } - result->phys =3D phys_addr; + result->f.phys_addr =3D phys_addr; return false; do_fault: fi->domain =3D domain; @@ -607,11 +607,11 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, phys_addr =3D (desc & 0xff000000) | (address & 0x00ffffff); phys_addr |=3D (uint64_t)extract32(desc, 20, 4) << 32; phys_addr |=3D (uint64_t)extract32(desc, 5, 4) << 36; - result->page_size =3D 0x1000000; + result->f.lg_page_size =3D 24; /* 16MB */ } else { /* Section. */ phys_addr =3D (desc & 0xfff00000) | (address & 0x000fffff); - result->page_size =3D 0x100000; + result->f.lg_page_size =3D 20; /* 1MB */ } ap =3D ((desc >> 10) & 3) | ((desc >> 13) & 4); xn =3D desc & (1 << 4); @@ -636,12 +636,12 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, case 1: /* 64k page. */ phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); xn =3D desc & (1 << 15); - result->page_size =3D 0x10000; + result->f.lg_page_size =3D 16; break; case 2: case 3: /* 4k page. */ phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); xn =3D desc & 1; - result->page_size =3D 0x1000; + result->f.lg_page_size =3D 12; break; default: /* Never happens, but compiler isn't smart enough to tell. */ @@ -649,7 +649,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, } } if (domain_prot =3D=3D 3) { - result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->f.prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; } else { if (pxn && !regime_is_user(env, mmu_idx)) { xn =3D 1; @@ -667,14 +667,14 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, fi->type =3D ARMFault_AccessFlag; goto do_fault; } - result->prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); + result->f.prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); } else { - result->prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + result->f.prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot= ); } - if (result->prot && !xn) { - result->prot |=3D PAGE_EXEC; + if (result->f.prot && !xn) { + result->f.prot |=3D PAGE_EXEC; } - if (!(result->prot & (1 << access_type))) { + if (!(result->f.prot & (1 << access_type))) { /* Access permission fault. */ fi->type =3D ARMFault_Permission; goto do_fault; @@ -685,9 +685,9 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, * the CPU doesn't support TZ or this is a non-secure translation * regime, because the attribute will already be non-secure. */ - result->attrs.secure =3D false; + result->f.attrs.secure =3D false; } - result->phys =3D phys_addr; + result->f.phys_addr =3D phys_addr; return false; do_fault: fi->domain =3D domain; @@ -1298,16 +1298,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { ns =3D mmu_idx =3D=3D ARMMMUIdx_Stage2; xn =3D extract32(attrs, 11, 2); - result->prot =3D get_S2prot(env, ap, xn, s1_is_el0); + result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); } else { ns =3D extract32(attrs, 3, 1); xn =3D extract32(attrs, 12, 1); pxn =3D extract32(attrs, 11, 1); - result->prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn= ); + result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, p= xn); } =20 fault_type =3D ARMFault_Permission; - if (!(result->prot & (1 << access_type))) { + if (!(result->f.prot & (1 << access_type))) { goto do_fault; } =20 @@ -1317,11 +1317,11 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, * the CPU doesn't support TZ or this is a non-secure translation * regime, because the attribute will already be non-secure. */ - result->attrs.secure =3D false; + result->f.attrs.secure =3D false; } /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB.= */ if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { - arm_tlb_bti_gp(&result->attrs) =3D true; + arm_tlb_bti_gp(&result->f.attrs) =3D true; } =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { @@ -1347,8 +1347,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, result->cacheattrs.shareability =3D extract32(attrs, 6, 2); } =20 - result->phys =3D descaddr; - result->page_size =3D page_size; + result->f.phys_addr =3D descaddr; + result->f.lg_page_size =3D ctz64(page_size); return false; =20 do_fault: @@ -1373,12 +1373,12 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, =20 if (regime_translation_disabled(env, mmu_idx, is_secure)) { /* MPU disabled. */ - result->phys =3D address; - result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->f.phys_addr =3D address; + result->f.prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return false; } =20 - result->phys =3D address; + result->f.phys_addr =3D address; for (n =3D 7; n >=3D 0; n--) { base =3D env->cp15.c6_region[n]; if ((base & 1) =3D=3D 0) { @@ -1414,16 +1414,16 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, fi->level =3D 1; return true; } - result->prot =3D PAGE_READ | PAGE_WRITE; + result->f.prot =3D PAGE_READ | PAGE_WRITE; break; case 2: - result->prot =3D PAGE_READ; + result->f.prot =3D PAGE_READ; if (!is_user) { - result->prot |=3D PAGE_WRITE; + result->f.prot |=3D PAGE_WRITE; } break; case 3: - result->prot =3D PAGE_READ | PAGE_WRITE; + result->f.prot =3D PAGE_READ | PAGE_WRITE; break; case 5: if (is_user) { @@ -1431,10 +1431,10 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, fi->level =3D 1; return true; } - result->prot =3D PAGE_READ; + result->f.prot =3D PAGE_READ; break; case 6: - result->prot =3D PAGE_READ; + result->f.prot =3D PAGE_READ; break; default: /* Bad permission. */ @@ -1442,12 +1442,12 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, fi->level =3D 1; return true; } - result->prot |=3D PAGE_EXEC; + result->f.prot |=3D PAGE_EXEC; return false; } =20 static void get_phys_addr_pmsav7_default(CPUARMState *env, ARMMMUIdx mmu_i= dx, - int32_t address, int *prot) + int32_t address, uint8_t *prot) { if (!arm_feature(env, ARM_FEATURE_M)) { *prot =3D PAGE_READ | PAGE_WRITE; @@ -1531,9 +1531,9 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, int n; bool is_user =3D regime_is_user(env, mmu_idx); =20 - result->phys =3D address; - result->page_size =3D TARGET_PAGE_SIZE; - result->prot =3D 0; + result->f.phys_addr =3D address; + result->f.lg_page_size =3D TARGET_PAGE_BITS; + result->f.prot =3D 0; =20 if (regime_translation_disabled(env, mmu_idx, secure) || m_is_ppb_region(env, address)) { @@ -1545,7 +1545,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, * which always does a direct read using address_space_ldl(), rath= er * than going via this function, so we don't need to check that he= re. */ - get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot); + get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.pro= t); } else { /* MPU enabled */ for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { /* region search */ @@ -1587,7 +1587,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, if (ranges_overlap(base, rmask, address & TARGET_PAGE_MASK, TARGET_PAGE_SIZE)) { - result->page_size =3D 1; + result->f.lg_page_size =3D 0; } continue; } @@ -1625,7 +1625,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, continue; } if (rsize < TARGET_PAGE_BITS) { - result->page_size =3D 1 << rsize; + result->f.lg_page_size =3D rsize; } break; } @@ -1636,7 +1636,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, fi->type =3D ARMFault_Background; return true; } - get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->p= rot); + get_phys_addr_pmsav7_default(env, mmu_idx, address, + &result->f.prot); } else { /* a MPU hit! */ uint32_t ap =3D extract32(env->pmsav7.dracr[n], 8, 3); uint32_t xn =3D extract32(env->pmsav7.dracr[n], 12, 1); @@ -1653,16 +1654,16 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, case 5: break; /* no access */ case 3: - result->prot |=3D PAGE_WRITE; + result->f.prot |=3D PAGE_WRITE; /* fall through */ case 2: case 6: - result->prot |=3D PAGE_READ | PAGE_EXEC; + result->f.prot |=3D PAGE_READ | PAGE_EXEC; break; case 7: /* for v7M, same as 6; for R profile a reserved value = */ if (arm_feature(env, ARM_FEATURE_M)) { - result->prot |=3D PAGE_READ | PAGE_EXEC; + result->f.prot |=3D PAGE_READ | PAGE_EXEC; break; } /* fall through */ @@ -1678,16 +1679,16 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, case 1: case 2: case 3: - result->prot |=3D PAGE_WRITE; + result->f.prot |=3D PAGE_WRITE; /* fall through */ case 5: case 6: - result->prot |=3D PAGE_READ | PAGE_EXEC; + result->f.prot |=3D PAGE_READ | PAGE_EXEC; break; case 7: /* for v7M, same as 6; for R profile a reserved value = */ if (arm_feature(env, ARM_FEATURE_M)) { - result->prot |=3D PAGE_READ | PAGE_EXEC; + result->f.prot |=3D PAGE_READ | PAGE_EXEC; break; } /* fall through */ @@ -1700,14 +1701,14 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, =20 /* execute never */ if (xn) { - result->prot &=3D ~PAGE_EXEC; + result->f.prot &=3D ~PAGE_EXEC; } } } =20 fi->type =3D ARMFault_Permission; fi->level =3D 1; - return !(result->prot & (1 << access_type)); + return !(result->f.prot & (1 << access_type)); } =20 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, @@ -1733,9 +1734,9 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, uint32_t addr_page_base =3D address & TARGET_PAGE_MASK; uint32_t addr_page_limit =3D addr_page_base + (TARGET_PAGE_SIZE - 1); =20 - result->page_size =3D TARGET_PAGE_SIZE; - result->phys =3D address; - result->prot =3D 0; + result->f.lg_page_size =3D TARGET_PAGE_BITS; + result->f.phys_addr =3D address; + result->f.prot =3D 0; if (mregion) { *mregion =3D -1; } @@ -1785,13 +1786,13 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, ranges_overlap(base, limit - base + 1, addr_page_base, TARGET_PAGE_SIZE)) { - result->page_size =3D 1; + result->f.lg_page_size =3D 0; } continue; } =20 if (base > addr_page_base || limit < addr_page_limit) { - result->page_size =3D 1; + result->f.lg_page_size =3D 0; } =20 if (matchregion !=3D -1) { @@ -1817,7 +1818,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, =20 if (matchregion =3D=3D -1) { /* hit using the background region */ - get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot); + get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.pro= t); } else { uint32_t ap =3D extract32(env->pmsav8.rbar[secure][matchregion], 1= , 2); uint32_t xn =3D extract32(env->pmsav8.rbar[secure][matchregion], 0= , 1); @@ -1832,9 +1833,9 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, xn =3D 1; } =20 - result->prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); - if (result->prot && !xn && !(pxn && !is_user)) { - result->prot |=3D PAGE_EXEC; + result->f.prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); + if (result->f.prot && !xn && !(pxn && !is_user)) { + result->f.prot |=3D PAGE_EXEC; } /* * We don't need to look the attribute up in the MAIR0/MAIR1 @@ -1847,7 +1848,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, =20 fi->type =3D ARMFault_Permission; fi->level =3D 1; - return !(result->prot & (1 << access_type)); + return !(result->f.prot & (1 << access_type)); } =20 static bool v8m_is_sau_exempt(CPUARMState *env, @@ -2011,9 +2012,9 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, } else { fi->type =3D ARMFault_QEMU_SFault; } - result->page_size =3D sattrs.subpage ? 1 : TARGET_PAGE_SIZ= E; - result->phys =3D address; - result->prot =3D 0; + result->f.lg_page_size =3D sattrs.subpage ? 0 : TARGET_PAG= E_BITS; + result->f.phys_addr =3D address; + result->f.prot =3D 0; return true; } } else { @@ -2023,7 +2024,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, * might downgrade a secure access to nonsecure. */ if (sattrs.ns) { - result->attrs.secure =3D false; + result->f.attrs.secure =3D false; } else if (!secure) { /* * NS access to S memory must fault. @@ -2036,9 +2037,9 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). */ fi->type =3D ARMFault_QEMU_SFault; - result->page_size =3D sattrs.subpage ? 1 : TARGET_PAGE_SIZ= E; - result->phys =3D address; - result->prot =3D 0; + result->f.lg_page_size =3D sattrs.subpage ? 0 : TARGET_PAG= E_BITS; + result->f.phys_addr =3D address; + result->f.prot =3D 0; return true; } } @@ -2047,7 +2048,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, ret =3D pmsav8_mpu_lookup(env, address, access_type, mmu_idx, secure, result, fi, NULL); if (sattrs.subpage) { - result->page_size =3D 1; + result->f.lg_page_size =3D 0; } return ret; } @@ -2338,9 +2339,9 @@ static bool get_phys_addr_disabled(CPUARMState *env, = target_ulong address, result->cacheattrs.is_s2_format =3D false; } =20 - result->phys =3D address; - result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - result->page_size =3D TARGET_PAGE_SIZE; + result->f.phys_addr =3D address; + result->f.prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->f.lg_page_size =3D TARGET_PAGE_BITS; result->cacheattrs.shareability =3D shareability; result->cacheattrs.attrs =3D memattr; return 0; @@ -2377,8 +2378,8 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, return ret; } =20 - ipa =3D result->phys; - ipa_secure =3D result->attrs.secure; + ipa =3D result->f.phys_addr; + ipa_secure =3D result->f.attrs.secure; if (is_secure) { /* Select TCR based on the NS bit from the S1 walk. */ s2walk_secure =3D !(ipa_secure @@ -2398,7 +2399,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, * Save the stage1 results so that we may merge * prot and cacheattrs later. */ - s1_prot =3D result->prot; + s1_prot =3D result->f.prot; cacheattrs1 =3D result->cacheattrs; memset(result, 0, sizeof(*result)); =20 @@ -2407,7 +2408,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ - result->prot &=3D s1_prot; + result->f.prot &=3D s1_prot; =20 /* If S2 fails, return early. */ if (ret) { @@ -2436,7 +2437,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, * Check if IPA translates to secure or non-secure PA space. * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA. */ - result->attrs.secure =3D + result->f.attrs.secure =3D (is_secure && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)) && (ipa_secure @@ -2456,8 +2457,8 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, * cannot upgrade an non-secure translation regime's attributes * to secure. */ - result->attrs.secure =3D is_secure; - result->attrs.user =3D regime_is_user(env, mmu_idx); + result->f.attrs.secure =3D is_secure; + result->f.attrs.user =3D regime_is_user(env, mmu_idx); =20 /* * Fast Context Switch Extension. This doesn't exist at all in v8. @@ -2474,7 +2475,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, =20 if (arm_feature(env, ARM_FEATURE_PMSA)) { bool ret; - result->page_size =3D TARGET_PAGE_SIZE; + result->f.lg_page_size =3D TARGET_PAGE_BITS; =20 if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ @@ -2495,9 +2496,9 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, (access_type =3D=3D MMU_DATA_STORE ? "writing" : "ex= ecute"), (uint32_t)address, mmu_idx, ret ? "Miss" : "Hit", - result->prot & PAGE_READ ? 'r' : '-', - result->prot & PAGE_WRITE ? 'w' : '-', - result->prot & PAGE_EXEC ? 'x' : '-'); + result->f.prot & PAGE_READ ? 'r' : '-', + result->f.prot & PAGE_WRITE ? 'w' : '-', + result->f.prot & PAGE_EXEC ? 'x' : '-'); =20 return ret; } @@ -2572,10 +2573,10 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *= cs, vaddr addr, bool ret; =20 ret =3D get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi); - *attrs =3D res.attrs; + *attrs =3D res.f.attrs; =20 if (ret) { return -1; } - return res.phys; + return res.f.phys_addr; } diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index ad225b1cb20..49601394ec1 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -227,17 +227,16 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, * target page size are handled specially, so for those we * pass in the exact addresses. */ - if (res.page_size >=3D TARGET_PAGE_SIZE) { - res.phys &=3D TARGET_PAGE_MASK; + if (res.f.lg_page_size >=3D TARGET_PAGE_BITS) { + res.f.phys_addr &=3D TARGET_PAGE_MASK; address &=3D TARGET_PAGE_MASK; } /* Notice and record tagged memory. */ if (cpu_isar_feature(aa64_mte, cpu) && res.cacheattrs.attrs =3D=3D= 0xf0) { - arm_tlb_mte_tagged(&res.attrs) =3D true; + arm_tlb_mte_tagged(&res.f.attrs) =3D true; } =20 - tlb_set_page_with_attrs(cs, address, res.phys, res.attrs, - res.prot, mmu_idx, res.page_size); + tlb_set_page_full(cs, mmu_idx, address, &res.f); return true; } else if (probe) { return false; --=20 2.25.1