From nobody Thu Dec 18 22:23:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665413982; cv=none; d=zohomail.com; s=zohoarc; b=C2DZ01jCugZDfiKNNMHZ0TS4KOc6MwKkqunWEj8o7df+QMeZfSSe0TN0O47vkt9kvCcw7EZYyDQptM3Qr7cpRZLUFMVkdKRk4SzmFZ3T1u2KzVwE3cXe+8lmeF5FLTEWtw1npFWBiX6RdXYx9Eu74z0me6uOwGVVL8TwbL2g+X8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665413982; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jk1ASaw8kSfO1pJsq09u4PXDxP2Xi5DSakhp2fUnzio=; b=fwH0xpcBqqQkbNZ8Or2JsC5O/sbO/Zgy18EjegqahtW1Hg/IclVOFnhMK+vm//RN0BtJzfzORM5MSBbsUFfKtLkchwDXauJblnMFWLE2jVwDFzZXCsi3uXoqqCf5jRLdh5DaI1RzRO3PKAGXOP5x4ww7w+RAJZHXHg+krAyH6b8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665413982041702.4900331588536; Mon, 10 Oct 2022 07:59:42 -0700 (PDT) Received: from localhost ([::1]:43082 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohuFn-0007Fz-M3 for importer@patchew.org; Mon, 10 Oct 2022 10:59:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60088) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtl8-0006UR-DN for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:58 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:47075) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtl6-0005YG-BF for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:58 -0400 Received: by mail-wr1-x42b.google.com with SMTP id bk15so17272521wrb.13 for ; Mon, 10 Oct 2022 07:27:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=jk1ASaw8kSfO1pJsq09u4PXDxP2Xi5DSakhp2fUnzio=; b=WI2qe6kiK0y/EC7iXuciQzZs43mNUZZm8JfkBQwk1sT67eLFXbRfd75+jvv6vx2Tl0 XKmsjIy0X32B7ve/+VLUZVi7G/P8wC1l2KiKU2PfyiWnNOFBoHsnQk4cPpg5br0xwteq Rvw8jqNquyDMkX9XyS/6W7O4GdNa1hHRLv9zneSnULpGSgeZAuEI8hVv0xecSVynazag FTIKnkh9hR5n1IGBGfLZBdpAhfr+hD6QE0Ia4jg9CMMOuF6x/eX8PA4jfJ/JIoUUOgoy WwZ7cUKKzLbpqEZqPQbeP6cOU7aoVsBqvhjqQxb6OqyK8ud37trXbg7INoBwSSt7RZpc dF2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jk1ASaw8kSfO1pJsq09u4PXDxP2Xi5DSakhp2fUnzio=; b=oDg0YWJmGhaQQo3YNcEXzpeAyfPVomGhusfB7rGSpFUCOZkWxETPftNe5eTqHOyB/z YM2bS+DxPe6h9WAstsLVtk3Nz5I1ezJDGCDvZEObM1uw1+TXdh6FkIB+FdMzVgNgqOK9 2jMcSQE4S01hmztTo8/Sl2Coq979W7JHz6qimm4AVTUi3FF6zJZfo8A40YyUHOkPIhH3 ER7uyWJBIgv4fNIEDd9qfZmcCnVftD4hiCPYrR2ROfSddKtlCzxgU4qvkynfYhPy0yG2 BwfdePxXy9LREC9OHFXu/lNUxtK5lcTWQP4Hi/b8D8iiHTrkJO+QXv+8PmQsFwTXBde4 MsIA== X-Gm-Message-State: ACrzQf1DixD/jxF6dwua0CJEzeKfBQw8TLuoPKbosyPRHVNBpGuCEJ8G kEEVnoNhFLvUVG/iGBg8lNwNE+mMcWfhpQ== X-Google-Smtp-Source: AMsMyM6LC1vMvqMMu9AFh4HOxtmN9VKMLXUHchKnEWRDlcQBinxedb0+e8gIXLYPVEM0yBfpOOUztQ== X-Received: by 2002:a5d:6442:0:b0:22e:2c71:fdac with SMTP id d2-20020a5d6442000000b0022e2c71fdacmr11088674wrw.243.1665412075392; Mon, 10 Oct 2022 07:27:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/28] target/arm: Split out get_phys_addr_disabled Date: Mon, 10 Oct 2022 15:27:24 +0100 Message-Id: <20221010142730.502083-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665413983936100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20221001162318.153420-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 138 +++++++++++++++++++++++++---------------------- 1 file changed, 74 insertions(+), 64 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a589cec8e36..96ab99c7b6f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2272,6 +2272,78 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, return ret; } =20 +/* + * MMU disabled. S1 addresses within aa64 translation regimes are + * still checked for bounds -- see AArch64.S1DisabledOutput(). + */ +static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, bool is_secure, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) +{ + uint64_t hcr; + uint8_t memattr; + + if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2_S) { + int r_el =3D regime_el(env, mmu_idx); + if (arm_el_is_aa64(env, r_el)) { + int pamax =3D arm_pamax(env_archcpu(env)); + uint64_t tcr =3D env->cp15.tcr_el[r_el]; + int addrtop, tbi; + + tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); + if (access_type =3D=3D MMU_INST_FETCH) { + tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); + } + tbi =3D (tbi >> extract64(address, 55, 1)) & 1; + addrtop =3D (tbi ? 55 : 63); + + if (extract64(address, pamax, addrtop - pamax + 1) !=3D 0) { + fi->type =3D ARMFault_AddressSize; + fi->level =3D 0; + fi->stage2 =3D false; + return 1; + } + + /* + * When TBI is disabled, we've just validated that all of the + * bits above PAMax are zero, so logically we only need to + * clear the top byte for TBI. But it's clearer to follow + * the pseudocode set of addrdesc.paddress. + */ + address =3D extract64(address, 0, 52); + } + } + + result->phys =3D address; + result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->page_size =3D TARGET_PAGE_SIZE; + + /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ + hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); + result->cacheattrs.shareability =3D 0; + result->cacheattrs.is_s2_format =3D false; + if (hcr & HCR_DC) { + if (hcr & HCR_DCT) { + memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ + } else { + memattr =3D 0xff; /* Normal, WB, RWA */ + } + } else if (access_type =3D=3D MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr =3D 0xee; /* Normal, WT, RA, NT */ + } else { + memattr =3D 0x44; /* Normal, NC, No */ + } + result->cacheattrs.shareability =3D 2; /* outer sharable */ + } else { + memattr =3D 0x00; /* Device, nGnRnE */ + } + result->cacheattrs.attrs =3D memattr; + return 0; +} + bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, bool is_secure, GetPhysAddrResult *result, @@ -2431,71 +2503,9 @@ bool get_phys_addr_with_secure(CPUARMState *env, tar= get_ulong address, /* Definitely a real MMU, not an MPU */ =20 if (regime_translation_disabled(env, mmu_idx, is_secure)) { - uint64_t hcr; - uint8_t memattr; - - /* - * MMU disabled. S1 addresses within aa64 translation regimes are - * still checked for bounds -- see AArch64.TranslateAddressS1Off. - */ - if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2= _S) { - int r_el =3D regime_el(env, mmu_idx); - if (arm_el_is_aa64(env, r_el)) { - int pamax =3D arm_pamax(env_archcpu(env)); - uint64_t tcr =3D env->cp15.tcr_el[r_el]; - int addrtop, tbi; - - tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); - if (access_type =3D=3D MMU_INST_FETCH) { - tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); - } - tbi =3D (tbi >> extract64(address, 55, 1)) & 1; - addrtop =3D (tbi ? 55 : 63); - - if (extract64(address, pamax, addrtop - pamax + 1) !=3D 0)= { - fi->type =3D ARMFault_AddressSize; - fi->level =3D 0; - fi->stage2 =3D false; - return 1; - } - - /* - * When TBI is disabled, we've just validated that all of = the - * bits above PAMax are zero, so logically we only need to - * clear the top byte for TBI. But it's clearer to follow - * the pseudocode set of addrdesc.paddress. - */ - address =3D extract64(address, 0, 52); - } - } - result->phys =3D address; - result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - result->page_size =3D TARGET_PAGE_SIZE; - - /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ - hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); - result->cacheattrs.shareability =3D 0; - result->cacheattrs.is_s2_format =3D false; - if (hcr & HCR_DC) { - if (hcr & HCR_DCT) { - memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ - } else { - memattr =3D 0xff; /* Normal, WB, RWA */ - } - } else if (access_type =3D=3D MMU_INST_FETCH) { - if (regime_sctlr(env, mmu_idx) & SCTLR_I) { - memattr =3D 0xee; /* Normal, WT, RA, NT */ - } else { - memattr =3D 0x44; /* Normal, NC, No */ - } - result->cacheattrs.shareability =3D 2; /* outer sharable */ - } else { - memattr =3D 0x00; /* Device, nGnRnE */ - } - result->cacheattrs.attrs =3D memattr; - return 0; + return get_phys_addr_disabled(env, address, access_type, mmu_idx, + is_secure, result, fi); } - if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, is_secure, false, result, fi); --=20 2.25.1