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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=U4bZaH9ewSTtKGJ2hCxNf/XLdmqRHOO4aZlMXbD0cQY=; b=GxVYy9sCyoGr8DOHU4jr7vQUSUEbfplVpoo16SMBWSuQ4j+f8cYTzEcKuQ1maR0AAs /NYySrY6EtyVgnrmZwnkjIfI3CH4CpByggzj3Yi7gx+qTrKcAO2nhGLxtJOQJgoEUbp5 PdaUqyEvOuYAU5dcaG1IwTimLGBcustxINrnBAm81V8RgRPOu1OgB5pes4shzX8e+7s0 5vWH220hlkulm6I+QfzhgBvt+Ack/9Hixw4ih1AFrrmtIu3z7Mtzkiw2Fr5G2ENZP8c2 1L6IWtSmGFBDR67DLL/0bh5oigZagKwvsxKpUqVImgqb3tYKvY0KyGpPjxlDy8275ZTJ ZvaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U4bZaH9ewSTtKGJ2hCxNf/XLdmqRHOO4aZlMXbD0cQY=; b=kV6N/2HvMoDuSWFrw7H+Ck9MjCH0et8z74G8JPjluaylfOG1gQUHGRRqOoo+YOwylK yHgZ1k1tmUTIhstegwNwcE0H4Zmsd6iVSXUWYpei31wYRC/qXvh1gjdGRkOL11t9B+G7 AJt7/gWszg1SGaMmnapHYDDZVzaoiTOpguBY1lZshaOKp77j22S6HwtPSOIxkE5ceESx 0H5RrBZCqc3k/9o9KTndgyWFIxlcATjYEkmblnBnVEgZV+4PQM9cFR8ygZODh4VY+sHT 8vhAOoYQVRhS0IPZFvaxPCjWN8IOobVcbTCQ0pYtcHtWwRckL/cUHYAKnfPw5wouvzqq 2T1w== X-Gm-Message-State: ACrzQf3bdSmb4I/Kd/dOIltTBEYU7PClaTZtwKAp6zDUd6+UMOC1lhAt xHExo1ad8EUFJibBUcyhx/KJcLzOh/YSSw== X-Google-Smtp-Source: AMsMyM4a+xBRoQ7ROsXMCd4VBluOhLr/f6oF1Ds2Jlt0aSlS/KfN6DL/BdMaKQKbSV3cS30Rcw+Gow== X-Received: by 2002:a05:600c:5114:b0:3b5:428:cf67 with SMTP id o20-20020a05600c511400b003b50428cf67mr20539446wms.80.1665412062233; Mon, 10 Oct 2022 07:27:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/28] target/arm: Split out get_phys_addr_with_secure Date: Mon, 10 Oct 2022 15:27:11 +0100 Message-Id: <20221010142730.502083-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665413263217100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Retain the existing get_phys_addr interface using the security state derived from mmu_idx. Move the kerneldoc comments to the header file where they belong. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20221001162318.153420-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 40 ++++++++++++++++++++++++++++++++++++++ target/arm/ptw.c | 44 ++++++++++++++---------------------------- 2 files changed, 55 insertions(+), 29 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 307a5965053..3524d11dc57 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1145,6 +1145,46 @@ typedef struct GetPhysAddrResult { ARMCacheAttrs cacheattrs; } GetPhysAddrResult; =20 +/** + * get_phys_addr_with_secure: get the physical address for a virtual addre= ss + * @env: CPUARMState + * @address: virtual address to get physical address for + * @access_type: 0 for read, 1 for write, 2 for execute + * @mmu_idx: MMU index indicating required translation regime + * @is_secure: security state for the access + * @result: set on translation success. + * @fi: set to fault info if the translation fails + * + * Find the physical address corresponding to the given virtual address, + * by doing a translation table walk on MMU based systems or using the + * MPU state on MPU based systems. + * + * Returns false if the translation was successful. Otherwise, phys_ptr, a= ttrs, + * prot and page_size may not be filled in, and the populated fsr value pr= ovides + * information on why the translation aborted, in the format of a + * DFSR/IFSR fault register, with the following caveats: + * * we honour the short vs long DFSR format differences. + * * the WnR bit is never set (the caller must do this). + * * for PSMAv5 based systems we don't bother to return a full FSR format + * value. + */ +bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, bool is_secure, + GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) + __attribute__((nonnull)); + +/** + * get_phys_addr: get the physical address for a virtual address + * @env: CPUARMState + * @address: virtual address to get physical address for + * @access_type: 0 for read, 1 for write, 2 for execute + * @mmu_idx: MMU index indicating required translation regime + * @result: set on translation success. + * @fi: set to fault info if the translation fails + * + * Similarly, but use the security regime of @mmu_idx. + */ bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index d789807b086..74dcb843fe2 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2260,35 +2260,12 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState= *env, return ret; } =20 -/** - * get_phys_addr - get the physical address for this virtual address - * - * Find the physical address corresponding to the given virtual address, - * by doing a translation table walk on MMU based systems or using the - * MPU state on MPU based systems. - * - * Returns false if the translation was successful. Otherwise, phys_ptr, a= ttrs, - * prot and page_size may not be filled in, and the populated fsr value pr= ovides - * information on why the translation aborted, in the format of a - * DFSR/IFSR fault register, with the following caveats: - * * we honour the short vs long DFSR format differences. - * * the WnR bit is never set (the caller must do this). - * * for PSMAv5 based systems we don't bother to return a full FSR format - * value. - * - * @env: CPUARMState - * @address: virtual address to get physical address for - * @access_type: 0 for read, 1 for write, 2 for execute - * @mmu_idx: MMU index indicating required translation regime - * @result: set on translation success. - * @fi: set to fault info if the translation fails - */ -bool get_phys_addr(CPUARMState *env, target_ulong address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, ARMMMUFaultInfo *fi) +bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_id= x, + bool is_secure, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) { ARMMMUIdx s1_mmu_idx =3D stage_1_mmu_idx(mmu_idx); - bool is_secure =3D regime_is_secure(env, mmu_idx); =20 if (mmu_idx !=3D s1_mmu_idx) { /* @@ -2304,8 +2281,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, ARMMMUIdx s2_mmu_idx; bool is_el0; =20 - ret =3D get_phys_addr(env, address, access_type, s1_mmu_idx, - result, fi); + ret =3D get_phys_addr_with_secure(env, address, access_type, + s1_mmu_idx, is_secure, result,= fi); =20 /* If S1 fails or S2 is disabled, return early. */ if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, @@ -2517,6 +2494,15 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, } } =20 +bool get_phys_addr(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) +{ + return get_phys_addr_with_secure(env, address, access_type, mmu_idx, + regime_is_secure(env, mmu_idx), + result, fi); +} + hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { --=20 2.25.1