From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665412168; cv=none; d=zohomail.com; s=zohoarc; b=N7oZ3vJ+eYgQrLqWFoPtPnkDX4zyJjZznFcWK+H6p6jriFxIc0ptIT65E6806AMHZJ18rktmj7a5q9awpfPb/mJl6u5Vctza/Onut0rHRbDAWt7+53lhwHMCgqSdr2Fnvnz1rYBzYf1BNoK/J/juvkLPTP6uu9tP5gdLXnJHsKU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665412168; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GXBLlnfCbK3K6UlIWvoHPFAcHN/A5jeDtX9d+QOJHH0=; b=SX+QFCNCmyQKLEm8HOk7eK8KwGix7xSHqxjwTMVUie1zrNt2Ef7RuKpPschoBvVNhl/aeMCqafw8S5HuB+VDiy3Osp1YswAm0KtsmDyr5uywkkavXITV5cCi91O2dSeYVy+kOhjatWMwrv5NQDb3rUlQmE3tb+wVH4rXHaVBOjE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665412168933588.6506164775213; Mon, 10 Oct 2022 07:29:28 -0700 (PDT) Received: from localhost ([::1]:40292 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohtmZ-0000D8-Nd for importer@patchew.org; Mon, 10 Oct 2022 10:29:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55754) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtko-0005oF-Ds for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:38 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:41864) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtkm-0005XH-Pr for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:38 -0400 Received: by mail-wr1-x42f.google.com with SMTP id bu30so17295310wrb.8 for ; Mon, 10 Oct 2022 07:27:36 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=GXBLlnfCbK3K6UlIWvoHPFAcHN/A5jeDtX9d+QOJHH0=; b=FctTs9fd/TRuiu2EB/SYDzawPDcyGgFO7brVj8JdQTOD4BR27JkKTL2+KNY98rQjxG 4hflGFKiLArFDMUcW16Z7+amnPL70bE9wIe1vhTVaRQlaiR8NLgtnoopP7YFNLg5hzwU nfC/XjU0h2TQhU1w63l1E+1YdQfT+B4C8Ea7s9+h9DjBRip+VbVxFHH94eat++BkrgZB sfJihg2RdoEn/rJgqDN/VRMmXS+9hxpFbeBttDTEBc1ap6WkjBOqiuXt5JsgsgELbTXE TFaQ7RBfpenqHbMAe0wbaBOuvCAcHPjUxRc5aWX2Opxbo5yd/BzY/Idv+l4JrpaX39Ij l3GA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GXBLlnfCbK3K6UlIWvoHPFAcHN/A5jeDtX9d+QOJHH0=; b=Rk/6FqoCrlsKvNySv2ZZlCTZcgzRDfPoJ0u/Y2nSF1A2eTarejXul9l5iVGVnwl/xC 7MV2JAXiY66XSwlGkuG8MSC1QfPGdYTx1ZKQ0l7XUTS/K338IHIMzP7jXvZOVlbfPQEB rGzXZW7YPxGNnql6tesJaY8D+uKKn5WYMN54frS9ypUPVr6sQLbsmuqOOOSA3Z1fPKaZ 27nLp0z/rcL6wZXJ51xfWulv/NEuFOy8owagDSzqLlCzbvmDE9qi57eVK+EdEGlrhzMT f3MJ6En6Jzt2pPK6xlY6D2pTFPuJBRVlBeJX7I7fIS70+2vWeDMd0mZnRjovTeiix6k0 na7A== X-Gm-Message-State: ACrzQf0ToDKOulcb7L+RjTG9D7k5MoJeV9rsX5QxpR311hNF7kw1LFkI LV8fkOcwY7ASZj/hI8yT9zXutDE9oNCW1A== X-Google-Smtp-Source: AMsMyM4azehWzXA4vzmyHui7qOwehi1FsVgTb/NxbLjOSzR8yTee9P+Oqq7YsG+4xuPgHFEjkOYRyg== X-Received: by 2002:a05:6000:1862:b0:230:fc9a:813b with SMTP id d2-20020a056000186200b00230fc9a813bmr1553564wri.552.1665412054462; Mon, 10 Oct 2022 07:27:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/28] target/arm/kvm: Retry KVM_CREATE_VM call if it fails EINTR Date: Mon, 10 Oct 2022 15:27:03 +0100 Message-Id: <20221010142730.502083-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665412169209100001 Content-Type: text/plain; charset="utf-8" Occasionally the KVM_CREATE_VM ioctl can return EINTR, even though there is no pending signal to be taken. In commit 94ccff13382055 we added a retry-on-EINTR loop to the KVM_CREATE_VM call in the generic KVM code. Adopt the same approach for the use of the ioctl in the Arm-specific KVM code (where we use it to create a scratch VM for probing for various things). For more information, see the mailing list thread: https://lore.kernel.org/qemu-devel/8735e0s1zw.wl-maz@kernel.org/ Reported-by: Vitaly Chikunov Signed-off-by: Peter Maydell Reviewed-by: Vitaly Chikunov Reviewed-by: Eric Auger Acked-by: Marc Zyngier Message-id: 20220930113824.1933293-1-peter.maydell@linaro.org --- target/arm/kvm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index e5c1bd50d29..1e4de9b42e3 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -79,7 +79,9 @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpu= s_to_try, if (max_vm_pa_size < 0) { max_vm_pa_size =3D 0; } - vmfd =3D ioctl(kvmfd, KVM_CREATE_VM, max_vm_pa_size); + do { + vmfd =3D ioctl(kvmfd, KVM_CREATE_VM, max_vm_pa_size); + } while (vmfd =3D=3D -1 && errno =3D=3D EINTR); if (vmfd < 0) { goto err; } --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665412489; cv=none; d=zohomail.com; s=zohoarc; b=CBgTVCpzOFcompB/4BXQ+YWaNWUh4DDf1DNTp40+WnOTKMz2CSGA2LnClFpjgnwHw2DOVJ/dnc46RRQvkRxnW2lqniV3cToWex/o8dxyoivygBF14Og0ZvrFlvnCAZP3INxMhkdAfRL8DnDou2FxKKqPTqU2EB/lEBaXHCE0Hxs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665412489; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SPGKioIMb/pLJ3nk36JFfL1iYwx+YE1iQzeuzMVhTD4=; b=XyuoEEVLZB96KhHWxas3+W+T5TPQkO3HLMC2sne+8MdpCu9gw6TNpdlvRnqPDnTMYnutDGP7rccO+mU3qf43q6FmqvYuk/JgWynzY1q1kGK2GeOkbHAcvAXpPXk++OrVYbuNDqV4D5EKVFYZqpkicjLjUk5Jsaa7scJjIpPswRE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665412489337241.46581383516582; Mon, 10 Oct 2022 07:34:49 -0700 (PDT) Received: from localhost ([::1]:50636 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohtrj-0005ya-Qt for importer@patchew.org; Mon, 10 Oct 2022 10:34:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55756) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtkp-0005p1-5U for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:39 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:44814) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtkn-0005XQ-1t for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:38 -0400 Received: by mail-wr1-x42b.google.com with SMTP id r13so17288311wrj.11 for ; Mon, 10 Oct 2022 07:27:36 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=SPGKioIMb/pLJ3nk36JFfL1iYwx+YE1iQzeuzMVhTD4=; b=liOLPdDz8dt4fXuPesosHu8ICaqstKBVP208nXbghsJJxnAkBjfjIIFvdLynsauF3w dbHaMW/I4r89NlAJFTId+Iggci0imZGjhjI+ihor2Ou/C0M5KikFq6AI/uVvyfT4UZtJ JQCpnxTum2SwVsFtWbMEil6hkCywCKCR207jm/YM0VrgMIvw0CHeReK/mtcFKeAvddJ+ p5dogAy6Y6vrua1yqwHRwhtSC3HMXgd++CIiVY/3D5+0u4wjfNZUU99/NJAUwpdJ2HYA yAJcxQNSgAXx0Tj6gfGtgw6swGdSc0sqqp1Zs/OVrUZLiY9rQ6TYXLvedKtqbflF+ME+ IToA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SPGKioIMb/pLJ3nk36JFfL1iYwx+YE1iQzeuzMVhTD4=; b=DblB++5gFrL/b+/hB0BvQMz8x1SIDLCpBEB5v4+1vEE/t8ZgRM3vHm1Uj1R/sDBpK2 v3CYivgkzCcxFQ6hM88r8w2tO3UpUTAvoNGfv97uzKaS3ogkVOy+Nxleh+NPFtmoA3ys wOMZZ0HMFIgiCX/jS8A/WJAd3ei70DDmnyN89jOPneDUGVw5lPcx8adbyg5VsV2Fknga ZHzW2wI+Il/CycukSsXus52Oqi2Mdj1dOYuUhVfGqjHCj8hJIo0ZFtY5JkxUrfjLY6XQ +MIoCRgoR+ZgLMZ1bM7wmhHzGFvLl4Lf9HEgyMtgp5RIkgjCffN6mzS58ft+zss3WY2t qw0A== X-Gm-Message-State: ACrzQf0KkQUY9qnJaFT7TImIkM36yj697rfGj/At98mvqfKd2UpWYzdX WcD/1m7dPnPaxL/rrpF+kpYaXu7xNFx7gQ== X-Google-Smtp-Source: AMsMyM6TH8XarXV1kmPd6mX8f2osiXRgP2s390oZLKg3vZYP/ShVBCKmj/2o7+5xkYPJ5EYEpHrXBA== X-Received: by 2002:a5d:648c:0:b0:22e:63be:be09 with SMTP id o12-20020a5d648c000000b0022e63bebe09mr11553549wri.159.1665412055437; Mon, 10 Oct 2022 07:27:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/28] target/arm: allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented Date: Mon, 10 Oct 2022 15:27:04 +0100 Message-Id: <20221010142730.502083-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665412490878100001 Content-Type: text/plain; charset="utf-8" From: Jerome Forissier Updates write_scr() to allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented. SCR_EL3 being a 64-bit register, valid_mask is changed to uint64_t and the SCR_* constants in target/arm/cpu.h are extended to 64-bit so that masking and bitwise not (~) behave as expected. This enables booting Linux with Trusted Firmware-A at EL3 with "-M virt,secure=3Don -cpu max". Cc: qemu-stable@nongnu.org Fixes: 78cb9776662a ("target/arm: Enable SME for -cpu max") Signed-off-by: Jerome Forissier Reviewed-by: Andre Przywara Reviewed-by: Richard Henderson Message-id: 20221004072354.27037-1-jerome.forissier@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 54 ++++++++++++++++++++++----------------------- target/arm/helper.c | 5 ++++- 2 files changed, 31 insertions(+), 28 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 429ed42eece..68d99565ac4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1664,33 +1664,33 @@ static inline void xpsr_write(CPUARMState *env, uin= t32_t val, uint32_t mask) =20 #define HPFAR_NS (1ULL << 63) =20 -#define SCR_NS (1U << 0) -#define SCR_IRQ (1U << 1) -#define SCR_FIQ (1U << 2) -#define SCR_EA (1U << 3) -#define SCR_FW (1U << 4) -#define SCR_AW (1U << 5) -#define SCR_NET (1U << 6) -#define SCR_SMD (1U << 7) -#define SCR_HCE (1U << 8) -#define SCR_SIF (1U << 9) -#define SCR_RW (1U << 10) -#define SCR_ST (1U << 11) -#define SCR_TWI (1U << 12) -#define SCR_TWE (1U << 13) -#define SCR_TLOR (1U << 14) -#define SCR_TERR (1U << 15) -#define SCR_APK (1U << 16) -#define SCR_API (1U << 17) -#define SCR_EEL2 (1U << 18) -#define SCR_EASE (1U << 19) -#define SCR_NMEA (1U << 20) -#define SCR_FIEN (1U << 21) -#define SCR_ENSCXT (1U << 25) -#define SCR_ATA (1U << 26) -#define SCR_FGTEN (1U << 27) -#define SCR_ECVEN (1U << 28) -#define SCR_TWEDEN (1U << 29) +#define SCR_NS (1ULL << 0) +#define SCR_IRQ (1ULL << 1) +#define SCR_FIQ (1ULL << 2) +#define SCR_EA (1ULL << 3) +#define SCR_FW (1ULL << 4) +#define SCR_AW (1ULL << 5) +#define SCR_NET (1ULL << 6) +#define SCR_SMD (1ULL << 7) +#define SCR_HCE (1ULL << 8) +#define SCR_SIF (1ULL << 9) +#define SCR_RW (1ULL << 10) +#define SCR_ST (1ULL << 11) +#define SCR_TWI (1ULL << 12) +#define SCR_TWE (1ULL << 13) +#define SCR_TLOR (1ULL << 14) +#define SCR_TERR (1ULL << 15) +#define SCR_APK (1ULL << 16) +#define SCR_API (1ULL << 17) +#define SCR_EEL2 (1ULL << 18) +#define SCR_EASE (1ULL << 19) +#define SCR_NMEA (1ULL << 20) +#define SCR_FIEN (1ULL << 21) +#define SCR_ENSCXT (1ULL << 25) +#define SCR_ATA (1ULL << 26) +#define SCR_FGTEN (1ULL << 27) +#define SCR_ECVEN (1ULL << 28) +#define SCR_TWEDEN (1ULL << 29) #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) #define SCR_TME (1ULL << 34) #define SCR_AMVOFFEN (1ULL << 35) diff --git a/target/arm/helper.c b/target/arm/helper.c index db3b1ea72da..c08a7b35a04 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1752,7 +1752,7 @@ static void vbar_write(CPUARMState *env, const ARMCPR= egInfo *ri, static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) { /* Begin with base v8.0 state. */ - uint32_t valid_mask =3D 0x3fff; + uint64_t valid_mask =3D 0x3fff; ARMCPU *cpu =3D env_archcpu(env); =20 /* @@ -1789,6 +1789,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_doublefault, cpu)) { valid_mask |=3D SCR_EASE | SCR_NMEA; } + if (cpu_isar_feature(aa64_sme, cpu)) { + valid_mask |=3D SCR_ENTP2; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665412784; cv=none; d=zohomail.com; s=zohoarc; b=mtKgklYe08WVJg66ysV83ZkYdwqRuhBygB/ILCutob08HSHRes2YHBk83ALK9na/IT+pdEa7xaLND/9UQAhZjfdITqkctsNVOXBIk5sTKsHeEsgB4HYScgBppmHG3NvYNWDioXB3UY98C4X1ClVSu7upRMwsJmDDUDlBcKY7/dE= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2l11ylByNeiqzqou8mXaI05tY4/Ztz0H+1BMCNUIG2M=; b=aDTReDEeVrRAWHAS5VuFxxiwzBNelP76tNFqTiOlkm1S+Q61+/ta9atvk3eUX4SGqO Ueg5iSmNPCQh0XugVt8gESpneMhqt2KkozHl2QGkFH9y4iAXbE+9v9ygouOdrl4CM+Hs 5dtm5Em+73l0IACL2MSX/1nkKwVN02LxSLMCDl0ID/b5TD4yixKGpYKmBDzKotZiPFTo e46qZ/MXEP+xPiDCAJ4LZmzvLXDkkVGdKDrBm8O7I5nGIPc/xCPTLgn71lNjNw7dHDsL s979rG5eAAtYh4TxtskUfDyINJgJ0PxCIYDLkWfsQI5m/wiJf1GJl76vlxn5smpZb07g C/5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2l11ylByNeiqzqou8mXaI05tY4/Ztz0H+1BMCNUIG2M=; b=0L66PWpKxm3vb/uMesJKq0rk/4piw9D67omln92Fw747JUu9OJTB+e2RNmKssHUCls BrNGuX7lzfP7V2uzeuZq9OnRoFwjetHBkb8POSgFbLdc9OMDjLh2DcuOZoYjyfyOwyaE U1KlXrfYGJtujHci3QNghHOfc7L8EVz0zO5Cb0g2qg2kTg5q+boQbT7SDZOdfgFzR3Pq JGqqM+XPBVlRCvYiIMSskC6yXdkttYtgQ3IciHOQ33VLjSyPbEGtCncPAjBpRWKnjIKD cHqTejMKcsw7idl7btY2XxI/ib3n8vpviZ7g0zEcRZsCJfSXIesHfjwhWvEJcvCwUYCm VHqQ== X-Gm-Message-State: ACrzQf0AIZE4narPCBD+g/KoAuOxDtQOwI5PDPQaX04+fkHEQ/vCiYG0 pfh0rgl1xNCcPI7BANpna7BohErWNofJHA== X-Google-Smtp-Source: AMsMyM6pJqBbIVirN5L2vHZnhLgcA4Hc/gOuXMow/6DWy6kN0gJLSI/E2fsyiTMA4mJlt5W/F8lj1Q== X-Received: by 2002:adf:ebc6:0:b0:22a:c5ee:b057 with SMTP id v6-20020adfebc6000000b0022ac5eeb057mr12131398wrn.317.1665412056351; Mon, 10 Oct 2022 07:27:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/28] docs/nuvoton: Update URL for images Date: Mon, 10 Oct 2022 15:27:05 +0100 Message-Id: <20221010142730.502083-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_PDS_OTHER_BAD_TLD=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665412785467100003 From: Joel Stanley openpower.xyz was retired some time ago. The OpenBMC Jenkins is where images can be found these days. Signed-off-by: Joel Stanley Reviewed-by: Hao Wu Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20221004050042.22681-1-joel@jms.id.au Signed-off-by: Peter Maydell --- docs/system/arm/nuvoton.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index ef2792076aa..c38df32bde0 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -82,9 +82,9 @@ Boot options =20 The Nuvoton machines can boot from an OpenBMC firmware image, or directly = into a kernel using the ``-kernel`` option. OpenBMC images for ``quanta-gsj`` a= nd -possibly others can be downloaded from the OpenPOWER jenkins : +possibly others can be downloaded from the OpenBMC jenkins : =20 - https://openpower.xyz/ + https://jenkins.openbmc.org/ =20 The firmware image should be attached as an MTD drive. Example : =20 --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665412169; cv=none; d=zohomail.com; s=zohoarc; b=LqzLIAHz5Bijc1nEcuqIcavCRhx/MgmBl3ddHOGRYZMD2O6bt75XcXBBqKqyNFBoyoxn2FDrvekpTx5srmOLTdj6w3E+mS1Bia7OW/EVWZTThMTjvZeB5QRVrA9e9flYM48yjAs5DEWoq78/3wPIXrxJA1KN0S+jSHlEA5BIqIc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665412169; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UhrnEzupfDW4VUrWZYS+8MEh7LjRrlG3/gLMwULTgSk=; b=DBjcLOCINCUU3ZvAKli3O1gZcASYB+cy4nfL3oCHpJqWVGSwZ+DiadhnFgwFWhls19Pak3au4WWxfud8HmBPgniXSeAz6jLg/y92dm5mspSwFqYik5m6e16y0ZZhutjKbKXyk+8Xa6Ob+91yHUVF5HxomSmT+zAYm6qOksne9Vo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665412169564657.7965094293138; Mon, 10 Oct 2022 07:29:29 -0700 (PDT) Received: from localhost ([::1]:40294 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohtma-0000IC-A3 for importer@patchew.org; Mon, 10 Oct 2022 10:29:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55762) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtkq-0005v0-Ki for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:40 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:34388) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtkp-0005Xn-13 for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:40 -0400 Received: by mail-wr1-x429.google.com with SMTP id b4so17334114wrs.1 for ; Mon, 10 Oct 2022 07:27:38 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=UhrnEzupfDW4VUrWZYS+8MEh7LjRrlG3/gLMwULTgSk=; b=kZeEGwuz74XaSMz02YTAoSWNHvRdc1H83RRD/mRiZayT+5Ry+ggOWnCzCp0wkwcGRh 3qvYz8Z88dNf0mV2v7ZQI7s/j/o8xdI7SCzbzVc0SkH0WpyeshzeqNJes4eZUgA2x8XZ GYrkEX5rlk1cpMjNPQWJ03Y114p9qmmjOgrRPcZilrPjNGgKBqLxJuJ4b7IRtmAvlmdg ncjcrXFx/XB9TkgN6p2iU4+Phslu3sGwXPydwp9m+0jV6C2mHpUWGffJsIlh2l5lKwsO A4ziI0PdsGamte6P4pjVOzqzEfH4vbxKEmr8QjY9E/uS550uSnidird1USiEWbbqo+mW XfbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UhrnEzupfDW4VUrWZYS+8MEh7LjRrlG3/gLMwULTgSk=; b=w7X4ftel/onMaXgaJo7yBO4YYmdEct1rHn+ugsoRjhoyfEz3gNu6O2IYc0ixwa4FNM kXZbeaepEVNj6S6Hl4JxfSPZcxTwtbmnEjFnAFmIbrhMzbTgfUcYQCs0dBOHVY+CQlVh 9IX8FTUtcT/yDes6Ou5ELRQ3gmQpILQh2mVxXvHuDmWjwWvYJ9rdgkcbpI9LKlPtmX6m ZiCK2Tdw+24T+8+u9syIWyojnfIV+SSmtAfA6ym4KVBJqLj3L1hBm4U+U2EUdkSSfDK8 LdWXjClq4iKJOZBg2XcfJuRJ8L6Y8z9/oyDggATAphH6zsvT3GBFonI74WEN8/DE365U ko7Q== X-Gm-Message-State: ACrzQf04HKo6YMaZdRVQgBBh1YsEmnD+NKYmPRxhKXVkphVU34M8QIkm Ac73M19J4/OkrK8BsFqM4h6l0Ji5kBu/sg== X-Google-Smtp-Source: AMsMyM5GbCzBZTtKtyc09uA8z/TDMi5XiO7OZv94e07PHyKw77nHtNIy8XUer4nIYHV3S1u2Dyqb3w== X-Received: by 2002:a05:6000:18a1:b0:230:f9fb:c83 with SMTP id b1-20020a05600018a100b00230f9fb0c83mr1640439wri.329.1665412057398; Mon, 10 Oct 2022 07:27:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/28] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr Date: Mon, 10 Oct 2022 15:27:06 +0100 Message-Id: <20221010142730.502083-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665412171254100005 Content-Type: text/plain; charset="utf-8" From: Richard Henderson The starting security state comes with the translation regime, not the current state of arm_is_secure_below_el3(). Create a new local variable, s2walk_secure, which does not need to be written back to result->attrs.secure -- we compute that value later, after the S2 walk is complete. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20221001162318.153420-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 2ddfc028abb..b8c494ad9f0 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2298,7 +2298,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, hwaddr ipa; int s1_prot; int ret; - bool ipa_secure; + bool ipa_secure, s2walk_secure; ARMCacheAttrs cacheattrs1; ARMMMUIdx s2_mmu_idx; bool is_el0; @@ -2313,17 +2313,17 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, =20 ipa =3D result->phys; ipa_secure =3D result->attrs.secure; - if (arm_is_secure_below_el3(env)) { - if (ipa_secure) { - result->attrs.secure =3D !(env->cp15.vstcr_el2 & VSTCR= _SW); - } else { - result->attrs.secure =3D !(env->cp15.vtcr_el2 & VTCR_N= SW); - } + if (is_secure) { + /* Select TCR based on the NS bit from the S1 walk. */ + s2walk_secure =3D !(ipa_secure + ? env->cp15.vstcr_el2 & VSTCR_SW + : env->cp15.vtcr_el2 & VTCR_NSW); } else { assert(!ipa_secure); + s2walk_secure =3D false; } =20 - s2_mmu_idx =3D (result->attrs.secure + s2_mmu_idx =3D (s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2); is_el0 =3D mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D AR= MMMUIdx_SE10_0; =20 @@ -2366,7 +2366,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, result->cacheattrs); =20 /* Check if IPA translates to secure or non-secure PA space. */ - if (arm_is_secure_below_el3(env)) { + if (is_secure) { if (ipa_secure) { result->attrs.secure =3D !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)); --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665412340; cv=none; d=zohomail.com; s=zohoarc; b=nNJBEmB5PjKO+lq2xXg/vzBGPedLXzcYzLz81zap2GYv9R7I9BamsoUtmACexl3SCM6RcfdTnRLN+A0J+AsrKoBMysHM+4actTXcpd8leG+P0o4P7RR4b+dghDSMnDYKizTdayfYGqNrYXx/D/i6VK5shym8FjgCfKITSpUU4FY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665412340; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3qV9Bd6BDRz/hfn9vSKAZJrKreSv3U0/Yi5V2ypL1h0=; b=KWZLwG3EhrI+OfpdT0lTARYe/ZMDLdAPnnWj8ORU99YPbqoX71H12nPFAA0IZHKDyYiPM8CYk6QlY7WTlTMy7jOJmf+cH3qfq3itcMIwSqIoDFGt4kNkuCzzFjt7wC4WbD+Bc5nsboFVooGTQ9Wc1F4tKDUjipsJTE5d1ikvxz0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665412340709983.1782971070344; Mon, 10 Oct 2022 07:32:20 -0700 (PDT) Received: from localhost ([::1]:36488 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohtpL-00044h-8K for importer@patchew.org; Mon, 10 Oct 2022 10:32:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55764) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtkq-0005vv-S5 for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:40 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:41864) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtkp-0005XH-90 for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:40 -0400 Received: by mail-wr1-x42f.google.com with SMTP id bu30so17295571wrb.8 for ; Mon, 10 Oct 2022 07:27:38 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3qV9Bd6BDRz/hfn9vSKAZJrKreSv3U0/Yi5V2ypL1h0=; b=IZaloUadulQgUI7/p3bCUby23IM1lPDsLiz5HSkF35uq/GGcHKXBqM8x6iOBdqaJeI nARRwVBHdqgO0tP7kLKcQwfjR+dgSpg4wLPUDmw5QQZyTpbB7fUhh9kTxeitJ5qBDSir mSvTH7spbqjCc1E7tbKQl4S8gMzLfTvl5FhuPIpzdmtK4mA7+NEbwWss+hWGezw6J2wn A0y3XrwQOEQ+FMpSoCoHD/rSmJgRYBJPZTHSIx1ZepoxUAeiMi5GZhxtFqsxkr+Z/5ep DyLfhwk4SQLe07Gu0LXWgg3tTw/Fm4DQ3+ieVBDeaikQlo6VzpSbif2HJdUXebXytcKZ 1HPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3qV9Bd6BDRz/hfn9vSKAZJrKreSv3U0/Yi5V2ypL1h0=; b=Gm/lV8hOyWhCj77oXljBwl1wiV3a5wUyr4A96qfkSojxf2fEVMHFDlCMn5odco14hP QkENkmKB4EqYRCblX7VUTKuuVjDLh2hA0AIz2nPdcqaNyeImOv/2G4e3n+IgCHl744M2 T165vFEPqm78ORviKGJ0H5ZP7pcW+a4S1Nsz2BsVe3ZvVFa0YtmMN+AB+a+elD91Ee59 l4wlPBrQ2EshDpQ2NM3fYSh9FXFtHIRF93yB3ppgbHq7fOBXNhWfPd9EGmfX5hvBrwUD gP4lhJ9FXeQajS9oKa9L174hlRvnBLm0Upd2Lwkdjvb16UAMslqJ083/McIs1tQeCNmc YO8A== X-Gm-Message-State: ACrzQf3iWZv9Ztw+HjAB5YgRpd1i1rThRNYueB30J4X67mEfLs7HEjqB iLrkYpGPWMu6q6swhWEPK4RFkz3zOMo21g== X-Google-Smtp-Source: AMsMyM4nAYqaB58iGGmXhn/zbbqZn/WZbK9HZ6tsnguSBZBtxPjTS4s2Nq4kfez+pzdtpaFGmZaX5Q== X-Received: by 2002:adf:fb10:0:b0:22a:f1d8:18d2 with SMTP id c16-20020adffb10000000b0022af1d818d2mr11678812wrr.483.1665412058349; Mon, 10 Oct 2022 07:27:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/28] target/arm: Make the final stage1+2 write to secure be unconditional Date: Mon, 10 Oct 2022 15:27:07 +0100 Message-Id: <20221010142730.502083-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665412341315100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson While the stage2 call to get_phys_addr_lpae should never set attrs.secure when given a non-secure input, it's just as easy to make the final update to attrs.secure be unconditional and false in the case of non-secure input. Suggested-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20221007152159.1414065-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b8c494ad9f0..7d763a58477 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2365,17 +2365,16 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, result->cacheattrs =3D combine_cacheattrs(env, cacheattrs1, result->cacheattrs); =20 - /* Check if IPA translates to secure or non-secure PA space. */ - if (is_secure) { - if (ipa_secure) { - result->attrs.secure =3D - !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)); - } else { - result->attrs.secure =3D - !((env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)) - || (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))); - } - } + /* + * Check if IPA translates to secure or non-secure PA space. + * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA. + */ + result->attrs.secure =3D + (is_secure + && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)) + && (ipa_secure + || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)))); + return 0; } else { /* --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665412989; cv=none; d=zohomail.com; s=zohoarc; b=DIOEmmTCli1D7acgJNPrJYy+BKxN9oiUPhH1Tx2bXlzZjM5xYi4NV4L9sv6mZDSG1m43Rj2qjxLRu45QS1sGaxxmgWUnZNwisjhfg8+Ozq59eoXXNCwCy5IZe4bvxV//ioxEFDYzdcDiFtGkVGpeUfhD0dgxKsE3XHOXaCIuAEM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665412989; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WkSdaubmZsgSKUeMueDtAeU2twM74yQQ9e2GcRuy584=; b=bcZ0LpAhgCnQSfdsIHiehbKNWlLv2Ah7diSMq/l8/CtVoJwsTBwD2fcpvYN8z3VeqqwrekHXSlZIfxBU88qOVIwkOUyW8mG0Sk9ZhVwj5VhGwp39CNeCV9M40p53F2jEe3HhMTsAdk7+7B/52IpfqLTOztkTLk4uumvMqX5rt00= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665412989298594.3486691750082; Mon, 10 Oct 2022 07:43:09 -0700 (PDT) Received: from localhost ([::1]:55162 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohtzn-0000ov-0c for importer@patchew.org; Mon, 10 Oct 2022 10:43:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55766) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtkt-00063b-L7 for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:43 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:47075) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtkr-0005YG-RJ for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:43 -0400 Received: by mail-wr1-x42b.google.com with SMTP id bk15so17271383wrb.13 for ; Mon, 10 Oct 2022 07:27:40 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=WkSdaubmZsgSKUeMueDtAeU2twM74yQQ9e2GcRuy584=; b=cCurrrjhvZJpDlGn3otC20frDXwJK/lzweblDkrwNPK4gt7iIDgXDF+kJji1JFhEeD A516anrdXIhzf4pcDoz34accH1LXraRONpEBm0Wz1OVYemRNMlPEdN2LPHtsY0zshff3 ZsukArbvKSFctoW3bEsAcgnQ1i5/F65vGQ79rF7nJ9RyEeQDUzi5T3AIBL9tN/qEZmOr HCb9ijGp5fdQPtnS/jFSOBx/cbUCSJ0HerLhC/j3e830W36EabFIV3GWoCOooeCTDkPP QoZ3PoO/HYeiNJZHxvh8lKUZ4ersGmQVkdaEYbThYiUrw2JBvVKnZDSIyDXcaEJeIri+ iE7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WkSdaubmZsgSKUeMueDtAeU2twM74yQQ9e2GcRuy584=; b=qxjVQOo8DZusGOuh7IQZ0huw7q3jvm6OSWT2ViW+FjHTSx1poyRDGFCm5W+o0zVMUB cSB2o8BNjh1AB9k9FoPbWpo+xDcSXAE5PcppVOd/AAMOLX3YhebHZddzG/md5qKEadz3 FaUZv5PTKTP8VkB3wwFWpDSRVt9X/xLBl9Aeparn8tqGoR+lJwrLaK+2/+FsSK/Zc/kF ITi+PHV03jTUNC3LtSdSI5ZpBtbK+kY0GyJyxTeNR7kMT68+YxrLRbHH0exAtByHMx52 2pgQrIctWHbFzZUP5QjdBiLHX1uSDTI399D9hhsQzQksY4vfAJWCwRTDGj0D5NvHSt1U pkjg== X-Gm-Message-State: ACrzQf2sfTgKotfjwD0ztjIg/R+0VMaR0VfDiEQdJ9lN+xpIdqAE037K B5il4wyMMYqGyUxZKc1Ea16ZBXBosrvVYw== X-Google-Smtp-Source: AMsMyM4I8/MvWOCux8EGc5kpn/p0bXOGQnstDb0mJ9L4qz3GkC8phXcEAW5YwG19QcOg0gJ1jBnqgA== X-Received: by 2002:a5d:4909:0:b0:22e:7bbf:c8d with SMTP id x9-20020a5d4909000000b0022e7bbf0c8dmr10878414wrq.80.1665412059333; Mon, 10 Oct 2022 07:27:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/28] target/arm: Add is_secure parameter to get_phys_addr_lpae Date: Mon, 10 Oct 2022 15:27:08 +0100 Message-Id: <20221010142730.502083-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665412991493100005 From: Richard Henderson Remove the use of regime_is_secure from get_phys_addr_lpae, using the new parameter instead. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20221001162318.153420-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7d763a58477..96ed8e13afc 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -16,8 +16,8 @@ =20 static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, - bool s1_is_el0, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) + bool is_secure, bool s1_is_el0, + GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) __attribute__((nonnull)); =20 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. = */ @@ -207,8 +207,8 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, GetPhysAddrResult s2 =3D {}; int ret; =20 - ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, f= alse, - &s2, fi); + ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, + *is_secure, false, &s2, fi); if (ret) { assert(fi->type !=3D ARMFault_None); fi->s2addr =3D addr; @@ -965,8 +965,8 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa6= 4, int level, */ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, - bool s1_is_el0, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) + bool is_secure, bool s1_is_el0, + GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) { ARMCPU *cpu =3D env_archcpu(env); /* Read an LPAE long-descriptor translation table. */ @@ -1183,7 +1183,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, * remain non-secure. We implement this by just ORing in the NSTable/NS * bits at each step. */ - tableattrs =3D regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); + tableattrs =3D is_secure ? 0 : (1 << 4); for (;;) { uint64_t descriptor; bool nstable; @@ -2337,7 +2337,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, memset(result, 0, sizeof(*result)); =20 ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, - is_el0, result, fi); + s2walk_secure, is_el0, result, fi); fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ @@ -2504,8 +2504,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, } =20 if (regime_using_lpae_format(env, mmu_idx)) { - return get_phys_addr_lpae(env, address, access_type, mmu_idx, fals= e, - result, fi); + return get_phys_addr_lpae(env, address, access_type, mmu_idx, + is_secure, false, result, fi); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, is_secure, result, fi); --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665412491; cv=none; d=zohomail.com; s=zohoarc; b=G/dcJZ7vfnyhzVXYwblP0ZJyjay4jQW7Hs9DIVsVceNuLlbgKBD9wWqrGBGhHL9h3SaK2RPtJD+J8Q2w9A6V8QIUc44HfRu5mzFDPJBfTqP1BbP0IObldLpaA8lIAJKpZqbdfB9vmnUrcfzYoMEca1AvFAY4bdSNHug3W6zujDE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665412491; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=d+uOzEPtiTSHwDyxaSMMYXFTDRv7DD1JfLQ5SIWNG1Y=; b=nO3MtW3agYjO7CcoQsTA1q6PyuKTb7EsDrsJvfU7mLM1CNBaUDtqiPTKcz/WKgWPJyy6cYFtCUC6fOCj0iXZIz47wrxqAn/JqhgWnK1DQJ1XM2U649SiD4bRfE1aIIK/KrDjpk8rWZT8KXFrki1bpmHRuhu+7UNfvjgRt72wi7g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665412491685806.6529699162784; Mon, 10 Oct 2022 07:34:51 -0700 (PDT) Received: from localhost ([::1]:50638 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohtrm-00060N-2l for importer@patchew.org; Mon, 10 Oct 2022 10:34:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55768) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtku-000689-PV for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:44 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:34742) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtks-0005Yg-70 for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:44 -0400 Received: by mail-wm1-x32f.google.com with SMTP id n35-20020a05600c502300b003b4924c6868so7246642wmr.1 for ; Mon, 10 Oct 2022 07:27:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=d+uOzEPtiTSHwDyxaSMMYXFTDRv7DD1JfLQ5SIWNG1Y=; b=EiaP5NxYkMJ0qLzXCKFD9y91xCzb4qsovwnjwbkuwJODufc6Xlh7w2gn9FS02kTIzN Yxut4O6WlLOF8LynTeZnjgNfp+AJrjZp2KuZdhiyQjXdaGsfK0P64WG5sEGqXvlCun+w Svuc1xTkzIBKqpgKmwF/dvc65E8DgvU0psFKO8r1sP1athzdJ0lwj2AyKAwrouBHLH3H surmIEseup4qM4mVJu0/cawPKh6jZ0MMrmY/AoHlcXLHAR2LHZBOSgvRrF8xsvufdFSs Vcmnp3w7aUFYWVtHmkYzbCCqkUw5wrhkcT1RORX8GkTaw9sQPGyIXMWNDxbpeLzbbjjv F99A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d+uOzEPtiTSHwDyxaSMMYXFTDRv7DD1JfLQ5SIWNG1Y=; b=O0Xg++xbDxC04e+k29mFBUhoBEVj88Zh2XBv/wvxV7bzy6H30mBk3Vd3LgYlUGmNkz b8YPDfRaNs/3Nbc0Zci83NS7XUKM2BvO7ACFoGXcL4PLsjd+QpWlxh48I5wBz3mw4TJh a/4n+f+M1oG2jvyC3deK3x1ldrvmG/7BO5Y8DifqqrGk/uTCXO3OhKg+LJ5Hx/x9mKUP hGohxooLa4Q/DS799de+HV3g1hBYVZ6RYfbLYWsYT9CR2a4sf5Uh3IYZrrZQDc/4+D+H Ye2VqnN6IviNxWt9cskNkk8KdzFbmRQsbatA1S8I2FtHwpbeaczpdIi7cxwZUdBDCYsM YfQg== X-Gm-Message-State: ACrzQf1hm2K9D/DpNBkJ6pftP4Y93EaZpVU1m01qaN2LCWsHIFixAyL7 NHExNsdUNfPSLtRVILX1wozIpPQ+lasMUg== X-Google-Smtp-Source: AMsMyM6lvJqv0VZfNZ+DVV0oSm0zngl8Hyylb6V5HhdeBLlJMp7KSdLzdWHq16e04gzrljAf2n3hsQ== X-Received: by 2002:a05:600c:a05:b0:3b9:cecc:9846 with SMTP id z5-20020a05600c0a0500b003b9cecc9846mr19809372wmp.3.1665412060206; Mon, 10 Oct 2022 07:27:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/28] target/arm: Fix S2 disabled check in S1_ptw_translate Date: Mon, 10 Oct 2022 15:27:09 +0100 Message-Id: <20221010142730.502083-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665412492754100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Pass the correct stage2 mmu_idx to regime_translation_disabled, which we computed afterward. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20221001162318.153420-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 96ed8e13afc..631d1e25f15 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -200,10 +200,10 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, hwaddr addr, bool *is_secure, ARMMMUFaultInfo *fi) { + ARMMMUIdx s2_mmu_idx =3D *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_S= tage2; + if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { - ARMMMUIdx s2_mmu_idx =3D *is_secure ? ARMMMUIdx_Stage2_S - : ARMMMUIdx_Stage2; + !regime_translation_disabled(env, s2_mmu_idx)) { GetPhysAddrResult s2 =3D {}; int ret; =20 --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665412683; cv=none; d=zohomail.com; s=zohoarc; b=So/HQWopcr/5iXzc3Ae5ztWuMlosXiBqcEQO88iR4d3QQxRhd07FR0PrrOQyd5Ok7Jm79Uog3oIe8zpFPl1R43NZ/z93ARfcYcOAVL+teitwXXjOPLoj7Wve2ZcwUfQb9Q6cw1Uoah+BXTRBMFcQkGf5m7gzOaSubC273NlJYrM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665412683; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=chejyLWzKm+amytX5VjNlCtg/brdV5o/nVcOeHFnjvk=; b=XPeNbGO9bf3fa+4R+s1/49rQ+hOg/eUQ6F6mSETHgPnYImhbitf3pTm5uHCcFfzSofD4KV5etDLxl6IgLS2n/b+tVlwTxU+tFAwDVY3XmqVqKJbSQowyLRCl35Uf7Usdt98YkqmPb2QHVWKwNxMDP1hkZkq41P85h12jd8UQ1jk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665412683834882.040596256063; Mon, 10 Oct 2022 07:38:03 -0700 (PDT) Received: from localhost ([::1]:57280 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohtus-0001Nq-OS for importer@patchew.org; Mon, 10 Oct 2022 10:38:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55770) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtkv-00069W-2h for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:45 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:40833) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtks-0005Yk-U4 for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:44 -0400 Received: by mail-wr1-x435.google.com with SMTP id w18so17308806wro.7 for ; Mon, 10 Oct 2022 07:27:42 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=chejyLWzKm+amytX5VjNlCtg/brdV5o/nVcOeHFnjvk=; b=mbrsbOmU9SkjUpXqqV/47K5N+87SfreWUQFMApH8wqsU5KcYXe09NuXatd4CXZlnTD LJGEALqAFAZcroWcDHXvthPxmDQS8cYkX8U+pXYYe+ZecyT9gG2QdJGpcRSFXpfmKBSm Qny6hwCAGiUhYVCf30qnPXZ5uBdXDAaO1/pM2uWrj49dROSLqeMiHWPIfFmVqq9FhmaV F10osci7CXK0u87QrZjEvknSX3v2ZGdR1x4e+cEPMJTFN17YMH5+ZNoHD/4TkYJP/2MW riGbOJigljRqJ6zQ1uUBWzNqTw5rFVUlTwwNf1RVd0k734wlGHNfNWvWeptyuAA6juVn jFmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=chejyLWzKm+amytX5VjNlCtg/brdV5o/nVcOeHFnjvk=; b=bUr/HDBywjsn9q8IdBKSK0PNhUqdhSXOBheeP4c+yhFddFQk7Mn8Txz0fXf+i38iVD a6nw2KrNl2w1HNOZ8Dv/P330934X9Q6JMhkDub8szcJ3OetMeDm4yPzqsWUBKsXuYf7x odD/PVbt8LBesBSti2UUFpKfVkkLkRvzU6iNeqLm7Z1rNMzeN9DB5C8At3NknwleXfF+ +VVtf10uIowf8u1h/67YyFgt4+odZsQDP/IyamNnb+a8psgYxZhfTHiiz2sIxo3mGbhR JuCaCSPBUj+/1sbmlebL2S0pug2l1ODSyju+KgC7fkF/6LsDIhCf//m8ufdVpHRj4URy TRIQ== X-Gm-Message-State: ACrzQf0aaXLkKUexTll3vMYAMri6MaF1m2yqGEL85CDxHkPlMBNbVcJr 2bqvcLJLaKrr1XahkWTN6963xbau2wodVA== X-Google-Smtp-Source: AMsMyM4EpnsBQW/JY/q+mYBijUFR6vBiC13iMeptjOGxiCZlui/Ka66dO0ilo4lsDZ9/89cC1K+tug== X-Received: by 2002:adf:f407:0:b0:22e:5848:f6b with SMTP id g7-20020adff407000000b0022e58480f6bmr11586883wro.46.1665412061217; Mon, 10 Oct 2022 07:27:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/28] target/arm: Add is_secure parameter to regime_translation_disabled Date: Mon, 10 Oct 2022 15:27:10 +0100 Message-Id: <20221010142730.502083-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665412686099100001 From: Richard Henderson Remove the use of regime_is_secure from regime_translation_disabled, using the new parameter instead. This fixes a bug in S1_ptw_translate and get_phys_addr where we had passed ARMMMUIdx_Stage2 and not ARMMMUIdx_Stage2_S to determine if Stage2 is disabled, affecting FEAT_SEL2. Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20221001162318.153420-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 631d1e25f15..d789807b086 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -131,12 +131,13 @@ static uint64_t regime_ttbr(CPUARMState *env, ARMMMUI= dx mmu_idx, int ttbrn) } =20 /* Return true if the specified stage of address translation is disabled */ -static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_id= x) +static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_id= x, + bool is_secure) { uint64_t hcr_el2; =20 if (arm_feature(env, ARM_FEATURE_M)) { - switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & + switch (env->v7m.mpu_ctrl[is_secure] & (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK= )) { case R_V7M_MPU_CTRL_ENABLE_MASK: /* Enabled, but not for HardFault and NMI */ @@ -163,7 +164,7 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx) =20 if (hcr_el2 & HCR_TGE) { /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ - if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) =3D= =3D 1) { + if (!is_secure && regime_el(env, mmu_idx) =3D=3D 1) { return true; } } @@ -203,7 +204,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, ARMMMUIdx s2_mmu_idx =3D *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_S= tage2; =20 if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, s2_mmu_idx)) { + !regime_translation_disabled(env, s2_mmu_idx, *is_secure)) { GetPhysAddrResult s2 =3D {}; int ret; =20 @@ -1357,7 +1358,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, ui= nt32_t address, uint32_t base; bool is_user =3D regime_is_user(env, mmu_idx); =20 - if (regime_translation_disabled(env, mmu_idx)) { + if (regime_translation_disabled(env, mmu_idx, is_secure)) { /* MPU disabled. */ result->phys =3D address; result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -1521,7 +1522,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, result->page_size =3D TARGET_PAGE_SIZE; result->prot =3D 0; =20 - if (regime_translation_disabled(env, mmu_idx) || + if (regime_translation_disabled(env, mmu_idx, secure) || m_is_ppb_region(env, address)) { /* * MPU disabled or M profile PPB access: use default memory map. @@ -1733,7 +1734,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, * are done in arm_v7m_load_vector(), which always does a direct * read using address_space_ldl(), rather than going via this function. */ - if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ + if (regime_translation_disabled(env, mmu_idx, secure)) { /* MPU disabl= ed */ hit =3D true; } else if (m_is_ppb_region(env, address)) { hit =3D true; @@ -2307,7 +2308,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, result, fi); =20 /* If S1 fails or S2 is disabled, return early. */ - if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2))= { + if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, + is_secure)) { return ret; } =20 @@ -2437,7 +2439,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, =20 /* Definitely a real MMU, not an MPU */ =20 - if (regime_translation_disabled(env, mmu_idx)) { + if (regime_translation_disabled(env, mmu_idx, is_secure)) { uint64_t hcr; uint8_t memattr; =20 --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665413262; cv=none; d=zohomail.com; s=zohoarc; b=T6IbhSS0BqssFV/GwwbFwvc8x2yEdmBqnhzrrx945j7j+BDSEbUKhnkHkVJmXOzgo2/pRxlClOt9JoaklTQALPo9iQgAswRL4hLD0wVe222PctiYTzglcwZDYskceC0E/ZpeVATESZkhoANrFERCdgtIY4hrCQtWRV5yY/qn5I4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665413262; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=U4bZaH9ewSTtKGJ2hCxNf/XLdmqRHOO4aZlMXbD0cQY=; b=GRWpXlXhPLlEjh06CeFa1CDCSAkKyCV7gYk8shnrI/HUM66/Z1v/31KFYjXuTR8uUvPTO7FxHrVPKfy4U05Ik+qTTtQskxFvapWs1f7sKbUvkHPlFQjstOUaCJmkV+4aUcb02pi323BQKH+dJm2+Uth1XJM8qb5SzFdPJ/AyEgU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665413262864783.9710846034516; Mon, 10 Oct 2022 07:47:42 -0700 (PDT) Received: from localhost ([::1]:35432 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohu4D-0006cr-GH for importer@patchew.org; Mon, 10 Oct 2022 10:47:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52956) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtkw-0006Dg-5F for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:46 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:45996) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtku-0005Yq-1F for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:45 -0400 Received: by mail-wm1-x332.google.com with SMTP id l16-20020a05600c4f1000b003c6c0d2a445so460947wmq.4 for ; Mon, 10 Oct 2022 07:27:43 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=U4bZaH9ewSTtKGJ2hCxNf/XLdmqRHOO4aZlMXbD0cQY=; b=GxVYy9sCyoGr8DOHU4jr7vQUSUEbfplVpoo16SMBWSuQ4j+f8cYTzEcKuQ1maR0AAs /NYySrY6EtyVgnrmZwnkjIfI3CH4CpByggzj3Yi7gx+qTrKcAO2nhGLxtJOQJgoEUbp5 PdaUqyEvOuYAU5dcaG1IwTimLGBcustxINrnBAm81V8RgRPOu1OgB5pes4shzX8e+7s0 5vWH220hlkulm6I+QfzhgBvt+Ack/9Hixw4ih1AFrrmtIu3z7Mtzkiw2Fr5G2ENZP8c2 1L6IWtSmGFBDR67DLL/0bh5oigZagKwvsxKpUqVImgqb3tYKvY0KyGpPjxlDy8275ZTJ ZvaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U4bZaH9ewSTtKGJ2hCxNf/XLdmqRHOO4aZlMXbD0cQY=; b=kV6N/2HvMoDuSWFrw7H+Ck9MjCH0et8z74G8JPjluaylfOG1gQUHGRRqOoo+YOwylK yHgZ1k1tmUTIhstegwNwcE0H4Zmsd6iVSXUWYpei31wYRC/qXvh1gjdGRkOL11t9B+G7 AJt7/gWszg1SGaMmnapHYDDZVzaoiTOpguBY1lZshaOKp77j22S6HwtPSOIxkE5ceESx 0H5RrBZCqc3k/9o9KTndgyWFIxlcATjYEkmblnBnVEgZV+4PQM9cFR8ygZODh4VY+sHT 8vhAOoYQVRhS0IPZFvaxPCjWN8IOobVcbTCQ0pYtcHtWwRckL/cUHYAKnfPw5wouvzqq 2T1w== X-Gm-Message-State: ACrzQf3bdSmb4I/Kd/dOIltTBEYU7PClaTZtwKAp6zDUd6+UMOC1lhAt xHExo1ad8EUFJibBUcyhx/KJcLzOh/YSSw== X-Google-Smtp-Source: AMsMyM4a+xBRoQ7ROsXMCd4VBluOhLr/f6oF1Ds2Jlt0aSlS/KfN6DL/BdMaKQKbSV3cS30Rcw+Gow== X-Received: by 2002:a05:600c:5114:b0:3b5:428:cf67 with SMTP id o20-20020a05600c511400b003b50428cf67mr20539446wms.80.1665412062233; Mon, 10 Oct 2022 07:27:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/28] target/arm: Split out get_phys_addr_with_secure Date: Mon, 10 Oct 2022 15:27:11 +0100 Message-Id: <20221010142730.502083-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665413263217100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Retain the existing get_phys_addr interface using the security state derived from mmu_idx. Move the kerneldoc comments to the header file where they belong. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20221001162318.153420-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 40 ++++++++++++++++++++++++++++++++++++++ target/arm/ptw.c | 44 ++++++++++++++---------------------------- 2 files changed, 55 insertions(+), 29 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 307a5965053..3524d11dc57 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1145,6 +1145,46 @@ typedef struct GetPhysAddrResult { ARMCacheAttrs cacheattrs; } GetPhysAddrResult; =20 +/** + * get_phys_addr_with_secure: get the physical address for a virtual addre= ss + * @env: CPUARMState + * @address: virtual address to get physical address for + * @access_type: 0 for read, 1 for write, 2 for execute + * @mmu_idx: MMU index indicating required translation regime + * @is_secure: security state for the access + * @result: set on translation success. + * @fi: set to fault info if the translation fails + * + * Find the physical address corresponding to the given virtual address, + * by doing a translation table walk on MMU based systems or using the + * MPU state on MPU based systems. + * + * Returns false if the translation was successful. Otherwise, phys_ptr, a= ttrs, + * prot and page_size may not be filled in, and the populated fsr value pr= ovides + * information on why the translation aborted, in the format of a + * DFSR/IFSR fault register, with the following caveats: + * * we honour the short vs long DFSR format differences. + * * the WnR bit is never set (the caller must do this). + * * for PSMAv5 based systems we don't bother to return a full FSR format + * value. + */ +bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, bool is_secure, + GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) + __attribute__((nonnull)); + +/** + * get_phys_addr: get the physical address for a virtual address + * @env: CPUARMState + * @address: virtual address to get physical address for + * @access_type: 0 for read, 1 for write, 2 for execute + * @mmu_idx: MMU index indicating required translation regime + * @result: set on translation success. + * @fi: set to fault info if the translation fails + * + * Similarly, but use the security regime of @mmu_idx. + */ bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index d789807b086..74dcb843fe2 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2260,35 +2260,12 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState= *env, return ret; } =20 -/** - * get_phys_addr - get the physical address for this virtual address - * - * Find the physical address corresponding to the given virtual address, - * by doing a translation table walk on MMU based systems or using the - * MPU state on MPU based systems. - * - * Returns false if the translation was successful. Otherwise, phys_ptr, a= ttrs, - * prot and page_size may not be filled in, and the populated fsr value pr= ovides - * information on why the translation aborted, in the format of a - * DFSR/IFSR fault register, with the following caveats: - * * we honour the short vs long DFSR format differences. - * * the WnR bit is never set (the caller must do this). - * * for PSMAv5 based systems we don't bother to return a full FSR format - * value. - * - * @env: CPUARMState - * @address: virtual address to get physical address for - * @access_type: 0 for read, 1 for write, 2 for execute - * @mmu_idx: MMU index indicating required translation regime - * @result: set on translation success. - * @fi: set to fault info if the translation fails - */ -bool get_phys_addr(CPUARMState *env, target_ulong address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, ARMMMUFaultInfo *fi) +bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_id= x, + bool is_secure, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) { ARMMMUIdx s1_mmu_idx =3D stage_1_mmu_idx(mmu_idx); - bool is_secure =3D regime_is_secure(env, mmu_idx); =20 if (mmu_idx !=3D s1_mmu_idx) { /* @@ -2304,8 +2281,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, ARMMMUIdx s2_mmu_idx; bool is_el0; =20 - ret =3D get_phys_addr(env, address, access_type, s1_mmu_idx, - result, fi); + ret =3D get_phys_addr_with_secure(env, address, access_type, + s1_mmu_idx, is_secure, result,= fi); =20 /* If S1 fails or S2 is disabled, return early. */ if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, @@ -2517,6 +2494,15 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, } } =20 +bool get_phys_addr(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) +{ + return get_phys_addr_with_secure(env, address, access_type, mmu_idx, + regime_is_secure(env, mmu_idx), + result, fi); +} + hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665412907; cv=none; d=zohomail.com; s=zohoarc; b=VKywjjyEer2fOuniSXfQ5wTs4VT8AdWjYTSmMETpphqjinEa7aRA46RNXQcZrLMjJRc8Az3ChuyWupoI2GvOda+0dS1ddoKa3iqjGosErq6nCe1qos1LKdG+KHq2uJS5jzyWpuYulfLwsBw+hOXw+1wcNLz4SqO/apPf5AuqXK4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665412907; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sCOloJHZeHe5fACLnqjx6IG4hS5rmNF8WAFU0jQEu+w=; b=MXhw2MzPR4VyH8ssrF1g6OMwKwvazqQTyzQuwjDgV6OZhndoNwI0ysL4nho0XGvznX8jKc+au5DErQPj7VfIYFMvNyLWqv+YL322HBwOpgdRdnEn5eMn/KW6BsisChczJ9PP047SHyyDX6Eq4/O/U8YCoJzE4XGos+GIN8ZpdZw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665412907102622.4276235914325; Mon, 10 Oct 2022 07:41:47 -0700 (PDT) Received: from localhost ([::1]:38394 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohtyS-0006nY-Nr for importer@patchew.org; Mon, 10 Oct 2022 10:41:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52958) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtkw-0006GE-PN for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:46 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:38835) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtkv-0005Z2-3X for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:46 -0400 Received: by mail-wm1-x32e.google.com with SMTP id r8-20020a1c4408000000b003c47d5fd475so3428281wma.3 for ; Mon, 10 Oct 2022 07:27:44 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=sCOloJHZeHe5fACLnqjx6IG4hS5rmNF8WAFU0jQEu+w=; b=auIbe8PW8r8nDIl7SZtwWVk8lk4xuXv1RKsC6JaP+w03HG3hF0xET8qfQQhrMZk7SV XV8NOuzYdY+G6oqhlx/6O0/vO4uyP27ZSFviMR5O7TpghjLQIvLOEqJ/V/hGZwtxNoWw 80Xceu8E6GlzDKPrDquW9fLdvliC2eof6zixDDyk4OcY32fHK0NuqB1/UqHnKagueLVe v8ph497s7LKRC7fDu/49nZz3T1XElxfqPi7c9sCFliNmpUeQJbubAHKQ1N3j0x2ubGJx 72xicsgzKXuoTCvdhPJlF8BVlZMY9gpHuxskGsAydB4umCz7OjykxtWaOAo4Ri0v1U/r xMFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sCOloJHZeHe5fACLnqjx6IG4hS5rmNF8WAFU0jQEu+w=; b=ZuI43QjafZj9zxqKauiSeSYthqx0Ju4Xw28Xm3csJH9xrbedpt+lYU7Deqnm5wvqrh JXGz6gCspQPRAQ0Xf0xS0xzqsH48rNPPlJX7i5v6tWyTbaj5X9WVA4U5EIFij8zZG0Qq poYtgs/ahyNqaeb6zUvspxEkrDSO0Ku5iVwphYJWMqeX0HXJh5Mc3hZvtPOUHPWwE5Nr Rbiv+54mtO6dKxqC3H8zmI8sf/Ff0DsWGnGmwyNIHGBBpoi91VYDK2BVtvTTMvwTpapq uCu1542Pdqw7S4cxA6HEfXHWgyUbpO+z1pBdqaRigElri/Pa6WD1M5oHAiXY6UmYANUy DZrw== X-Gm-Message-State: ACrzQf34Q1tqM+Pp3ShMt6bHQrWtP/9KjTEUOFB2cJrbqFl6617Mf56P b0kW7JE/jF3ZS7mb4PU/rnKodPVS6LtMew== X-Google-Smtp-Source: AMsMyM67zG2IX4jptFXnZfPr5Xc6KY3FCPsjiq6H9mlyjuhN59DmFHT0apE7f1B/YRRxiA/6McjTAQ== X-Received: by 2002:a7b:c5c2:0:b0:3c4:fd96:fb68 with SMTP id n2-20020a7bc5c2000000b003c4fd96fb68mr7556742wmk.36.1665412063194; Mon, 10 Oct 2022 07:27:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/28] target/arm: Add is_secure parameter to v7m_read_half_insn Date: Mon, 10 Oct 2022 15:27:12 +0100 Message-Id: <20221010142730.502083-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665412908695100001 From: Richard Henderson Remove the use of regime_is_secure from v7m_read_half_insn, using the new parameter instead. As it happens, both callers pass true, propagated from the argument to arm_v7m_mmu_idx_for_secstate which created the mmu_idx argument, but that is a detail of v7m_handle_execute_nsc we need not expose to the callee. Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20221001162318.153420-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/m_helper.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 5ee4ee15b36..203ba411f64 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -1981,7 +1981,7 @@ static bool do_v7m_function_return(ARMCPU *cpu) return true; } =20 -static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, +static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure, uint32_t addr, uint16_t *insn) { /* @@ -2003,8 +2003,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, ARMMMUFaultInfo fi =3D {}; MemTxResult txres; =20 - v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, - regime_is_secure(env, mmu_idx), &sattrs); + v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, secure, &sattr= s); if (!sattrs.nsc || sattrs.ns) { /* * This must be the second half of the insn, and it straddles a @@ -2109,7 +2108,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) /* We want to do the MPU lookup as secure; work out what mmu_idx that = is */ mmu_idx =3D arm_v7m_mmu_idx_for_secstate(env, true); =20 - if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) { + if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15], &insn)) { return false; } =20 @@ -2125,7 +2124,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) goto gen_invep; } =20 - if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) { + if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15] + 2, &insn))= { return false; } =20 --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665412989; cv=none; d=zohomail.com; s=zohoarc; b=ZolsgQifUD+rS7i/FMTNmc2HygZ7UjYH3rH9q9dWtU8WoNJgPWPeOJw3qFbju4kcyhjsr7vkloTtEIOS0sBnqBn3pzX205ouam9CX58m0blDGmDw22Qii7gSKpa/EsvsvGEVbAJy2ep18cW51YCG1KAdQ0A2xbrSEumRG0R6sto= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665412989; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7cxLu4UXCoYBUifAO+tW7g0KPLs2vmro0DH/gpL87Mc=; b=R8LKh4KgGonQIol4QCrPGKA/qsNX1F1lgWjoM6+kG1IhVqpp/frcDE2Jt3CoufV3/8tSDr0PQdGJhCT/a/v/+wUlXDwA1iaQndlGsHF5FMi0KAtvdVharzsFPryFrD4anNQsK8/v7d04fLeYhlNMf4Yfa0D8h0JtY8jTYq3aCUQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665412989095110.02940672858062; Mon, 10 Oct 2022 07:43:09 -0700 (PDT) Received: from localhost ([::1]:55160 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohtzm-0000os-OK for importer@patchew.org; Mon, 10 Oct 2022 10:43:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52964) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtl1-0006Nk-8l for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:53 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:37779) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtkv-0005ZE-UH for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:51 -0400 Received: by mail-wm1-x334.google.com with SMTP id bi26-20020a05600c3d9a00b003c1e11f54d2so5421096wmb.2 for ; Mon, 10 Oct 2022 07:27:45 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7cxLu4UXCoYBUifAO+tW7g0KPLs2vmro0DH/gpL87Mc=; b=wo4GKH7wBkW6zy0LLxJyaIJE5iTs1NiQkWiQG/3GVz8VrKIThEtcBZM8MoKmuVCx0Z UAX94RJs7xS7DkqL94G7Y9NkfudGBF/zX+zow/59huOzqy8BvyRIi2i0PnaqLZmC017/ Yb3v5QndEtIDsnnG5FRR7CUvs8sYcTfm1y5+zcTI1sH15LP3vd9BZM4+dCq5M8N23B/j lq9W4pKzHZrLud+4AcJ0vXKoFc/i9mjNlEB2air5p+KNk+8glAhNwYF9ynpX+SkK9fKE snw0Bnu1/U6ZcYh71FgJ8NCjOu4PJzHEFq95tWgwX70nBOAxF6+gd9YrldDPT/RU43eY 4sFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7cxLu4UXCoYBUifAO+tW7g0KPLs2vmro0DH/gpL87Mc=; b=M2t49csZqWEerzf6+U22G9XT2rzAiS719DMgcvMqrtgcoJsDqMKTwZRDwJD6vB47gD k1+hB9eB4H3QM2a7esbwd1AYZ0HH9rNhmpRbCs5B31Pb8F/xCiLQh2N6k5BiAjjCLxgp 5MdoeQtnu7e+b54kUsHfZ3zS4YZu5caO9wWn9xBBNcG7Flpn/CzNpwp8JKiiIcFPm8nr dhx9h5W0eth+SODD3E2lSYK7Frf0vhv/Vdr5QvR150kgh63g3vxn7i+tAL09FdoxVGDt 1znGWOjEu0uuIWfKjultd3piLN3KnNf56HIOhZwwV3euFG/JVZSiU/MqXDy0N/8SVSBt hFEg== X-Gm-Message-State: ACrzQf3NApplZgKuwCUwjEH4+PLxr5evfMcUNTPc/tNqQB01c++axtd8 x+gwmADmP+eu07YaQ676ScjExRriUIEFYw== X-Google-Smtp-Source: AMsMyM7g5T3Fb6GVUWfoBX18AVk0J9lMI5kqg9Af45dHxoAWwqk6HpBSOZuDmkjQLa36G5e2FJ3Esg== X-Received: by 2002:a05:600c:1c16:b0:3c6:bb05:702c with SMTP id j22-20020a05600c1c1600b003c6bb05702cmr2519110wms.203.1665412064363; Mon, 10 Oct 2022 07:27:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/28] target/arm: Add TBFLAG_M32.SECURE Date: Mon, 10 Oct 2022 15:27:13 +0100 Message-Id: <20221010142730.502083-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665412989495100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Remove the use of regime_is_secure from arm_tr_init_disas_context. Instead, provide the value of v8m_secure directly from tb_flags. Rather than use regime_is_secure, use the env->v7m.secure directly, as per arm_mmu_idx_el. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20221001162318.153420-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/helper.c | 4 ++++ target/arm/translate.c | 3 +-- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 68d99565ac4..a085c172974 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3203,6 +3203,8 @@ FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* No= t cached. */ FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ +/* Set if in secure mode */ +FIELD(TBFLAG_M32, SECURE, 6, 1) =20 /* * Bit usage when in AArch64 state diff --git a/target/arm/helper.c b/target/arm/helper.c index c08a7b35a04..8d82c147623 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10948,6 +10948,10 @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMStat= e *env, int fp_el, DP_TBFLAG_M32(flags, STACKCHECK, 1); } =20 + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) { + DP_TBFLAG_M32(flags, SECURE, 1); + } + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 5aaccbbf71d..ac647e02628 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9351,8 +9351,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) dc->vfp_enabled =3D 1; dc->be_data =3D MO_TE; dc->v7m_handler_mode =3D EX_TBFLAG_M32(tb_flags, HANDLER); - dc->v8m_secure =3D arm_feature(env, ARM_FEATURE_M_SECURITY) && - regime_is_secure(env, dc->mmu_idx); + dc->v8m_secure =3D EX_TBFLAG_M32(tb_flags, SECURE); dc->v8m_stackcheck =3D EX_TBFLAG_M32(tb_flags, STACKCHECK); dc->v8m_fpccr_s_wrong =3D EX_TBFLAG_M32(tb_flags, FPCCR_S_WRONG); dc->v7m_new_fp_ctxt_needed =3D --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665413605; cv=none; d=zohomail.com; s=zohoarc; b=YnXI23ke2yFJFxGmPm7+98DL58K5lfWiAsAKGz88BP1U8M/+RE5ePznCGe3HQO0t0VtsLfZgJdMvmKHhbt8U7IKDnRKz7UREaE42fQfwsNG01RjHgVtNQYNpticRlIlvMHsOWIYzjgDE1siUm3JuwpeO1spM4cZ0mDK3iulDFO8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665413605; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Fje2xIcK7TdFPjWxKpgsq3uECMq4Tvvs5Jp3UhFaNNE=; b=ebNSZfYnLqc1ssSJjfMa0WdlxMS5qoj+tkP0RyioPqvrKrchQkfqwZ+ChGLfWbOy/MIBeZ42AqrFvQoX4fbdm4Hrg9M1xZoHVmY9lCf9ThvxEWJsldPCp6dbT/ru1BS+6B7EMuFEx+G0Rm7HHqm/drqHTWjzbG+SsZbuRHSTTrM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665413605294551.053926016677; Mon, 10 Oct 2022 07:53:25 -0700 (PDT) Received: from localhost ([::1]:35820 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohu9i-0004NG-VB for importer@patchew.org; Mon, 10 Oct 2022 10:53:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52960) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtky-0006Kf-GL for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:48 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:53061) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtkw-0005ZV-R5 for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:48 -0400 Received: by mail-wm1-x332.google.com with SMTP id l8so6952230wmi.2 for ; Mon, 10 Oct 2022 07:27:46 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Fje2xIcK7TdFPjWxKpgsq3uECMq4Tvvs5Jp3UhFaNNE=; b=CBEZS18lFBiLbETZHK0XzagEXVp/KMG9AMDBRgfLQBBOLYDGAeyRo9mq895ALkDmv0 jX1nsm4hVBp9yLWqURT3dnXXEeb/Jj60beEVgazX/XTMeHKWgt/FAz0NYXu+MAdpRkLX 9tP4rZeYXjy9D5stuWtSmIO6eVuqm7b00mV6tsCu634dIM1Ub9GJ3yEjsXZXPksdFQMH pzIlrRWDp2ApWUJ/xnupLHfrap+8giqUSG2C1LBM3upgSnXIOx9C57lqvE/mzzKauUl6 tY4vuY1TzdbrfTYw4z9RIwMiMjOfkfExgYmVMisSEJcCRyCprIeXZDFil6i4CFI72B2f poiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Fje2xIcK7TdFPjWxKpgsq3uECMq4Tvvs5Jp3UhFaNNE=; b=foiZan1huvimSWSXiemJLOAAo32CwaBBBLklwCz321sp4gHMYbiumy2O8ycPnr9Rn8 iqWn0LIXACLGFt2l5kj2F1nFD9kazrG3FImiUczbQOFnr0vF6F2LqpIFMZLsiElzc/gW K3Jz8hGU3PT3RuAvQCabzXPM6Gmls45XnPdlVa5rR1bKcx1WjLNIRH8laE/XHhHrAvrc i62rdDeo4SQGR+hoT4635iVOxDoQras18QkdFOTCj6VnnpQetPX0Xb+SYC2Qsk950Khn 0nFahu24JU1waykUdJuk3oaZqqoZGKzMB93i+HITCLsV9dEAfM0qxcYw2oNzfmZq6Ffy dSkg== X-Gm-Message-State: ACrzQf0XRVlphyDKlkngSrM/FycRa3Csk34e91eFPNYvfBUUTcNMzzx5 cslvSGfhOGo87v+q6aRcxvAafXB2YRJmaA== X-Google-Smtp-Source: AMsMyM4Np6whpQJaZIJi99RetL2cQV4h3kIoTa7gEAT9AdBcILzcWJg2fH/NLhNsTz1lmc32Lg/HUA== X-Received: by 2002:a05:600c:1989:b0:3b4:b6b6:737 with SMTP id t9-20020a05600c198900b003b4b6b60737mr13008560wmq.79.1665412065348; Mon, 10 Oct 2022 07:27:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/28] target/arm: Merge regime_is_secure into get_phys_addr Date: Mon, 10 Oct 2022 15:27:14 +0100 Message-Id: <20221010142730.502083-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665413606534100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is the last use of regime_is_secure; remove it entirely before changing the layout of ARMMMUIdx. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20221001162318.153420-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 42 ---------------------------------------- target/arm/ptw.c | 44 ++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 42 insertions(+), 44 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 3524d11dc57..14428730d44 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -670,48 +670,6 @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_i= dx) } } =20 -/* Return true if this address translation regime is secure */ -static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_E10_0: - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_E20_0: - case ARMMMUIdx_E20_2: - case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_Stage1_E1: - case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_E2: - case ARMMMUIdx_Stage2: - case ARMMMUIdx_MPrivNegPri: - case ARMMMUIdx_MUserNegPri: - case ARMMMUIdx_MPriv: - case ARMMMUIdx_MUser: - return false; - case ARMMMUIdx_SE3: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: - case ARMMMUIdx_Stage1_SE0: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: - case ARMMMUIdx_SE2: - case ARMMMUIdx_Stage2_S: - case ARMMMUIdx_MSPrivNegPri: - case ARMMMUIdx_MSUserNegPri: - case ARMMMUIdx_MSPriv: - case ARMMMUIdx_MSUser: - return true; - default: - g_assert_not_reached(); - } -} - static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 74dcb843fe2..55e8f33c508 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2498,9 +2498,49 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, MMUAccessType access_type, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { + bool is_secure; + + switch (mmu_idx) { + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: + case ARMMMUIdx_E2: + case ARMMMUIdx_Stage2: + case ARMMMUIdx_MPrivNegPri: + case ARMMMUIdx_MUserNegPri: + case ARMMMUIdx_MPriv: + case ARMMMUIdx_MUser: + is_secure =3D false; + break; + case ARMMMUIdx_SE3: + case ARMMMUIdx_SE10_0: + case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: + case ARMMMUIdx_SE20_0: + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: + case ARMMMUIdx_Stage1_SE0: + case ARMMMUIdx_Stage1_SE1: + case ARMMMUIdx_Stage1_SE1_PAN: + case ARMMMUIdx_SE2: + case ARMMMUIdx_Stage2_S: + case ARMMMUIdx_MSPrivNegPri: + case ARMMMUIdx_MSUserNegPri: + case ARMMMUIdx_MSPriv: + case ARMMMUIdx_MSUser: + is_secure =3D true; + break; + default: + g_assert_not_reached(); + } return get_phys_addr_with_secure(env, address, access_type, mmu_idx, - regime_is_secure(env, mmu_idx), - result, fi); + is_secure, result, fi); } =20 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2Cbe2RL9yMwjYDxnJ88DM/XvOfa2sAnKZm5Pr+E4U18=; b=I8AO2BQlGi0OFo2JbvQC05h1uDBvy1KJkfrLsqU61mW9L8CfUsboHqtDEUTDWtFYAY 5UZdOZU0jkixWiW2CmOnYjkAnC8RcixZJVQY/VVlgVvsqE+iJQLQY356MHDauGDz0Vp/ XSKkUU8ntXKUezIM911+uhVusEXxxs/76Eo6vwtRHTI4t9htPt5r8wTHlF7AH5zCBomy hd/3LiSFg3AEopbnBGT600GN34IEwYdLMBMMbjU7ulEfrlxr72b1Dtnvavm9Ju3k7t04 r/v6yPaS5/5AGvuGHxXakrwjrCh5+kqbSwkO5tEQc5TTXq0ecifsqwYwU0XgNuLYCYPW Q74g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2Cbe2RL9yMwjYDxnJ88DM/XvOfa2sAnKZm5Pr+E4U18=; b=at8o/sNQg3GfYXYkj1vbp2pmf1lQNW+JfCN+4PE0b1IdazWQC+KQep9Io2DZ3QDknh SqPM4QXklguEbFn8EGkfbMqynArvnDVyCTyuwpmyG5tzLEYS5rS3Fs7wCh5rHu12Fykp xicsh4eo5yb13swpM+EpZ4XxOEyix83cp5U2EdaDFPHxUIPKdbkHwwosAJh8pNscda2X WjkUYoxRA2TXwbKMF9bM04WQRGLtLgGpFmCVqxLGt7DTnehuup7CUvSiOizgEqBUj0Sq sL0fUoVN/KZ3+vRAnBWLK7EwRN7NLITzvctlw55RHsORqtf4i7bYhX9OauBSxLJ4pgAM WOTw== X-Gm-Message-State: ACrzQf0QKPm63DWeMU9woS6m7eJ6yFeEGoVrV1T1ghn+sTd0aaQcZZAA 5A99jKTbUvEyI13lLV2Z10OO7qsTL9ExNg== X-Google-Smtp-Source: AMsMyM542VePV3X48R53planE2U2xEg/uUkw9Gb/L0dcvpNlddFace0jNlz72pCeiBK67CsNt58hEQ== X-Received: by 2002:a7b:c455:0:b0:3c6:bd0e:f9b0 with SMTP id l21-20020a7bc455000000b003c6bd0ef9b0mr2272212wmi.21.1665412066330; Mon, 10 Oct 2022 07:27:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/28] target/arm: Add is_secure parameter to do_ats_write Date: Mon, 10 Oct 2022 15:27:15 +0100 Message-Id: <20221010142730.502083-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665413239061100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use get_phys_addr_with_secure directly. For a-profile, this is the one place where the value of is_secure may not equal arm_is_secure(env). Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20221001162318.153420-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8d82c147623..fd4663a9467 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3191,7 +3191,8 @@ static CPAccessResult ats_access(CPUARMState *env, co= nst ARMCPRegInfo *ri, =20 #ifdef CONFIG_TCG static uint64_t do_ats_write(CPUARMState *env, uint64_t value, - MMUAccessType access_type, ARMMMUIdx mmu_idx) + MMUAccessType access_type, ARMMMUIdx mmu_idx, + bool is_secure) { bool ret; uint64_t par64; @@ -3199,7 +3200,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, ARMMMUFaultInfo fi =3D {}; GetPhysAddrResult res =3D {}; =20 - ret =3D get_phys_addr(env, value, access_type, mmu_idx, &res, &fi); + ret =3D get_phys_addr_with_secure(env, value, access_type, mmu_idx, + is_secure, &res, &fi); =20 /* * ATS operations only do S1 or S1+S2 translations, so we never @@ -3371,6 +3373,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) switch (el) { case 3: mmu_idx =3D ARMMMUIdx_SE3; + secure =3D true; break; case 2: g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ @@ -3392,6 +3395,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) switch (el) { case 3: mmu_idx =3D ARMMMUIdx_SE10_0; + secure =3D true; break; case 2: g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ @@ -3407,16 +3411,18 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) case 4: /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ mmu_idx =3D ARMMMUIdx_E10_1; + secure =3D false; break; case 6: /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ mmu_idx =3D ARMMMUIdx_E10_0; + secure =3D false; break; default: g_assert_not_reached(); } =20 - par64 =3D do_ats_write(env, value, access_type, mmu_idx); + par64 =3D do_ats_write(env, value, access_type, mmu_idx, secure); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); #else @@ -3432,7 +3438,8 @@ static void ats1h_write(CPUARMState *env, const ARMCP= RegInfo *ri, MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; uint64_t par64; =20 - par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2); + /* There is no SecureEL2 for AArch32. */ + par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2, false); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); #else @@ -3475,6 +3482,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx =3D ARMMMUIdx_SE3; + secure =3D true; break; default: g_assert_not_reached(); @@ -3493,7 +3501,8 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, g_assert_not_reached(); } =20 - env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, mmu_idx); + env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, + mmu_idx, secure); #else /* Handled by hardware accelerator. */ g_assert_not_reached(); --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665412515; cv=none; d=zohomail.com; s=zohoarc; b=ZfXnJbGtzEVGbm5Fvj7aL15J44uEUsNGOhc5K0PIDZLwg5JdzD9qMjUudHY3UsrotX3bshtZRXoQib3JMv5HBGspxovxhZsTg6O1ldhwj/YN8upzHAZrWmVW8ooUe67k0k1EB+eLaJ85/3JxvEVtAYn/qZXnV2uyiFEtPtfMoZ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665412515; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8KN39KxuuUpoFwsZlwa3jHRbr69AfXnER2za+6zeO64=; b=fvQs3CMAA+qYQI4i4kBBWodFYnJ3RZoqCKA+X+d+ttc5ywVa7PrEG1BoB0psXdB/gBI0oNfutNXeLAwufYheijLDzCdAq8KzAspwwA/NtWY0a28r7FLCkuSnqlpmCQGYp1hJwW2A1hy4qZLC7O1DhNYacpKTJH+Cyq+mqQSWkFo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665412515056212.7964300571747; Mon, 10 Oct 2022 07:35:15 -0700 (PDT) Received: from localhost ([::1]:50640 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohts9-00066l-IC for importer@patchew.org; Mon, 10 Oct 2022 10:35:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52968) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtl1-0006Nm-L9 for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:53 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:40833) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtky-0005Yk-RI for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:51 -0400 Received: by mail-wr1-x435.google.com with SMTP id w18so17309359wro.7 for ; Mon, 10 Oct 2022 07:27:48 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8KN39KxuuUpoFwsZlwa3jHRbr69AfXnER2za+6zeO64=; b=Ujwz74+5iRRJT2Zor8RypET98yHJRnwJ2rcbqU++deAkaWQigt+7dJvDMppiQn1Fxz Vs8upwPWZ59ArJfc314F+erlkeWo4kq2MdEs6tEAT6GOC7cCEeSewkSIoiw4/OVYZebu wCn7FBrU8tfzZIFXHosyb+laRpomlDSaOE8GepAVcPaBAAnTJIt3xt01sEGWybpzIIaI XsW7iNYvQcNI59r1rP5ijGB3Zvhviw2p13IWT1U6xf/orJJbWf1lmFaYH/0rWlmMkSZZ O+TXUgfxmk976qGYf030fW3SVlpC+iYupWUohskf8aK6J4pVbpr1T4oKlm0qYyTXULRf 4Mzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8KN39KxuuUpoFwsZlwa3jHRbr69AfXnER2za+6zeO64=; b=38UiZQAqeUJ1djok68cGjcMOjzqpTnbwvfGEViJdBewoaBJYgiM+DaIPdkrvzV0qrK bfSPPLM3aQrk9IYOx/LiE9s78Pbc6rd8Kke1igIG6hsBY3DNaC9TBO7pZ5BNWmIyDCMo +PXMQvW6aH/f6mz1AA8QUnlKizmQaM/aN4r7V2TNgxjiw3a3ceoSS7W7meVZ+3k9BJRx 0yDmHqQ4e4RiV1qvutiPvkg6lVxp+iEPWG5z51q2aIRtiQXFfRetrjwwk5pv6ZBi9A1D ToS2nalkps2bZddQmV02hfIGSgsk/KtHzuIpxi/fZtsu5nHjFnfrxsPexw2ylnYJn80D KUFA== X-Gm-Message-State: ACrzQf0EIB80aMtcG00Oq5EBgcx6yoX5u3BhCtSxm2IYeWAZHrcvvy5N TGMDlV6r8w2QzyWisgiD9NC+Xbz8VMZHdg== X-Google-Smtp-Source: AMsMyM7gPq0kjyq+N50HCL5wm49EDUvsvZlFPtgpv8FkMzvBoS35y39ggePPeR8tlTNBcv5mDZ6bVQ== X-Received: by 2002:a5d:6906:0:b0:22c:d6d5:6322 with SMTP id t6-20020a5d6906000000b0022cd6d56322mr11951620wru.355.1665412067708; Mon, 10 Oct 2022 07:27:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/28] target/arm: Fold secure and non-secure a-profile mmu indexes Date: Mon, 10 Oct 2022 15:27:16 +0100 Message-Id: <20221010142730.502083-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665412516875100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson For a-profile aarch64, which does not bank system registers, it takes quite a lot of code to switch between security states. In the process, registers such as TCR_EL{1,2} must be swapped, which in itself requires the flushing of softmmu tlbs. Therefore it doesn't buy us anything to separate tlbs by security state. Retain the distinction between Stage2 and Stage2_S. This will be important as we implement FEAT_RME, and do not wish to add a third set of mmu indexes for Realm state. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20221001162318.153420-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 72 +++++++------------ target/arm/internals.h | 31 +------- target/arm/helper.c | 144 +++++++++++++------------------------ target/arm/ptw.c | 25 ++----- target/arm/translate-a64.c | 8 --- target/arm/translate.c | 6 +- 7 files changed, 85 insertions(+), 203 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 68ffb124278..08681828ac4 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -32,6 +32,6 @@ # define TARGET_PAGE_BITS_MIN 10 #endif =20 -#define NB_MMU_MODES 15 +#define NB_MMU_MODES 8 =20 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a085c172974..53f4c236e1f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2884,26 +2884,27 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_s= ync); * table over and over. * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access * Never (PAN) bit within PSTATE. + * 7. we fold together the secure and non-secure regimes for A-profile, + * because there are no banked system registers for aarch64, so the + * process of switching between secure and non-secure is + * already heavyweight. * * This gives us the following list of cases: * - * NS EL0 EL1&0 stage 1+2 (aka NS PL0) - * NS EL1 EL1&0 stage 1+2 (aka NS PL1) - * NS EL1 EL1&0 stage 1+2 +PAN - * NS EL0 EL2&0 - * NS EL2 EL2&0 - * NS EL2 EL2&0 +PAN - * NS EL2 (aka NS PL2) - * S EL0 EL1&0 (aka S PL0) - * S EL1 EL1&0 (not used if EL3 is 32 bit) - * S EL1 EL1&0 +PAN - * S EL3 (aka S PL1) + * EL0 EL1&0 stage 1+2 (aka NS PL0) + * EL1 EL1&0 stage 1+2 (aka NS PL1) + * EL1 EL1&0 stage 1+2 +PAN + * EL0 EL2&0 + * EL2 EL2&0 + * EL2 EL2&0 +PAN + * EL2 (aka NS PL2) + * EL3 (aka S PL1) * - * for a total of 11 different mmu_idx. + * for a total of 8 different mmu_idx. * * R profile CPUs have an MPU, but can use the same set of MMU indexes - * as A profile. They only need to distinguish NS EL0 and NS EL1 (and - * NS EL2 if we ever model a Cortex-R52). + * as A profile. They only need to distinguish EL0 and EL1 (and + * EL2 if we ever model a Cortex-R52). * * M profile CPUs are rather different as they do not have a true MMU. * They have the following different MMU indexes: @@ -2942,9 +2943,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_syn= c); #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ #define ARM_MMU_IDX_M 0x40 /* M profile */ =20 -/* Meanings of the bits for A profile mmu idx values */ -#define ARM_MMU_IDX_A_NS 0x8 - /* Meanings of the bits for M profile mmu idx values */ #define ARM_MMU_IDX_M_PRIV 0x1 #define ARM_MMU_IDX_M_NEGPRI 0x2 @@ -2958,22 +2956,14 @@ typedef enum ARMMMUIdx { /* * A-profile. */ - ARMMMUIdx_SE10_0 =3D 0 | ARM_MMU_IDX_A, - ARMMMUIdx_SE20_0 =3D 1 | ARM_MMU_IDX_A, - ARMMMUIdx_SE10_1 =3D 2 | ARM_MMU_IDX_A, - ARMMMUIdx_SE20_2 =3D 3 | ARM_MMU_IDX_A, - ARMMMUIdx_SE10_1_PAN =3D 4 | ARM_MMU_IDX_A, - ARMMMUIdx_SE20_2_PAN =3D 5 | ARM_MMU_IDX_A, - ARMMMUIdx_SE2 =3D 6 | ARM_MMU_IDX_A, - ARMMMUIdx_SE3 =3D 7 | ARM_MMU_IDX_A, - - ARMMMUIdx_E10_0 =3D ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E20_0 =3D ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E10_1 =3D ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E20_2 =3D ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E10_1_PAN =3D ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E20_2_PAN =3D ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E2 =3D ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS, + ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_0 =3D 1 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1 =3D 2 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2 =3D 3 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1_PAN =3D 4 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2_PAN =3D 5 | ARM_MMU_IDX_A, + ARMMMUIdx_E2 =3D 6 | ARM_MMU_IDX_A, + ARMMMUIdx_E3 =3D 7 | ARM_MMU_IDX_A, =20 /* * These are not allocated TLBs and are used only for AT system @@ -2982,9 +2972,6 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1_PAN =3D 2 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage1_SE0 =3D 3 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage1_SE1 =3D 4 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage1_SE1_PAN =3D 5 | ARM_MMU_IDX_NOTLB, /* * Not allocated a TLB: used only for second stage of an S12 page * table walk, or for descriptor loads during first stage of an S1 @@ -2992,8 +2979,8 @@ typedef enum ARMMMUIdx { * then various TLB flush insns which currently are no-ops or flush * only stage 1 MMU indexes will need to change to flush stage 2. */ - ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage2_S =3D 7 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage2 =3D 3 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage2_S =3D 4 | ARM_MMU_IDX_NOTLB, =20 /* * M-profile. @@ -3023,14 +3010,7 @@ typedef enum ARMMMUIdxBit { TO_CORE_BIT(E2), TO_CORE_BIT(E20_2), TO_CORE_BIT(E20_2_PAN), - TO_CORE_BIT(SE10_0), - TO_CORE_BIT(SE20_0), - TO_CORE_BIT(SE10_1), - TO_CORE_BIT(SE20_2), - TO_CORE_BIT(SE10_1_PAN), - TO_CORE_BIT(SE20_2_PAN), - TO_CORE_BIT(SE2), - TO_CORE_BIT(SE3), + TO_CORE_BIT(E3), =20 TO_CORE_BIT(MUser), TO_CORE_BIT(MPriv), diff --git a/target/arm/internals.h b/target/arm/internals.h index 14428730d44..b509d708514 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -649,21 +649,12 @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_= idx) case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_Stage1_SE0: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: return true; default: return false; @@ -674,11 +665,8 @@ static inline bool regime_is_pan(CPUARMState *env, ARM= MMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_Stage1_SE1_PAN: case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE10_1_PAN: - case ARMMMUIdx_SE20_2_PAN: return true; default: return false; @@ -689,30 +677,20 @@ static inline bool regime_is_pan(CPUARMState *env, AR= MMMUIdx mmu_idx) static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_Stage2: case ARMMMUIdx_Stage2_S: - case ARMMMUIdx_SE2: case ARMMMUIdx_E2: return 2; - case ARMMMUIdx_SE3: + case ARMMMUIdx_E3: return 3; - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_Stage1_SE0: - return arm_el_is_aa64(env, 3) ? 1 : 3; - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: + case ARMMMUIdx_E10_0: case ARMMMUIdx_Stage1_E0: + return arm_el_is_aa64(env, 3) || !arm_is_secure_below_el3(env) ? 1= : 3; case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: - case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_MPrivNegPri: @@ -954,9 +932,6 @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx= mmu_idx) case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_Stage1_SE0: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: return true; default: return false; diff --git a/target/arm/helper.c b/target/arm/helper.c index fd4663a9467..b1b8725628b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1754,6 +1754,7 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) /* Begin with base v8.0 state. */ uint64_t valid_mask =3D 0x3fff; ARMCPU *cpu =3D env_archcpu(env); + uint64_t changed; =20 /* * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset alw= ays @@ -1816,7 +1817,22 @@ static void scr_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) =20 /* Clear all-context RES0 bits. */ value &=3D valid_mask; - raw_write(env, ri, value); + changed =3D env->cp15.scr_el3 ^ value; + env->cp15.scr_el3 =3D value; + + /* + * If SCR_EL3.NS changes, i.e. arm_is_secure_below_el3, then + * we must invalidate all TLBs below EL3. + */ + if (changed & SCR_NS) { + tlb_flush_by_mmuidx(env_cpu(env), (ARMMMUIdxBit_E10_0 | + ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E2)); + } } =20 static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri) @@ -2647,9 +2663,6 @@ static int gt_phys_redir_timeridx(CPUARMState *env) case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: return GTIMER_HYP; default: return GTIMER_PHYS; @@ -2662,9 +2675,6 @@ static int gt_virt_redir_timeridx(CPUARMState *env) case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: return GTIMER_HYPVIRT; default: return GTIMER_VIRT; @@ -3372,7 +3382,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP= */ switch (el) { case 3: - mmu_idx =3D ARMMMUIdx_SE3; + mmu_idx =3D ARMMMUIdx_E3; secure =3D true; break; case 2: @@ -3380,10 +3390,9 @@ static void ats_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) /* fall through */ case 1: if (ri->crm =3D=3D 9 && (env->uncached_cpsr & CPSR_PAN)) { - mmu_idx =3D (secure ? ARMMMUIdx_Stage1_SE1_PAN - : ARMMMUIdx_Stage1_E1_PAN); + mmu_idx =3D ARMMMUIdx_Stage1_E1_PAN; } else { - mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stag= e1_E1; + mmu_idx =3D ARMMMUIdx_Stage1_E1; } break; default: @@ -3394,7 +3403,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ switch (el) { case 3: - mmu_idx =3D ARMMMUIdx_SE10_0; + mmu_idx =3D ARMMMUIdx_E10_0; secure =3D true; break; case 2: @@ -3402,7 +3411,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) mmu_idx =3D ARMMMUIdx_Stage1_E0; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E= 0; + mmu_idx =3D ARMMMUIdx_Stage1_E0; break; default: g_assert_not_reached(); @@ -3471,17 +3480,16 @@ static void ats_write64(CPUARMState *env, const ARM= CPRegInfo *ri, switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ if (ri->crm =3D=3D 9 && (env->pstate & PSTATE_PAN)) { - mmu_idx =3D (secure ? ARMMMUIdx_Stage1_SE1_PAN - : ARMMMUIdx_Stage1_E1_PAN); + mmu_idx =3D ARMMMUIdx_Stage1_E1_PAN; } else { - mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stag= e1_E1; + mmu_idx =3D ARMMMUIdx_Stage1_E1; } break; case 4: /* AT S1E2R, AT S1E2W */ - mmu_idx =3D secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2; + mmu_idx =3D ARMMMUIdx_E2; break; case 6: /* AT S1E3R, AT S1E3W */ - mmu_idx =3D ARMMMUIdx_SE3; + mmu_idx =3D ARMMMUIdx_E3; secure =3D true; break; default: @@ -3489,13 +3497,13 @@ static void ats_write64(CPUARMState *env, const ARM= CPRegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0; + mmu_idx =3D ARMMMUIdx_Stage1_E0; break; case 4: /* AT S12E1R, AT S12E1W */ - mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1; + mmu_idx =3D ARMMMUIdx_E10_1; break; case 6: /* AT S12E0R, AT S12E0W */ - mmu_idx =3D secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0; + mmu_idx =3D ARMMMUIdx_E10_0; break; default: g_assert_not_reached(); @@ -3765,11 +3773,6 @@ static void vmsa_tcr_ttbr_el2_write(CPUARMState *env= , const ARMCPRegInfo *ri, uint16_t mask =3D ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_2_PAN | ARMMMUIdxBit_E20_0; - - if (arm_is_secure_below_el3(env)) { - mask >>=3D ARM_MMU_IDX_A_NS; - } - tlb_flush_by_mmuidx(env_cpu(env), mask); } raw_write(env, ri, value); @@ -3789,11 +3792,6 @@ static void vttbr_write(CPUARMState *env, const ARMC= PRegInfo *ri, uint16_t mask =3D ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0; - - if (arm_is_secure_below_el3(env)) { - mask >>=3D ARM_MMU_IDX_A_NS; - } - tlb_flush_by_mmuidx(cs, mask); raw_write(env, ri, value); } @@ -4264,11 +4262,6 @@ static int vae1_tlbmask(CPUARMState *env) ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0; } - - if (arm_is_secure_below_el3(env)) { - mask >>=3D ARM_MMU_IDX_A_NS; - } - return mask; } =20 @@ -4295,10 +4288,6 @@ static int vae1_tlbbits(CPUARMState *env, uint64_t a= ddr) mmu_idx =3D ARMMMUIdx_E10_0; } =20 - if (arm_is_secure_below_el3(env)) { - mmu_idx &=3D ~ARM_MMU_IDX_A_NS; - } - return tlbbits_for_regime(env, mmu_idx, addr); } =20 @@ -4331,30 +4320,17 @@ static int alle1_tlbmask(CPUARMState *env) * stage 2 translations, whereas most other scopes only invalidate * stage 1 translations. */ - if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE10_1 | - ARMMMUIdxBit_SE10_1_PAN | - ARMMMUIdxBit_SE10_0; - } else { - return ARMMMUIdxBit_E10_1 | - ARMMMUIdxBit_E10_1_PAN | - ARMMMUIdxBit_E10_0; - } + return (ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0); } =20 static int e2_tlbmask(CPUARMState *env) { - if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE20_0 | - ARMMMUIdxBit_SE20_2 | - ARMMMUIdxBit_SE20_2_PAN | - ARMMMUIdxBit_SE2; - } else { - return ARMMMUIdxBit_E20_0 | - ARMMMUIdxBit_E20_2 | - ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E2; - } + return (ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4381,7 +4357,7 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E3); } =20 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4407,7 +4383,7 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env,= const ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E3); } =20 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4435,7 +4411,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E3); } =20 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -4474,12 +4450,10 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env= , const ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - bool secure =3D arm_is_secure_below_el3(env); - int mask =3D secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; - int bits =3D tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUId= x_E2, - pageaddr); + int bits =3D tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr); =20 - tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits= ); + tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + ARMMMUIdxBit_E2, bits); } =20 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -4487,10 +4461,10 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env= , const ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - int bits =3D tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr); + int bits =3D tlbbits_for_regime(env, ARMMMUIdx_E3, pageaddr); =20 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_SE3, bits); + ARMMMUIdxBit_E3, bits); } =20 #ifdef TARGET_AARCH64 @@ -4596,8 +4570,7 @@ static void tlbi_aa64_rvae1is_write(CPUARMState *env, =20 static int vae2_tlbmask(CPUARMState *env) { - return (arm_is_secure_below_el3(env) - ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2); + return ARMMMUIdxBit_E2; } =20 static void tlbi_aa64_rvae2_write(CPUARMState *env, @@ -4643,8 +4616,7 @@ static void tlbi_aa64_rvae3_write(CPUARMState *env, * flush-last-level-only. */ =20 - do_rvae_write(env, value, ARMMMUIdxBit_SE3, - tlb_force_broadcast(env)); + do_rvae_write(env, value, ARMMMUIdxBit_E3, tlb_force_broadcast(env)); } =20 static void tlbi_aa64_rvae3is_write(CPUARMState *env, @@ -4658,7 +4630,7 @@ static void tlbi_aa64_rvae3is_write(CPUARMState *env, * flush-last-level-only or inner/outer specific flushes. */ =20 - do_rvae_write(env, value, ARMMMUIdxBit_SE3, true); + do_rvae_write(env, value, ARMMMUIdxBit_E3, true); } #endif =20 @@ -10271,8 +10243,7 @@ uint64_t arm_sctlr(CPUARMState *env, int el) /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ if (el =3D=3D 0) { ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, 0); - el =3D (mmu_idx =3D=3D ARMMMUIdx_E20_0 || mmu_idx =3D=3D ARMMMUIdx= _SE20_0) - ? 2 : 1; + el =3D mmu_idx =3D=3D ARMMMUIdx_E20_0 ? 2 : 1; } return env->cp15.sctlr_el[el]; } @@ -10816,22 +10787,15 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_E10_0: case ARMMMUIdx_E20_0: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE20_0: return 0; case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: return 1; case ARMMMUIdx_E2: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE2: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: return 2; - case ARMMMUIdx_SE3: + case ARMMMUIdx_E3: return 3; default: g_assert_not_reached(); @@ -10884,15 +10848,11 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) } break; case 3: - return ARMMMUIdx_SE3; + return ARMMMUIdx_E3; default: g_assert_not_reached(); } =20 - if (arm_is_secure_below_el3(env)) { - idx &=3D ~ARM_MMU_IDX_A_NS; - } - return idx; } =20 @@ -11095,15 +11055,11 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMSta= te *env, int el, int fp_el, switch (mmu_idx) { case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: /* TODO: ARMv8.3-NV */ DP_TBFLAG_A64(flags, UNPRIV, 1); break; case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: /* * Note that EL20_2 is gated by HCR_EL2.E2H =3D=3D 1, but EL20= _0 is * gated by HCR_EL2. =3D=3D '11', and so is LDTR. diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 55e8f33c508..2055d684e63 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -65,12 +65,6 @@ unsigned int arm_pamax(ARMCPU *cpu) ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_SE10_0: - return ARMMMUIdx_Stage1_SE0; - case ARMMMUIdx_SE10_1: - return ARMMMUIdx_Stage1_SE1; - case ARMMMUIdx_SE10_1_PAN: - return ARMMMUIdx_Stage1_SE1_PAN; case ARMMMUIdx_E10_0: return ARMMMUIdx_Stage1_E0; case ARMMMUIdx_E10_1: @@ -95,11 +89,8 @@ static bool regime_translation_big_endian(CPUARMState *e= nv, ARMMMUIdx mmu_idx) static bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_SE10_0: case ARMMMUIdx_E20_0: - case ARMMMUIdx_SE20_0: case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_Stage1_SE0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: case ARMMMUIdx_MUserNegPri: @@ -2304,7 +2295,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, =20 s2_mmu_idx =3D (s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2); - is_el0 =3D mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D AR= MMMUIdx_SE10_0; + is_el0 =3D mmu_idx =3D=3D ARMMMUIdx_E10_0; =20 /* * S1 is done, now do S2 translation. @@ -2511,6 +2502,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E2: + is_secure =3D arm_is_secure_below_el3(env); + break; case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: @@ -2518,17 +2511,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, case ARMMMUIdx_MUser: is_secure =3D false; break; - case ARMMMUIdx_SE3: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: - case ARMMMUIdx_Stage1_SE0: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: - case ARMMMUIdx_SE2: + case ARMMMUIdx_E3: case ARMMMUIdx_Stage2_S: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 78b2d91ed40..5b67375f4ec 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -111,14 +111,6 @@ static int get_a64_user_mem_index(DisasContext *s) case ARMMMUIdx_E20_2_PAN: useridx =3D ARMMMUIdx_E20_0; break; - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - useridx =3D ARMMMUIdx_SE10_0; - break; - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: - useridx =3D ARMMMUIdx_SE20_0; - break; default: g_assert_not_reached(); } diff --git a/target/arm/translate.c b/target/arm/translate.c index ac647e02628..2f72afe019a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -237,16 +237,12 @@ static inline int get_a32_user_mem_index(DisasContext= *s) * otherwise, access as if at PL0. */ switch (s->mmu_idx) { + case ARMMMUIdx_E3: case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */ case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: return arm_to_core_mmu_idx(ARMMMUIdx_E10_0); - case ARMMMUIdx_SE3: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0); case ARMMMUIdx_MUser: case ARMMMUIdx_MPriv: return arm_to_core_mmu_idx(ARMMMUIdx_MUser); --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665412784; cv=none; d=zohomail.com; s=zohoarc; b=A73byf1VAYcLG4zqG0b8ehB9OBrCH9GNyc7z+kZA8+0woD/FzxEHkR/lLfP8bdArUK22/85lrS7BIhlQsv+zPyzQSExIajrrUicUJcKD6s1UsBP1ogwfJwByLtzZ9/yl6eTiXuj2n741URrykwY8CRcQslFOX9hLumMpxzZC0LE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665412784; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xcqyCitgRrJzyAqXxWJiCb8GgP/3UYAazPshhYBejpI=; b=IOePrsxZB7B4TeRv/o4hNfMqWBxLq6vNE8qs3GkaO1M6tRHCdhU7OP6Ptb3m7xTKwa4L8RjUD6Yu6vHYQdtlNpC8/MBXk7N4iE58g1WjHoro2Cxi/g1F7n3ylbav75FzYTvFr6dFiyL13Dq5EZLpEQLfhJoC6B6IeHVvCU7qfa0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665412784878851.0048221614115; Mon, 10 Oct 2022 07:39:44 -0700 (PDT) Received: from localhost ([::1]:56746 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohtwV-0003Zm-LH for importer@patchew.org; Mon, 10 Oct 2022 10:39:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52966) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtl1-0006Nl-K4 for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:53 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:36623) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtl0-0005a6-1K for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:51 -0400 Received: by mail-wm1-x32e.google.com with SMTP id c3-20020a1c3503000000b003bd21e3dd7aso8661289wma.1 for ; Mon, 10 Oct 2022 07:27:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=xcqyCitgRrJzyAqXxWJiCb8GgP/3UYAazPshhYBejpI=; b=gDRSgXtzSEfjMt8DXjU/RPXqr/LCv29SD1IF18CUvXGfvQQwHhRWEf/1QnuXKEvTP5 FluTzRv4z/rrmc/QJa6liQbdlQ4oVhErQxDk9u5/VWyvvqVdrK/6E4eCXaQn87kYCIn2 lhKeSVF1LGxg6aonjsRokY/eE4hZnNryGjuKmmfCSw7n+CJRj3gdHflF52yLDYtd53pH oaQPM34C5R85eVss8T+z6qq3dwNpNfcvwQyVAeLQhq77w0w3rW8Qixq6h7a5lVqgvmsG 5xJkynW55r5OQ4BTraugEeAh1kyCO01h+Hou0L2tJCYKq8um7MX7uYF1jkPObj+ouat6 83nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xcqyCitgRrJzyAqXxWJiCb8GgP/3UYAazPshhYBejpI=; b=YZ/852lpWjR8tFwYM36VIrXNeswNcI2ic9zfDBD6mdryqv0jZfwHLJ1TyLxhsW0Y4G 7rypwU2OzEQ/uaNr3dQQvLRh5fWAd5sgHZz8bgWmS02rmgazrGrsYeCQQuUOyYxAsiYu Vah+hZ1wP7n0AQXZ4elhI9o0vsJAyYHx8x3jm/pMm9Mqx6aHjJRnGcLp9KjMsLnJSXvm gz6bY2gRFNtCf2E3Or6mqcB2mA4IuA28Mqyvl/GZ9bsXBsdgzGbafdaiDSEb1eeB2VfG pElWVJqCapINYXSzZqgd8zjOt8pCh0RYM6oeefGy1a/NwE/q+XXR0Q6ETk0oc/4odHwD W1pw== X-Gm-Message-State: ACrzQf0QFuWAU8u0GkBaG7Cde7weY8lGTEmzYvZxeBCCeWpgO86Zo8CK b/x4gyz9ouIFlO6758FUuC9KLzVsSGBBDw== X-Google-Smtp-Source: AMsMyM5h62dPLxi8qC6e1LPRZ4L+UI/c67ih6ddggsBNWJbEjpEbysQR/79OnmLn34lFD/BX5HoT+g== X-Received: by 2002:a05:600c:500d:b0:3b5:234:d7e9 with SMTP id n13-20020a05600c500d00b003b50234d7e9mr12993952wmr.57.1665412068655; Mon, 10 Oct 2022 07:27:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/28] target/arm: Reorg regime_translation_disabled Date: Mon, 10 Oct 2022 15:27:17 +0100 Message-Id: <20221010142730.502083-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665412785483100004 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use a switch on mmu_idx for the a-profile indexes, instead of three different if's vs regime_el and arm_mmu_idx_is_stage1_of_2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20221001162318.153420-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 2055d684e63..a514a78c924 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -148,21 +148,39 @@ static bool regime_translation_disabled(CPUARMState *= env, ARMMMUIdx mmu_idx, =20 hcr_el2 =3D arm_hcr_el2_eff(env); =20 - if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { + switch (mmu_idx) { + case ARMMMUIdx_Stage2: + case ARMMMUIdx_Stage2_S: /* HCR.DC means HCR.VM behaves as 1 */ return (hcr_el2 & (HCR_DC | HCR_VM)) =3D=3D 0; - } =20 - if (hcr_el2 & HCR_TGE) { + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ - if (!is_secure && regime_el(env, mmu_idx) =3D=3D 1) { + if (!is_secure && (hcr_el2 & HCR_TGE)) { return true; } - } + break; =20 - if ((hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: /* HCR.DC means SCTLR_EL1.M behaves as 0 */ - return true; + if (hcr_el2 & HCR_DC) { + return true; + } + break; + + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_E2: + case ARMMMUIdx_E3: + break; + + default: + g_assert_not_reached(); } =20 return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665413769; cv=none; d=zohomail.com; s=zohoarc; b=G7AaLMA3aH46B6zgLZL59IqyRE4Xs4rqv0ilZtuHZmkiCKljedee/iWZHbGHS3hNdaMje8YFxOBI7BGkNdak0WGHPb5uLZdwDG/d3gLchCR7GSUIMMM5a1LBf5mGPMZTh0y+9zruI8amI/1eRA0vEY332l/ZX2+l0Ruf5Z/K5Ik= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665413769; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=D9f9Ogi7C2qQwTonIlgIUzx/S6n2fOCeloaV1MSlzPc=; b=f0wpUvrZiVxoedirmT/h2NoKY0JogCGQLwE08df3paC4Z6C7xKZbpKfA8M2M09siw6+ECjK6dkdIGMkERxtlb8920MkORoAwpsbMWqggaiZt/qGhDBwtynkWOYxvA0HoZRVMiTFc+kZvNggNot4vRYGg8H9hifqU/gZnxnzIS5c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665413769605549.6781082523628; Mon, 10 Oct 2022 07:56:09 -0700 (PDT) Received: from localhost ([::1]:38044 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohuCO-0001c4-C4 for importer@patchew.org; Mon, 10 Oct 2022 10:56:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52970) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtl2-0006Nn-El for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:53 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:34388) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtl0-0005Xn-Bq for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:52 -0400 Received: by mail-wr1-x429.google.com with SMTP id b4so17335095wrs.1 for ; Mon, 10 Oct 2022 07:27:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=D9f9Ogi7C2qQwTonIlgIUzx/S6n2fOCeloaV1MSlzPc=; b=EjnOgeWYlnl5hkOgovDlUcBl4GmA4ipE+pri6PWeQ76qgeIitDEkPQPjGDF3iXPP4G E3Prm/N+Rg6yu9LE0u7liKTYb9RqolGa7xVlE30/HOoxMQ0RntAvpwoJc4CrqFY91eQd g0aidgpbO65F31IcqDfhQy2mXvYCUh1TngRpPd6gGkuBcYZwxUN2VU01gR2G3fqPA3Ut Kt5Mj7VoJVZLh/8BTgUVxlsfAESlX4wRBBl+Zcf1yN3YCYdPaP2hn4XAFvnMKfc3BU4Z K2jC+PIqfs8mrRWSLg6FtqLbY5036ONcoODiQmhQ96agcpWvSsqkXdIazIztmHZt/dpl f2xQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D9f9Ogi7C2qQwTonIlgIUzx/S6n2fOCeloaV1MSlzPc=; b=MhOBBz8dqh9fXo+X5fmeyXvAr4vT0+4pUdpceXLfc/dTAGOKVPRjjO6MKfm9eQ7Rtb Vcojnc+MvGpzz1+Ly+UU2NV9wSipw4FKsclWiCDChhrZIeeKVty/5pYYh7fmr1GfHRI1 Czw3mOPoBADlcpG03Qaa32qn3B/hfBzl5BOQ3ab4DpponJ6uHDga3rhvZled77xHwWFC mYDijUSURI+jFG6BVWw9vFQnXekiWl847MmCGz+Sb9lmOf4UaartgsPCdwu9fbk6p+o9 6vPg9lmkQj62MrDRCz6hm5u9ddT+AjeqVU+cNEzo1Hye9Hov8Xf4wy6F2XxqD1POjcMr A6iA== X-Gm-Message-State: ACrzQf2rdrv5S2DOknX+hoyFHtPW+c0/wfIx92x3J+hJ3MyQtv94DGdk XJE2IpC/Q47yuLPbaVM6x6CrGQ1vMeDUGg== X-Google-Smtp-Source: AMsMyM5pZEXHTcFzeD8mM60opLKRJNWHQqQFJcR+dHAy4uuwOI3+mFZNQyh+c7SW3OMvaEssijKR8Q== X-Received: by 2002:a5d:648b:0:b0:22e:ee60:db37 with SMTP id o11-20020a5d648b000000b0022eee60db37mr10261011wri.116.1665412069545; Mon, 10 Oct 2022 07:27:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/28] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M Date: Mon, 10 Oct 2022 15:27:18 +0100 Message-Id: <20221010142730.502083-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665413769945100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson The effect of TGE does not only apply to non-secure state, now that Secure EL2 exists. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20221001162318.153420-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a514a78c924..b3e0db19369 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -157,8 +157,8 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx, case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: - /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ - if (!is_secure && (hcr_el2 & HCR_TGE)) { + /* TGE means that EL0/1 act as if SCTLR_EL1.M is zero */ + if (hcr_el2 & HCR_TGE) { return true; } break; --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665413252; cv=none; d=zohomail.com; s=zohoarc; b=FY+ZZPmDvrXxMzpeZX3nG1CogkIZm3mVFnV1vMX+urmbXJI2crqpV+Cqpik+yL7iza6UF1nVb5HCLrSQyy5mG40zS4efmiPyXe/Rqjsl69LlTDYRE/j04xK8Dmy0/bLo/b6Zhlc4iU3htnAm3+uKP7Lx6G88uhPiai6tJSm8dEM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665413252; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JtZGH55VaZfgWgsMLT00zdGdGKdNAG1BkKtA55HW2Jc=; b=ZhPtBdytV7fcDK106nosEJrV+uidQWeTBT9/E/3hwFF9iElvxLZMRzh2eZmarwQnLBdKhCouTCPDSq4DxtQqBl2Fj7XTp0a6gmyjHJzZUst/01quXAw2HD71WKiI37gYJ03dkAMZahNuqXYbGlTYR+HyDKJ7ANvegd3gdDbeG/0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665413252135320.74410836128425; Mon, 10 Oct 2022 07:47:32 -0700 (PDT) Received: from localhost ([::1]:35430 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohu42-0006ci-QT for importer@patchew.org; Mon, 10 Oct 2022 10:47:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52972) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtl3-0006OJ-KQ for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:53 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:56110) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtl1-0005aG-Vz for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:53 -0400 Received: by mail-wm1-x329.google.com with SMTP id t4so6938286wmj.5 for ; Mon, 10 Oct 2022 07:27:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=JtZGH55VaZfgWgsMLT00zdGdGKdNAG1BkKtA55HW2Jc=; b=iW58+btw1cNAvCvINapVVDtaHx7WlqbjUafQ49+42N/lf0ma/gjeEtwKTvL2PnCBkC /m5C3Jf/3BM3nL9Dq7HhntzNXe10NYX4tBmLhFynlal2/Z5wp5oi61Y8bID3yxTBuHoq Og7Et3v7bHkJuoVh8s+sSMZHkWcYxNM7aiMzmod6IfNBRt826iAsB0GV1OqjevEQ1kPF Gu2p631ma8vJ58yfdg50YUPRyGgmNsRD9F0cmgmi+XVi/SiOB2dYgQfbIbjCwyADUJx/ VA/27H3iOJnkOCl6yAgPUpUBv3wVuxE6AxU2Dxjjr/A8xVYs4UPPy4xMkAzDnKOQ0w3q rPdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JtZGH55VaZfgWgsMLT00zdGdGKdNAG1BkKtA55HW2Jc=; b=Mmb9+ScEORe8Gor0lsA6yUvnE4QEa9VxxBJujF1o3Q91kL/Ew5114XiCmUgaQ9yOdd FMrA0J0ApGPTfdYCQ9T+4WARTQMZ4q2u82z3Ri+yEWyhDjqkKwYxPGG6N4rM9RNzZVbQ WTdC94BPp7llLDqNLSImimHaleHxLNIVs9HsNZUVlX3WN546vxVo8ITPMwufmDm26R7w FnIGINclZrSf0r5Toee1uYfg8UJQLeBGqorY9NYxvOATsS2x7HAXmjIvS9crAodrG6+R ADkENjAYlZuVoqzenEjgTSjuYniYUgCnXaFlC39IgfOe/KrDoy9mAfju22AnXHgSjcN8 ieJw== X-Gm-Message-State: ACrzQf1PmEQXR1ZJ7hZWXJ3tD93m/9Rka7xPVX7RLBjGXEdsmlzxLna1 u2xN8zfLhMnAKOXBoZwBEYUWjERKcYF63w== X-Google-Smtp-Source: AMsMyM64GpReisa/LbLmi859UjZjqPSdl86orIJIfY7ArWhxx9v40zBpOUkwMdprM6Dy4dCGVY1AZg== X-Received: by 2002:a05:600c:3b9e:b0:3b4:4cf1:9531 with SMTP id n30-20020a05600c3b9e00b003b44cf19531mr19625480wms.64.1665412070486; Mon, 10 Oct 2022 07:27:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/28] target/arm: Introduce arm_hcr_el2_eff_secstate Date: Mon, 10 Oct 2022 15:27:19 +0100 Message-Id: <20221010142730.502083-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665413253326100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson For page walking, we may require HCR for a security state that is not "current". Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20221001162318.153420-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 20 +++++++++++++------- target/arm/helper.c | 11 ++++++++--- 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 53f4c236e1f..d541392170e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2412,15 +2412,15 @@ static inline bool arm_is_secure(CPUARMState *env) * Return true if the current security state has AArch64 EL2 or AArch32 Hy= p. * This corresponds to the pseudocode EL2Enabled() */ +static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secu= re) +{ + return arm_feature(env, ARM_FEATURE_EL2) + && (!secure || (env->cp15.scr_el3 & SCR_EEL2)); +} + static inline bool arm_is_el2_enabled(CPUARMState *env) { - if (arm_feature(env, ARM_FEATURE_EL2)) { - if (arm_is_secure_below_el3(env)) { - return (env->cp15.scr_el3 & SCR_EEL2) !=3D 0; - } - return true; - } - return false; + return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env)); } =20 #else @@ -2434,6 +2434,11 @@ static inline bool arm_is_secure(CPUARMState *env) return false; } =20 +static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secu= re) +{ + return false; +} + static inline bool arm_is_el2_enabled(CPUARMState *env) { return false; @@ -2446,6 +2451,7 @@ static inline bool arm_is_el2_enabled(CPUARMState *en= v) * "for all purposes other than a direct read or write access of HCR_EL2." * Not included here is HCR_RW. */ +uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure); uint64_t arm_hcr_el2_eff(CPUARMState *env); uint64_t arm_hcrx_el2_eff(CPUARMState *env); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index b1b8725628b..f1266bb1579 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5229,15 +5229,15 @@ static void hcr_writelow(CPUARMState *env, const AR= MCPRegInfo *ri, } =20 /* - * Return the effective value of HCR_EL2. + * Return the effective value of HCR_EL2, at the given security state. * Bits that are not included here: * RW (read from SCR_EL3.RW as needed) */ -uint64_t arm_hcr_el2_eff(CPUARMState *env) +uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure) { uint64_t ret =3D env->cp15.hcr_el2; =20 - if (!arm_is_el2_enabled(env)) { + if (!arm_is_el2_enabled_secstate(env, secure)) { /* * "This register has no effect if EL2 is not enabled in the * current Security state". This is ARMv8.4-SecEL2 speak for @@ -5296,6 +5296,11 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) return ret; } =20 +uint64_t arm_hcr_el2_eff(CPUARMState *env) +{ + return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env)); +} + /* * Corresponds to ARM pseudocode function ELIsInHost(). */ --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665413598; cv=none; d=zohomail.com; s=zohoarc; b=SF94vOghqr/qONpdZi1inzl73HCFqOu+gYdUMdpMJCXU9/YyfDhoR7M+LCVYNKDrH+vh7qjYhQWfIrbtfjQNVbKQp5vK3zBSVF6NB7RwjSxuG+3kR5t3Tj7Se9I938rIHiq5f2KAYZty5HcTAoblSQHfcqobanMVOCXNOyHovxk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665413598; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=I9U26+V5C/CkK7B8UL55/rDbIxkmkXtApVD0MXqZAlI=; b=S6tjl7RHPGQGQS8kWW6PjtrQKJ0CxjmfmwCWn3GwpIr3WdoT/cYCtmWwGuBnPrbNivGpsrL6sIjQnAivnFliyCjH35oncAJ87TX1ur+9lnnLyvloVZ+mgWWmMkPapfoQwPU+DudgUNGl5tSijaQWh6qh7f18xKj7ElQgkFPX1nQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665413598758100.86542670333802; Mon, 10 Oct 2022 07:53:18 -0700 (PDT) Received: from localhost ([::1]:35818 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohu9d-00049b-Gj for importer@patchew.org; Mon, 10 Oct 2022 10:53:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52974) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtl4-0006Ox-NM for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:54 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:43542) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtl3-0005aa-4v for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:54 -0400 Received: by mail-wr1-x433.google.com with SMTP id n12so17285157wrp.10 for ; Mon, 10 Oct 2022 07:27:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=I9U26+V5C/CkK7B8UL55/rDbIxkmkXtApVD0MXqZAlI=; b=KnFvsa0HE+CDYRZNIPeB5LeupDsanlgw7O/1Q7EpMLvyTs/MEktXQohZlqzVWLZdu+ gJxv/1TZHTnmHiba+ZLjM0mvR7B3Jn4NAXLl0+Em39gUdw62ZDlo7FIqB3WpDA/0Qt0m 5oMhQpR61RsmEI5u2slNu2tk/XoQtSogBaOBTkVP0A2i4WpEGLutD9snG0qonQNycD37 LJUEkwa72WH9DtZP1qIH8irv9rryRvM+S4kFo/0bsKIAYLZMndfM1yBxkpdPdrQn96iL HaGAxlu7qE0VHSNr/5EBk56s6nBnjEDVzdyxYBr0Tjb5o3ieL/cBSb+hK4b/fD5L6lJM 9pVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I9U26+V5C/CkK7B8UL55/rDbIxkmkXtApVD0MXqZAlI=; b=fxvvQ/wVmId1Ta73o1rs64Guck5FUrn7RaDaAQ0FeF7RDo9LwzijwHgsFf5jjjBbrF dBP57RJ6UJEpIsfOTqgiftbpEfN9n0449bujMeRyUSllfCjkPxkR82cmpiCjmmvi+t5q 8cHsumw9G6gx3SEi2+3f1Di7i7MP76vl3LPZhLqiGlX/2b5lNFovtZhvUOhZtqcUnFl5 cYDmjMltAtWkpTr1o/Yg5QWkSxkZjDmIOrNGemNoxoCK3ci8iV5TRJr8mTR59TTEne7b a4G2kofn8V3G/2oVm8jHCJcPl1Q4dXcCCnYmYrff9Y42UkM3nvs3qCQslnavzQFoOzGZ QBRQ== X-Gm-Message-State: ACrzQf3coXLbnPHEKb/orVWQ7A2Ub7hYZ5uEnp9tDuvBoMzeH1XPAa7f g565229bGfIQSLKrxEMiQLCrtBDQGePJSw== X-Google-Smtp-Source: AMsMyM7YNd8T6ySGE8XYs011pNiqGreU8rDOHpAsQPeGF/31/bZ26WUjQjiimXFy8E09e/fF4HNkYQ== X-Received: by 2002:a5d:47a6:0:b0:22e:7c73:feb2 with SMTP id 6-20020a5d47a6000000b0022e7c73feb2mr11572755wrb.715.1665412071529; Mon, 10 Oct 2022 07:27:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/28] target/arm: Hoist read of *is_secure in S1_ptw_translate Date: Mon, 10 Oct 2022 15:27:20 +0100 Message-Id: <20221010142730.502083-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665413600504100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Rename the argument to is_secure_ptr, and introduce a local variable is_secure with the value. We only write back to the pointer toward the end of the function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20221001162318.153420-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b3e0db19369..b40b4586f87 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -207,24 +207,25 @@ static bool ptw_attrs_are_device(CPUARMState *env, AR= MCacheAttrs cacheattrs) =20 /* Translate a S1 pagetable walk through S2 if needed. */ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, - hwaddr addr, bool *is_secure, + hwaddr addr, bool *is_secure_ptr, ARMMMUFaultInfo *fi) { - ARMMMUIdx s2_mmu_idx =3D *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_S= tage2; + bool is_secure =3D *is_secure_ptr; + ARMMMUIdx s2_mmu_idx =3D is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_St= age2; =20 if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, s2_mmu_idx, *is_secure)) { + !regime_translation_disabled(env, s2_mmu_idx, is_secure)) { GetPhysAddrResult s2 =3D {}; int ret; =20 ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, - *is_secure, false, &s2, fi); + is_secure, false, &s2, fi); if (ret) { assert(fi->type !=3D ARMFault_None); fi->s2addr =3D addr; fi->stage2 =3D true; fi->s1ptw =3D true; - fi->s1ns =3D !*is_secure; + fi->s1ns =3D !is_secure; return ~0; } if ((arm_hcr_el2_eff(env) & HCR_PTW) && @@ -237,19 +238,20 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, fi->s2addr =3D addr; fi->stage2 =3D true; fi->s1ptw =3D true; - fi->s1ns =3D !*is_secure; + fi->s1ns =3D !is_secure; return ~0; } =20 if (arm_is_secure_below_el3(env)) { /* Check if page table walk is to secure or non-secure PA spac= e. */ - if (*is_secure) { - *is_secure =3D !(env->cp15.vstcr_el2 & VSTCR_SW); + if (is_secure) { + is_secure =3D !(env->cp15.vstcr_el2 & VSTCR_SW); } else { - *is_secure =3D !(env->cp15.vtcr_el2 & VTCR_NSW); + is_secure =3D !(env->cp15.vtcr_el2 & VTCR_NSW); } + *is_secure_ptr =3D is_secure; } else { - assert(!*is_secure); + assert(!is_secure); } =20 addr =3D s2.phys; --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665413595; cv=none; d=zohomail.com; s=zohoarc; b=C4kq9ZCh8ZQ50bWXPGKUF/3cCxnx4N3sK0qeMyQLeUSLqZ7AnkzhFKAgJgWqrrcp1rrZCVqq3J8G5Arny7ZSyhIxww4TZK0+fCmVTQUYUAyFPAukwzp7ET/f/H6Pw2/bifIblCFJUx+fsk7n9Cn7Yfrdec+b+x/WXPtr4DV29no= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665413595; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=e+zdmXfTwEDKvAlf77ndTlEHPt6WHX1xALzzxaa3N9s=; b=FWa3F39n5nJSyr3NUZVhixBJczVXIMPCKlSegCzhHD1vq7ZCHVF7hyWwCtUEAV4kGs02wsXKsqtk5HIGQQLI5HbeRJ/UQAG6kolJajJvG/MWFYIQPHjcEAy11nTqbz3GgwoJbA37BNqhSK2spFmpBVryycZu5d9X3M0v21Jn5cc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665413595325916.7829294632418; Mon, 10 Oct 2022 07:53:15 -0700 (PDT) Received: from localhost ([::1]:35816 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohu9Z-00040B-Ui for importer@patchew.org; Mon, 10 Oct 2022 10:53:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52976) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtl4-0006Oy-R1 for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:54 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:47075) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtl3-0005YG-BH for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:54 -0400 Received: by mail-wr1-x42b.google.com with SMTP id bk15so17272320wrb.13 for ; Mon, 10 Oct 2022 07:27:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=e+zdmXfTwEDKvAlf77ndTlEHPt6WHX1xALzzxaa3N9s=; b=ejz0ZKUE+LTWQYhuCAky/l7DTK+nGsvHtU879SaczMpzHEkrUaI74uJBoq0VCxWu1j VSH1maV/IWQzlRVm79Tix7ssYaCtHxTHSBYrVM3ZRmJlfGPOWqgyi7IE+2NPW8thQ+Hq 0XMpRAxMuKdBIdOW4C1PfxrAKfA4jWQgjFMandKG9BmhvqkCz8DPd4VfZbwYJxaZ3apO uOEGJ/Dy4vrfGpvoj+weC2H24Oaqg8lvjlij8aZ4PQA5+3kr+sX//0c2J9hIes9e1CV8 PRD07Xm7ENOH6RG5DWaT3fvc6GExZDoDQjDDOcWqt3bUiiAZ9fltNYTGm9Qx+5jNAAV+ 2/ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e+zdmXfTwEDKvAlf77ndTlEHPt6WHX1xALzzxaa3N9s=; b=4IZ015v11+0UogtUi3pSAAvL5kh3QDlbeZlTX7ww9jnaBEEgB82SOvRZ+YAzP6Xom+ TfYRx6EKyMeZfMK3E+kYw2/xZv1LKHo2cuFJuXap9I+aFPnKEUskEisuG1b8HV1aaEHC t4K+tycANSQ33/+JaSHgw3eovwhQsIfH7uxuXYH5T6YmBHxsyOJeGDCihlIkW48mEB7F 4DxQlZKY1AWKDapeWu3D/VeH/nQ+l1HHEOsKHTPAMkTR7non03xtHtsYjOENeQAtjLXi NUs6FmmxyIJsUIExez4HZKkUTTQUixBxkQF99NSC3PAMMzHWyKJRmMUvGOJx49s+YuHw tX7g== X-Gm-Message-State: ACrzQf1YsUadncHRKv93XzHrOFvKcIhb7IDFQdXOz501ArF23eBZz6Fa S7kE71jDX+45+mQVZrLp+O34jxWpTweFog== X-Google-Smtp-Source: AMsMyM5GA75bYC1afDS1zWMgbdGWARaZb5saaPitAsrUJ5YNhopGjUunUgJjCDLv8uUghlHGSafhyA== X-Received: by 2002:a5d:648c:0:b0:22e:63be:be09 with SMTP id o12-20020a5d648c000000b0022e63bebe09mr11554333wri.159.1665412072465; Mon, 10 Oct 2022 07:27:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/28] target/arm: Remove env argument from combined_attrs_fwb Date: Mon, 10 Oct 2022 15:27:21 +0100 Message-Id: <20221010142730.502083-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665413596616100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This value is unused. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20221001162318.153420-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b40b4586f87..7d607c2e7b5 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2172,8 +2172,7 @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr) * s1 and s2 for the HCR_EL2.FWB =3D=3D 1 case, returning the * combined attributes in MAIR_EL1 format. */ -static uint8_t combined_attrs_fwb(CPUARMState *env, - ARMCacheAttrs s1, ARMCacheAttrs s2) +static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2) { switch (s2.attrs) { case 7: @@ -2246,7 +2245,7 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *= env, =20 /* Combine memory type and cacheability attributes */ if (arm_hcr_el2_eff(env) & HCR_FWB) { - ret.attrs =3D combined_attrs_fwb(env, s1, s2); + ret.attrs =3D combined_attrs_fwb(s1, s2); } else { ret.attrs =3D combined_attrs_nofwb(env, s1, s2); } --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665412782; cv=none; d=zohomail.com; s=zohoarc; b=HTx04uvojrRT/MPqHB0QQ+oiZkTVSA7YgM+FgimvXO7YUSqQHxdrh36empwhhoEzWtU3T3c+4Wh4y8pQjn8XgGdu81em1GTnwN7SA/Ot/+xNlOuArQ680YGpANT7EYbywxtEeAKaXC9fGlSr1esJJpNOqJqAX0O0j7bSQ4OuOgI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665412782; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=B/NSK08PHYfCbr/Iig3swg/Ik7nPMnQ9pNlEcYvtrnQ=; b=Gm/McHUM7uXhLT3nhSk//N5nLAZ4wFYs2XqF54Ry40s1gt15wIIPy4XwLih6sxYGiUd7b1Tb6nRp/ur4dIOcnJkULo0B61nEIkcwpPF+tmSrDKVWyZXwe+xjEtgFk0aHMLCj32+8l9oM24dReSjCn/rGMeZGJqUnFaXEvGcPr0s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665412782974209.0897138348256; Mon, 10 Oct 2022 07:39:42 -0700 (PDT) Received: from localhost ([::1]:56742 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohtwT-0003M2-Fj for importer@patchew.org; Mon, 10 Oct 2022 10:39:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60086) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtl7-0006Rc-Ee for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:57 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:45721) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtl4-0005b0-VK for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:57 -0400 Received: by mail-wr1-x42c.google.com with SMTP id a10so17266986wrm.12 for ; Mon, 10 Oct 2022 07:27:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=B/NSK08PHYfCbr/Iig3swg/Ik7nPMnQ9pNlEcYvtrnQ=; b=kM8guZuhlYewVHNy5wPXIy1fgQ4hLpND7GoPe36jKjL+s4qcx0HSCWpbMGnED28led L09U9kp82/5KhWw2XLsKqRxXEWIk4IXkaa4IOpFCJS9DxTyTuLnS2L/ncnrHisUxe4oT 8sncrB5ttyGAIIrY2DzvYmXmCBUJdJ0G2GPYsP+ZUw/C8SUop4Y6yxxcj0hWXMPMFK4J kyp7anT+R6rm7Tw0CfjFKtfG21aehSXqrW/y3hk/2eiQmhxYt5f6bFq9uF4vWPM+d1XW eJcVQGApurCqXq9n8jWgWoV0h4F74JB3hPbumHsHOFtJ8wRkZeVkBQdf8iT19XOvgOda xaxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B/NSK08PHYfCbr/Iig3swg/Ik7nPMnQ9pNlEcYvtrnQ=; b=Dr7FcTvk7NomEo9D5iLCGcOGXTaanUsjL1/fJeyD5f+6S3Q6tONVjgd8QxLvm1IH25 GeYIKN57p6evQEv+JUNbpNxqpxWPh+sv1KTIxl2kztT1Uu2EIo462NFfsanX4OhNFrtA pmF+N2Zypr5AHrly5UM1D/maOHJ6lYtrh4lwcfEQCpLjVcm2n/biZeavQFqe7izXLjR5 xALbmdqtu+GtFFgbj571KxsIu+PlesgnLZIATImKgdS2xO9e6oKVfd4mAWSgylldoYIc 1ZqQWY2/DTe0vnrtJal8Kh6DrHvkgELfhWFl8/Awb+QaZtAStYImsxVmP4dnNSNu/LKh kFJg== X-Gm-Message-State: ACrzQf3JwkePjiunIgj408STWagGEc20EL9SVhZ1JvUFIVNc6yQZyMJB llHXA/OOdNf80OpP4XnPuWEc6fneX7ApSg== X-Google-Smtp-Source: AMsMyM6tn5GEmfXpKT/+XHDmv2jt2J7kUkBjJswPhcxvKM3OOY/Ce9Y0RY7BFP+T6FZHsnwGsLzKLw== X-Received: by 2002:a5d:6d8a:0:b0:22f:1ade:de87 with SMTP id l10-20020a5d6d8a000000b0022f1adede87mr8645580wrs.3.1665412073459; Mon, 10 Oct 2022 07:27:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/28] target/arm: Pass HCR to attribute subroutines. Date: Mon, 10 Oct 2022 15:27:22 +0100 Message-Id: <20221010142730.502083-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665412783679100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson These subroutines did not need ENV for anything except retrieving the effective value of HCR anyway. We have computed the effective value of HCR in the callers, and this will be especially important for interpreting HCR in a non-current security state. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20221001162318.153420-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7d607c2e7b5..b4fd4d3fac1 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -186,7 +186,7 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; } =20 -static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattr= s) +static bool ptw_attrs_are_device(uint64_t hcr, ARMCacheAttrs cacheattrs) { /* * For an S1 page table walk, the stage 1 attributes are always @@ -198,7 +198,7 @@ static bool ptw_attrs_are_device(CPUARMState *env, ARMC= acheAttrs cacheattrs) * when cacheattrs.attrs bit [2] is 0. */ assert(cacheattrs.is_s2_format); - if (arm_hcr_el2_eff(env) & HCR_FWB) { + if (hcr & HCR_FWB) { return (cacheattrs.attrs & 0x4) =3D=3D 0; } else { return (cacheattrs.attrs & 0xc) =3D=3D 0; @@ -216,6 +216,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && !regime_translation_disabled(env, s2_mmu_idx, is_secure)) { GetPhysAddrResult s2 =3D {}; + uint64_t hcr; int ret; =20 ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, @@ -228,8 +229,9 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, fi->s1ns =3D !is_secure; return ~0; } - if ((arm_hcr_el2_eff(env) & HCR_PTW) && - ptw_attrs_are_device(env, s2.cacheattrs)) { + + hcr =3D arm_hcr_el2_eff(env); + if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) { /* * PTW set and S1 walk touched S2 Device memory: * generate Permission fault. @@ -2059,14 +2061,14 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, = uint32_t address, * ref: shared/translation/attrs/S2AttrDecode() * .../S2ConvertAttrsHints() */ -static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) +static uint8_t convert_stage2_attrs(uint64_t hcr, uint8_t s2attrs) { uint8_t hiattr =3D extract32(s2attrs, 2, 2); uint8_t loattr =3D extract32(s2attrs, 0, 2); uint8_t hihint =3D 0, lohint =3D 0; =20 if (hiattr !=3D 0) { /* normal memory */ - if (arm_hcr_el2_eff(env) & HCR_CD) { /* cache disabled */ + if (hcr & HCR_CD) { /* cache disabled */ hiattr =3D loattr =3D 1; /* non-cacheable */ } else { if (hiattr !=3D 1) { /* Write-through or write-back */ @@ -2112,12 +2114,12 @@ static uint8_t combine_cacheattr_nibble(uint8_t s1,= uint8_t s2) * s1 and s2 for the HCR_EL2.FWB =3D=3D 0 case, returning the * combined attributes in MAIR_EL1 format. */ -static uint8_t combined_attrs_nofwb(CPUARMState *env, +static uint8_t combined_attrs_nofwb(uint64_t hcr, ARMCacheAttrs s1, ARMCacheAttrs s2) { uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs; =20 - s2_mair_attrs =3D convert_stage2_attrs(env, s2.attrs); + s2_mair_attrs =3D convert_stage2_attrs(hcr, s2.attrs); =20 s1lo =3D extract32(s1.attrs, 0, 4); s2lo =3D extract32(s2_mair_attrs, 0, 4); @@ -2217,7 +2219,7 @@ static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, A= RMCacheAttrs s2) * @s1: Attributes from stage 1 walk * @s2: Attributes from stage 2 walk */ -static ARMCacheAttrs combine_cacheattrs(CPUARMState *env, +static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, ARMCacheAttrs s1, ARMCacheAttrs s2) { ARMCacheAttrs ret; @@ -2244,10 +2246,10 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState= *env, } =20 /* Combine memory type and cacheability attributes */ - if (arm_hcr_el2_eff(env) & HCR_FWB) { + if (hcr & HCR_FWB) { ret.attrs =3D combined_attrs_fwb(s1, s2); } else { - ret.attrs =3D combined_attrs_nofwb(env, s1, s2); + ret.attrs =3D combined_attrs_nofwb(hcr, s1, s2); } =20 /* @@ -2290,6 +2292,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, ARMCacheAttrs cacheattrs1; ARMMMUIdx s2_mmu_idx; bool is_el0; + uint64_t hcr; =20 ret =3D get_phys_addr_with_secure(env, address, access_type, s1_mmu_idx, is_secure, result,= fi); @@ -2338,7 +2341,8 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, } =20 /* Combine the S1 and S2 cache attributes. */ - if (arm_hcr_el2_eff(env) & HCR_DC) { + hcr =3D arm_hcr_el2_eff(env); + if (hcr & HCR_DC) { /* * HCR.DC forces the first stage attributes to * Normal Non-Shareable, @@ -2351,7 +2355,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, } cacheattrs1.shareability =3D 0; } - result->cacheattrs =3D combine_cacheattrs(env, cacheattrs1, + result->cacheattrs =3D combine_cacheattrs(hcr, cacheattrs1, result->cacheattrs); =20 /* --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665413759; cv=none; d=zohomail.com; s=zohoarc; b=WabV5ClGOUTrSCuFSgIOWCZ1mkjoiGJgWf1XYYCLLa1EuULAgGGNzI2c5SDkEq0M/sN+LdR8Fatz5GH2bCshB2viExZTLXW36stS+sYnlgYB3SyFCOxrdHDbyLOrxEZvM9MZavrbZ0m1dzmB2qQQqErNCnbaMalejdRluOo7G60= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665413759; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=LdE7Yti6FxQSUdCITEyW9uuJhLKh/sdf2KHare74vR0=; b=aFQEuFHisonfMCGI5FQjrVwCx5akThnTiL3cOTUP6MDy+JwuaY9vxnbq7nYuljtg2g PgR1iQNV/lbwaVqbcV2oPzwgbgWVullEjVE16qqq1H/d+RcnwF+FdP65Hmnugyo6aBgV 3entSGfjdvDpVY4Fi1zEgMabgppWAfoTelY2TvW+oL+6tscFlTzN4awbqOWZDq3dLc8i rj8VwKBbzsNmaQKmY/Ms64zL5mb4/32QjTwCUhxPHtF1P4Bw7rmkcJH5V/6yyCx7BW9y L0DiREGwBf3TNPmJiFEvI/EMqtLntnrs4rslqsBz6JCSEGofcyV7P5Q+giDWikP8r0Td aiLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LdE7Yti6FxQSUdCITEyW9uuJhLKh/sdf2KHare74vR0=; b=yin5HEQw0gEDvGxkXAcvLig+xDo2VQ7ajEHd0HFjbedbypi0/xOVyZM4gGZMiRYhEq askGKFOAMc0ovh41hbPgAVnIm9r8XJnd6WKGks3Q4sl28/58q7D6peqyIJfuzCkaAjsr wTg6dcLfddymi2y5Xa0ijm9ZFaVD+GsHYE6V71o0qcwwQHmHiGqFS0gA/zukIUOTix4D eAHcC3f7FWZvjgx2WivKAIZPgWQtsvVMvBm/mXoI5WXnrPk5f8OVGjILOceooYdF/0dF QSwBz+BLmAokxmaJ/2A00vyxxdsB9RQ7oVV8FmecMNoJDxTOhRAXSZsEw7sUfgOM/BVV /8Lg== X-Gm-Message-State: ACrzQf3cXkP1cE9/EOqtsvMRJto1VelOuzCTmo2rhPdRGt16DFw5FRIf Qo8ZEotJ3QIND13EJeEsy5lKJuyYwQb0LA== X-Google-Smtp-Source: AMsMyM4zFsUvxN6nAPuwWYL3K/zmKhr9UOZ0/t0ouZ/7WVlIHr46D2+Z3ja/vCZ48buZHl9/3FX/rg== X-Received: by 2002:a05:6000:186e:b0:22e:5dd3:e32a with SMTP id d14-20020a056000186e00b0022e5dd3e32amr11749231wri.167.1665412074389; Mon, 10 Oct 2022 07:27:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/28] target/arm: Fix ATS12NSO* from S PL1 Date: Mon, 10 Oct 2022 15:27:23 +0100 Message-Id: <20221010142730.502083-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665413759991100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use arm_hcr_el2_eff_secstate instead of arm_hcr_el2_eff, so that we use is_secure instead of the current security state. These AT* operations have been broken since arm_hcr_el2_eff gained a check for "el2 enabled" for Secure EL2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20221001162318.153420-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b4fd4d3fac1..a589cec8e36 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -146,7 +146,7 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx, } } =20 - hcr_el2 =3D arm_hcr_el2_eff(env); + hcr_el2 =3D arm_hcr_el2_eff_secstate(env, is_secure); =20 switch (mmu_idx) { case ARMMMUIdx_Stage2: @@ -230,7 +230,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, return ~0; } =20 - hcr =3D arm_hcr_el2_eff(env); + hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) { /* * PTW set and S1 walk touched S2 Device memory: @@ -2341,7 +2341,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, } =20 /* Combine the S1 and S2 cache attributes. */ - hcr =3D arm_hcr_el2_eff(env); + hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); if (hcr & HCR_DC) { /* * HCR.DC forces the first stage attributes to @@ -2473,7 +2473,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, result->page_size =3D TARGET_PAGE_SIZE; =20 /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ - hcr =3D arm_hcr_el2_eff(env); + hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); result->cacheattrs.shareability =3D 0; result->cacheattrs.is_s2_format =3D false; if (hcr & HCR_DC) { --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665413982; cv=none; d=zohomail.com; s=zohoarc; b=C2DZ01jCugZDfiKNNMHZ0TS4KOc6MwKkqunWEj8o7df+QMeZfSSe0TN0O47vkt9kvCcw7EZYyDQptM3Qr7cpRZLUFMVkdKRk4SzmFZ3T1u2KzVwE3cXe+8lmeF5FLTEWtw1npFWBiX6RdXYx9Eu74z0me6uOwGVVL8TwbL2g+X8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665413982; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jk1ASaw8kSfO1pJsq09u4PXDxP2Xi5DSakhp2fUnzio=; b=fwH0xpcBqqQkbNZ8Or2JsC5O/sbO/Zgy18EjegqahtW1Hg/IclVOFnhMK+vm//RN0BtJzfzORM5MSBbsUFfKtLkchwDXauJblnMFWLE2jVwDFzZXCsi3uXoqqCf5jRLdh5DaI1RzRO3PKAGXOP5x4ww7w+RAJZHXHg+krAyH6b8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665413982041702.4900331588536; Mon, 10 Oct 2022 07:59:42 -0700 (PDT) Received: from localhost ([::1]:43082 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohuFn-0007Fz-M3 for importer@patchew.org; Mon, 10 Oct 2022 10:59:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60088) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtl8-0006UR-DN for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:58 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:47075) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtl6-0005YG-BF for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:58 -0400 Received: by mail-wr1-x42b.google.com with SMTP id bk15so17272521wrb.13 for ; Mon, 10 Oct 2022 07:27:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=jk1ASaw8kSfO1pJsq09u4PXDxP2Xi5DSakhp2fUnzio=; b=WI2qe6kiK0y/EC7iXuciQzZs43mNUZZm8JfkBQwk1sT67eLFXbRfd75+jvv6vx2Tl0 XKmsjIy0X32B7ve/+VLUZVi7G/P8wC1l2KiKU2PfyiWnNOFBoHsnQk4cPpg5br0xwteq Rvw8jqNquyDMkX9XyS/6W7O4GdNa1hHRLv9zneSnULpGSgeZAuEI8hVv0xecSVynazag FTIKnkh9hR5n1IGBGfLZBdpAhfr+hD6QE0Ia4jg9CMMOuF6x/eX8PA4jfJ/JIoUUOgoy WwZ7cUKKzLbpqEZqPQbeP6cOU7aoVsBqvhjqQxb6OqyK8ud37trXbg7INoBwSSt7RZpc dF2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jk1ASaw8kSfO1pJsq09u4PXDxP2Xi5DSakhp2fUnzio=; b=oDg0YWJmGhaQQo3YNcEXzpeAyfPVomGhusfB7rGSpFUCOZkWxETPftNe5eTqHOyB/z YM2bS+DxPe6h9WAstsLVtk3Nz5I1ezJDGCDvZEObM1uw1+TXdh6FkIB+FdMzVgNgqOK9 2jMcSQE4S01hmztTo8/Sl2Coq979W7JHz6qimm4AVTUi3FF6zJZfo8A40YyUHOkPIhH3 ER7uyWJBIgv4fNIEDd9qfZmcCnVftD4hiCPYrR2ROfSddKtlCzxgU4qvkynfYhPy0yG2 BwfdePxXy9LREC9OHFXu/lNUxtK5lcTWQP4Hi/b8D8iiHTrkJO+QXv+8PmQsFwTXBde4 MsIA== X-Gm-Message-State: ACrzQf1DixD/jxF6dwua0CJEzeKfBQw8TLuoPKbosyPRHVNBpGuCEJ8G kEEVnoNhFLvUVG/iGBg8lNwNE+mMcWfhpQ== X-Google-Smtp-Source: AMsMyM6LC1vMvqMMu9AFh4HOxtmN9VKMLXUHchKnEWRDlcQBinxedb0+e8gIXLYPVEM0yBfpOOUztQ== X-Received: by 2002:a5d:6442:0:b0:22e:2c71:fdac with SMTP id d2-20020a5d6442000000b0022e2c71fdacmr11088674wrw.243.1665412075392; Mon, 10 Oct 2022 07:27:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/28] target/arm: Split out get_phys_addr_disabled Date: Mon, 10 Oct 2022 15:27:24 +0100 Message-Id: <20221010142730.502083-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665413983936100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20221001162318.153420-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 138 +++++++++++++++++++++++++---------------------- 1 file changed, 74 insertions(+), 64 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a589cec8e36..96ab99c7b6f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2272,6 +2272,78 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, return ret; } =20 +/* + * MMU disabled. S1 addresses within aa64 translation regimes are + * still checked for bounds -- see AArch64.S1DisabledOutput(). + */ +static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, bool is_secure, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) +{ + uint64_t hcr; + uint8_t memattr; + + if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2_S) { + int r_el =3D regime_el(env, mmu_idx); + if (arm_el_is_aa64(env, r_el)) { + int pamax =3D arm_pamax(env_archcpu(env)); + uint64_t tcr =3D env->cp15.tcr_el[r_el]; + int addrtop, tbi; + + tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); + if (access_type =3D=3D MMU_INST_FETCH) { + tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); + } + tbi =3D (tbi >> extract64(address, 55, 1)) & 1; + addrtop =3D (tbi ? 55 : 63); + + if (extract64(address, pamax, addrtop - pamax + 1) !=3D 0) { + fi->type =3D ARMFault_AddressSize; + fi->level =3D 0; + fi->stage2 =3D false; + return 1; + } + + /* + * When TBI is disabled, we've just validated that all of the + * bits above PAMax are zero, so logically we only need to + * clear the top byte for TBI. But it's clearer to follow + * the pseudocode set of addrdesc.paddress. + */ + address =3D extract64(address, 0, 52); + } + } + + result->phys =3D address; + result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->page_size =3D TARGET_PAGE_SIZE; + + /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ + hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); + result->cacheattrs.shareability =3D 0; + result->cacheattrs.is_s2_format =3D false; + if (hcr & HCR_DC) { + if (hcr & HCR_DCT) { + memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ + } else { + memattr =3D 0xff; /* Normal, WB, RWA */ + } + } else if (access_type =3D=3D MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr =3D 0xee; /* Normal, WT, RA, NT */ + } else { + memattr =3D 0x44; /* Normal, NC, No */ + } + result->cacheattrs.shareability =3D 2; /* outer sharable */ + } else { + memattr =3D 0x00; /* Device, nGnRnE */ + } + result->cacheattrs.attrs =3D memattr; + return 0; +} + bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, bool is_secure, GetPhysAddrResult *result, @@ -2431,71 +2503,9 @@ bool get_phys_addr_with_secure(CPUARMState *env, tar= get_ulong address, /* Definitely a real MMU, not an MPU */ =20 if (regime_translation_disabled(env, mmu_idx, is_secure)) { - uint64_t hcr; - uint8_t memattr; - - /* - * MMU disabled. S1 addresses within aa64 translation regimes are - * still checked for bounds -- see AArch64.TranslateAddressS1Off. - */ - if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2= _S) { - int r_el =3D regime_el(env, mmu_idx); - if (arm_el_is_aa64(env, r_el)) { - int pamax =3D arm_pamax(env_archcpu(env)); - uint64_t tcr =3D env->cp15.tcr_el[r_el]; - int addrtop, tbi; - - tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); - if (access_type =3D=3D MMU_INST_FETCH) { - tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); - } - tbi =3D (tbi >> extract64(address, 55, 1)) & 1; - addrtop =3D (tbi ? 55 : 63); - - if (extract64(address, pamax, addrtop - pamax + 1) !=3D 0)= { - fi->type =3D ARMFault_AddressSize; - fi->level =3D 0; - fi->stage2 =3D false; - return 1; - } - - /* - * When TBI is disabled, we've just validated that all of = the - * bits above PAMax are zero, so logically we only need to - * clear the top byte for TBI. But it's clearer to follow - * the pseudocode set of addrdesc.paddress. - */ - address =3D extract64(address, 0, 52); - } - } - result->phys =3D address; - result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - result->page_size =3D TARGET_PAGE_SIZE; - - /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ - hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); - result->cacheattrs.shareability =3D 0; - result->cacheattrs.is_s2_format =3D false; - if (hcr & HCR_DC) { - if (hcr & HCR_DCT) { - memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ - } else { - memattr =3D 0xff; /* Normal, WB, RWA */ - } - } else if (access_type =3D=3D MMU_INST_FETCH) { - if (regime_sctlr(env, mmu_idx) & SCTLR_I) { - memattr =3D 0xee; /* Normal, WT, RA, NT */ - } else { - memattr =3D 0x44; /* Normal, NC, No */ - } - result->cacheattrs.shareability =3D 2; /* outer sharable */ - } else { - memattr =3D 0x00; /* Device, nGnRnE */ - } - result->cacheattrs.attrs =3D memattr; - return 0; + return get_phys_addr_disabled(env, address, access_type, mmu_idx, + is_secure, result, fi); } - if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, is_secure, false, result, fi); --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665413761; cv=none; d=zohomail.com; s=zohoarc; b=g9RVNvnEgibgq18Y93FKgzi0nBM8clwaSZfrFeh5wcOyPEGsAwbT8EveDFMykcy6Ny1qldBXhjpagMSPYufhMkcm2B5iwU3YWO+LehtcNGsMiAKkmnK8SWNj1n/VAsu4Mj1k4BL/dxK8BwJCHQI3rsRmIINsXTLT2eCRHEtw3wQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665413761; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uYAkUC1FMKDAZVTYLTGfkDMxAgY5msooi2W/EbleAk8=; b=C7RHB2O0SUsPOiJ0FvP519Vm0xUXHx2iVOhLBupytHR2tycFnN4VDIJ1EVXPB9Un0h3P3FOTI3p+Wj+mfdBchlA0VJETSMhSddCeevy01LyvuADGxE4rZYqSJXz1ZGn0zcR/ISJWIK1TPANQ37eWAGVWhakUHoc7oQTdgoBafNI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665413761125534.6832622032841; Mon, 10 Oct 2022 07:56:01 -0700 (PDT) Received: from localhost ([::1]:39622 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohuCF-0001G1-Sa for importer@patchew.org; Mon, 10 Oct 2022 10:55:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60090) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtl9-0006V7-BI for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:59 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:35609) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtl7-0005X6-Md for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:27:59 -0400 Received: by mail-wr1-x42e.google.com with SMTP id u10so17326670wrq.2 for ; Mon, 10 Oct 2022 07:27:56 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=uYAkUC1FMKDAZVTYLTGfkDMxAgY5msooi2W/EbleAk8=; b=a5toCK5D90RjDRU5Rtffi+lIWAIcjGH1vveQqSn4DXu3eVLmb7b4aed8aYQ+uXRhpA 759lL5qO8iVS3k356LiWLVRi1o4OmWyAEV0y3UnJ8AHSsrfu7hFsi+ozJ1FguYdNsIFK vNlljongbT7JVaYWxYwFSbuQkA1kwZDc+EY6iWpewyJ97I3stLinz/k5NAhW0g84LEV2 Ke7FJ6bQimgOxAKZvEZySJgR3Uad5FOYYVOR9i17uLm81hG1ReSU+FGTKG8eoPE65Axs VkRRCc1lpoTyp/NUMWuuwSNaW9yrmnlOzyre8wRiucxKauPll085BqyESsifKKHKI4Gi aRng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uYAkUC1FMKDAZVTYLTGfkDMxAgY5msooi2W/EbleAk8=; b=mpIUdFu8h/uACn6WxjRLR/ZNwuPvRKU38QJV0Z0ZJqAuqf6DfLs+S8q//FqcTZZCxN 7rGPHUZApzlIhEG/PY5ugeKrwfB9Q8few8qcsg9mY7Ka3JYTzNddaU62xOQQirc7//LY jnr7ARFlglAQ8Zoj0xmCxHkRru8bjbzCQtHvGSnKKBaQEsjMv2Iu0Iz5nvPrWx+RPX/5 Sg/v4SuFXVN9pFYcTsz29pSl9Tld951RdIxK+Cj60k8G/cOpSZ41FqOh2sUJb++V+H1z Po/WAulNFBfd328dJdsSS7q27OYNkmji1OysIQhHiqnDNWqATucQOj75N+OjrH/vjHIY DISQ== X-Gm-Message-State: ACrzQf26REInijkElCXaeFh4Q7aQNNQlUUwPikVISXE3UcbeHxC+51iP c2Y0HjR7YdQeNFhoO8bzySP9XbaUAVT1cw== X-Google-Smtp-Source: AMsMyM6Qth4reBi+qM92vPoeIFwN/O/mJRDNGUM1A7bLX6N2sKEnSTjmjazdnJEZfLHHdQ/BWlRwfg== X-Received: by 2002:adf:f14b:0:b0:22e:f162:f728 with SMTP id y11-20020adff14b000000b0022ef162f728mr9053710wro.681.1665412076338; Mon, 10 Oct 2022 07:27:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/28] target/arm: Fix cacheattr in get_phys_addr_disabled Date: Mon, 10 Oct 2022 15:27:25 +0100 Message-Id: <20221010142730.502083-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665413761914100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Do not apply memattr or shareability for Stage2 translations. Make sure to apply HCR_{DC,DCT} only to Regime_EL10, per the pseudocode in AArch64.S1DisabledOutput. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20221001162318.153420-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 48 +++++++++++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 23 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 96ab99c7b6f..15c37b52c97 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2282,11 +2282,12 @@ static bool get_phys_addr_disabled(CPUARMState *env= , target_ulong address, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - uint64_t hcr; - uint8_t memattr; + uint8_t memattr =3D 0x00; /* Device nGnRnE */ + uint8_t shareability =3D 0; /* non-sharable */ =20 if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2_S) { int r_el =3D regime_el(env, mmu_idx); + if (arm_el_is_aa64(env, r_el)) { int pamax =3D arm_pamax(env_archcpu(env)); uint64_t tcr =3D env->cp15.tcr_el[r_el]; @@ -2314,32 +2315,33 @@ static bool get_phys_addr_disabled(CPUARMState *env= , target_ulong address, */ address =3D extract64(address, 0, 52); } + + /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ + if (r_el =3D=3D 1) { + uint64_t hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); + if (hcr & HCR_DC) { + if (hcr & HCR_DCT) { + memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ + } else { + memattr =3D 0xff; /* Normal, WB, RWA */ + } + } + } + if (memattr =3D=3D 0 && access_type =3D=3D MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr =3D 0xee; /* Normal, WT, RA, NT */ + } else { + memattr =3D 0x44; /* Normal, NC, No */ + } + shareability =3D 2; /* outer sharable */ + } + result->cacheattrs.is_s2_format =3D false; } =20 result->phys =3D address; result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; result->page_size =3D TARGET_PAGE_SIZE; - - /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ - hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); - result->cacheattrs.shareability =3D 0; - result->cacheattrs.is_s2_format =3D false; - if (hcr & HCR_DC) { - if (hcr & HCR_DCT) { - memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ - } else { - memattr =3D 0xff; /* Normal, WB, RWA */ - } - } else if (access_type =3D=3D MMU_INST_FETCH) { - if (regime_sctlr(env, mmu_idx) & SCTLR_I) { - memattr =3D 0xee; /* Normal, WT, RA, NT */ - } else { - memattr =3D 0x44; /* Normal, NC, No */ - } - result->cacheattrs.shareability =3D 2; /* outer sharable */ - } else { - memattr =3D 0x00; /* Device, nGnRnE */ - } + result->cacheattrs.shareability =3D shareability; result->cacheattrs.attrs =3D memattr; return 0; } --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665412989; cv=none; d=zohomail.com; s=zohoarc; b=MfnXqCQV2hwU54XLfpzj9AmtLPWib7MzE1EpZ1IN7nYHg53ik3XgyEfKHNoy58I5SMGQvY6GIc2n2EHGTWZh3JAuqgWmgZaNOF5mKHobNbG/WVB3ztdPzZ8nPePSIeYFomKzIASQoaFr6rw3bT5Utc5FOvWpmR7sBVCm86v/tX0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665412989; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3s+FyWiCaE2Ik3+lgb9MwwUIPvJVHRPhFGnB5s7T1cU=; b=O+k5bnxZl/lkYbcMQaOLFpwJnisfGxNB4wKh7/RxFrot/S5CckzYVscZUIWr1gVevQ7+tHEEP1jy40QYz0M8Nx2MsXacE4zPvhh397uknaRck+AyokGxZgJ6SurXOhe9vjrjMwBUvmzFSTr+lPsKOvM3XhEcvcmmpxCXOIGAP/k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665412989208952.1692278704851; Mon, 10 Oct 2022 07:43:09 -0700 (PDT) Received: from localhost ([::1]:44012 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohtzm-0000iA-BK for importer@patchew.org; Mon, 10 Oct 2022 10:43:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60096) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtlD-0006bz-IG for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:28:03 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:54254) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtl9-0005bp-9V for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:28:03 -0400 Received: by mail-wm1-x32f.google.com with SMTP id e18so6939615wmq.3 for ; Mon, 10 Oct 2022 07:27:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3s+FyWiCaE2Ik3+lgb9MwwUIPvJVHRPhFGnB5s7T1cU=; b=HXCjUijpTqCY55BXOAZGzQPaNyq6BBPhBHJFfO4brSNx9xc4X9RsByeJtNsHkbb1Ld GNzlMWjKbJUukDPd4RG3IRbWre4eerTnt8sx73NyKzn+Iz/WkFK/o2Agf0h4v8Bipxqm meaZf+sBELQHRsmarv+AMGqGwNF6ULlBrDxSohq/TX5RN5v3Qmp+MfmoYrs9dA/PE6iK aeu8RJN+UHuqY75QnHaRk6kwy78MMSnaho+YiolgtzHItpXsU+jXcd4qMybgOLWqIhkl tKnuWZSZ82GCLAccT3jS1BpUChBeEpdj/+VCQ2m1zFgDtPlcSzLl5Emj8YUTNzRAPox3 hz2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3s+FyWiCaE2Ik3+lgb9MwwUIPvJVHRPhFGnB5s7T1cU=; b=zKCO7SXpfKrhdl9+7lVu/7j7AdJ2g4caTg/AskdvVfzglDuO+1WAYEiM0b07z9i1VT YE8E3yQ92FEEtwDTRXcUD+D9Kk48Bois3tE+tcAn4CLFE1E8xJzSoPCbZpF2QcMnuqv2 sDPCU+mIzzOcvz8hEEygZX/T8WscGFFGRPkNyjrGSw0Ig86APKQScwc94ga6mLAAEV1E mVlh5EvUNgAa33AW8CU+GgYUrpixOcN7vNCQ1+UTMm5ZX6vMlDIlApF/R1DFhby3hDE9 7P7G3nR5oydLTx5F4Qul1ZvbRLVGKTlc9CMuDOXjlf9tuIDv+yAAzbGUpImYhqNdG3bN Nm3w== X-Gm-Message-State: ACrzQf1jOYxSMYPjaMDQh1Dl6qlPWLhKQ89KRS3DoNJDWF4oPzPOAq9g mLVG8nJxfwOzovwOwVFjz7/5Ou0FFgXI5Q== X-Google-Smtp-Source: AMsMyM40p194Hwl/Dtjczj3LU2/ADUfQmIw4tfRQPzGVPBO1/wYCZ9gIDMd2YuaIYNOccqSJiCx3lw== X-Received: by 2002:a05:600c:3b8f:b0:3b4:9cdc:dbd8 with SMTP id n15-20020a05600c3b8f00b003b49cdcdbd8mr12763691wms.148.1665412077741; Mon, 10 Oct 2022 07:27:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/28] target/arm: Use tlb_set_page_full Date: Mon, 10 Oct 2022 15:27:26 +0100 Message-Id: <20221010142730.502083-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665412989548100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Adjust GetPhysAddrResult to fill in CPUTLBEntryFull, so that it may be passed directly to tlb_set_page_full. The change is large, but mostly mechanical. The major non-mechanical change is page_size -> lg_page_size. Most of the time this is obvious, and is related to TARGET_PAGE_BITS. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20221001162318.153420-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 5 +- target/arm/helper.c | 12 +-- target/arm/m_helper.c | 20 ++--- target/arm/ptw.c | 179 ++++++++++++++++++++-------------------- target/arm/tlb_helper.c | 9 +- 5 files changed, 111 insertions(+), 114 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index b509d708514..fd17aee4599 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1071,10 +1071,7 @@ typedef struct ARMCacheAttrs { =20 /* Fields that are valid upon success. */ typedef struct GetPhysAddrResult { - hwaddr phys; - target_ulong page_size; - int prot; - MemTxAttrs attrs; + CPUTLBEntryFull f; ARMCacheAttrs cacheattrs; } GetPhysAddrResult; =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index f1266bb1579..e1338ed6e22 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3323,8 +3323,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, /* Create a 64-bit PAR */ par64 =3D (1 << 11); /* LPAE bit always set */ if (!ret) { - par64 |=3D res.phys & ~0xfffULL; - if (!res.attrs.secure) { + par64 |=3D res.f.phys_addr & ~0xfffULL; + if (!res.f.attrs.secure) { par64 |=3D (1 << 9); /* NS */ } par64 |=3D (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */ @@ -3348,13 +3348,13 @@ static uint64_t do_ats_write(CPUARMState *env, uint= 64_t value, */ if (!ret) { /* We do not set any attribute bits in the PAR */ - if (res.page_size =3D=3D (1 << 24) + if (res.f.lg_page_size =3D=3D 24 && arm_feature(env, ARM_FEATURE_V7)) { - par64 =3D (res.phys & 0xff000000) | (1 << 1); + par64 =3D (res.f.phys_addr & 0xff000000) | (1 << 1); } else { - par64 =3D res.phys & 0xfffff000; + par64 =3D res.f.phys_addr & 0xfffff000; } - if (!res.attrs.secure) { + if (!res.f.attrs.secure) { par64 |=3D (1 << 9); /* NS */ } } else { diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 203ba411f64..355cd4d60a7 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -223,8 +223,8 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr,= uint32_t value, } goto pend_fault; } - address_space_stl_le(arm_addressspace(cs, res.attrs), res.phys, value, - res.attrs, &txres); + address_space_stl_le(arm_addressspace(cs, res.f.attrs), res.f.phys_add= r, + value, res.f.attrs, &txres); if (txres !=3D MEMTX_OK) { /* BusFault trying to write the data */ if (mode =3D=3D STACK_LAZYFP) { @@ -298,8 +298,8 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest,= uint32_t addr, goto pend_fault; } =20 - value =3D address_space_ldl(arm_addressspace(cs, res.attrs), res.phys, - res.attrs, &txres); + value =3D address_space_ldl(arm_addressspace(cs, res.f.attrs), + res.f.phys_addr, res.f.attrs, &txres); if (txres !=3D MEMTX_OK) { /* BusFault trying to read the data */ qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n"); @@ -2022,8 +2022,8 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, bool secure, qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL= \n"); return false; } - *insn =3D address_space_lduw_le(arm_addressspace(cs, res.attrs), res.p= hys, - res.attrs, &txres); + *insn =3D address_space_lduw_le(arm_addressspace(cs, res.f.attrs), + res.f.phys_addr, res.f.attrs, &txres); if (txres !=3D MEMTX_OK) { env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_IBUSERR_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); @@ -2069,8 +2069,8 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMM= UIdx mmu_idx, } return false; } - value =3D address_space_ldl(arm_addressspace(cs, res.attrs), res.phys, - res.attrs, &txres); + value =3D address_space_ldl(arm_addressspace(cs, res.f.attrs), + res.f.phys_addr, res.f.attrs, &txres); if (txres !=3D MEMTX_OK) { /* BusFault trying to read the data */ qemu_log_mask(CPU_LOG_INT, @@ -2817,8 +2817,8 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t ad= dr, uint32_t op) } else { mrvalid =3D true; } - r =3D res.prot & PAGE_READ; - rw =3D res.prot & PAGE_WRITE; + r =3D res.f.prot & PAGE_READ; + rw =3D res.f.prot & PAGE_WRITE; } else { r =3D false; rw =3D false; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 15c37b52c97..ddacffa7ee6 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -256,7 +256,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, assert(!is_secure); } =20 - addr =3D s2.phys; + addr =3D s2.f.phys_addr; } return addr; } @@ -476,7 +476,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, /* 1Mb section. */ phys_addr =3D (desc & 0xfff00000) | (address & 0x000fffff); ap =3D (desc >> 10) & 3; - result->page_size =3D 1024 * 1024; + result->f.lg_page_size =3D 20; /* 1MB */ } else { /* Lookup l2 entry. */ if (type =3D=3D 1) { @@ -497,12 +497,12 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32= _t address, case 1: /* 64k page. */ phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); ap =3D (desc >> (4 + ((address >> 13) & 6))) & 3; - result->page_size =3D 0x10000; + result->f.lg_page_size =3D 16; break; case 2: /* 4k page. */ phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); ap =3D (desc >> (4 + ((address >> 9) & 6))) & 3; - result->page_size =3D 0x1000; + result->f.lg_page_size =3D 12; break; case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ if (type =3D=3D 1) { @@ -510,7 +510,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, if (arm_feature(env, ARM_FEATURE_XSCALE) || arm_feature(env, ARM_FEATURE_V6)) { phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); - result->page_size =3D 0x1000; + result->f.lg_page_size =3D 12; } else { /* * UNPREDICTABLE in ARMv5; we choose to take a @@ -521,7 +521,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, } } else { phys_addr =3D (desc & 0xfffffc00) | (address & 0x3ff); - result->page_size =3D 0x400; + result->f.lg_page_size =3D 10; } ap =3D (desc >> 4) & 3; break; @@ -530,14 +530,14 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32= _t address, g_assert_not_reached(); } } - result->prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); - result->prot |=3D result->prot ? PAGE_EXEC : 0; - if (!(result->prot & (1 << access_type))) { + result->f.prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + result->f.prot |=3D result->f.prot ? PAGE_EXEC : 0; + if (!(result->f.prot & (1 << access_type))) { /* Access permission fault. */ fi->type =3D ARMFault_Permission; goto do_fault; } - result->phys =3D phys_addr; + result->f.phys_addr =3D phys_addr; return false; do_fault: fi->domain =3D domain; @@ -607,11 +607,11 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, phys_addr =3D (desc & 0xff000000) | (address & 0x00ffffff); phys_addr |=3D (uint64_t)extract32(desc, 20, 4) << 32; phys_addr |=3D (uint64_t)extract32(desc, 5, 4) << 36; - result->page_size =3D 0x1000000; + result->f.lg_page_size =3D 24; /* 16MB */ } else { /* Section. */ phys_addr =3D (desc & 0xfff00000) | (address & 0x000fffff); - result->page_size =3D 0x100000; + result->f.lg_page_size =3D 20; /* 1MB */ } ap =3D ((desc >> 10) & 3) | ((desc >> 13) & 4); xn =3D desc & (1 << 4); @@ -636,12 +636,12 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, case 1: /* 64k page. */ phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); xn =3D desc & (1 << 15); - result->page_size =3D 0x10000; + result->f.lg_page_size =3D 16; break; case 2: case 3: /* 4k page. */ phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); xn =3D desc & 1; - result->page_size =3D 0x1000; + result->f.lg_page_size =3D 12; break; default: /* Never happens, but compiler isn't smart enough to tell. */ @@ -649,7 +649,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, } } if (domain_prot =3D=3D 3) { - result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->f.prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; } else { if (pxn && !regime_is_user(env, mmu_idx)) { xn =3D 1; @@ -667,14 +667,14 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, fi->type =3D ARMFault_AccessFlag; goto do_fault; } - result->prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); + result->f.prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); } else { - result->prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + result->f.prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot= ); } - if (result->prot && !xn) { - result->prot |=3D PAGE_EXEC; + if (result->f.prot && !xn) { + result->f.prot |=3D PAGE_EXEC; } - if (!(result->prot & (1 << access_type))) { + if (!(result->f.prot & (1 << access_type))) { /* Access permission fault. */ fi->type =3D ARMFault_Permission; goto do_fault; @@ -685,9 +685,9 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, * the CPU doesn't support TZ or this is a non-secure translation * regime, because the attribute will already be non-secure. */ - result->attrs.secure =3D false; + result->f.attrs.secure =3D false; } - result->phys =3D phys_addr; + result->f.phys_addr =3D phys_addr; return false; do_fault: fi->domain =3D domain; @@ -1298,16 +1298,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { ns =3D mmu_idx =3D=3D ARMMMUIdx_Stage2; xn =3D extract32(attrs, 11, 2); - result->prot =3D get_S2prot(env, ap, xn, s1_is_el0); + result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); } else { ns =3D extract32(attrs, 3, 1); xn =3D extract32(attrs, 12, 1); pxn =3D extract32(attrs, 11, 1); - result->prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn= ); + result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, p= xn); } =20 fault_type =3D ARMFault_Permission; - if (!(result->prot & (1 << access_type))) { + if (!(result->f.prot & (1 << access_type))) { goto do_fault; } =20 @@ -1317,11 +1317,11 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, * the CPU doesn't support TZ or this is a non-secure translation * regime, because the attribute will already be non-secure. */ - result->attrs.secure =3D false; + result->f.attrs.secure =3D false; } /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB.= */ if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { - arm_tlb_bti_gp(&result->attrs) =3D true; + arm_tlb_bti_gp(&result->f.attrs) =3D true; } =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { @@ -1347,8 +1347,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, result->cacheattrs.shareability =3D extract32(attrs, 6, 2); } =20 - result->phys =3D descaddr; - result->page_size =3D page_size; + result->f.phys_addr =3D descaddr; + result->f.lg_page_size =3D ctz64(page_size); return false; =20 do_fault: @@ -1373,12 +1373,12 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, =20 if (regime_translation_disabled(env, mmu_idx, is_secure)) { /* MPU disabled. */ - result->phys =3D address; - result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->f.phys_addr =3D address; + result->f.prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return false; } =20 - result->phys =3D address; + result->f.phys_addr =3D address; for (n =3D 7; n >=3D 0; n--) { base =3D env->cp15.c6_region[n]; if ((base & 1) =3D=3D 0) { @@ -1414,16 +1414,16 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, fi->level =3D 1; return true; } - result->prot =3D PAGE_READ | PAGE_WRITE; + result->f.prot =3D PAGE_READ | PAGE_WRITE; break; case 2: - result->prot =3D PAGE_READ; + result->f.prot =3D PAGE_READ; if (!is_user) { - result->prot |=3D PAGE_WRITE; + result->f.prot |=3D PAGE_WRITE; } break; case 3: - result->prot =3D PAGE_READ | PAGE_WRITE; + result->f.prot =3D PAGE_READ | PAGE_WRITE; break; case 5: if (is_user) { @@ -1431,10 +1431,10 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, fi->level =3D 1; return true; } - result->prot =3D PAGE_READ; + result->f.prot =3D PAGE_READ; break; case 6: - result->prot =3D PAGE_READ; + result->f.prot =3D PAGE_READ; break; default: /* Bad permission. */ @@ -1442,12 +1442,12 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, fi->level =3D 1; return true; } - result->prot |=3D PAGE_EXEC; + result->f.prot |=3D PAGE_EXEC; return false; } =20 static void get_phys_addr_pmsav7_default(CPUARMState *env, ARMMMUIdx mmu_i= dx, - int32_t address, int *prot) + int32_t address, uint8_t *prot) { if (!arm_feature(env, ARM_FEATURE_M)) { *prot =3D PAGE_READ | PAGE_WRITE; @@ -1531,9 +1531,9 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, int n; bool is_user =3D regime_is_user(env, mmu_idx); =20 - result->phys =3D address; - result->page_size =3D TARGET_PAGE_SIZE; - result->prot =3D 0; + result->f.phys_addr =3D address; + result->f.lg_page_size =3D TARGET_PAGE_BITS; + result->f.prot =3D 0; =20 if (regime_translation_disabled(env, mmu_idx, secure) || m_is_ppb_region(env, address)) { @@ -1545,7 +1545,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, * which always does a direct read using address_space_ldl(), rath= er * than going via this function, so we don't need to check that he= re. */ - get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot); + get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.pro= t); } else { /* MPU enabled */ for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { /* region search */ @@ -1587,7 +1587,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, if (ranges_overlap(base, rmask, address & TARGET_PAGE_MASK, TARGET_PAGE_SIZE)) { - result->page_size =3D 1; + result->f.lg_page_size =3D 0; } continue; } @@ -1625,7 +1625,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, continue; } if (rsize < TARGET_PAGE_BITS) { - result->page_size =3D 1 << rsize; + result->f.lg_page_size =3D rsize; } break; } @@ -1636,7 +1636,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, fi->type =3D ARMFault_Background; return true; } - get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->p= rot); + get_phys_addr_pmsav7_default(env, mmu_idx, address, + &result->f.prot); } else { /* a MPU hit! */ uint32_t ap =3D extract32(env->pmsav7.dracr[n], 8, 3); uint32_t xn =3D extract32(env->pmsav7.dracr[n], 12, 1); @@ -1653,16 +1654,16 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, case 5: break; /* no access */ case 3: - result->prot |=3D PAGE_WRITE; + result->f.prot |=3D PAGE_WRITE; /* fall through */ case 2: case 6: - result->prot |=3D PAGE_READ | PAGE_EXEC; + result->f.prot |=3D PAGE_READ | PAGE_EXEC; break; case 7: /* for v7M, same as 6; for R profile a reserved value = */ if (arm_feature(env, ARM_FEATURE_M)) { - result->prot |=3D PAGE_READ | PAGE_EXEC; + result->f.prot |=3D PAGE_READ | PAGE_EXEC; break; } /* fall through */ @@ -1678,16 +1679,16 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, case 1: case 2: case 3: - result->prot |=3D PAGE_WRITE; + result->f.prot |=3D PAGE_WRITE; /* fall through */ case 5: case 6: - result->prot |=3D PAGE_READ | PAGE_EXEC; + result->f.prot |=3D PAGE_READ | PAGE_EXEC; break; case 7: /* for v7M, same as 6; for R profile a reserved value = */ if (arm_feature(env, ARM_FEATURE_M)) { - result->prot |=3D PAGE_READ | PAGE_EXEC; + result->f.prot |=3D PAGE_READ | PAGE_EXEC; break; } /* fall through */ @@ -1700,14 +1701,14 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, =20 /* execute never */ if (xn) { - result->prot &=3D ~PAGE_EXEC; + result->f.prot &=3D ~PAGE_EXEC; } } } =20 fi->type =3D ARMFault_Permission; fi->level =3D 1; - return !(result->prot & (1 << access_type)); + return !(result->f.prot & (1 << access_type)); } =20 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, @@ -1733,9 +1734,9 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, uint32_t addr_page_base =3D address & TARGET_PAGE_MASK; uint32_t addr_page_limit =3D addr_page_base + (TARGET_PAGE_SIZE - 1); =20 - result->page_size =3D TARGET_PAGE_SIZE; - result->phys =3D address; - result->prot =3D 0; + result->f.lg_page_size =3D TARGET_PAGE_BITS; + result->f.phys_addr =3D address; + result->f.prot =3D 0; if (mregion) { *mregion =3D -1; } @@ -1785,13 +1786,13 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, ranges_overlap(base, limit - base + 1, addr_page_base, TARGET_PAGE_SIZE)) { - result->page_size =3D 1; + result->f.lg_page_size =3D 0; } continue; } =20 if (base > addr_page_base || limit < addr_page_limit) { - result->page_size =3D 1; + result->f.lg_page_size =3D 0; } =20 if (matchregion !=3D -1) { @@ -1817,7 +1818,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, =20 if (matchregion =3D=3D -1) { /* hit using the background region */ - get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot); + get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.pro= t); } else { uint32_t ap =3D extract32(env->pmsav8.rbar[secure][matchregion], 1= , 2); uint32_t xn =3D extract32(env->pmsav8.rbar[secure][matchregion], 0= , 1); @@ -1832,9 +1833,9 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, xn =3D 1; } =20 - result->prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); - if (result->prot && !xn && !(pxn && !is_user)) { - result->prot |=3D PAGE_EXEC; + result->f.prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); + if (result->f.prot && !xn && !(pxn && !is_user)) { + result->f.prot |=3D PAGE_EXEC; } /* * We don't need to look the attribute up in the MAIR0/MAIR1 @@ -1847,7 +1848,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, =20 fi->type =3D ARMFault_Permission; fi->level =3D 1; - return !(result->prot & (1 << access_type)); + return !(result->f.prot & (1 << access_type)); } =20 static bool v8m_is_sau_exempt(CPUARMState *env, @@ -2011,9 +2012,9 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, } else { fi->type =3D ARMFault_QEMU_SFault; } - result->page_size =3D sattrs.subpage ? 1 : TARGET_PAGE_SIZ= E; - result->phys =3D address; - result->prot =3D 0; + result->f.lg_page_size =3D sattrs.subpage ? 0 : TARGET_PAG= E_BITS; + result->f.phys_addr =3D address; + result->f.prot =3D 0; return true; } } else { @@ -2023,7 +2024,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, * might downgrade a secure access to nonsecure. */ if (sattrs.ns) { - result->attrs.secure =3D false; + result->f.attrs.secure =3D false; } else if (!secure) { /* * NS access to S memory must fault. @@ -2036,9 +2037,9 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). */ fi->type =3D ARMFault_QEMU_SFault; - result->page_size =3D sattrs.subpage ? 1 : TARGET_PAGE_SIZ= E; - result->phys =3D address; - result->prot =3D 0; + result->f.lg_page_size =3D sattrs.subpage ? 0 : TARGET_PAG= E_BITS; + result->f.phys_addr =3D address; + result->f.prot =3D 0; return true; } } @@ -2047,7 +2048,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, ret =3D pmsav8_mpu_lookup(env, address, access_type, mmu_idx, secure, result, fi, NULL); if (sattrs.subpage) { - result->page_size =3D 1; + result->f.lg_page_size =3D 0; } return ret; } @@ -2338,9 +2339,9 @@ static bool get_phys_addr_disabled(CPUARMState *env, = target_ulong address, result->cacheattrs.is_s2_format =3D false; } =20 - result->phys =3D address; - result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - result->page_size =3D TARGET_PAGE_SIZE; + result->f.phys_addr =3D address; + result->f.prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->f.lg_page_size =3D TARGET_PAGE_BITS; result->cacheattrs.shareability =3D shareability; result->cacheattrs.attrs =3D memattr; return 0; @@ -2377,8 +2378,8 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, return ret; } =20 - ipa =3D result->phys; - ipa_secure =3D result->attrs.secure; + ipa =3D result->f.phys_addr; + ipa_secure =3D result->f.attrs.secure; if (is_secure) { /* Select TCR based on the NS bit from the S1 walk. */ s2walk_secure =3D !(ipa_secure @@ -2398,7 +2399,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, * Save the stage1 results so that we may merge * prot and cacheattrs later. */ - s1_prot =3D result->prot; + s1_prot =3D result->f.prot; cacheattrs1 =3D result->cacheattrs; memset(result, 0, sizeof(*result)); =20 @@ -2407,7 +2408,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ - result->prot &=3D s1_prot; + result->f.prot &=3D s1_prot; =20 /* If S2 fails, return early. */ if (ret) { @@ -2436,7 +2437,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, * Check if IPA translates to secure or non-secure PA space. * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA. */ - result->attrs.secure =3D + result->f.attrs.secure =3D (is_secure && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)) && (ipa_secure @@ -2456,8 +2457,8 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, * cannot upgrade an non-secure translation regime's attributes * to secure. */ - result->attrs.secure =3D is_secure; - result->attrs.user =3D regime_is_user(env, mmu_idx); + result->f.attrs.secure =3D is_secure; + result->f.attrs.user =3D regime_is_user(env, mmu_idx); =20 /* * Fast Context Switch Extension. This doesn't exist at all in v8. @@ -2474,7 +2475,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, =20 if (arm_feature(env, ARM_FEATURE_PMSA)) { bool ret; - result->page_size =3D TARGET_PAGE_SIZE; + result->f.lg_page_size =3D TARGET_PAGE_BITS; =20 if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ @@ -2495,9 +2496,9 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, (access_type =3D=3D MMU_DATA_STORE ? "writing" : "ex= ecute"), (uint32_t)address, mmu_idx, ret ? "Miss" : "Hit", - result->prot & PAGE_READ ? 'r' : '-', - result->prot & PAGE_WRITE ? 'w' : '-', - result->prot & PAGE_EXEC ? 'x' : '-'); + result->f.prot & PAGE_READ ? 'r' : '-', + result->f.prot & PAGE_WRITE ? 'w' : '-', + result->f.prot & PAGE_EXEC ? 'x' : '-'); =20 return ret; } @@ -2572,10 +2573,10 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *= cs, vaddr addr, bool ret; =20 ret =3D get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi); - *attrs =3D res.attrs; + *attrs =3D res.f.attrs; =20 if (ret) { return -1; } - return res.phys; + return res.f.phys_addr; } diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index ad225b1cb20..49601394ec1 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -227,17 +227,16 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, * target page size are handled specially, so for those we * pass in the exact addresses. */ - if (res.page_size >=3D TARGET_PAGE_SIZE) { - res.phys &=3D TARGET_PAGE_MASK; + if (res.f.lg_page_size >=3D TARGET_PAGE_BITS) { + res.f.phys_addr &=3D TARGET_PAGE_MASK; address &=3D TARGET_PAGE_MASK; } /* Notice and record tagged memory. */ if (cpu_isar_feature(aa64_mte, cpu) && res.cacheattrs.attrs =3D=3D= 0xf0) { - arm_tlb_mte_tagged(&res.attrs) =3D true; + arm_tlb_mte_tagged(&res.f.attrs) =3D true; } =20 - tlb_set_page_with_attrs(cs, address, res.phys, res.attrs, - res.prot, mmu_idx, res.page_size); + tlb_set_page_full(cs, mmu_idx, address, &res.f); return true; } else if (probe) { return false; --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665416579; cv=none; d=zohomail.com; s=zohoarc; b=JehGxaMe8yLHXSoxY1UwUorvJ038REV4IYYdDonzeLrElFtqFHvsenYowwh3rdoyscoyjGXcrtXAVlyXOKEX1/bkeE5THTFIrI0ArjN6sgx+Qr/3XHzGYldb+yGJTLM7TQHSE8Sq91lpD051Ww7d0Dm+ZohM99IsFvJoZ5aSCZs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665416579; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nSdHJeWqWDZOQeABzXBHYYSEmw+sgR02dIC9udOVmMk=; b=iKvrgfLUWyyBtXwhLwPf6UVndWeWakaPlixqxFaC1psGJRNpjSuAbL22sVP7Jwixy1f4vehpKh7fDtFaFgvfoZzCdCuxYqGdrnW38Q5drdo4Jn3b7GdDo6W4PrRwONxWWrgyeCgdIvJr97vtlrf9ztqs1DR90g8AjfeWsU6eFMI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665416579164817.5287774397274; Mon, 10 Oct 2022 08:42:59 -0700 (PDT) Received: from localhost ([::1]:44254 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohuJo-0004J5-RH for importer@patchew.org; Mon, 10 Oct 2022 11:03:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60094) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtlB-0006WI-QI for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:28:01 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:56110) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtl9-0005aG-At for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:28:00 -0400 Received: by mail-wm1-x329.google.com with SMTP id t4so6938510wmj.5 for ; Mon, 10 Oct 2022 07:27:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=nSdHJeWqWDZOQeABzXBHYYSEmw+sgR02dIC9udOVmMk=; b=t+BErM9br1YlQLslYwau5GkqlHmMJKbeFKdIE+dRMBkUsviOxvr7nqMVC4h4Rfd3P3 Z+l2Kg89EAYCfqD5t92+O9I8A2D4/dOI0yLoIWkjuDvIpww7WrXyNAiWn+/wRr92Y1m5 aO7KLE2CxnI9wYle+Pa8Nc80TV+G0VBZraux65W557GTAxKnZcfJJLpO9nRXdiBctSGS JZRtNG/v7WIK2pz3kNi2SQWUtjoi0H4Aqj4++zq3s1CrgHYJ/w3XoZQgbhGtWKa4Zmsj uSBCZ6MlpTlghwRw5KqM9IWrpVLyeo1hqsRjeQ0RXyA9sVvD7DPVcbUDwYKFU5qPkJ73 KT7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nSdHJeWqWDZOQeABzXBHYYSEmw+sgR02dIC9udOVmMk=; b=x7eouCXmtSF0ZPIDkXg3b+674SJkWgJvnHcSSKJEVwuj7BuSxfYWoo1Nsaz3/go4OE +wDWW1yg/OZqqcY2Bw7gTm8mnsNcu1b2vqa5dW1dml4dkPYclRHgKf+WfDr5uTCg0THD ByDHG/SqM768B8QFJGB5OFu2fI1r9+Q3afLOwYm31g2XcLib0InDtLV/OzXnbfKy6KQu efnLugRlm7MEXbAEAotTNWjFAkjSbG9m++/vmxtt/anLUJ/aFXw3XdYYIR+NanZDl6+k kwUgarxRcYvHSv8/sQbGPK0z3QAidmopG0ajOSoJTPd5ch/6klVEdy1GN9HmOgV3Lp88 8SKA== X-Gm-Message-State: ACrzQf3+BfJKkHyJGaVQ9CwNLMjxgadveOd6c8mmDub/fPrEZgB9IiOQ 4ZIdBkKoUIsKHUSoyAJThQ5U3bq9N45z9g== X-Google-Smtp-Source: AMsMyM7vGpq9iKlD4tYYt2TCx0PX9NwCaZjthv72EbK0U02h1Sat/yS3/JQZ/zKgvf3nZrfbQ+kl6w== X-Received: by 2002:a1c:730e:0:b0:3b4:b0c0:d616 with SMTP id d14-20020a1c730e000000b003b4b0c0d616mr13128048wmb.72.1665412078642; Mon, 10 Oct 2022 07:27:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/28] hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3 Date: Mon, 10 Oct 2022 15:27:27 +0100 Message-Id: <20221010142730.502083-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665416580126100001 Content-Type: text/plain; charset="utf-8" From: Jerome Forissier According to the Linux kernel booting.rst [1], CPTR_EL3.ESM and SCR_EL3.EnTP2 must be initialized to 1 when EL3 is present and FEAT_SME is advertised. This has to be taken care of when QEMU boots directly into the kernel (i.e., "-M virt,secure=3Don -cpu max -kernel Image"). Cc: qemu-stable@nongnu.org Fixes: 78cb9776662a ("target/arm: Enable SME for -cpu max") Link: [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.gi= t/tree/Documentation/arm64/booting.rst?h=3Dv6.0#n321 Signed-off-by: Jerome Forissier Message-id: 20221003145641.1921467-1-jerome.forissier@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/boot.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index ada2717f760..ee3858b673a 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -763,6 +763,10 @@ static void do_cpu_reset(void *opaque) if (cpu_isar_feature(aa64_sve, cpu)) { env->cp15.cptr_el[3] |=3D R_CPTR_EL3_EZ_MASK; } + if (cpu_isar_feature(aa64_sme, cpu)) { + env->cp15.cptr_el[3] |=3D R_CPTR_EL3_ESM_MASK; + env->cp15.scr_el3 |=3D SCR_ENTP2; + } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); /* This hook is only supported for AArch32 currently: --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665413274; cv=none; d=zohomail.com; s=zohoarc; b=I6plrfzTJNhU1yNRT+ZbIQ/R4zATKkCHz/OQUUZYpvldLizYp+xIcTSDyhTt//FxmMGpCn/0lqtBctmBbNPo1uJDbgqk5kVVTafSGyRku80WfzXu9er3OxFLzSgO/HvUIT8g161Lp1nVQFMzCsWtzvrPzLJnxfhbyxtKH7QrL+s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665413274; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jy15vtNWJUoTZz5dOl5JPn5PUMEvXzpyspwJEl564+Y=; b=JM7aISBpKLgHET5KdBpzsyg0ElRYbBi8CPL2jUzxazr3thr4ofzl4OJEcRUDLKBH+K9fbFIavdQYWdTNAA2XaxvyE0SYi2zPiPi7I/n1KAa+oLS7WpPhc6b9swdB3bzy6rr8Pts62p8l3UGRL7Sdlh94CAKcMHLqnRdxn8APpEM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166541327427672.728693468075; Mon, 10 Oct 2022 07:47:54 -0700 (PDT) Received: from localhost ([::1]:35434 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohu4N-0006og-Je for importer@patchew.org; Mon, 10 Oct 2022 10:47:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60098) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtlD-0006c1-KO for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:28:03 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:46963) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtlB-0005c6-I5 for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:28:03 -0400 Received: by mail-wm1-x32e.google.com with SMTP id az22-20020a05600c601600b003c6b72797fdso1474665wmb.5 for ; Mon, 10 Oct 2022 07:28:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:27:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=jy15vtNWJUoTZz5dOl5JPn5PUMEvXzpyspwJEl564+Y=; b=JH46iBzp2d2ZCI9t60RAGocROJqJyNmQZbAiTM6Y6dGz5JFm6SsB0SN8xo00Vy4qLT BAKHvWD8VYDVdKYoSolHASrI4W6/ueFiT/IzP5WBZ2SNlCwZ+3ng06FYyg6NVdyLSTtE 1iN2yqIa9hPyvPQEJ/Q1UzPw2JZk/joULv50bNgL5WKRb9cBPdm1TSe+zhVNWmok6BvF 3Ta9NKIN+8OArrUEO+E8hN1BrMgEtuMBqChAd3IPPxQltsVQFNnAeFiqfEUsicdVmmoB nLdp/BFgXeb+xBY403FHvrvwuK+E9PCcB0knp7mGXne+02RK2Y2xiDkmGGgQyksExyX0 QQMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jy15vtNWJUoTZz5dOl5JPn5PUMEvXzpyspwJEl564+Y=; b=j20uwUrodWghgrMGZ4+iqDrtJlSLvr+mbJvAaFkM3sIxwSDxBhefNQdRYnWuLb93Ud CB/1NFJYI04z9Cx22AfCc3xiNj2eg5azbFrl3DlAarLzl2xTDuKRizIdZE+6Lrzn1HNf U/73EZSOeIC4EtGOGeEjfDJ3ItKbMIGT0xq4DpEQjFZW2dYFqp5nIcUztLLZFKuRKlTx DqkoSh7D0m2B3QHo0ra5tD428EuPL4ppvLKn7I5BzHQ5VtAEqa+gCQCIhGzGZg470/ls tu4YMQc215fhhpUy0NLxNtzXo25nKbMxkCEnMIoVUwnQ09j5ZKI09jWvFQbS+lzSUTeW wEzA== X-Gm-Message-State: ACrzQf0429i2BHUIzCUsOZ0lGZbr7DLFg3XCNUn6VeG/RCsImiEdHlmF ENlhLQF9Q+31gpQ9PWRObDwspq5asPJPYw== X-Google-Smtp-Source: AMsMyM7Ne7FN/SMQoi4hztxXKCSuO0ucZNLwgQphw6D2GxOs5ldpSeLzl/ukhqaru2iWPPb0HqqJ5w== X-Received: by 2002:a05:600c:a05:b0:3b9:cecc:9846 with SMTP id z5-20020a05600c0a0500b003b9cecc9846mr19810402wmp.3.1665412079652; Mon, 10 Oct 2022 07:27:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/28] target/arm: Don't allow guest to use unimplemented granule sizes Date: Mon, 10 Oct 2022 15:27:28 +0100 Message-Id: <20221010142730.502083-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665413275411100001 Content-Type: text/plain; charset="utf-8" Arm CPUs support some subset of the granule (page) sizes 4K, 16K and 64K. The guest selects the one it wants using bits in the TCR_ELx registers. If it tries to program these registers with a value that is either reserved or which requests a size that the CPU does not implement, the architecture requires that the CPU behaves as if the field was programmed to some size that has been implemented. Currently we don't implement this, and instead let the guest use any granule size, even if the CPU ID register fields say it isn't present. Make aa64_va_parameters() check against the supported granule size and force use of a different one if it is not implemented. (A subsequent commit will make ARMVAParameters use the new enum rather than the current pair of using16k/using64k bools.) Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20221003162315.2833797-2-peter.maydell@linaro.org --- target/arm/cpu.h | 33 +++++++++++++ target/arm/internals.h | 9 ++++ target/arm/helper.c | 102 +++++++++++++++++++++++++++++++++++++---- 3 files changed, 136 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d541392170e..1a909a1b436 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4097,6 +4097,39 @@ static inline bool isar_feature_aa64_tgran16_2_lpa2(= const ARMISARegisters *id) return t >=3D 3 || (t =3D=3D 0 && isar_feature_aa64_tgran16_lpa2(id)); } =20 +static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id) +{ + return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >=3D 0; +} + +static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >=3D 1; +} + +static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id) +{ + return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >=3D 0; +} + +static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id) +{ + unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); + return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran4(id)); +} + +static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id) +{ + unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); + return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran16(id)); +} + +static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) +{ + unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2); + return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran64(id)); +} + static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) !=3D 0; diff --git a/target/arm/internals.h b/target/arm/internals.h index fd17aee4599..6166ac0a98f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -998,6 +998,15 @@ static inline uint32_t aarch64_pstate_valid_mask(const= ARMISARegisters *id) return valid; } =20 +/* Granule size (i.e. page size) */ +typedef enum ARMGranuleSize { + /* Same order as TG0 encoding */ + Gran4K, + Gran64K, + Gran16K, + GranInvalid, +} ARMGranuleSize; + /* * Parameters of a given virtual address, as extracted from the * translation control register (TCR) for a given regime. diff --git a/target/arm/helper.c b/target/arm/helper.c index e1338ed6e22..d7f578f2baa 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10287,20 +10287,105 @@ static int aa64_va_parameter_tcma(uint64_t tcr, = ARMMMUIdx mmu_idx) } } =20 +static ARMGranuleSize tg0_to_gran_size(int tg) +{ + switch (tg) { + case 0: + return Gran4K; + case 1: + return Gran64K; + case 2: + return Gran16K; + default: + return GranInvalid; + } +} + +static ARMGranuleSize tg1_to_gran_size(int tg) +{ + switch (tg) { + case 1: + return Gran16K; + case 2: + return Gran4K; + case 3: + return Gran64K; + default: + return GranInvalid; + } +} + +static inline bool have4k(ARMCPU *cpu, bool stage2) +{ + return stage2 ? cpu_isar_feature(aa64_tgran4_2, cpu) + : cpu_isar_feature(aa64_tgran4, cpu); +} + +static inline bool have16k(ARMCPU *cpu, bool stage2) +{ + return stage2 ? cpu_isar_feature(aa64_tgran16_2, cpu) + : cpu_isar_feature(aa64_tgran16, cpu); +} + +static inline bool have64k(ARMCPU *cpu, bool stage2) +{ + return stage2 ? cpu_isar_feature(aa64_tgran64_2, cpu) + : cpu_isar_feature(aa64_tgran64, cpu); +} + +static ARMGranuleSize sanitize_gran_size(ARMCPU *cpu, ARMGranuleSize gran, + bool stage2) +{ + switch (gran) { + case Gran4K: + if (have4k(cpu, stage2)) { + return gran; + } + break; + case Gran16K: + if (have16k(cpu, stage2)) { + return gran; + } + break; + case Gran64K: + if (have64k(cpu, stage2)) { + return gran; + } + break; + case GranInvalid: + break; + } + /* + * If the guest selects a granule size that isn't implemented, + * the architecture requires that we behave as if it selected one + * that is (with an IMPDEF choice of which one to pick). We choose + * to implement the smallest supported granule size. + */ + if (have4k(cpu, stage2)) { + return Gran4K; + } + if (have16k(cpu, stage2)) { + return Gran16K; + } + assert(have64k(cpu, stage2)); + return Gran64K; +} + ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data) { uint64_t tcr =3D regime_tcr(env, mmu_idx); bool epd, hpd, using16k, using64k, tsz_oob, ds; int select, tsz, tbi, max_tsz, min_tsz, ps, sh; + ARMGranuleSize gran; ARMCPU *cpu =3D env_archcpu(env); + bool stage2 =3D mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMM= MUIdx_Stage2_S; =20 if (!regime_has_2_ranges(mmu_idx)) { select =3D 0; tsz =3D extract32(tcr, 0, 6); - using64k =3D extract32(tcr, 14, 1); - using16k =3D extract32(tcr, 15, 1); - if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_St= age2_S) { + gran =3D tg0_to_gran_size(extract32(tcr, 14, 2)); + if (stage2) { /* VTCR_EL2 */ hpd =3D false; } else { @@ -10318,16 +10403,13 @@ ARMVAParameters aa64_va_parameters(CPUARMState *e= nv, uint64_t va, select =3D extract64(va, 55, 1); if (!select) { tsz =3D extract32(tcr, 0, 6); + gran =3D tg0_to_gran_size(extract32(tcr, 14, 2)); epd =3D extract32(tcr, 7, 1); sh =3D extract32(tcr, 12, 2); - using64k =3D extract32(tcr, 14, 1); - using16k =3D extract32(tcr, 15, 1); hpd =3D extract64(tcr, 41, 1); } else { - int tg =3D extract32(tcr, 30, 2); - using16k =3D tg =3D=3D 1; - using64k =3D tg =3D=3D 3; tsz =3D extract32(tcr, 16, 6); + gran =3D tg1_to_gran_size(extract32(tcr, 30, 2)); epd =3D extract32(tcr, 23, 1); sh =3D extract32(tcr, 28, 2); hpd =3D extract64(tcr, 42, 1); @@ -10336,6 +10418,10 @@ ARMVAParameters aa64_va_parameters(CPUARMState *en= v, uint64_t va, ds =3D extract64(tcr, 59, 1); } =20 + gran =3D sanitize_gran_size(cpu, gran, stage2); + using64k =3D gran =3D=3D Gran64K; + using16k =3D gran =3D=3D Gran16K; + if (cpu_isar_feature(aa64_st, cpu)) { max_tsz =3D 48 - using64k; } else { --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665413976; cv=none; d=zohomail.com; s=zohoarc; b=egYVh8RxNDsuO0euWG83udUsjw40Mq3ZlFEz/0LIFbIDka3whElvqJ+Je5nX677cjovoyr+S43qDOuYnIWL36NqxSzzxhbcKqsXcBp721PtR8oj4/O74XQh0zV2J6dQKgUcmJQ2B5IMc9Vvv84NgmkECP0aYFClyn/EJjeHf6hE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665413976; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4WEyc+UOMjigXkaKxU362KXr8MSgbNuL5VrZCUOmcFw=; b=iWjiiXcRPZ0lGHv+LAbwJ0MXDnv+IduvWD0+O/m8DyiD61qWqg3rGmMYdSf2C5cj1XZIhSHakP6dBnzIDEhL4V5vIQtEKJcViHI9sFyL6YUPTL7mNbBjE9TDT35H9RzQRJr0v2K+utLfxg4vBpbEKCVqroepd08CySQRv/CVRgU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166541397644583.3361514036352; Mon, 10 Oct 2022 07:59:36 -0700 (PDT) Received: from localhost ([::1]:34290 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohuFi-0006yz-S4 for importer@patchew.org; Mon, 10 Oct 2022 10:59:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60102) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtlF-0006fo-51 for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:28:05 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:55182) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtlC-0005cH-9Q for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:28:04 -0400 Received: by mail-wm1-x336.google.com with SMTP id iv17so6953191wmb.4 for ; Mon, 10 Oct 2022 07:28:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.27.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:28:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4WEyc+UOMjigXkaKxU362KXr8MSgbNuL5VrZCUOmcFw=; b=LCE2VdkCPFL1kqB6MT5jioEr9HR5/lalnFjCdn4G/XPeMwqpMK6i40bg8l7N5tLxx3 WpUq2VUDv/lwgds4CaGedYX13XBgELsJnB7Gdl+mt0dki9oa5BCf4171xAkVgMedBiC9 oWijOdzn5PZ4wdMhDvT5FNWCF3+8IuwRojqQaq/zQ+RoR+VsfWi98FFmzmSNPpesrgvG ItW3/Cl2jB/Fd9iofGCdLoI3Z0zRKWNFSgtzSMngvaQs5nm5tt4w6tPGe3nITBAhbgG1 NIYU617WQ6XiEqasH9R67iaH/plxEof44CqbGnQ4714Re1CL2MoqcvrVl90qRHx2wq7M 4NAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4WEyc+UOMjigXkaKxU362KXr8MSgbNuL5VrZCUOmcFw=; b=SUA3rQPC5mxeQz9mwJ9/txvKpBUMd9maSVtDw2naRJYXEJLOaaBXBjBqvhmd/k6hMd LWgAfTeNCy/QiKGmvp+lWukgglRt1JOOG/MF9uR2xIgDu+TXwfUN/K1GcEwN1KN/6kU8 HjdSCGvYp0Cn8JG2RdwYHTzgDak581ldUrAuQV1a3ThEQNejqmWzt75LZsJW6WQvUCWC MfdywBXixYCkGxdFTjJ2ktyuspwbreUFF6eyw8+eihTO4GVecMny+X8peQrk3h/6sqrK C/KuBomva/8ZP7WxqrefdvCqI2XRIiEf/Jmfsz+5ZX4lSbeZH3uHUgUfkaipFnU7jlWu jpZg== X-Gm-Message-State: ACrzQf3svx4UU/IE/mPy1jBlTTaTNR8Fs8qJenD+QV7rTFNpsAZ5TXvS 11EDBQGyey0xvJgilgp+LnfuWDql02AANQ== X-Google-Smtp-Source: AMsMyM6IF1uaUzsAgWcZyoLjPXdcNb/VYdUTycM+AiHZj7L4RuFRcMbNwUmWECntT4IEqXX8GnJHBg== X-Received: by 2002:a05:600c:12c6:b0:3bd:eeec:309 with SMTP id v6-20020a05600c12c600b003bdeeec0309mr20583446wmd.167.1665412080665; Mon, 10 Oct 2022 07:28:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/28] target/arm: Use ARMGranuleSize in ARMVAParameters Date: Mon, 10 Oct 2022 15:27:29 +0100 Message-Id: <20221010142730.502083-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665413978060100001 Content-Type: text/plain; charset="utf-8" Now we have an enum for the granule size, use it in the ARMVAParameters struct instead of the using16k/using64k bools. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20221003162315.2833797-3-peter.maydell@linaro.org --- target/arm/internals.h | 23 +++++++++++++++++++++-- target/arm/helper.c | 39 ++++++++++++++++++++++++++++----------- target/arm/ptw.c | 8 +------- 3 files changed, 50 insertions(+), 20 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 6166ac0a98f..9566364dcae 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1007,6 +1007,26 @@ typedef enum ARMGranuleSize { GranInvalid, } ARMGranuleSize; =20 +/** + * arm_granule_bits: Return address size of the granule in bits + * + * Return the address size of the granule in bits. This corresponds + * to the pseudocode TGxGranuleBits(). + */ +static inline int arm_granule_bits(ARMGranuleSize gran) +{ + switch (gran) { + case Gran64K: + return 16; + case Gran16K: + return 14; + case Gran4K: + return 12; + default: + g_assert_not_reached(); + } +} + /* * Parameters of a given virtual address, as extracted from the * translation control register (TCR) for a given regime. @@ -1019,10 +1039,9 @@ typedef struct ARMVAParameters { bool tbi : 1; bool epd : 1; bool hpd : 1; - bool using16k : 1; - bool using64k : 1; bool tsz_oob : 1; /* tsz has been clamped to legal range */ bool ds : 1; + ARMGranuleSize gran : 2; } ARMVAParameters; =20 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, diff --git a/target/arm/helper.c b/target/arm/helper.c index d7f578f2baa..dde64a487ae 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4473,6 +4473,24 @@ typedef struct { uint64_t length; } TLBIRange; =20 +static ARMGranuleSize tlbi_range_tg_to_gran_size(int tg) +{ + /* + * Note that the TLBI range TG field encoding differs from both + * TG0 and TG1 encodings. + */ + switch (tg) { + case 1: + return Gran4K; + case 2: + return Gran16K; + case 3: + return Gran64K; + default: + return GranInvalid; + } +} + static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, uint64_t value) { @@ -4481,17 +4499,19 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *e= nv, ARMMMUIdx mmuidx, uint64_t select =3D sextract64(value, 36, 1); ARMVAParameters param =3D aa64_va_parameters(env, select, mmuidx, true= ); TLBIRange ret =3D { }; + ARMGranuleSize gran; =20 page_size_granule =3D extract64(value, 46, 2); + gran =3D tlbi_range_tg_to_gran_size(page_size_granule); =20 /* The granule encoded in value must match the granule in use. */ - if (page_size_granule !=3D (param.using64k ? 3 : param.using16k ? 2 : = 1)) { + if (gran !=3D param.gran) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\= n", page_size_granule); return ret; } =20 - page_shift =3D (page_size_granule - 1) * 2 + 12; + page_shift =3D arm_granule_bits(gran); num =3D extract64(value, 39, 5); scale =3D extract64(value, 44, 2); exponent =3D (5 * scale) + 1; @@ -10375,7 +10395,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, ARMMMUIdx mmu_idx, bool data) { uint64_t tcr =3D regime_tcr(env, mmu_idx); - bool epd, hpd, using16k, using64k, tsz_oob, ds; + bool epd, hpd, tsz_oob, ds; int select, tsz, tbi, max_tsz, min_tsz, ps, sh; ARMGranuleSize gran; ARMCPU *cpu =3D env_archcpu(env); @@ -10419,11 +10439,9 @@ ARMVAParameters aa64_va_parameters(CPUARMState *en= v, uint64_t va, } =20 gran =3D sanitize_gran_size(cpu, gran, stage2); - using64k =3D gran =3D=3D Gran64K; - using16k =3D gran =3D=3D Gran16K; =20 if (cpu_isar_feature(aa64_st, cpu)) { - max_tsz =3D 48 - using64k; + max_tsz =3D 48 - (gran =3D=3D Gran64K); } else { max_tsz =3D 39; } @@ -10433,7 +10451,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, * adjust the effective value of DS, as documented. */ min_tsz =3D 16; - if (using64k) { + if (gran =3D=3D Gran64K) { if (cpu_isar_feature(aa64_lva, cpu)) { min_tsz =3D 12; } @@ -10442,14 +10460,14 @@ ARMVAParameters aa64_va_parameters(CPUARMState *e= nv, uint64_t va, switch (mmu_idx) { case ARMMMUIdx_Stage2: case ARMMMUIdx_Stage2_S: - if (using16k) { + if (gran =3D=3D Gran16K) { ds =3D cpu_isar_feature(aa64_tgran16_2_lpa2, cpu); } else { ds =3D cpu_isar_feature(aa64_tgran4_2_lpa2, cpu); } break; default: - if (using16k) { + if (gran =3D=3D Gran16K) { ds =3D cpu_isar_feature(aa64_tgran16_lpa2, cpu); } else { ds =3D cpu_isar_feature(aa64_tgran4_lpa2, cpu); @@ -10486,10 +10504,9 @@ ARMVAParameters aa64_va_parameters(CPUARMState *en= v, uint64_t va, .tbi =3D tbi, .epd =3D epd, .hpd =3D hpd, - .using16k =3D using16k, - .using64k =3D using64k, .tsz_oob =3D tsz_oob, .ds =3D ds, + .gran =3D gran, }; } =20 diff --git a/target/arm/ptw.c b/target/arm/ptw.c index ddacffa7ee6..23f16f4ff7f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1062,13 +1062,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uin= t64_t address, } } =20 - if (param.using64k) { - stride =3D 13; - } else if (param.using16k) { - stride =3D 11; - } else { - stride =3D 9; - } + stride =3D arm_granule_bits(param.gran) - 3; =20 /* * Note that QEMU ignores shareability and cacheability attributes, --=20 2.25.1 From nobody Thu Dec 18 19:35:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1665413606; cv=none; d=zohomail.com; s=zohoarc; b=YFdNislPPHz6weklt4GS08M1zeMfl8EgauY0KulcwZbG1F6LtnVeJF5wJr5paIBaE+q17kSeTdAOSbcARvkT1aGvRxhABJLTzv87MWYRHDJjAccb3ibsQqqrxnyNAfluT0SphDIh9jg3lrWkvy2YRi61N9pLeRuyyblV73UX7Is= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665413606; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZyrQwdJTnkRxmzsd2VOm6mWaiY1ZM83JO9WWcUYcQOs=; b=HUL/kMdHH6Zgjg2DS5hEp0hIrg9MgwfJ+PlZHB6e+ht1hcdXWMUnQGYwxsj267cF8mofGG6zSFtRaULvPWZT9OeoTooc+A9zH/YPT1FbWp6LHAUHZ/J9uSebFRuypeJRev3Bco0mvJwiIoiM8QLl1QFbCJjkgJ+mPtGD6CLGKR8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665413606645921.6482233210692; Mon, 10 Oct 2022 07:53:26 -0700 (PDT) Received: from localhost ([::1]:35822 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ohu9l-0004ZH-9i for importer@patchew.org; Mon, 10 Oct 2022 10:53:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60100) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ohtlE-0006ed-S9 for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:28:04 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:42706) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ohtlD-0005ca-7F for qemu-devel@nongnu.org; Mon, 10 Oct 2022 10:28:04 -0400 Received: by mail-wm1-x336.google.com with SMTP id o20-20020a05600c4fd400b003b4a516c479so6524474wmq.1 for ; Mon, 10 Oct 2022 07:28:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u6-20020adfed46000000b0022e04bfa661sm9037054wro.59.2022.10.10.07.28.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 07:28:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ZyrQwdJTnkRxmzsd2VOm6mWaiY1ZM83JO9WWcUYcQOs=; b=U0DYTgngaclUZKgzcv2dnzsaBrhG6kL1a29tfI7w8+aJADz9CWa16Z9maJ7wuraust Ut4new1OfmDLrElOQkm40ubazGQ2UcSM3yiCBlHGl9cZDGbkJHYt3n1OvjIeAYn7D0q5 /BlSxcNbps+0CnC4BeiyzT9/+ciG7OjCwQ9srdVzK4+lcViMDCSVSNaYijDHqCDvENdP 9ZrT8CFx5iqsrnFQdzXROVpyNqEixD2/NzTdvXhNMxr5aGeNzrWZNM1iXJ50nRYlmxH0 4CLE0W8xOQBuBabjbk9UusEz/EyyYWxoaKGN0D57JP1d65gxXaltIzZ3R0c/15hKLoAd 5OfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZyrQwdJTnkRxmzsd2VOm6mWaiY1ZM83JO9WWcUYcQOs=; b=h9cBjIIVicofXDN78VM0kAZ7GR1xvWoAa5SeWlBI1V470yzKm7Xx6JqJbbzo3r5SJX ghN4ZI7L2XG8r36ODsRU0SrinhdCqmFiGTIFDMyjz+N0ZChTYoZR3QJwEBRAhsW3YJlJ rS082xuLjW1PJjfVuQ7gPIYOMAlpgKYg6S8hoGKJRNJcMioyITlvdHtOgzFPEMZU6xDA CChx9vYlJcA2nrcuqQQZM1us8+i0V1NXnIEn7mmEn/y/lXSF3pE6/+jl3rs+AIyxaDH7 XCC9KkVpjigzEvBgWiKcCOvoW/wC5kxqpvm7C5OPi1KVQjvjgEHZWh/bshEO0Jg5NRiO rOfg== X-Gm-Message-State: ACrzQf3w5NEPWGT8UMp2uZkyWyF7vb/L3Xkew/lnacDr9FRql+lMZK6N XuDN4EkrRJHBqvaDtJ23Wks/VBmQpEYpbA== X-Google-Smtp-Source: AMsMyM5ogKwSHC8nYB+JzJ5vbged/fEujINUfFTyJFIJw9K/EsQakecxAZmh2NU8Heg9wgEbsTAxZQ== X-Received: by 2002:a05:600c:1d02:b0:3c3:e6f0:6e4b with SMTP id l2-20020a05600c1d0200b003c3e6f06e4bmr10143855wms.202.1665412081541; Mon, 10 Oct 2022 07:28:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/28] docs/system/arm/emulation.rst: Report FEAT_GTG support Date: Mon, 10 Oct 2022 15:27:30 +0100 Message-Id: <20221010142730.502083-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org> References: <20221010142730.502083-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665413609201100005 Content-Type: text/plain; charset="utf-8" FEAT_GTG is a change tho the ID register ID_AA64MMFR0_EL1 so that it can report a different set of supported granule (page) sizes for stage 1 and stage 2 translation tables. As of commit c20281b2a5048 we already report the granule sizes that way for '-cpu max', and now we also correctly make attempts to use unimplemented granule sizes fail, so we can report the support of the feature in the documentation. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20221003162315.2833797-4-peter.maydell@linaro.org --- docs/system/arm/emulation.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index be7bbffe595..cfb4b0768b0 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -31,6 +31,7 @@ the following architecture extensions: - FEAT_FRINTTS (Floating-point to integer instructions) - FEAT_FlagM (Flag manipulation instructions v2) - FEAT_FlagM2 (Enhancements to flag manipulation instructions) +- FEAT_GTG (Guest translation granule size) - FEAT_HCX (Support for the HCRX_EL2 register) - FEAT_HPDS (Hierarchical permission disables) - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) --=20 2.25.1