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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id u5-20020a05622a17c500b0035d0655b079sm14701090qtk.30.2022.10.05.17.01.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 17:01:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date; bh=UBVwWgULhLFdOJ8/yh2JcEmMtkMZ7Qr893AfvaYDDm8=; b=Cgi8YQNanL6xwenTx079WNpTELbUVZSiEvOIslbONiLXcbQ94Ah5bAmBFuEXROjnhR K6AgivHSwCT8Li8VrhTtkIWYORHcRrIJr7bMNBqfoUt3KmaeGlnypk8Iq8cgeCbZsPev fdi7ROX1A5lY7MDSG976GHEtc9CRniEDkk/ERh36iCaUJb0KNa9WNCz277zJFnfvEMfk 2s/lF4e4RtKzAdkIT1g0nR6iHo3Cl4+8ofCr2aG3Y1QA4L4SnmTlJbxIO4p48Z5xRXPK zFidxN0BhPT3YC9gAoqiXEv21kuXlQ4n43S64yZukDyEmbpMUu1jJ3vEph5kyDQVWNbD 8M3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date; bh=UBVwWgULhLFdOJ8/yh2JcEmMtkMZ7Qr893AfvaYDDm8=; b=jccfkrK56IkYLFUgA2HgTRwkQxnF/dVmeNxhm2bjs+0EburVHE1rvYGLLFASyh20JF pKE++Pf6QP04N6QDCWKP749Ca2Wk73ufNVrC9eVsJ33VooxCMAFYakmATqdlXD5QBHtp YHLbD3aP07VomDmu9pWlrO1senYxNpqb8c7qZPuahVGDVMjM65lhg5ugQz9e70F0wbv+ AzbfXe+RO01fEeKNYsJl5UR1fHtAk7EmvBUIpTm41mQBOBBcGaIDm577FmCcsWA2PYUM lbEVGb62X9BV7iKti4T+FjfmzHNK6JDs3TircOvk293H9KIgzvs8pdW0gUdgUSQcjN/2 R1Mg== X-Gm-Message-State: ACrzQf1ftX2JLmhh6cQ4SsgmfRrgrkvNuaEPEi8QmJcW2sCEtf+DFjOM WmWnEXvJUeMrxfkHPx8hUKnKNo9nhw== X-Google-Smtp-Source: AMsMyM7bUeZZfNtYrg6lNpBcwbsowWrN0Hq0CSAaHr0Sp/JEftmZ7fpuBC2QszaMZriXhFGnhbCDMA== X-Received: by 2002:a05:620a:1239:b0:6ce:24c1:12d7 with SMTP id v25-20020a05620a123900b006ce24c112d7mr1482773qkj.496.1665014466057; Wed, 05 Oct 2022 17:01:06 -0700 (PDT) From: Gourry X-Google-Original-From: Gourry To: qemu-devel@nongnu.org Cc: jonathan.cameron@huawei.com, Gourry Subject: [PATCH RFC] hw/cxl: type 3 devices can now present volatile or persistent memory Date: Wed, 5 Oct 2022 20:01:03 -0400 Message-Id: <20221006000103.49542-1-gregory.price@memverge.com> X-Mailer: git-send-email 2.37.3 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::744; envelope-from=gourry.memverge@gmail.com; helo=mail-qk1-x744.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 05 Oct 2022 20:57:20 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1665017967877100001 Content-Type: text/plain; charset="utf-8" Type 3 devices were hard-coded to always present as persistent memory devic= es. This patch adds the "is_pmem" attribute which can be used to instantiate a device as either a pmem or vmem. Right now it is only possible to choose one or the other, but future devices may present both (such as multi-logical devices with different regions backed by different types of memory). Reviewed-by: Davidlohr Bueso --- docs/system/devices/cxl.rst | 31 ++++++++++++++++--------- hw/cxl/cxl-mailbox-utils.c | 24 +++++++++++--------- hw/mem/cxl_type3.c | 10 +++++---- include/hw/cxl/cxl_device.h | 5 +++-- tests/qtest/bios-tables-test.c | 8 +++---- tests/qtest/cxl-test.c | 41 ++++++++++++++++++++++++++++------ 6 files changed, 82 insertions(+), 37 deletions(-) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index f25783a4ec..3a62d46e8a 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -300,7 +300,7 @@ Example topology involving a switch:: =20 Example command lines --------------------- -A very simple setup with just one directly attached CXL Type 3 device:: +A very simple setup with just one directly attached CXL Type 3 Persistent = Memory device:: =20 qemu-system-aarch64 -M virt,gic-version=3D3,cxl=3Don -m 4g,maxmem=3D8G,s= lots=3D8 -cpu max \ ... @@ -308,7 +308,18 @@ A very simple setup with just one directly attached CX= L Type 3 device:: -object memory-backend-file,id=3Dcxl-lsa1,share=3Don,mem-path=3D/tmp/lsa= .raw,size=3D256M \ -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id=3Dcxl.1 \ -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Droot_port13,chassis=3D0,slot=3D= 2 \ - -device cxl-type3,bus=3Droot_port13,memdev=3Dcxl-mem1,lsa=3Dcxl-lsa1,id= =3Dcxl-pmem0 \ + -device cxl-type3,bus=3Droot_port13,pmem=3Dtrue,memdev=3Dcxl-mem1,lsa=3D= cxl-lsa1,id=3Dcxl-pmem0 \ + -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G + +A very simple setup with just one directly attached CXL Type 3 Volatile Me= mory device:: + + qemu-system-aarch64 -M virt,gic-version=3D3,cxl=3Don -m 4g,maxmem=3D8G,s= lots=3D8 -cpu max \ + ... + -object memory-backend-ram,id=3Dcxl-mem1,share=3Don,size=3D256M \ + -object memory-backend-ram,id=3Dcxl-lsa1,share=3Don,size=3D256M \ + -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id=3Dcxl.1 \ + -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Droot_port13,chassis=3D0,slot=3D= 2 \ + -device cxl-type3,bus=3Droot_port13,pmem=3Dfalse,memdev=3Dcxl-mem1,lsa= =3Dcxl-lsa1,id=3Dcxl-pmem0 \ -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G =20 A setup suitable for 4 way interleave. Only one fixed window provided, to = enable 2 way @@ -328,13 +339,13 @@ the CXL Type3 device directly attached (no switches).= :: -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id=3Dcxl.1 \ -device pxb-cxl,bus_nr=3D222,bus=3Dpcie.0,id=3Dcxl.2 \ -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Droot_port13,chassis=3D0,slot=3D= 2 \ - -device cxl-type3,bus=3Droot_port13,memdev=3Dcxl-mem1,lsa=3Dcxl-lsa1,id= =3Dcxl-pmem0 \ + -device cxl-type3,bus=3Droot_port13,pmem=3Dtrue,memdev=3Dcxl-mem1,lsa=3D= cxl-lsa1,id=3Dcxl-pmem0 \ -device cxl-rp,port=3D1,bus=3Dcxl.1,id=3Droot_port14,chassis=3D0,slot=3D= 3 \ - -device cxl-type3,bus=3Droot_port14,memdev=3Dcxl-mem2,lsa=3Dcxl-lsa2,id= =3Dcxl-pmem1 \ + -device cxl-type3,bus=3Droot_port14,pmem=3Dtrue,memdev=3Dcxl-mem2,lsa=3D= cxl-lsa2,id=3Dcxl-pmem1 \ -device cxl-rp,port=3D0,bus=3Dcxl.2,id=3Droot_port15,chassis=3D0,slot=3D= 5 \ - -device cxl-type3,bus=3Droot_port15,memdev=3Dcxl-mem3,lsa=3Dcxl-lsa3,id= =3Dcxl-pmem2 \ + -device cxl-type3,bus=3Droot_port15,pmem=3Dtrue,memdev=3Dcxl-mem3,lsa=3D= cxl-lsa3,id=3Dcxl-pmem2 \ -device cxl-rp,port=3D1,bus=3Dcxl.2,id=3Droot_port16,chassis=3D0,slot=3D= 6 \ - -device cxl-type3,bus=3Droot_port16,memdev=3Dcxl-mem4,lsa=3Dcxl-lsa4,id= =3Dcxl-pmem3 \ + -device cxl-type3,bus=3Droot_port16,pmem=3Dtrue,memdev=3Dcxl-mem4,lsa=3D= cxl-lsa4,id=3Dcxl-pmem3 \ -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.targets.1=3Dcxl.2,cxl-fmw.0.siz= e=3D4G,cxl-fmw.0.interleave-granularity=3D8k =20 An example of 4 devices below a switch suitable for 1, 2 or 4 way interlea= ve:: @@ -354,13 +365,13 @@ An example of 4 devices below a switch suitable for 1= , 2 or 4 way interleave:: -device cxl-rp,port=3D1,bus=3Dcxl.1,id=3Droot_port1,chassis=3D0,slot=3D1= \ -device cxl-upstream,bus=3Droot_port0,id=3Dus0 \ -device cxl-downstream,port=3D0,bus=3Dus0,id=3Dswport0,chassis=3D0,slot= =3D4 \ - -device cxl-type3,bus=3Dswport0,memdev=3Dcxl-mem0,lsa=3Dcxl-lsa0,id=3Dcx= l-pmem0,size=3D256M \ + -device cxl-type3,bus=3Dswport0,pmem=3Dtrue,memdev=3Dcxl-mem0,lsa=3Dcxl-= lsa0,id=3Dcxl-pmem0,size=3D256M \ -device cxl-downstream,port=3D1,bus=3Dus0,id=3Dswport1,chassis=3D0,slot= =3D5 \ - -device cxl-type3,bus=3Dswport1,memdev=3Dcxl-mem1,lsa=3Dcxl-lsa1,id=3Dcx= l-pmem1,size=3D256M \ + -device cxl-type3,bus=3Dswport1,pmem=3Dtrue,memdev=3Dcxl-mem1,lsa=3Dcxl-= lsa1,id=3Dcxl-pmem1,size=3D256M \ -device cxl-downstream,port=3D2,bus=3Dus0,id=3Dswport2,chassis=3D0,slot= =3D6 \ - -device cxl-type3,bus=3Dswport2,memdev=3Dcxl-mem2,lsa=3Dcxl-lsa2,id=3Dcx= l-pmem2,size=3D256M \ + -device cxl-type3,bus=3Dswport2,pmem=3Dtrue,memdev=3Dcxl-mem2,lsa=3Dcxl-= lsa2,id=3Dcxl-pmem2,size=3D256M \ -device cxl-downstream,port=3D3,bus=3Dus0,id=3Dswport3,chassis=3D0,slot= =3D7 \ - -device cxl-type3,bus=3Dswport3,memdev=3Dcxl-mem3,lsa=3Dcxl-lsa3,id=3Dcx= l-pmem3,size=3D256M \ + -device cxl-type3,bus=3Dswport3,pmem=3Dtrue,memdev=3Dcxl-mem3,lsa=3Dcxl-= lsa3,id=3Dcxl-pmem3,size=3D256M \ -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G,cxl-fmw.0.interleave-= granularity=3D4k =20 Kernel Configuration Options diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index bc1bb18844..3ed4dfeb69 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -138,7 +138,7 @@ static ret_code cmd_firmware_update_get_info(struct cxl= _cmd *cmd, } QEMU_PACKED *fw_info; QEMU_BUILD_BUG_ON(sizeof(*fw_info) !=3D 0x50); =20 - if (cxl_dstate->pmem_size < (256 << 20)) { + if (cxl_dstate->mem_size < (256 << 20)) { return CXL_MBOX_INTERNAL_ERROR; } =20 @@ -281,7 +281,7 @@ static ret_code cmd_identify_memory_device(struct cxl_c= md *cmd, =20 CXLType3Dev *ct3d =3D container_of(cxl_dstate, CXLType3Dev, cxl_dstate= ); CXLType3Class *cvc =3D CXL_TYPE3_GET_CLASS(ct3d); - uint64_t size =3D cxl_dstate->pmem_size; + uint64_t size =3D cxl_dstate->mem_size; =20 if (!QEMU_IS_ALIGNED(size, 256 << 20)) { return CXL_MBOX_INTERNAL_ERROR; @@ -290,11 +290,13 @@ static ret_code cmd_identify_memory_device(struct cxl= _cmd *cmd, id =3D (void *)cmd->payload; memset(id, 0, sizeof(*id)); =20 - /* PMEM only */ - snprintf(id->fw_revision, 0x10, "BWFW VERSION %02d", 0); + /* Version 0: PMEM Only. Version 1: PMEM and VMEM */ + snprintf(id->fw_revision, 0x10, "BWFW VERSION %02d", 1); =20 - id->total_capacity =3D size / (256 << 20); - id->persistent_capacity =3D size / (256 << 20); + size /=3D (256 << 20); + id->total_capacity =3D size; + id->persistent_capacity =3D ct3d->is_pmem ? size : 0; + id->volatile_capacity =3D ct3d->is_pmem ? 0 : size; id->lsa_size =3D cvc->get_lsa_size(ct3d); =20 *len =3D sizeof(*id); @@ -312,16 +314,18 @@ static ret_code cmd_ccls_get_partition_info(struct cx= l_cmd *cmd, uint64_t next_pmem; } QEMU_PACKED *part_info =3D (void *)cmd->payload; QEMU_BUILD_BUG_ON(sizeof(*part_info) !=3D 0x20); - uint64_t size =3D cxl_dstate->pmem_size; + + CXLType3Dev *ct3d =3D container_of(cxl_dstate, CXLType3Dev, cxl_dstate= ); + uint64_t size =3D cxl_dstate->mem_size; =20 if (!QEMU_IS_ALIGNED(size, 256 << 20)) { return CXL_MBOX_INTERNAL_ERROR; } =20 - /* PMEM only */ - part_info->active_vmem =3D 0; + size /=3D (256 << 20); + part_info->active_vmem =3D ct3d->is_pmem ? 0 : size; part_info->next_vmem =3D 0; - part_info->active_pmem =3D size / (256 << 20); + part_info->active_pmem =3D ct3d->is_pmem ? size : 0; part_info->next_pmem =3D 0; =20 *len =3D sizeof(*part_info); diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index ada2108fac..18c5b9ff90 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -111,7 +111,7 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error *= *errp) error_setg(errp, "memdev property must be set"); return false; } - memory_region_set_nonvolatile(mr, true); + memory_region_set_nonvolatile(mr, ct3d->is_pmem); memory_region_set_enabled(mr, true); host_memory_backend_set_mapped(ct3d->hostmem, true); =20 @@ -123,7 +123,7 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error *= *errp) address_space_init(&ct3d->hostmem_as, mr, name); g_free(name); =20 - ct3d->cxl_dstate.pmem_size =3D ct3d->hostmem->size; + ct3d->cxl_dstate.mem_size =3D ct3d->hostmem->size; =20 if (!ct3d->lsa) { error_setg(errp, "lsa property must be set"); @@ -271,6 +271,7 @@ static void ct3d_reset(DeviceState *dev) } =20 static Property ct3_props[] =3D { + DEFINE_PROP_BOOL("pmem", CXLType3Dev, is_pmem, false), DEFINE_PROP_LINK("memdev", CXLType3Dev, hostmem, TYPE_MEMORY_BACKEND, HostMemoryBackend *), DEFINE_PROP_LINK("lsa", CXLType3Dev, lsa, TYPE_MEMORY_BACKEND, @@ -278,6 +279,7 @@ static Property ct3_props[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 + static uint64_t get_lsa_size(CXLType3Dev *ct3d) { MemoryRegion *mr; @@ -338,10 +340,10 @@ static void ct3_class_init(ObjectClass *oc, void *dat= a) pc->class_id =3D PCI_CLASS_STORAGE_EXPRESS; pc->vendor_id =3D PCI_VENDOR_ID_INTEL; pc->device_id =3D 0xd93; /* LVF for now */ - pc->revision =3D 1; + pc->revision =3D 2; =20 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); - dc->desc =3D "CXL PMEM Device (Type 3)"; + dc->desc =3D "CXL Memory Device (Type 3)"; dc->reset =3D ct3d_reset; device_class_set_props(dc, ct3_props); =20 diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 1e141b6621..67fc65f047 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -117,8 +117,8 @@ typedef struct cxl_device_state { uint64_t host_set; } timestamp; =20 - /* memory region for persistent memory, HDM */ - uint64_t pmem_size; + /* memory region for persistent and volatile memory, HDM */ + uint64_t mem_size; } CXLDeviceState; =20 /* Initialize the register block for a device */ @@ -235,6 +235,7 @@ struct CXLType3Dev { PCIDevice parent_obj; =20 /* Properties */ + bool is_pmem; HostMemoryBackend *hostmem; HostMemoryBackend *lsa; =20 diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 2ebeb530b2..40c392056d 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1578,13 +1578,13 @@ static void test_acpi_q35_cxl(void) " -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id= =3Dcxl.1" " -device pxb-cxl,bus_nr=3D222,bus=3Dpcie.0,i= d=3Dcxl.2" " -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Drp= 1,chassis=3D0,slot=3D2" - " -device cxl-type3,bus=3Drp1,memdev=3Dcxl-me= m1,lsa=3Dlsa1" + " -device cxl-type3,bus=3Drp1,pmem=3Dtrue,mem= dev=3Dcxl-mem1,lsa=3Dlsa1" " -device cxl-rp,port=3D1,bus=3Dcxl.1,id=3Drp= 2,chassis=3D0,slot=3D3" - " -device cxl-type3,bus=3Drp2,memdev=3Dcxl-me= m2,lsa=3Dlsa2" + " -device cxl-type3,bus=3Drp2,pmem=3Dtrue,mem= dev=3Dcxl-mem2,lsa=3Dlsa2" " -device cxl-rp,port=3D0,bus=3Dcxl.2,id=3Drp= 3,chassis=3D0,slot=3D5" - " -device cxl-type3,bus=3Drp3,memdev=3Dcxl-me= m3,lsa=3Dlsa3" + " -device cxl-type3,bus=3Drp3,pmem=3Dtrue,mem= dev=3Dcxl-mem3,lsa=3Dlsa3" " -device cxl-rp,port=3D1,bus=3Dcxl.2,id=3Drp= 4,chassis=3D0,slot=3D6" - " -device cxl-type3,bus=3Drp4,memdev=3Dcxl-me= m4,lsa=3Dlsa4" + " -device cxl-type3,bus=3Drp4,pmem=3Dtrue,mem= dev=3Dcxl-mem4,lsa=3Dlsa4" " -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.si= ze=3D4G,cxl-fmw.0.interleave-granularity=3D8k," "cxl-fmw.1.targets.0=3Dcxl.1,cxl-fmw.1.target= s.1=3Dcxl.2,cxl-fmw.1.size=3D4G,cxl-fmw.1.interleave-granularity=3D8k", tmp_path, tmp_path, tmp_path, tmp_path, diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c index cbe0fb549b..667e590c5f 100644 --- a/tests/qtest/cxl-test.c +++ b/tests/qtest/cxl-test.c @@ -31,27 +31,40 @@ =20 #define QEMU_T3D "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s,= size=3D256M " \ "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,size= =3D256M " \ - "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,lsa=3Dlsa0= ,id=3Dcxl-pmem0 " + "-device cxl-type3,bus=3Drp0,pmem=3Dfalse,memdev=3Dcxl-me= m0," \ + "lsa=3Dlsa0,id=3Dcxl-pmem0 " + +#define QEMU_T3DV "-object memory-backend-ram,id=3Dcxl-mem0,size=3D256M " \ + "-object memory-backend-ram,id=3Dlsa0,size=3D256M " \ + "-device cxl-type3,bus=3Drp0,pmem=3Dtrue,memdev=3Dcxl-me= m0," \ + "lsa=3Dlsa0,id=3Dcxl-pmem0 " + =20 #define QEMU_2T3D "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s= ,size=3D256M " \ "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,siz= e=3D256M " \ - "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,lsa=3Dlsa= 0,id=3Dcxl-pmem0 " \ + "-device cxl-type3,bus=3Drp0,pmem=3Dtrue,memdev=3Dcxl-me= m0," \ + "lsa=3Dlsa0,id=3Dcxl-pmem0 " \ "-object memory-backend-file,id=3Dcxl-mem1,mem-path=3D%s= ,size=3D256M " \ "-object memory-backend-file,id=3Dlsa1,mem-path=3D%s,siz= e=3D256M " \ - "-device cxl-type3,bus=3Drp1,memdev=3Dcxl-mem1,lsa=3Dlsa= 1,id=3Dcxl-pmem1 " + "-device cxl-type3,bus=3Drp1,pmem=3Dtrue,memdev=3Dcxl-me= m1," \ + "lsa=3Dlsa1,id=3Dcxl-pmem1 " =20 #define QEMU_4T3D "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s= ,size=3D256M " \ "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,siz= e=3D256M " \ - "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,lsa=3Dlsa= 0,id=3Dcxl-pmem0 " \ + "-device cxl-type3,bus=3Drp0,pmem=3Dtrue,memdev=3Dcxl-me= m0," \ + "lsa=3Dlsa0,id=3Dcxl-pmem0 " \ "-object memory-backend-file,id=3Dcxl-mem1,mem-path=3D%s= ,size=3D256M " \ "-object memory-backend-file,id=3Dlsa1,mem-path=3D%s,siz= e=3D256M " \ - "-device cxl-type3,bus=3Drp1,memdev=3Dcxl-mem1,lsa=3Dlsa= 1,id=3Dcxl-pmem1 " \ + "-device cxl-type3,bus=3Drp1,pmem=3Dtrue,memdev=3Dcxl-me= m1," \ + "lsa=3Dlsa1,id=3Dcxl-pmem1 " \ "-object memory-backend-file,id=3Dcxl-mem2,mem-path=3D%s= ,size=3D256M " \ "-object memory-backend-file,id=3Dlsa2,mem-path=3D%s,siz= e=3D256M " \ - "-device cxl-type3,bus=3Drp2,memdev=3Dcxl-mem2,lsa=3Dlsa= 2,id=3Dcxl-pmem2 " \ + "-device cxl-type3,bus=3Drp2,pmem=3Dtrue,memdev=3Dcxl-me= m2," \ + "lsa=3Dlsa2,id=3Dcxl-pmem2 " \ "-object memory-backend-file,id=3Dcxl-mem3,mem-path=3D%s= ,size=3D256M " \ "-object memory-backend-file,id=3Dlsa3,mem-path=3D%s,siz= e=3D256M " \ - "-device cxl-type3,bus=3Drp3,memdev=3Dcxl-mem3,lsa=3Dlsa= 3,id=3Dcxl-pmem3 " + "-device cxl-type3,bus=3Drp3,pmem=3Dtrue,memdev=3Dcxl-me= m3," \ + "lsa=3Dlsa3,id=3Dcxl-pmem3 " =20 static void cxl_basic_hb(void) { @@ -103,6 +116,19 @@ static void cxl_t3d(void) qtest_end(); } =20 +static void cxl_t3d_vmem(void) +{ + g_autoptr(GString) cmdline =3D g_string_new(NULL); + g_autofree const char *tmpfs =3D NULL; + + tmpfs =3D g_dir_make_tmp("cxl-test-XXXXXX", NULL); + + g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3DV); + + qtest_start(cmdline->str); + qtest_end(); +} + static void cxl_1pxb_2rp_2t3d(void) { g_autoptr(GString) cmdline =3D g_string_new(NULL); @@ -145,6 +171,7 @@ int main(int argc, char **argv) qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); #ifdef CONFIG_POSIX qtest_add_func("/pci/cxl/type3_device", cxl_t3d); + qtest_add_func("/pci/cxl/type3_vmem_device", cxl_t3d_vmem); qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4= t3d); #endif --=20 2.37.3