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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: stefanha@redhat.com,
Leandro Lupori <leandro.lupori@eldorado.org.br>
Subject: [PULL 19/20] tcg/ppc: Optimize 26-bit jumps
Date: Tue, 4 Oct 2022 12:52:40 -0700
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From: Leandro Lupori <leandro.lupori@eldorado.org.br>
PowerPC64 processors handle direct branches better than indirect
ones, resulting in less stalled cycles and branch misses.
However, PPC's tb_target_set_jmp_target() was only using direct
branches for 16-bit jumps, while PowerPC64's unconditional branch
instructions are able to handle displacements of up to 26 bits.
To take advantage of this, now jumps whose displacements fit in
between 17 and 26 bits are also converted to direct branches.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
[rth: Expanded some commentary.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 119 +++++++++++++++++++++++++++++----------
1 file changed, 88 insertions(+), 31 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 1cbd047ab3..e3dba47697 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -1847,44 +1847,101 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
tcg_out32(s, insn);
}
=20
+static inline uint64_t make_pair(tcg_insn_unit i1, tcg_insn_unit i2)
+{
+ if (HOST_BIG_ENDIAN) {
+ return (uint64_t)i1 << 32 | i2;
+ }
+ return (uint64_t)i2 << 32 | i1;
+}
+
+static inline void ppc64_replace2(uintptr_t rx, uintptr_t rw,
+ tcg_insn_unit i0, tcg_insn_unit i1)
+{
+#if TCG_TARGET_REG_BITS =3D=3D 64
+ qatomic_set((uint64_t *)rw, make_pair(i0, i1));
+ flush_idcache_range(rx, rw, 8);
+#else
+ qemu_build_not_reached();
+#endif
+}
+
+static inline void ppc64_replace4(uintptr_t rx, uintptr_t rw,
+ tcg_insn_unit i0, tcg_insn_unit i1,
+ tcg_insn_unit i2, tcg_insn_unit i3)
+{
+ uint64_t p[2];
+
+ p[!HOST_BIG_ENDIAN] =3D make_pair(i0, i1);
+ p[HOST_BIG_ENDIAN] =3D make_pair(i2, i3);
+
+ /*
+ * There's no convenient way to get the compiler to allocate a pair
+ * of registers at an even index, so copy into r6/r7 and clobber.
+ */
+ asm("mr %%r6, %1\n\t"
+ "mr %%r7, %2\n\t"
+ "stq %%r6, %0"
+ : "=3DQ"(*(__int128 *)rw) : "r"(p[0]), "r"(p[1]) : "r6", "r7");
+ flush_idcache_range(rx, rw, 16);
+}
+
void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
uintptr_t jmp_rw, uintptr_t addr)
{
- if (TCG_TARGET_REG_BITS =3D=3D 64) {
- tcg_insn_unit i1, i2;
- intptr_t tb_diff =3D addr - tc_ptr;
- intptr_t br_diff =3D addr - (jmp_rx + 4);
- uint64_t pair;
+ tcg_insn_unit i0, i1, i2, i3;
+ intptr_t tb_diff =3D addr - tc_ptr;
+ intptr_t br_diff =3D addr - (jmp_rx + 4);
+ intptr_t lo, hi;
=20
- /* This does not exercise the range of the branch, but we do
- still need to be able to load the new value of TCG_REG_TB.
- But this does still happen quite often. */
- if (tb_diff =3D=3D (int16_t)tb_diff) {
- i1 =3D ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
- i2 =3D B | (br_diff & 0x3fffffc);
- } else {
- intptr_t lo =3D (int16_t)tb_diff;
- intptr_t hi =3D (int32_t)(tb_diff - lo);
- assert(tb_diff =3D=3D hi + lo);
- i1 =3D ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
- i2 =3D ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
- }
-#if HOST_BIG_ENDIAN
- pair =3D (uint64_t)i1 << 32 | i2;
-#else
- pair =3D (uint64_t)i2 << 32 | i1;
-#endif
-
- /* As per the enclosing if, this is ppc64. Avoid the _Static_asse=
rt
- within qatomic_set that would fail to build a ppc32 host. */
- qatomic_set__nocheck((uint64_t *)jmp_rw, pair);
- flush_idcache_range(jmp_rx, jmp_rw, 8);
- } else {
+ if (TCG_TARGET_REG_BITS =3D=3D 32) {
intptr_t diff =3D addr - jmp_rx;
tcg_debug_assert(in_range_b(diff));
qatomic_set((uint32_t *)jmp_rw, B | (diff & 0x3fffffc));
flush_idcache_range(jmp_rx, jmp_rw, 4);
+ return;
}
+
+ /*
+ * For 16-bit displacements, we can use a single add + branch.
+ * This happens quite often.
+ */
+ if (tb_diff =3D=3D (int16_t)tb_diff) {
+ i0 =3D ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
+ i1 =3D B | (br_diff & 0x3fffffc);
+ ppc64_replace2(jmp_rx, jmp_rw, i0, i1);
+ return;
+ }
+
+ lo =3D (int16_t)tb_diff;
+ hi =3D (int32_t)(tb_diff - lo);
+ assert(tb_diff =3D=3D hi + lo);
+ i0 =3D ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
+ i1 =3D ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
+
+ /*
+ * Without stq from 2.07, we can only update two insns,
+ * and those must be the ones that load the target address.
+ */
+ if (!have_isa_2_07) {
+ ppc64_replace2(jmp_rx, jmp_rw, i0, i1);
+ return;
+ }
+
+ /*
+ * For 26-bit displacements, we can use a direct branch.
+ * Otherwise we still need the indirect branch, which we
+ * must restore after a potential direct branch write.
+ */
+ br_diff -=3D 4;
+ if (in_range_b(br_diff)) {
+ i2 =3D B | (br_diff & 0x3fffffc);
+ i3 =3D NOP;
+ } else {
+ i2 =3D MTSPR | RS(TCG_REG_TB) | CTR;
+ i3 =3D BCCTR | BO_ALWAYS;
+ }
+ ppc64_replace4(jmp_rx, jmp_rw, i0, i1, i2, i3);
}
=20
static void tcg_out_call_int(TCGContext *s, int lk,
@@ -2574,8 +2631,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
if (s->tb_jmp_insn_offset) {
/* Direct jump. */
if (TCG_TARGET_REG_BITS =3D=3D 64) {
- /* Ensure the next insns are 8-byte aligned. */
- if ((uintptr_t)s->code_ptr & 7) {
+ /* Ensure the next insns are 8 or 16-byte aligned. */
+ while ((uintptr_t)s->code_ptr & (have_isa_2_07 ? 15 : 7)) {
tcg_out32(s, NOP);
}
s->tb_jmp_insn_offset[args[0]] =3D tcg_current_code_size(s=
);
--=20
2.34.1