From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664913495; cv=none; d=zohomail.com; s=zohoarc; b=UfcC8DJA+r+3riCcnusX3ySr+ODBBmeoQCr0xvEqd7Auendsft2dYea2lMsuraStFJV89PtnGgyixCxCGHyO0WU7q6tYkS328HIME8CPnUCf8ZnZKMCbWznSXTmHtjOkYxkdCJXWqlC+QB2s6jr1x/uIvh14XOvcRHk58iPNnHs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664913495; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nRMEXB7YPadVE5hdI4341oxvhxYYKiN9qf3uVsx6pus=; b=a9ap+awKBo7VQ3zqYp7L1xOzvnWN8i/RWYGKPJdPVBA0Cfiz6T2dQ+NIYxYQEWKaNfLwO9yP9wmxwtNkOz4gJniC/0o0sdaWaMMzWNy58/EyACeExkaOaAy8yzvf1+LsFOY/p+gIhwNmhWnlFd5ouqhPS43cGhWbtfBkqeaoLNE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166491349518010.843714890172464; Tue, 4 Oct 2022 12:58:15 -0700 (PDT) Received: from localhost ([::1]:42040 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofo3S-0006yq-55 for importer@patchew.org; Tue, 04 Oct 2022 15:58:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41258) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyC-0001hR-5d for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:48 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:45666) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofny8-0000F8-RF for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:46 -0400 Received: by mail-pg1-x535.google.com with SMTP id r18so446926pgr.12 for ; Tue, 04 Oct 2022 12:52:44 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.52.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:52:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=nRMEXB7YPadVE5hdI4341oxvhxYYKiN9qf3uVsx6pus=; b=Ovr8LVjxTZV4jPUkhmNVH/mkP4ioR74o75OUxxB7YAzmGKP+yEx8B2HyRPgvBcubo+ ZjhA450AErjI0/ZdHO7XfKlU5bfxJcX+O38N3FO1YD3JE/0ZFIFoauOdAM+ga367jBVo AIK4sbKwse3aTuLqsq3ASj59GOA8FRKm09LKNHV0qx/APAIJT09QMX6AgxvP4nm/zzL9 VdwMXytkGaNpgYTUkmDkMb6wWRZqX3wapmaf7z5PlufRFMSBsAOuWBhz8zJ4flq6r/5p Pf94sLuWUxeiXEgIW6nhFBtpJKxYV+iTtBozCjBEZTprjPDbDmhbY0OIN/Vz0SKM04sP DScA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=nRMEXB7YPadVE5hdI4341oxvhxYYKiN9qf3uVsx6pus=; b=VZr0RD54+vUGepN4mwIbsnRZSybqhuJ5wjjRIy/IpYJ+qLQFV+AZ4QYhjr8vZHePHD R4VCqg6cVXRKrdt4hAnekEV5Ia7gUX6AaJ6U2mMvUeVNHHjdN/cFVwThm6VrQtdc10RP JATvd1iM2+b+wdFarx5MBZQIezN+XQIUoKq3O0g2/z3NRssfMFXOHzfr1MjdMJwlrqpm hjobe1WD40A4iXD6AMy77NPD4lmaKzLDtvQ939ADIXIZtZ5fOMHqZ1yLL00iRj5eW/+H uLGHxyxeHwOuzWTOAGg/o3zQFpKFaNx4FNWmPw91YhxtP4V9Xe/oCLMlMXI/OxdxHTQt N8lg== X-Gm-Message-State: ACrzQf0kUKtpJYe21mTphWpIpxUlz14t6hexhOCYSptCUk6fjV5fg5S4 et6FRj7FTi/j5poqpsXtDhJwqkpN7LKSCw== X-Google-Smtp-Source: AMsMyM6kNK9ny1qiTxf01FTX49ldjKcCPs6qbFn2OIL66cUxRscvrLI2nFnL1h9xJHGKdP56DUkyMw== X-Received: by 2002:a05:6a00:2449:b0:528:3a29:e79d with SMTP id d9-20020a056a00244900b005283a29e79dmr29488266pfj.39.1664913163539; Tue, 04 Oct 2022 12:52:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 01/20] cpu: cache CPUClass in CPUState for hot code paths Date: Tue, 4 Oct 2022 12:52:22 -0700 Message-Id: <20221004195241.46491-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664913496468100001 From: Alex Benn=C3=A9e The class cast checkers are quite expensive and always on (unlike the dynamic case who's checks are gated by CONFIG_QOM_CAST_DEBUG). To avoid the overhead of repeatedly checking something which should never change we cache the CPUClass reference for use in the hot code paths. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-Id: <20220811151413.3350684-3-alex.bennee@linaro.org> Signed-off-by: C=C3=A9dric Le Goater Message-Id: <20220923084803.498337-3-clg@kaod.org> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 9 +++++++++ cpu.c | 9 ++++----- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 500503da13..1a7e1a9380 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -51,6 +51,13 @@ typedef int (*WriteCoreDumpFunction)(const void *buf, si= ze_t size, */ #define CPU(obj) ((CPUState *)(obj)) =20 +/* + * The class checkers bring in CPU_GET_CLASS() which is potentially + * expensive given the eventual call to + * object_class_dynamic_cast_assert(). Because of this the CPUState + * has a cached value for the class in cs->cc which is set up in + * cpu_exec_realizefn() for use in hot code paths. + */ typedef struct CPUClass CPUClass; DECLARE_CLASS_CHECKERS(CPUClass, CPU, TYPE_CPU) @@ -317,6 +324,8 @@ struct qemu_work_item; struct CPUState { /*< private >*/ DeviceState parent_obj; + /* cache to avoid expensive CPU_GET_CLASS */ + CPUClass *cc; /*< public >*/ =20 int nr_cores; diff --git a/cpu.c b/cpu.c index 584ac78baf..14365e36f3 100644 --- a/cpu.c +++ b/cpu.c @@ -131,9 +131,8 @@ const VMStateDescription vmstate_cpu_common =3D { =20 void cpu_exec_realizefn(CPUState *cpu, Error **errp) { -#ifndef CONFIG_USER_ONLY - CPUClass *cc =3D CPU_GET_CLASS(cpu); -#endif + /* cache the cpu class for the hotpath */ + cpu->cc =3D CPU_GET_CLASS(cpu); =20 cpu_list_add(cpu); if (!accel_cpu_realizefn(cpu, errp)) { @@ -151,8 +150,8 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); } - if (cc->sysemu_ops->legacy_vmsd !=3D NULL) { - vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd= , cpu); + if (cpu->cc->sysemu_ops->legacy_vmsd !=3D NULL) { + vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy= _vmsd, cpu); } #endif /* CONFIG_USER_ONLY */ } --=20 2.34.1 From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664913631; cv=none; d=zohomail.com; s=zohoarc; b=nAdd+v2VmaRoRQpI9Vm3m/Q8AWt9meRHZ4UbRBc7hv8u/lkxuKOzE23pWDFoD00SvoItkD63B9ivzCWwgEFjr7VOUGu81PQ3njZ4eSKowCQYEr6JDN622H4REW+L8wksaOMOx6P1FH6By1HU14+mVdwz4IW+meCY5f6UYWDIZ4o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664913631; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FcUiK2Okdru3cG4LiS1rgcAo1RAHSsbMmma9k9kUJWI=; b=gAriRt9c25s5geuHV4i7JqBezwKU5YnKJrXRHG4cHmaQmGNc8lwLBChve4uUI2n3p3s7UEra4UwlhxOz8C07G4K0hZ8O9ZyMYOzSDNxybqgdASsQYh7f5QOuVHsqmEApIz+GsxfwRAbAv7fB+w1Tn6qCYAguNH9gt90BwYxo6Z8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664913631973181.41413476389937; Tue, 4 Oct 2022 13:00:31 -0700 (PDT) Received: from localhost ([::1]:40930 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofo5d-0002PA-8n for importer@patchew.org; Tue, 04 Oct 2022 16:00:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41260) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyC-0001hc-Sn for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:49 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:45940) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofnyA-0000FQ-4s for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:48 -0400 Received: by mail-pj1-x102f.google.com with SMTP id o9-20020a17090a0a0900b0020ad4e758b3so3329753pjo.4 for ; Tue, 04 Oct 2022 12:52:45 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.52.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:52:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=FcUiK2Okdru3cG4LiS1rgcAo1RAHSsbMmma9k9kUJWI=; b=kuBZvX5feW4t64zNS9h+KCca7LFoyZtDleefHmb3s5RqSF1SZPn8sdNGESf0hOfmF9 KLsKEjnyF0FDmAL5S3TN5l91e+OgOnxO3m5o+GPC+gI0UM2fM6qoOYPuWGVvl5VnRlEj dxquTvo0ASip/L8XVHEkJiJYoS/Gi/LcAn8hm3kIQjFmOjonZfFVsJ83VAGO3f5qxODC rUmrGABrnrb4ToLS/bOh29YdZnCkp5VrBUNQFJhcWNyqK+lx6JYF+5IGVU1upDpMWnfv 3P/nzn4eLw2sRfTG39Fiz4tHKp9+LowQ3Rkg4+orsllwxXQMmNXlWOSw383l0wLjoa8m Smxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=FcUiK2Okdru3cG4LiS1rgcAo1RAHSsbMmma9k9kUJWI=; b=OjAs34NpBOY2pJ2mqmuIgTZLrM9jW7p/4/rA/0wEbojQMPWEzY8/F1BA1ZxHiVVPcU 7yNp9JckJudXFiINmUd7hxsoDl+HrHaYJN2utiqMQoQ2JrN/CzgiXGT+EoRP9T/Rba9Q XVZpBR+LkQuuYGwlJUEYcm6UR2lpnkZI0l03uqER6mAe6SSDpe/R32xUcNvsey+1UYBY 5PlhrkLMvVw6z2MFn7cMUNbfe6YhB79KtDAZSHnhN+xO2zLxna4JL4qKvx53D2GgO3dX SBKdkv8UF35lUTJg+yZlflHPLp1S8vWFCrN/RQjCXaoB2RsUqAL4qnNYyKAUcv0AkRPv HJIw== X-Gm-Message-State: ACrzQf0zsqXmFT/JbSu/A3bPcGfVsTcEKAkYH2wl0swWKrCSOkmhCV2r 2qrrFLoOk8XdLDwigA7Mmdo7pmDfBA8hvg== X-Google-Smtp-Source: AMsMyM5rOV7t9AKsgCY6qmS01tmPsH5/tIG/c9l+OED8WlrvMC5qUXLWPyEvbZP+TgNFkQUreRO0qg== X-Received: by 2002:a17:902:7b95:b0:178:ab50:76b5 with SMTP id w21-20020a1709027b9500b00178ab5076b5mr28864247pll.161.1664913164593; Tue, 04 Oct 2022 12:52:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 02/20] hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs Date: Tue, 4 Oct 2022 12:52:23 -0700 Message-Id: <20221004195241.46491-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664913633133100001 From: Alex Benn=C3=A9e This is a heavily used function so lets avoid the cost of CPU_GET_CLASS. On the romulus-bmc run it has a modest effect: Before: 36.812 s =C2=B1 0.506 s After: 35.912 s =C2=B1 0.168 s Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-Id: <20220811151413.3350684-4-alex.bennee@linaro.org> Signed-off-by: C=C3=A9dric Le Goater Message-Id: <20220923084803.498337-4-clg@kaod.org> Signed-off-by: Richard Henderson --- hw/core/cpu-sysemu.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index 00253f8929..5eaf2e79e6 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -69,11 +69,10 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr add= r) =20 int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); int ret =3D 0; =20 - if (cc->sysemu_ops->asidx_from_attrs) { - ret =3D cc->sysemu_ops->asidx_from_attrs(cpu, attrs); + if (cpu->cc->sysemu_ops->asidx_from_attrs) { + ret =3D cpu->cc->sysemu_ops->asidx_from_attrs(cpu, attrs); assert(ret < cpu->num_ases && ret >=3D 0); } return ret; --=20 2.34.1 From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664913456; cv=none; d=zohomail.com; s=zohoarc; b=UvzEIlsF1cspsU/YRwB+KJNNgXjhcUHrx6BSlHL3Rmb881ibyVT8u9Ue2ofWpuUWc30bPT/NO6NkmoSjvYU8I+NjonlBq87/1s5vjIaiUL+29izymQ22Kim6R3GpQHwFxrZ8v+YFLByn5FuozgzBdsyhxvi9TALMFPtd4dcZ4ZA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664913456; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=q0eg+3QiI3aRqtvdrrAtNwv7hcqy9NWtzJtlLArJ6SQ=; b=cXc7md39Y1Ls65sqGbdYfJjD/E72iGWQPY8L9qXPJNE69eeYZe+SnAQ7Szsj5SoESk3jfSrgIW19eZX7+QHjbccvEFVGqsAq2hQogr1NVLF+nJt7i8sIdpZU0jheL76s+8/n5eluqBiv/FKtDsrXXMiH9ftQPud4cWrzTm7VKq4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664913456158711.1453449568069; Tue, 4 Oct 2022 12:57:36 -0700 (PDT) Received: from localhost ([::1]:59862 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofo2p-0004pn-3I for importer@patchew.org; Tue, 04 Oct 2022 15:57:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41262) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyD-0001hq-Kv for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:50 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:34357) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofnyB-0000FZ-2D for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:49 -0400 Received: by mail-pl1-x633.google.com with SMTP id n7so13566911plp.1 for ; Tue, 04 Oct 2022 12:52:46 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.52.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:52:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=q0eg+3QiI3aRqtvdrrAtNwv7hcqy9NWtzJtlLArJ6SQ=; b=MF2kf+e30KGYajtSlps4xlAxA2V5HaJx31EtVVrG9j427FWLhwxps+HcmV3H3a4cWg 1jnddZBhLWiTia5Wxpjk6eCsKB+iMEK2ZPVNBpyyGGke1kywWbWtyRVHn64hkt27fv1K GwVwTSoHHb3NPpF/s4Prs0wvhca4t69/fj+aRoMGrsby9XUf6IZrtJodFJYfmGmNrb45 uwQLqRYeTHq6rBGPBRlN8+xBJjHpFGXLCd8tPJ7cR/dNQUjwuNdBS3SuUU604J00l8Jb X5OF70vUPRbFKq4J5/YzBQXwHswPECr/faTt8H3rJ2Jq/a+5TXUB2Duno9yi2OqPizue TynA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=q0eg+3QiI3aRqtvdrrAtNwv7hcqy9NWtzJtlLArJ6SQ=; b=hTH145/z0+HsCsfvA4Ab0NU26Jb/DAJqrtuAlqCsz8A8K+xG2i26y47gnIsTz0tHiI XunJMoh3B48aUz9pT4lkzrp0QdBqfPDTN8+oYcb9J0JMmAOQZFOOqUxz4+MybHm1FCdY gH8R8Kwm8NVdwHxv6qi+plevB5QV6lh2nMb9letwWfk/H1Pij+RCreUIvTlJsLyyUOkb sFHwxSSNe7pbI0qRE660p/Uj9erXGzeFrQlDrnx+6+nNYJ6cYiPDxvtqxvDEQcoMmMlN EO70SsQbiwJIJc32LVJbCHBIDY3UYL0Wq39ow3kSeEsgA1vOLK6tdQpOP5drYkblugDR wuow== X-Gm-Message-State: ACrzQf2nW3T5wKaSNyqI7u0sJgkb7lfMy5QUVMN+FYEATuWCSzgoTpqA LZpWQSHFTRw80e/7Uh4q4BnTpzp9if2avQ== X-Google-Smtp-Source: AMsMyM5Q3DKSLQ5bvOvNuG+AexgH4+43TlI17vPsi77MIUzVy597XKdqc2w3NZKH3ni7Douug5PZZg== X-Received: by 2002:a17:902:edcd:b0:17a:6fa:228d with SMTP id q13-20020a170902edcd00b0017a06fa228dmr28581603plk.29.1664913165607; Tue, 04 Oct 2022 12:52:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 03/20] cputlb: used cached CPUClass in our hot-paths Date: Tue, 4 Oct 2022 12:52:24 -0700 Message-Id: <20221004195241.46491-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664913456952100001 From: Alex Benn=C3=A9e Before: 35.912 s =C2=B1 0.168 s After: 35.565 s =C2=B1 0.087 s Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-Id: <20220811151413.3350684-5-alex.bennee@linaro.org> Signed-off-by: C=C3=A9dric Le Goater Message-Id: <20220923084803.498337-5-clg@kaod.org> Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 8fad2d9b83..193bfc1cfc 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1291,15 +1291,14 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, static void tlb_fill(CPUState *cpu, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t ret= addr) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); bool ok; =20 /* * This is not a probe, so only valid return is success; failure * should result in exception + longjmp to the cpu loop. */ - ok =3D cc->tcg_ops->tlb_fill(cpu, addr, size, - access_type, mmu_idx, false, retaddr); + ok =3D cpu->cc->tcg_ops->tlb_fill(cpu, addr, size, + access_type, mmu_idx, false, retaddr); assert(ok); } =20 @@ -1307,9 +1306,8 @@ static inline void cpu_unaligned_access(CPUState *cpu= , vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, mmu_idx, reta= ddr); + cpu->cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, + mmu_idx, retaddr); } =20 static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, @@ -1539,10 +1537,9 @@ static int probe_access_internal(CPUArchState *env, = target_ulong addr, if (!tlb_hit_page(tlb_addr, page_addr)) { if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) { CPUState *cs =3D env_cpu(env); - CPUClass *cc =3D CPU_GET_CLASS(cs); =20 - if (!cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_type, - mmu_idx, nonfault, retaddr)) { + if (!cs->cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_ty= pe, + mmu_idx, nonfault, retaddr)) { /* Non-faulting page table read failed. */ *phost =3D NULL; return TLB_INVALID_MASK; --=20 2.34.1 From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664913711; cv=none; d=zohomail.com; s=zohoarc; b=m4qMOsm0pocHLS2/P/5k2zG3PbO861wRrfw0zj4ildus3BZ/QreOBKffZg2F4+A7kP28YmrCt9088MDgVOJDVkrGAUfKBtzfzatGXjJcFR/A4hI7J3Xnxd790TVo6ewFTbOWgYnvhvWV1WN//tn/g+Zyk5VuDfKnPuGhYBhZqQc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664913711; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=egSMCzuiwg0v2IHxtNXQw4L5wKP7YmYYVIDjRNnn+8I=; b=dxeiVbuNfAW3llgxtzTZrUH+pw2hjJiXllIKiN4J8KDHYrxZNH7lGMhCnE6jwUPIJrU5D1ly/l50rKLuVi+Y0m9vaU4ibvahroen7W5rfzuJAjlJ7fgPr4DTquiz7G2/p4nexE3ztvZuSFHDUmek55y7y2jmPhsQ8+M90QfTOKg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664913711183520.4639581129927; Tue, 4 Oct 2022 13:01:51 -0700 (PDT) Received: from localhost ([::1]:34806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofo6u-0002jE-Ud for importer@patchew.org; Tue, 04 Oct 2022 16:01:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41266) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyF-0001iO-PZ for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:52 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:40531) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofnyC-0000Fs-Jn for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:51 -0400 Received: by mail-pj1-x1033.google.com with SMTP id h8-20020a17090a054800b00205ccbae31eso19549830pjf.5 for ; Tue, 04 Oct 2022 12:52:47 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.52.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:52:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=egSMCzuiwg0v2IHxtNXQw4L5wKP7YmYYVIDjRNnn+8I=; b=X3PIQfI0JlJaaWMIyf6z3xBYoB9UqR6TfV3lJR9yXPWxIgxIZEf0MnnGxXWc327XFJ RSuUsCcqYd2807yChoMtEjJhDWDKaTsnL/yd1wknVjPffhB5+Vk3iBBcH3vyIDRmGr70 tn4F/FrHDLVIjyjf5329AoE0fAviuKhIvtPZc5DH7VlfG4jQv2PAuEj9Z4GLwqFp44fk CLLihpdAKb86a5cfDHLiDXA6ho0DnReCJ5NqXoTXmHoexvDW2rwvJPCeMQht5xXFNxBQ J1sH4arAyxTR6WoLoKl/HkyOqmLhooTfv4Y/NVHsTda/f09PxAoMkUA/W1D4aGFEXr4c jPhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=egSMCzuiwg0v2IHxtNXQw4L5wKP7YmYYVIDjRNnn+8I=; b=RzRKPP7ahSatdYjDUbama4o3+tKcMseiQErlYk8yA1XO0/YKRkP95MWpfTvOkQKusq 9EH2rxlDTTe1wjcPe7UfJ3YVNqSn9ag4I9KWJR0wixtY+8S33wD1qb9ClhBvfAxq1e+y Mpyfczyvh52PxvF8eVmC5YbocZ1svarnqeT+V/leSeYWi1ajJK1CJff7Xg5GIJiL5MrK 6TYkNK46jlcZu7h5CRqhGWvI+Y05wA1OSi8AWXOOwYZx1lTh1PL/3wgDyLnRA8TSPrj4 FUCKBVHcD5h69wIgQj3AnHLymR57c//mSjRlrxv/JPLcqgSRz9QgvA7R6eBVeuxvxghe JNrg== X-Gm-Message-State: ACrzQf3fqcymREpU1vg1Fz0RcC0ZKF2fiXo4K/qpIChgPcCRP/5cDpDL N3DnTU8/OA6R6fTCyaibhjbDM+UwDxqzBQ== X-Google-Smtp-Source: AMsMyM5sgcb4r0xvADg6NzTnod199abjNt25r+LCghifMiUPg1aa5F5P7uYCBsuprRkA59yRfsUT9g== X-Received: by 2002:a17:90a:7305:b0:20a:6ffd:1f8e with SMTP id m5-20020a17090a730500b0020a6ffd1f8emr1269395pjk.69.1664913166662; Tue, 04 Oct 2022 12:52:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 04/20] accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull Date: Tue, 4 Oct 2022 12:52:25 -0700 Message-Id: <20221004195241.46491-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664913712662100001 This structure will shortly contain more than just data for accessing MMIO. Rename the 'addr' member to 'xlat_section' to more clearly indicate its purpose. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 22 ++++---- accel/tcg/cputlb.c | 102 +++++++++++++++++++------------------ target/arm/mte_helper.c | 14 ++--- target/arm/sve_helper.c | 4 +- target/arm/translate-a64.c | 2 +- 5 files changed, 73 insertions(+), 71 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index ba3cd32a1e..f70f54d850 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -108,6 +108,7 @@ typedef uint64_t target_ulong; # endif # endif =20 +/* Minimalized TLB entry for use by TCG fast path. */ typedef struct CPUTLBEntry { /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not @@ -131,14 +132,14 @@ typedef struct CPUTLBEntry { =20 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) !=3D (1 << CPU_TLB_ENTRY_BITS)); =20 -/* The IOTLB is not accessed directly inline by generated TCG code, - * so the CPUIOTLBEntry layout is not as critical as that of the - * CPUTLBEntry. (This is also why we don't want to combine the two - * structs into one.) +/* + * The full TLB entry, which is not accessed by generated TCG code, + * so the layout is not as critical as that of CPUTLBEntry. This is + * also why we don't want to combine the two structs. */ -typedef struct CPUIOTLBEntry { +typedef struct CPUTLBEntryFull { /* - * @addr contains: + * @xlat_section contains: * - in the lower TARGET_PAGE_BITS, a physical section number * - with the lower TARGET_PAGE_BITS masked off, an offset which * must be added to the virtual address to obtain: @@ -146,9 +147,9 @@ typedef struct CPUIOTLBEntry { * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) * + the offset within the target MemoryRegion (otherwise) */ - hwaddr addr; + hwaddr xlat_section; MemTxAttrs attrs; -} CPUIOTLBEntry; +} CPUTLBEntryFull; =20 /* * Data elements that are per MMU mode, minus the bits accessed by @@ -172,9 +173,8 @@ typedef struct CPUTLBDesc { size_t vindex; /* The tlb victim table, in two parts. */ CPUTLBEntry vtable[CPU_VTLB_SIZE]; - CPUIOTLBEntry viotlb[CPU_VTLB_SIZE]; - /* The iotlb. */ - CPUIOTLBEntry *iotlb; + CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE]; + CPUTLBEntryFull *fulltlb; } CPUTLBDesc; =20 /* diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 193bfc1cfc..aa22f578cb 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -200,13 +200,13 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, C= PUTLBDescFast *fast, } =20 g_free(fast->table); - g_free(desc->iotlb); + g_free(desc->fulltlb); =20 tlb_window_reset(desc, now, 0); /* desc->n_used_entries is cleared by the caller */ fast->mask =3D (new_size - 1) << CPU_TLB_ENTRY_BITS; fast->table =3D g_try_new(CPUTLBEntry, new_size); - desc->iotlb =3D g_try_new(CPUIOTLBEntry, new_size); + desc->fulltlb =3D g_try_new(CPUTLBEntryFull, new_size); =20 /* * If the allocations fail, try smaller sizes. We just freed some @@ -215,7 +215,7 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPU= TLBDescFast *fast, * allocations to fail though, so we progressively reduce the allocati= on * size, aborting if we cannot even allocate the smallest TLB we suppo= rt. */ - while (fast->table =3D=3D NULL || desc->iotlb =3D=3D NULL) { + while (fast->table =3D=3D NULL || desc->fulltlb =3D=3D NULL) { if (new_size =3D=3D (1 << CPU_TLB_DYN_MIN_BITS)) { error_report("%s: %s", __func__, strerror(errno)); abort(); @@ -224,9 +224,9 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPU= TLBDescFast *fast, fast->mask =3D (new_size - 1) << CPU_TLB_ENTRY_BITS; =20 g_free(fast->table); - g_free(desc->iotlb); + g_free(desc->fulltlb); fast->table =3D g_try_new(CPUTLBEntry, new_size); - desc->iotlb =3D g_try_new(CPUIOTLBEntry, new_size); + desc->fulltlb =3D g_try_new(CPUTLBEntryFull, new_size); } } =20 @@ -258,7 +258,7 @@ static void tlb_mmu_init(CPUTLBDesc *desc, CPUTLBDescFa= st *fast, int64_t now) desc->n_used_entries =3D 0; fast->mask =3D (n_entries - 1) << CPU_TLB_ENTRY_BITS; fast->table =3D g_new(CPUTLBEntry, n_entries); - desc->iotlb =3D g_new(CPUIOTLBEntry, n_entries); + desc->fulltlb =3D g_new(CPUTLBEntryFull, n_entries); tlb_mmu_flush_locked(desc, fast); } =20 @@ -299,7 +299,7 @@ void tlb_destroy(CPUState *cpu) CPUTLBDescFast *fast =3D &env_tlb(env)->f[i]; =20 g_free(fast->table); - g_free(desc->iotlb); + g_free(desc->fulltlb); } } =20 @@ -1219,7 +1219,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, =20 /* Evict the old entry into the victim tlb. */ copy_tlb_helper_locked(tv, te); - desc->viotlb[vidx] =3D desc->iotlb[index]; + desc->vfulltlb[vidx] =3D desc->fulltlb[index]; tlb_n_used_entries_dec(env, mmu_idx); } =20 @@ -1236,8 +1236,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, * subtract here is that of the page base, and not the same as the * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). */ - desc->iotlb[index].addr =3D iotlb - vaddr_page; - desc->iotlb[index].attrs =3D attrs; + desc->fulltlb[index].xlat_section =3D iotlb - vaddr_page; + desc->fulltlb[index].attrs =3D attrs; =20 /* Now calculate the new entry */ tn.addend =3D addend - vaddr_page; @@ -1327,7 +1327,7 @@ static inline void cpu_transaction_failed(CPUState *c= pu, hwaddr physaddr, } } =20 -static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, +static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full, int mmu_idx, target_ulong addr, uintptr_t retaddr, MMUAccessType access_type, MemOp op) { @@ -1339,9 +1339,9 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBE= ntry *iotlbentry, bool locked =3D false; MemTxResult r; =20 - section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); + section =3D iotlb_to_section(cpu, full->xlat_section, full->attrs); mr =3D section->mr; - mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; + mr_offset =3D (full->xlat_section & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc =3D retaddr; if (!cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); @@ -1351,14 +1351,14 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTL= BEntry *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_read(mr, mr_offset, &val, op, iotlbentry-= >attrs); + r =3D memory_region_dispatch_read(mr, mr_offset, &val, op, full->attrs= ); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - section->offset_within_region; =20 cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), access= _type, - mmu_idx, iotlbentry->attrs, r, retaddr); + mmu_idx, full->attrs, r, retaddr); } if (locked) { qemu_mutex_unlock_iothread(); @@ -1368,8 +1368,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBE= ntry *iotlbentry, } =20 /* - * Save a potentially trashed IOTLB entry for later lookup by plugin. - * This is read by tlb_plugin_lookup if the iotlb entry doesn't match + * Save a potentially trashed CPUTLBEntryFull for later lookup by plugin. + * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match * because of the side effect of io_writex changing memory layout. */ static void save_iotlb_data(CPUState *cs, hwaddr addr, @@ -1383,7 +1383,7 @@ static void save_iotlb_data(CPUState *cs, hwaddr addr, #endif } =20 -static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, +static void io_writex(CPUArchState *env, CPUTLBEntryFull *full, int mmu_idx, uint64_t val, target_ulong addr, uintptr_t retaddr, MemOp op) { @@ -1394,9 +1394,9 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntr= y *iotlbentry, bool locked =3D false; MemTxResult r; =20 - section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); + section =3D iotlb_to_section(cpu, full->xlat_section, full->attrs); mr =3D section->mr; - mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; + mr_offset =3D (full->xlat_section & TARGET_PAGE_MASK) + addr; if (!cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); } @@ -1406,20 +1406,20 @@ static void io_writex(CPUArchState *env, CPUIOTLBEn= try *iotlbentry, * The memory_region_dispatch may trigger a flush/resize * so for plugins we save the iotlb_data just in case. */ - save_iotlb_data(cpu, iotlbentry->addr, section, mr_offset); + save_iotlb_data(cpu, full->xlat_section, section, mr_offset); =20 if (!qemu_mutex_iothread_locked()) { qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_write(mr, mr_offset, val, op, iotlbentry-= >attrs); + r =3D memory_region_dispatch_write(mr, mr_offset, val, op, full->attrs= ); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - section->offset_within_region; =20 cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), - MMU_DATA_STORE, mmu_idx, iotlbentry->attrs,= r, + MMU_DATA_STORE, mmu_idx, full->attrs, r, retaddr); } if (locked) { @@ -1466,9 +1466,10 @@ static bool victim_tlb_hit(CPUArchState *env, size_t= mmu_idx, size_t index, copy_tlb_helper_locked(vtlb, &tmptlb); qemu_spin_unlock(&env_tlb(env)->c.lock); =20 - CPUIOTLBEntry tmpio, *io =3D &env_tlb(env)->d[mmu_idx].iotlb[i= ndex]; - CPUIOTLBEntry *vio =3D &env_tlb(env)->d[mmu_idx].viotlb[vidx]; - tmpio =3D *io; *io =3D *vio; *vio =3D tmpio; + CPUTLBEntryFull *f1 =3D &env_tlb(env)->d[mmu_idx].fulltlb[inde= x]; + CPUTLBEntryFull *f2 =3D &env_tlb(env)->d[mmu_idx].vfulltlb[vid= x]; + CPUTLBEntryFull tmpf; + tmpf =3D *f1; *f1 =3D *f2; *f2 =3D tmpf; return true; } } @@ -1481,9 +1482,9 @@ static bool victim_tlb_hit(CPUArchState *env, size_t = mmu_idx, size_t index, (ADDR) & TARGET_PAGE_MASK) =20 static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size, - CPUIOTLBEntry *iotlbentry, uintptr_t retaddr) + CPUTLBEntryFull *full, uintptr_t retaddr) { - ram_addr_t ram_addr =3D mem_vaddr + iotlbentry->addr; + ram_addr_t ram_addr =3D mem_vaddr + full->xlat_section; =20 trace_memory_notdirty_write_access(mem_vaddr, ram_addr, size); =20 @@ -1575,9 +1576,9 @@ int probe_access_flags(CPUArchState *env, target_ulon= g addr, /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUIOTLBEntry *iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[inde= x]; + CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; =20 - notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr); + notdirty_write(env_cpu(env), addr, 1, full, retaddr); flags &=3D ~TLB_NOTDIRTY; } =20 @@ -1602,19 +1603,19 @@ void *probe_access(CPUArchState *env, target_ulong = addr, int size, =20 if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) { uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUIOTLBEntry *iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[inde= x]; + CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; =20 /* Handle watchpoints. */ if (flags & TLB_WATCHPOINT) { int wp_access =3D (access_type =3D=3D MMU_DATA_STORE ? BP_MEM_WRITE : BP_MEM_READ); cpu_check_watchpoint(env_cpu(env), addr, size, - iotlbentry->attrs, wp_access, retaddr); + full->attrs, wp_access, retaddr); } =20 /* Handle clean RAM pages. */ if (flags & TLB_NOTDIRTY) { - notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr); + notdirty_write(env_cpu(env), addr, 1, full, retaddr); } } =20 @@ -1671,7 +1672,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState = *env, target_ulong addr, * should have just filled the TLB. The one corner case is io_writex * which can cause TLB flushes and potential resizing of the TLBs * losing the information we need. In those cases we need to recover - * data from a copy of the iotlbentry. As long as this always occurs + * data from a copy of the CPUTLBEntryFull. As long as this always occurs * from the same thread (which a mem callback will be) this is safe. */ =20 @@ -1686,11 +1687,12 @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong = addr, int mmu_idx, if (likely(tlb_hit(tlb_addr, addr))) { /* We must have an iotlb entry for MMIO */ if (tlb_addr & TLB_MMIO) { - CPUIOTLBEntry *iotlbentry; - iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[index]; + CPUTLBEntryFull *full; + full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; data->is_io =3D true; - data->v.io.section =3D iotlb_to_section(cpu, iotlbentry->addr,= iotlbentry->attrs); - data->v.io.offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + = addr; + data->v.io.section =3D + iotlb_to_section(cpu, full->xlat_section, full->attrs); + data->v.io.offset =3D (full->xlat_section & TARGET_PAGE_MASK) = + addr; } else { data->is_io =3D false; data->v.ram.hostaddr =3D (void *)((uintptr_t)addr + tlbe->adde= nd); @@ -1798,7 +1800,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, =20 if (unlikely(tlb_addr & TLB_NOTDIRTY)) { notdirty_write(env_cpu(env), addr, size, - &env_tlb(env)->d[mmu_idx].iotlb[index], retaddr); + &env_tlb(env)->d[mmu_idx].fulltlb[index], retaddr); } =20 return hostaddr; @@ -1906,7 +1908,7 @@ load_helper(CPUArchState *env, target_ulong addr, Mem= OpIdx oi, =20 /* Handle anything that isn't just a straight memory access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - CPUIOTLBEntry *iotlbentry; + CPUTLBEntryFull *full; bool need_swap; =20 /* For anything that is unaligned, recurse through full_load. */ @@ -1914,20 +1916,20 @@ load_helper(CPUArchState *env, target_ulong addr, M= emOpIdx oi, goto do_unaligned_access; } =20 - iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[index]; + full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; =20 /* Handle watchpoints. */ if (unlikely(tlb_addr & TLB_WATCHPOINT)) { /* On watchpoint hit, this will longjmp out. */ cpu_check_watchpoint(env_cpu(env), addr, size, - iotlbentry->attrs, BP_MEM_READ, retaddr); + full->attrs, BP_MEM_READ, retaddr); } =20 need_swap =3D size > 1 && (tlb_addr & TLB_BSWAP); =20 /* Handle I/O access. */ if (likely(tlb_addr & TLB_MMIO)) { - return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, + return io_readx(env, full, mmu_idx, addr, retaddr, access_type, op ^ (need_swap * MO_BSWAP)); } =20 @@ -2242,12 +2244,12 @@ store_helper_unaligned(CPUArchState *env, target_ul= ong addr, uint64_t val, */ if (unlikely(tlb_addr & TLB_WATCHPOINT)) { cpu_check_watchpoint(env_cpu(env), addr, size - size2, - env_tlb(env)->d[mmu_idx].iotlb[index].attrs, + env_tlb(env)->d[mmu_idx].fulltlb[index].attrs, BP_MEM_WRITE, retaddr); } if (unlikely(tlb_addr2 & TLB_WATCHPOINT)) { cpu_check_watchpoint(env_cpu(env), page2, size2, - env_tlb(env)->d[mmu_idx].iotlb[index2].attrs, + env_tlb(env)->d[mmu_idx].fulltlb[index2].attr= s, BP_MEM_WRITE, retaddr); } =20 @@ -2311,7 +2313,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, =20 /* Handle anything that isn't just a straight memory access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - CPUIOTLBEntry *iotlbentry; + CPUTLBEntryFull *full; bool need_swap; =20 /* For anything that is unaligned, recurse through byte stores. */ @@ -2319,20 +2321,20 @@ store_helper(CPUArchState *env, target_ulong addr, = uint64_t val, goto do_unaligned_access; } =20 - iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[index]; + full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; =20 /* Handle watchpoints. */ if (unlikely(tlb_addr & TLB_WATCHPOINT)) { /* On watchpoint hit, this will longjmp out. */ cpu_check_watchpoint(env_cpu(env), addr, size, - iotlbentry->attrs, BP_MEM_WRITE, retaddr); + full->attrs, BP_MEM_WRITE, retaddr); } =20 need_swap =3D size > 1 && (tlb_addr & TLB_BSWAP); =20 /* Handle I/O access. */ if (tlb_addr & TLB_MMIO) { - io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, + io_writex(env, full, mmu_idx, val, addr, retaddr, op ^ (need_swap * MO_BSWAP)); return; } @@ -2344,7 +2346,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, =20 /* Handle clean RAM pages. */ if (tlb_addr & TLB_NOTDIRTY) { - notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr); + notdirty_write(env_cpu(env), addr, size, full, retaddr); } =20 haddr =3D (void *)((uintptr_t)addr + entry->addend); diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index d11a8c70d0..fdd23ab3f8 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -106,7 +106,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, return tags + index; #else uintptr_t index; - CPUIOTLBEntry *iotlbentry; + CPUTLBEntryFull *full; int in_page, flags; ram_addr_t ptr_ra; hwaddr ptr_paddr, tag_paddr, xlat; @@ -129,7 +129,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, assert(!(flags & TLB_INVALID_MASK)); =20 /* - * Find the iotlbentry for ptr. This *must* be present in the TLB + * Find the CPUTLBEntryFull for ptr. This *must* be present in the TLB * because we just found the mapping. * TODO: Perhaps there should be a cputlb helper that returns a * matching tlb entry + iotlb entry. @@ -144,10 +144,10 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, = int ptr_mmu_idx, g_assert(tlb_hit(comparator, ptr)); } # endif - iotlbentry =3D &env_tlb(env)->d[ptr_mmu_idx].iotlb[index]; + full =3D &env_tlb(env)->d[ptr_mmu_idx].fulltlb[index]; =20 /* If the virtual page MemAttr !=3D Tagged, access unchecked. */ - if (!arm_tlb_mte_tagged(&iotlbentry->attrs)) { + if (!arm_tlb_mte_tagged(&full->attrs)) { return NULL; } =20 @@ -181,7 +181,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, int wp =3D ptr_access =3D=3D MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_= WRITE; assert(ra !=3D 0); cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, - iotlbentry->attrs, wp, ra); + full->attrs, wp, ra); } =20 /* @@ -202,11 +202,11 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, = int ptr_mmu_idx, tag_paddr =3D ptr_paddr >> (LOG2_TAG_GRANULE + 1); =20 /* Look up the address in tag space. */ - tag_asi =3D iotlbentry->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; + tag_asi =3D full->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; tag_as =3D cpu_get_address_space(env_cpu(env), tag_asi); mr =3D address_space_translate(tag_as, tag_paddr, &xlat, NULL, tag_access =3D=3D MMU_DATA_STORE, - iotlbentry->attrs); + full->attrs); =20 /* * Note that @mr will never be NULL. If there is nothing in the addre= ss diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index d6f7ef94fe..9cae8fd352 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -5384,8 +5384,8 @@ bool sve_probe_page(SVEHostPage *info, bool nofault, = CPUARMState *env, g_assert(tlb_hit(comparator, addr)); # endif =20 - CPUIOTLBEntry *iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[inde= x]; - info->attrs =3D iotlbentry->attrs; + CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + info->attrs =3D full->attrs; } #endif =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9bed336b47..78b2d91ed4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14624,7 +14624,7 @@ static bool is_guarded_page(CPUARMState *env, Disas= Context *s) * table entry even for that case. */ return (tlb_hit(entry->addr_code, addr) && - arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].iotlb[index].attrs)); + arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].fulltlb[index].attrs)= ); #endif } =20 --=20 2.34.1 From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664914115; cv=none; d=zohomail.com; s=zohoarc; b=DVnahdDCLmvMOJxRUrdduU/BsZvYY8icW5kUXwS/pueZV1Pqjztv6tzDgTc9Ut09kv4rW+CmKB96cCxAPecKz6q3hG2m9BW0Z9mreTlADlo6rfKdhP6b+fyOsCHdTjqt7fVsH0FEQx8uQi4rF4iE3vIFilh3woSVfyzQ5PddqOY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664914115; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=z6NCzPC6tE1OG0rvY3WzwqtBapUdS48hi6o10eMrDQY=; b=aUz5mAx3WI155MqJEutQKJw4yx+5UIQUt5v3JJrSgMlKYxT3/275qBpixfB7JQnTcQm38EQEfD0lGru9uyJ73dH6ODWJpy8zbHBRK6WIO/z6DsWcg8bSIh/l6deWrD1pW5dJJKnVEylXlmBv/v0jcljWwa41oa2RObFsSCD/txQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664914115341145.55997835804862; Tue, 4 Oct 2022 13:08:35 -0700 (PDT) Received: from localhost ([::1]:56186 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofoDR-0000rI-9U for importer@patchew.org; Tue, 04 Oct 2022 16:08:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41264) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyE-0001hx-Mu for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:51 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:43943) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofnyD-0000Fv-4N for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:50 -0400 Received: by mail-pl1-x629.google.com with SMTP id z20so7029124plb.10 for ; Tue, 04 Oct 2022 12:52:48 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.52.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:52:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=z6NCzPC6tE1OG0rvY3WzwqtBapUdS48hi6o10eMrDQY=; b=sB2O+93JRgNMyj3Q75ejeAZhVarfc/per4TQUzgVCnuPhBUa8RbVmNPDDGeRyqdce5 /FozoEVDJ7CGhApviHqWXmoIyxFOqPacGWHR86qJXYmuMkko7QlMFtap7rXlQlYOaWkv zyjRpInB+YbcJRenK3hTnAZ3jkZHqDrcUJA5cUk90ZF6nfsJaECPIZFnRg8LjIC1Ey6R oLNnY8UI2BxUKK4hcxLaVtTsiuBUVGEkl94MOOyOGkXYbQQAdUNtWZI7Gqw+rTUVzIL4 nJ9pePrnzrS63MucUK8JAi6SbN+2x1H9SSpoQPHXlSJRuH5TMJtA7plAC8EJwO1jv1md Y2Rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=z6NCzPC6tE1OG0rvY3WzwqtBapUdS48hi6o10eMrDQY=; b=Zi4uQFSLiqlnhMetJ3KQnm9nDOkLSiJI7J4swX8Et8t5fBoYvBtddBqLfELeBn10gJ 4kPf/JcVtLQrPo8kDqNaP8C9rW9n95kqiRv6EzCrvrN7M17OUqhiFQvMak98ttmazdTD SfOkQVIkIz88rXWeLLDIw/Ioaj755f8SwII3o60Tn0gRM68/y/SSHXdqWREoB46pikWf tgXE34rR0xymAR8QM6GdxijFr4mbutOVa3i/E/yCUR81PYcvtSOWu/Ltu5BZReyGKQr1 nNGZwC/kVY22xmbCXe7uppHbJYRm0VftfABzw3fd7iLHkHnfcOyvQ2CfAKj2wzjq1NRZ JPYQ== X-Gm-Message-State: ACrzQf3qxNC3l2+jWHqRDsV3iAFGW0bwdWXWFsf+2vKyRz5BfEy1DO75 urk6RSbCzhsRvZCdEjbjZbBatzDbWzZfSQ== X-Google-Smtp-Source: AMsMyM6WRbGLszXRdIFfrrWaDvSDYPyGx5tgrZaUTJJMDIzts6w4YPgW+P/7Z7ek/TUiNQ/iPzmbFg== X-Received: by 2002:a17:902:8548:b0:179:e4db:42e0 with SMTP id d8-20020a170902854800b00179e4db42e0mr28561649plo.0.1664913167660; Tue, 04 Oct 2022 12:52:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 05/20] accel/tcg: Drop addr member from SavedIOTLB Date: Tue, 4 Oct 2022 12:52:26 -0700 Message-Id: <20221004195241.46491-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664914117054100001 This field is only written, not read; remove it. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 1 - accel/tcg/cputlb.c | 7 +++---- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 1a7e1a9380..009dc0d336 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -225,7 +225,6 @@ struct CPUWatchpoint { * the memory regions get moved around by io_writex. */ typedef struct SavedIOTLB { - hwaddr addr; MemoryRegionSection *section; hwaddr mr_offset; } SavedIOTLB; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index aa22f578cb..d06ff44ce9 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1372,12 +1372,11 @@ static uint64_t io_readx(CPUArchState *env, CPUTLBE= ntryFull *full, * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match * because of the side effect of io_writex changing memory layout. */ -static void save_iotlb_data(CPUState *cs, hwaddr addr, - MemoryRegionSection *section, hwaddr mr_offset) +static void save_iotlb_data(CPUState *cs, MemoryRegionSection *section, + hwaddr mr_offset) { #ifdef CONFIG_PLUGIN SavedIOTLB *saved =3D &cs->saved_iotlb; - saved->addr =3D addr; saved->section =3D section; saved->mr_offset =3D mr_offset; #endif @@ -1406,7 +1405,7 @@ static void io_writex(CPUArchState *env, CPUTLBEntryF= ull *full, * The memory_region_dispatch may trigger a flush/resize * so for plugins we save the iotlb_data just in case. */ - save_iotlb_data(cpu, full->xlat_section, section, mr_offset); + save_iotlb_data(cpu, section, mr_offset); =20 if (!qemu_mutex_iothread_locked()) { qemu_mutex_lock_iothread(); --=20 2.34.1 From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664913456; cv=none; d=zohomail.com; s=zohoarc; b=YJV0j0ZAAWx3wHVZAD4CMQeEOZfMPAdFF8/whjEm0FOOWnCC8SE76mNyFFvS01jsw3/vavPu+nVHDIM5nuxIzIkd0aR+RGrWE+5d748FXGryUjYPLOlZNyroVk0Tr9Qu2drf3ehxwa1Jitc4LG11EUWpRVi4qvQvA2CpBkupX2o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664913456; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=St5dCg8yC5zIkIV0jUFWp9UWjpefIW881mvaUfGPCfo=; b=YiJOa05rakb0O8F+3E0QEe6ap9KFcntpYlElRdrEziOhJ1rapF0pMQXOqJs8fdVtdfV67bLHkGBRdG/UF+vgxYtiD/9BPSMB6RoCCy2ztJVoYshO/4Fkl0KQ5N5SF36rUvUtYbt514w9LINba6qQCqmTWmayGdRRdXIFfPFVREo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664913456916103.92080613660971; Tue, 4 Oct 2022 12:57:36 -0700 (PDT) Received: from localhost ([::1]:59860 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofo2o-0004mx-GF for importer@patchew.org; Tue, 04 Oct 2022 15:57:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41268) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyG-0001iS-2G for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:52 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:46614) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofnyE-0000GD-FH for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:51 -0400 Received: by mail-pl1-x62a.google.com with SMTP id l1so729895pld.13 for ; Tue, 04 Oct 2022 12:52:49 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.52.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:52:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=St5dCg8yC5zIkIV0jUFWp9UWjpefIW881mvaUfGPCfo=; b=KBNKLDkoV6FyvbfjKKLGdRo3UUeOFuWALGQt/O7p7ylLoI4IMaE8rYSNu0a04WqIwM Ha0WUHTgWqLyAXXgp4YlNtmrgG15mfS0J1UJLmmQP7Dzk0Vd2mhtPm3S7xqHmKRmkgqe pkZP1Ft/sqEuagv8q3FSPGN8sA6Lnv7+mWT3eOhAOcx7kp1JBbE7qf5G33CuHWkJuKn1 FelsDWIDzVvzI5wWJDnnbyyVucl5HsZbHW2ymh2TXDk80SV+P4MU53txb7GQ9wg1dqyo J5MD/OP3/8rt+mBY6mt3lUN4sQ1NP2839ow6PRHJZ1RoR0tl8YrNuAWVxp3iPUq3q+XQ 2Q+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=St5dCg8yC5zIkIV0jUFWp9UWjpefIW881mvaUfGPCfo=; b=zDUAD41fT1JYSF2ttyFnXm9B+bsB2j20ye/gLilzfXqnhe730jI4Sl+KDNRBIgwLrT UTjHdgSfpL6xm778osz3caWpwbZ5LincSpAYjukrRUGA8fglDz60HkbWAV+V26aHD09q BHkKgdlUovfqrhUTzNLfpLwj720jWw4NsmU/8UnjVKcuwxdPviVC+RedD8vMlPqBz0uk b9I7/NuEvETgCFyQfuiQaooJcJDMun7OS3Ml4yPe99WsMPGRsW1pPufX2/WG0dLPtKTN ziT5X+8UHHbZYHKI5uBdtM0Qak4DGs5adIhRU197hE4fdl4CbUM4ULsb3twZtLzH3/yb vUwQ== X-Gm-Message-State: ACrzQf3Hi+7aLNTZ4p9b19B61/nUX7Zeds6QuUzvjuZNJh+AF1aV2heX L+gaqPbZk07+rs08dYfw9q5r5qRUvOU3ew== X-Google-Smtp-Source: AMsMyM41pGfkiduqIsgrAIuwo+6KqyJb0Nx9qXEKYAS4zrMXjiqdP3DrZcVYBMul242tcAIb6kNRBg== X-Received: by 2002:a17:90a:1c02:b0:1e0:df7:31f2 with SMTP id s2-20020a17090a1c0200b001e00df731f2mr1264580pjs.222.1664913168688; Tue, 04 Oct 2022 12:52:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Hildenbrand , Peter Maydell Subject: [PULL 06/20] accel/tcg: Suppress auto-invalidate in probe_access_internal Date: Tue, 4 Oct 2022 12:52:27 -0700 Message-Id: <20221004195241.46491-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664913458857100003 When PAGE_WRITE_INV is set when calling tlb_set_page, we immediately set TLB_INVALID_MASK in order to force tlb_fill to be called on the next lookup. Here in probe_access_internal, we have just called tlb_fill and eliminated true misses, thus the lookup must be valid. This allows us to remove a warning comment from s390x. There doesn't seem to be a reason to change the code though. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 10 +++++++++- target/s390x/tcg/mem_helper.c | 4 ---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d06ff44ce9..264f84a248 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1533,6 +1533,7 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, } tlb_addr =3D tlb_read_ofs(entry, elt_ofs); =20 + flags =3D TLB_FLAGS_MASK; page_addr =3D addr & TARGET_PAGE_MASK; if (!tlb_hit_page(tlb_addr, page_addr)) { if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) { @@ -1547,10 +1548,17 @@ static int probe_access_internal(CPUArchState *env,= target_ulong addr, =20 /* TLB resize via tlb_fill may have moved the entry. */ entry =3D tlb_entry(env, mmu_idx, addr); + + /* + * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately, + * to force the next access through tlb_fill. We've just + * called tlb_fill, so we know that this entry *is* valid. + */ + flags &=3D ~TLB_INVALID_MASK; } tlb_addr =3D tlb_read_ofs(entry, elt_ofs); } - flags =3D tlb_addr & TLB_FLAGS_MASK; + flags &=3D tlb_addr; =20 /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) { diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index fc52aa128b..3758b9e688 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -148,10 +148,6 @@ static int s390_probe_access(CPUArchState *env, target= _ulong addr, int size, #else int flags; =20 - /* - * For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr= =3D=3DNULL - * to detect if there was an exception during tlb_fill(). - */ env->tlb_fill_exc =3D 0; flags =3D probe_access_flags(env, addr, access_type, mmu_idx, nonfault= , phost, ra); --=20 2.34.1 From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664914123; cv=none; d=zohomail.com; s=zohoarc; b=NM975uJ6F/SNihCAxEioKZ9KX/c+tIh2LjmNA39qiZdzgb691oeU1QqgaVDaoCL/s0BY9CfA1YX750VSBFVXv76LIsLhyA0E9eRRyrHMAyF3Ye9nIqmSRAjeW7OMzbSOko7izCusnp8uYeEvZbkBP05jUoGTU8iONIcEIqynPTw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664914123; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wqv6omjESGpT0GzTsXvELEKQHyruXHoBEMwfSKPGC6w=; b=MkiPOBb7VoIswuPq8lCzfY+xjxjegIyaYsF4M5t9c8bNfyII2T6GlRagqCEFNZdvUc5a4j8a0zi3/P2fy4fjHwdwroG3EuVPFIpHCVUq2N/scOHenOKfsJVBtX9meeQMgZ6CJjpU1kWKEqmUqxawcgwptPF218zdCWFOlz3NOZY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664914123549267.5349629578392; Tue, 4 Oct 2022 13:08:43 -0700 (PDT) Received: from localhost ([::1]:46764 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofoDa-00019b-BA for importer@patchew.org; Tue, 04 Oct 2022 16:08:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41270) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyI-0001j9-GM for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:54 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:41872) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofnyF-0000GO-Hy for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:53 -0400 Received: by mail-pl1-x632.google.com with SMTP id d11so13557763pll.8 for ; Tue, 04 Oct 2022 12:52:50 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.52.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:52:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=wqv6omjESGpT0GzTsXvELEKQHyruXHoBEMwfSKPGC6w=; b=oj3gJprnxRJtajlnFS4jZNc3Ic36rYVtAcl2nivo3vlsk7XoNAbA8wYkJtB70QSCDA QPqmAWsez6EQPonCVT1fpG3jkzyDfCHWsFki9awTAmjEWwgMMK8GBjqPU3mvR03Pi76j wxgvg+oA3fsverhEGAJoHktphT6miYoOC6JKLnm4CaiSRg7iW/gjne37qE4XCNqI1fqQ +VNtBDyik0T/lkL9QqQvMcojKe7Vt2OJ7h+LR0BuHJxNOvOWRG3nWbNPm1hhQ8EVXd2W u+wgCGRsp3YdzBAqYCbYSWy6oHpmyLmJLS5rADbkBVaWJhsIjxAV1j9Pd4Z6fvk+8lNa E0MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=wqv6omjESGpT0GzTsXvELEKQHyruXHoBEMwfSKPGC6w=; b=QoKnFGEAxCxxgsDqE+g755Z3cshgcnUR6zhQ8U8WkuS+T4uyG5awRRjcmLkMddbByc CJ669Tk6E4tohncFNE/LBzplKOw9JNkjMe8h0FXG+KOImZ57f2SzHWYucrwj8oiTV3c6 oK46foHPImarbxGA+CRuJ4Qry8DERQY4/VfL5ifRDb5TS8dH5UTjnT1ZCN/FsdzaeXvP IlqIMjbLVf57jEvInfbKQbkjfjbNLdnIieiBCdA/3JY2SxOStm9hKLOa8DWeHv64H0F5 QtBQR4HkpQ84CjTzudFmI1+fLf6MDgz2/OSZZWk7ozJqsl92iOJ8OUF/rOaUOzeFfGZ1 Q6Pg== X-Gm-Message-State: ACrzQf1uV/AqzF9RI6Y7xA1RCvAjhhoEup0g1MuK5Q1staPuxNwdKMnb XDu41IFuyL0/ed3Dw3u7DsGj7AbPELWWrQ== X-Google-Smtp-Source: AMsMyM4bLmNGA+tFRwNBykx6htrMDvb6k4P/6Acw9V5jCI4K24/xMvpqcnbr/7KSMT6RqW878Nfg/A== X-Received: by 2002:a17:903:11c7:b0:178:afa2:43fd with SMTP id q7-20020a17090311c700b00178afa243fdmr28433507plh.126.1664913169758; Tue, 04 Oct 2022 12:52:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 07/20] accel/tcg: Introduce probe_access_full Date: Tue, 4 Oct 2022 12:52:28 -0700 Message-Id: <20221004195241.46491-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664914125061100001 Add an interface to return the CPUTLBEntryFull struct that goes with the lookup. The result is not intended to be valid across multiple lookups, so the user must use the results immediately. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 15 +++++++++++++ include/qemu/typedefs.h | 1 + accel/tcg/cputlb.c | 47 +++++++++++++++++++++++++---------------- 3 files changed, 45 insertions(+), 18 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index bcad607c4e..d255d69bc1 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -434,6 +434,21 @@ int probe_access_flags(CPUArchState *env, target_ulong= addr, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr); =20 +#ifndef CONFIG_USER_ONLY +/** + * probe_access_full: + * Like probe_access_flags, except also return into @pfull. + * + * The CPUTLBEntryFull structure returned via @pfull is transient + * and must be consumed or copied immediately, before any further + * access or changes to TLB @mmu_idx. + */ +int probe_access_full(CPUArchState *env, target_ulong addr, + MMUAccessType access_type, int mmu_idx, + bool nonfault, void **phost, + CPUTLBEntryFull **pfull, uintptr_t retaddr); +#endif + #define CODE_GEN_ALIGN 16 /* must be >=3D of the size of a icach= e line */ =20 /* Estimated block size for TB allocation. */ diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 42f4ceb701..a4aee238c7 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -42,6 +42,7 @@ typedef struct ConfidentialGuestSupport ConfidentialGuest= Support; typedef struct CPUAddressSpace CPUAddressSpace; typedef struct CPUArchState CPUArchState; typedef struct CPUState CPUState; +typedef struct CPUTLBEntryFull CPUTLBEntryFull; typedef struct DeviceListener DeviceListener; typedef struct DeviceState DeviceState; typedef struct DirtyBitmapSnapshot DirtyBitmapSnapshot; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 264f84a248..e3ee4260bd 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1510,7 +1510,8 @@ static void notdirty_write(CPUState *cpu, vaddr mem_v= addr, unsigned size, static int probe_access_internal(CPUArchState *env, target_ulong addr, int fault_size, MMUAccessType access_type, int mmu_idx, bool nonfault, - void **phost, uintptr_t retaddr) + void **phost, CPUTLBEntryFull **pfull, + uintptr_t retaddr) { uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); @@ -1543,10 +1544,12 @@ static int probe_access_internal(CPUArchState *env,= target_ulong addr, mmu_idx, nonfault, retaddr)) { /* Non-faulting page table read failed. */ *phost =3D NULL; + *pfull =3D NULL; return TLB_INVALID_MASK; } =20 /* TLB resize via tlb_fill may have moved the entry. */ + index =3D tlb_index(env, mmu_idx, addr); entry =3D tlb_entry(env, mmu_idx, addr); =20 /* @@ -1560,6 +1563,8 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, } flags &=3D tlb_addr; =20 + *pfull =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) { *phost =3D NULL; @@ -1571,37 +1576,44 @@ static int probe_access_internal(CPUArchState *env,= target_ulong addr, return flags; } =20 -int probe_access_flags(CPUArchState *env, target_ulong addr, - MMUAccessType access_type, int mmu_idx, - bool nonfault, void **phost, uintptr_t retaddr) +int probe_access_full(CPUArchState *env, target_ulong addr, + MMUAccessType access_type, int mmu_idx, + bool nonfault, void **phost, CPUTLBEntryFull **pfull, + uintptr_t retaddr) { - int flags; - - flags =3D probe_access_internal(env, addr, 0, access_type, mmu_idx, - nonfault, phost, retaddr); + int flags =3D probe_access_internal(env, addr, 0, access_type, mmu_idx, + nonfault, phost, pfull, retaddr); =20 /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; - - notdirty_write(env_cpu(env), addr, 1, full, retaddr); + notdirty_write(env_cpu(env), addr, 1, *pfull, retaddr); flags &=3D ~TLB_NOTDIRTY; } =20 return flags; } =20 +int probe_access_flags(CPUArchState *env, target_ulong addr, + MMUAccessType access_type, int mmu_idx, + bool nonfault, void **phost, uintptr_t retaddr) +{ + CPUTLBEntryFull *full; + + return probe_access_full(env, addr, access_type, mmu_idx, + nonfault, phost, &full, retaddr); +} + void *probe_access(CPUArchState *env, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retad= dr) { + CPUTLBEntryFull *full; void *host; int flags; =20 g_assert(-(addr | TARGET_PAGE_MASK) >=3D size); =20 flags =3D probe_access_internal(env, addr, size, access_type, mmu_idx, - false, &host, retaddr); + false, &host, &full, retaddr); =20 /* Per the interface, size =3D=3D 0 merely faults the access. */ if (size =3D=3D 0) { @@ -1609,9 +1621,6 @@ void *probe_access(CPUArchState *env, target_ulong ad= dr, int size, } =20 if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) { - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; - /* Handle watchpoints. */ if (flags & TLB_WATCHPOINT) { int wp_access =3D (access_type =3D=3D MMU_DATA_STORE @@ -1632,11 +1641,12 @@ void *probe_access(CPUArchState *env, target_ulong = addr, int size, void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, MMUAccessType access_type, int mmu_idx) { + CPUTLBEntryFull *full; void *host; int flags; =20 flags =3D probe_access_internal(env, addr, 0, access_type, - mmu_idx, true, &host, 0); + mmu_idx, true, &host, &full, 0); =20 /* No combination of flags are expected by the caller. */ return flags ? NULL : host; @@ -1655,10 +1665,11 @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr = addr, tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong ad= dr, void **hostp) { + CPUTLBEntryFull *full; void *p; =20 (void)probe_access_internal(env, addr, 1, MMU_INST_FETCH, - cpu_mmu_index(env, true), false, &p, 0); + cpu_mmu_index(env, true), false, &p, &full= , 0); if (p =3D=3D NULL) { return -1; } --=20 2.34.1 From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664914466; cv=none; d=zohomail.com; s=zohoarc; b=WgaNeOE336T15vsZiS5ZHC2uLNu9joRqODiMMa70i22JmWGu5U/q/hUqMhbOba/29sgimnTA/rh0yQMklxzglPtxnlM/jUI+R+75Dqt7QWjXHdfceJh2ew2+w9ZcYBL5v5dJh48uo3bqxycrDJD6rtRJ/pa2JHSi6SQXl2a6R4w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664914466; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dAY3x/lc+/32wE3SHUuBvqOuB1dTrfgmxaF5UaNYDSM=; b=OWgSQ6YzqEQ5bcFpARWsbp77ggpvO4M9Wy3gcGsmrovprt/4EURGCOQe0sbc9KnjEH/SuUY006v0ux1QgpnlaTk8Ndcm4TTO/CdDOyrnoCingHZpzoBLhP3f3K+YBK35zI+k2lXExL+4P0NOOELNc2XsK1EoFuo9mwbIeQwSXfc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664914466371468.9040406298179; Tue, 4 Oct 2022 13:14:26 -0700 (PDT) Received: from localhost ([::1]:37782 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofoJ5-0000KJ-VO for importer@patchew.org; Tue, 04 Oct 2022 16:14:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41272) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyI-0001jC-GW for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:54 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:42542) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofnyG-0000GX-8s for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:53 -0400 Received: by mail-pl1-x62d.google.com with SMTP id c24so3488947pls.9 for ; Tue, 04 Oct 2022 12:52:51 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.52.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:52:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=dAY3x/lc+/32wE3SHUuBvqOuB1dTrfgmxaF5UaNYDSM=; b=w0P32aVrKB8kZshVn7wxdMSySieYubCTJ1BEs0SkykhCuH55O+C92Jt5K3RyB4R0aq z+ltoP9yAyBsVq7FV29UbiEc60WYPVaD/lH6JWLMcLcspHS0mhY/pAZj1cQBQsPRspdE ixC2DmV/Peemw7O7dpHTIha8512gkW76NwMImaTfJLVAeWtRLZwu9FftGzZeOjX+bj7c 2Dn15SbIyJX6mIqHmrUHR3HEeu1J7m2w27rI275BIImWNBtt+yknAcrysd6lmgYpkcFp 2PsW4nroruZsDk/yxGSqc5pRSvE7Ehp0wz7YYzP5Bh6jFGJ9Vn27nZ3GB8Ofi/L+xUsO 37Hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=dAY3x/lc+/32wE3SHUuBvqOuB1dTrfgmxaF5UaNYDSM=; b=sJsVzMnaA0v5lzhl+f7gIrN2tOTsKa3rpEcYRUfOh2VVB/tmBReRiY34PKnQQZc4h3 25aYsVfyl7xzwQy+e/JBWAQ9XN9ZPQWONLoSKRGh3ikoLAAutljUyjsX5CQ81do3ywGm onHlSQ/4gUOjG1NjEKAwfQGyyi1Amf6jYTXxMAMTZfeSDJwffyMoRNgfA44al/V+rs1p 7BX+hkun+IIenVqJQ+2Lkd8OlqtWs10BbTMIxePTaKsqOy5Yd0QOXcieUsxGP48nXlFm FpuUzq2Lbsa7tWevAywkh24Dqv4t7nFtHin2Bkme4xTfDDF19Of0nHBfwhxOLoXorrfU afzA== X-Gm-Message-State: ACrzQf2EzLaAriZOaTAmT1OUtF8KXX2xQf646oj4WfCgjL4oLHerR11/ ezP6K5wKdeh6BENY+w/W8J5WZV/7J8xpwA== X-Google-Smtp-Source: AMsMyM4lmQD5oTk8sUN3cfLc0rYhkzMrLit7+ahiBgehUTN+AlHB3HsPLGeBIVasd+crEqQo1MPomw== X-Received: by 2002:a17:90b:1d11:b0:20a:9b3a:bf10 with SMTP id on17-20020a17090b1d1100b0020a9b3abf10mr1241628pjb.215.1664913170876; Tue, 04 Oct 2022 12:52:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 08/20] accel/tcg: Introduce tlb_set_page_full Date: Tue, 4 Oct 2022 12:52:29 -0700 Message-Id: <20221004195241.46491-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664914468190100001 Now that we have collected all of the page data into CPUTLBEntryFull, provide an interface to record that all in one go, instead of using 4 arguments. This interface allows CPUTLBEntryFull to be extended without having to change the number of arguments. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 14 +++++++++++ include/exec/exec-all.h | 22 ++++++++++++++++++ accel/tcg/cputlb.c | 51 ++++++++++++++++++++++++++--------------- 3 files changed, 69 insertions(+), 18 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index f70f54d850..5e12cc1854 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -148,7 +148,21 @@ typedef struct CPUTLBEntryFull { * + the offset within the target MemoryRegion (otherwise) */ hwaddr xlat_section; + + /* + * @phys_addr contains the physical address in the address space + * given by cpu_asidx_from_attrs(cpu, @attrs). + */ + hwaddr phys_addr; + + /* @attrs contains the memory transaction attributes for the page. */ MemTxAttrs attrs; + + /* @prot contains the complete protections for the page. */ + uint8_t prot; + + /* @lg_page_size contains the log2 of the page size. */ + uint8_t lg_page_size; } CPUTLBEntryFull; =20 /* diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index d255d69bc1..b1b920a713 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -257,6 +257,28 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUStat= e *cpu, uint16_t idxmap, unsigned bits); =20 +/** + * tlb_set_page_full: + * @cpu: CPU context + * @mmu_idx: mmu index of the tlb to modify + * @vaddr: virtual address of the entry to add + * @full: the details of the tlb entry + * + * Add an entry to @cpu tlb index @mmu_idx. All of the fields of + * @full must be filled, except for xlat_section, and constitute + * the complete description of the translated page. + * + * This is generally called by the target tlb_fill function after + * having performed a successful page table walk to find the physical + * address and attributes for the translation. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only + * used by tlb_flush_page. + */ +void tlb_set_page_full(CPUState *cpu, int mmu_idx, target_ulong vaddr, + CPUTLBEntryFull *full); + /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e3ee4260bd..361078471b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1095,16 +1095,16 @@ static void tlb_add_large_page(CPUArchState *env, i= nt mmu_idx, env_tlb(env)->d[mmu_idx].large_page_mask =3D lp_mask; } =20 -/* Add a new TLB entry. At most one entry for a given virtual address +/* + * Add a new TLB entry. At most one entry for a given virtual address * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the * supplied size is only used by tlb_flush_page. * * Called from TCG-generated code, which is under an RCU read-side * critical section. */ -void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, - hwaddr paddr, MemTxAttrs attrs, int prot, - int mmu_idx, target_ulong size) +void tlb_set_page_full(CPUState *cpu, int mmu_idx, + target_ulong vaddr, CPUTLBEntryFull *full) { CPUArchState *env =3D cpu->env_ptr; CPUTLB *tlb =3D env_tlb(env); @@ -1117,35 +1117,36 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_= ulong vaddr, CPUTLBEntry *te, tn; hwaddr iotlb, xlat, sz, paddr_page; target_ulong vaddr_page; - int asidx =3D cpu_asidx_from_attrs(cpu, attrs); - int wp_flags; + int asidx, wp_flags, prot; bool is_ram, is_romd; =20 assert_cpu_is_self(cpu); =20 - if (size <=3D TARGET_PAGE_SIZE) { + if (full->lg_page_size <=3D TARGET_PAGE_BITS) { sz =3D TARGET_PAGE_SIZE; } else { - tlb_add_large_page(env, mmu_idx, vaddr, size); - sz =3D size; + sz =3D (hwaddr)1 << full->lg_page_size; + tlb_add_large_page(env, mmu_idx, vaddr, sz); } vaddr_page =3D vaddr & TARGET_PAGE_MASK; - paddr_page =3D paddr & TARGET_PAGE_MASK; + paddr_page =3D full->phys_addr & TARGET_PAGE_MASK; =20 + prot =3D full->prot; + asidx =3D cpu_asidx_from_attrs(cpu, full->attrs); section =3D address_space_translate_for_iotlb(cpu, asidx, paddr_page, - &xlat, &sz, attrs, &prot); + &xlat, &sz, full->attrs, &= prot); assert(sz >=3D TARGET_PAGE_SIZE); =20 tlb_debug("vaddr=3D" TARGET_FMT_lx " paddr=3D0x" TARGET_FMT_plx " prot=3D%x idx=3D%d\n", - vaddr, paddr, prot, mmu_idx); + vaddr, full->phys_addr, prot, mmu_idx); =20 address =3D vaddr_page; - if (size < TARGET_PAGE_SIZE) { + if (full->lg_page_size < TARGET_PAGE_BITS) { /* Repeat the MMU check and TLB fill on every access. */ address |=3D TLB_INVALID_MASK; } - if (attrs.byte_swap) { + if (full->attrs.byte_swap) { address |=3D TLB_BSWAP; } =20 @@ -1236,8 +1237,10 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_u= long vaddr, * subtract here is that of the page base, and not the same as the * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). */ + desc->fulltlb[index] =3D *full; desc->fulltlb[index].xlat_section =3D iotlb - vaddr_page; - desc->fulltlb[index].attrs =3D attrs; + desc->fulltlb[index].phys_addr =3D paddr_page; + desc->fulltlb[index].prot =3D prot; =20 /* Now calculate the new entry */ tn.addend =3D addend - vaddr_page; @@ -1272,9 +1275,21 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_u= long vaddr, qemu_spin_unlock(&tlb->c.lock); } =20 -/* Add a new TLB entry, but without specifying the memory - * transaction attributes to be used. - */ +void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, + hwaddr paddr, MemTxAttrs attrs, int prot, + int mmu_idx, target_ulong size) +{ + CPUTLBEntryFull full =3D { + .phys_addr =3D paddr, + .attrs =3D attrs, + .prot =3D prot, + .lg_page_size =3D ctz64(size) + }; + + assert(is_power_of_2(size)); + tlb_set_page_full(cpu, mmu_idx, vaddr, &full); +} + void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size) --=20 2.34.1 From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664913634; cv=none; d=zohomail.com; s=zohoarc; b=fIuHEw8Sp9LyvL7gBcMcPi8safdm5R+B7nuqsiTznDRNtzyjhzOncIkhoWvcqZkapMteFa4jTwUt/uKy6ERzd8OOiClIwpFtFfTjdEnroDXamITS6X9FQpQiQjOsAk7uA+JtTPuJiqqfmbNvpaU+x2ogoCLoLQfJyFFaFUl+NM4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664913634; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pPZ5BGim//7jDbDR7RtfT/BbVdLxSz70QtZLu4dhW0s=; b=Qd+R6TT1aa7dsFsrpdwLJH5TMO97uMoAQ95uYeJMBhp0E2EGPkB8e4zLXGui/H36nxVgb8YGkYS8OCePKU69v3wOrmnpj62tai6axtHoYJWy4XrukGV/KuwzNI5B/Nll2ZJuhTTUBBqXKd7w+laXNeXYROiVZ16PCqbPkrKcAKw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166491363424749.758763879629214; Tue, 4 Oct 2022 13:00:34 -0700 (PDT) Received: from localhost ([::1]:40932 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofo5f-0002TV-4m for importer@patchew.org; Tue, 04 Oct 2022 16:00:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41274) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyI-0001jM-Lv for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:54 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:33661) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofnyG-0000F3-SK for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:54 -0400 Received: by mail-pj1-x1034.google.com with SMTP id bu5-20020a17090aee4500b00202e9ca2182so1954939pjb.0 for ; Tue, 04 Oct 2022 12:52:52 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.52.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:52:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=pPZ5BGim//7jDbDR7RtfT/BbVdLxSz70QtZLu4dhW0s=; b=Nzkdx8wMab2FC3EoOBOi6eRGllfgeMx1ZGIOPQOawZEnNIIL/+N3ZXTCX2MTICzW2w IkqV586uT9MYbLN0G1UVQacrg+4CnXO3uINDrVF+Kx7W+TK6Eg5GkVzi7t/QWLt8aEro /Ceb8Il+mLSmx32l0COkXdYMl3kGZLNRB26K56gMhmL4k0nJYcg0Hc7g17m1aOuXoUFk u4hiRsDSFlwHFkWMN/R726vC60FmcKL4Mlp3GIdyNvVQ2Ulinvxz6Kwh4kOiszOhYt+B 2M+V4D9x0dxdPsS26QFrUt4E3GicEdbdqrb786++ylENHc7oHxOdZngX/XUJk1TfyTgi boFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=pPZ5BGim//7jDbDR7RtfT/BbVdLxSz70QtZLu4dhW0s=; b=hrxMCocgjeq6lP/nQ5I+61HjQB6nLzW2euGxwGmWrK034v9U0mx8wG43sU2qSOThV7 MyjfZQlQvp55FXkIIdge+DgzHCxRzPfOl18r2fTRcZnROnpWJVM+yj0uUt9D1qohmPY8 CyqjzJwLmPwUCaYNhsh6Xo9tYRRlDWYCdsl+uhYNOMJNlUiaJ5e4YWPhPxVBxhQIWbCm fu00J3Xt4BXeMxuck3zJ22LPA2DyEihdgVJOx23CCuUXMfcA9FU0gvmj1cMLMAg8peTy fSnQlZCWh0J8DJRJOTQ49jk7Xa2UUYrnnaZXuPdwLzzs8ZHFLYuq6XvTIRcAbOIWHAjE vXXw== X-Gm-Message-State: ACrzQf2xyzmUU+OMMQ+WA86S9nrz2y4JvOzoqwzs1xn8tiwD+Vdv2VVQ ntwVodqr/hVBqa1+i3C07LNbcNt/fcm0pg== X-Google-Smtp-Source: AMsMyM5nywcae2wKpdH9zfM11oWZirkJq43BRx0J8boIBx0GPzaBXOELBh8TO611Idk61X1D/FPwtg== X-Received: by 2002:a17:90b:4b47:b0:20a:cfcb:8561 with SMTP id mi7-20020a17090b4b4700b0020acfcb8561mr1256480pjb.55.1664913172092; Tue, 04 Oct 2022 12:52:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 09/20] include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA Date: Tue, 4 Oct 2022 12:52:30 -0700 Message-Id: <20221004195241.46491-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664913635112100003 Allow the target to cache items from the guest page tables. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 5e12cc1854..67239b4e5e 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -163,6 +163,15 @@ typedef struct CPUTLBEntryFull { =20 /* @lg_page_size contains the log2 of the page size. */ uint8_t lg_page_size; + + /* + * Allow target-specific additions to this structure. + * This may be used to cache items from the guest cpu + * page tables for later use by the implementation. + */ +#ifdef TARGET_PAGE_ENTRY_EXTRA + TARGET_PAGE_ENTRY_EXTRA +#endif } CPUTLBEntryFull; =20 /* --=20 2.34.1 From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664913865; cv=none; d=zohomail.com; s=zohoarc; b=M9y5ZSivEiUy+/KTITPGRGvkHbyinkJuL1oiUfA3Yw1U87lHf/3IysNMBttvfVHkMa57pofe2ny8JKqK+DNA704ngmvLpy4Tw9klfQxjoY4L7YHP2+pZjXXD1TYKc7GJ5Q5gFMWowE5o2fwZd56m64ReRl2aG4njc4OtHRjOFt4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664913865; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iNSv5kupswjOCEJBCw0DforCHK3ePnESyn5fLqIud2Q=; b=J+5iup7qHoPkFp+tBww8fYdn1PMoKq+lWnqLZ7+X9AoLFtpwCnJL4Qvd/I3BjYC07JQwvCp9HdMyuWB/KgelFYX51QRWFG0u2taD+Yw1dy+v5SJ1K9/4OPM/mRopHTDj+D7Wl/pwC7jttcReh6yAmOpLpYYZdTWADcRJmBbvJEg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664913865759200.6963223509465; Tue, 4 Oct 2022 13:04:25 -0700 (PDT) Received: from localhost ([::1]:60808 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofo9Q-0004lV-J4 for importer@patchew.org; Tue, 04 Oct 2022 16:04:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49316) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyK-0001lx-0X for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:56 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:34357) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofnyI-0000FZ-8B for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:55 -0400 Received: by mail-pl1-x633.google.com with SMTP id n7so13567140plp.1 for ; Tue, 04 Oct 2022 12:52:53 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.52.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:52:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=iNSv5kupswjOCEJBCw0DforCHK3ePnESyn5fLqIud2Q=; b=VbtX/RQsgmanSqQVOLThGKAfLkkEHbxl+vzpngM3iHQkbofUCP2RZe+qkzJX6u13o4 IIvIMxZI335xuCdAP0WkX/wfXjfl653bI8CV6pQYiI0gQzK83Ldz6f8WNcOnI6s1i8Ma XyAe95yGZjdV8eGj0XCgt3SzmAghnVENHTl91G3Nyv3J6kP1Q781cXa470VEyEibkpn3 aNUOKxQxw79RuPrFwBrqWuHrP80fIwE6vfwEaPgWGLyRBD/QU63Us4yxyIZFCNf1ZvoN uC3gZNQ/i0M6k0V+CoRVDbgXaRk39iV3HntVXQI2MzCXSYaExol38+bIsiA7v+7cHWeP 4SFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=iNSv5kupswjOCEJBCw0DforCHK3ePnESyn5fLqIud2Q=; b=5eGLQs7TYNNWuwQr99iaNnvxaBAiniYItC+2Qw7GFJA01o/O2rYZjiB4uKsllsvdhi WjZQ4PCGDZ6zzZQA3Sa5+jNI/KWeP3FjDVwLxj2+plXvL3icS48x0SdZ52FKBjkHRB9V h2XOq3L7nRYNImaitedVTYXl5yH5F7UMlbTc6n71GHnRsjZR57Xh56GsQ0Ve0hM/kwZ3 2bdkmCfAAAkPTlmXNoQNboGlOsWvrB0b2rGOzC4Y3Y7g7tYrcWZ2rlC83RX0eWsoTC0i El3+rdgp+ofwtjxPRIxTKQ0NIWtSgCDO+Q7lmd05387zpUY9av1J5IJCYrktLsaDtoKi Auag== X-Gm-Message-State: ACrzQf3dWRSowa3VWKpaeb0HE52lT3qRz0r79vWE83diWA5eRMZNB8wl pF/PdTd1I/4dU8xqKqsQiXVALf8eX6cCLA== X-Google-Smtp-Source: AMsMyM5pAN/IUWZAhAp1xFHfknkQ3TVE6hWQSg3+tGNbMUfKcwEaO13vbyYZuT/rGtHZAs2d56Ncxg== X-Received: by 2002:a17:902:dad1:b0:17a:940:9c81 with SMTP id q17-20020a170902dad100b0017a09409c81mr28263532plx.93.1664913173159; Tue, 04 Oct 2022 12:52:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 10/20] accel/tcg: Remove PageDesc code_bitmap Date: Tue, 4 Oct 2022 12:52:31 -0700 Message-Id: <20221004195241.46491-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664913866358100001 This bitmap is created and discarded immediately. We gain nothing by its existence. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-Id: <20220822232338.1727934-2-richard.henderson@linaro.org> --- accel/tcg/translate-all.c | 78 ++------------------------------------- 1 file changed, 4 insertions(+), 74 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index d71d04d338..59432dc558 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -102,21 +102,14 @@ #define assert_memory_lock() tcg_debug_assert(have_mmap_lock()) #endif =20 -#define SMC_BITMAP_USE_THRESHOLD 10 - typedef struct PageDesc { /* list of TBs intersecting this ram page */ uintptr_t first_tb; -#ifdef CONFIG_SOFTMMU - /* in order to optimize self modifying code, we count the number - of lookups we do to a given page to use a bitmap */ - unsigned long *code_bitmap; - unsigned int code_write_count; -#else +#ifdef CONFIG_USER_ONLY unsigned long flags; void *target_data; #endif -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_SOFTMMU QemuSpin lock; #endif } PageDesc; @@ -907,17 +900,6 @@ void tb_htable_init(void) qht_init(&tb_ctx.htable, tb_cmp, CODE_GEN_HTABLE_SIZE, mode); } =20 -/* call with @p->lock held */ -static inline void invalidate_page_bitmap(PageDesc *p) -{ - assert_page_locked(p); -#ifdef CONFIG_SOFTMMU - g_free(p->code_bitmap); - p->code_bitmap =3D NULL; - p->code_write_count =3D 0; -#endif -} - /* Set to NULL all the 'first_tb' fields in all PageDescs. */ static void page_flush_tb_1(int level, void **lp) { @@ -932,7 +914,6 @@ static void page_flush_tb_1(int level, void **lp) for (i =3D 0; i < V_L2_SIZE; ++i) { page_lock(&pd[i]); pd[i].first_tb =3D (uintptr_t)NULL; - invalidate_page_bitmap(pd + i); page_unlock(&pd[i]); } } else { @@ -1197,11 +1178,9 @@ static void do_tb_phys_invalidate(TranslationBlock *= tb, bool rm_from_page_list) if (rm_from_page_list) { p =3D page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); tb_page_remove(p, tb); - invalidate_page_bitmap(p); if (tb->page_addr[1] !=3D -1) { p =3D page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); tb_page_remove(p, tb); - invalidate_page_bitmap(p); } } =20 @@ -1246,35 +1225,6 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_pag= e_addr_t page_addr) } } =20 -#ifdef CONFIG_SOFTMMU -/* call with @p->lock held */ -static void build_page_bitmap(PageDesc *p) -{ - int n, tb_start, tb_end; - TranslationBlock *tb; - - assert_page_locked(p); - p->code_bitmap =3D bitmap_new(TARGET_PAGE_SIZE); - - PAGE_FOR_EACH_TB(p, tb, n) { - /* NOTE: this is subtle as a TB may span two physical pages */ - if (n =3D=3D 0) { - /* NOTE: tb_end may be after the end of the page, but - it is not a problem */ - tb_start =3D tb->pc & ~TARGET_PAGE_MASK; - tb_end =3D tb_start + tb->size; - if (tb_end > TARGET_PAGE_SIZE) { - tb_end =3D TARGET_PAGE_SIZE; - } - } else { - tb_start =3D 0; - tb_end =3D ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); - } - bitmap_set(p->code_bitmap, tb_start, tb_end - tb_start); - } -} -#endif - /* add the tb in the target page and protect it if necessary * * Called with mmap_lock held for user-mode emulation. @@ -1295,7 +1245,6 @@ static inline void tb_page_add(PageDesc *p, Translati= onBlock *tb, page_already_protected =3D p->first_tb !=3D (uintptr_t)NULL; #endif p->first_tb =3D (uintptr_t)tb | n; - invalidate_page_bitmap(p); =20 #if defined(CONFIG_USER_ONLY) /* translator_loop() must have made all TB pages non-writable */ @@ -1357,10 +1306,8 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t ph= ys_pc, /* remove TB from the page(s) if we couldn't insert it */ if (unlikely(existing_tb)) { tb_page_remove(p, tb); - invalidate_page_bitmap(p); if (p2) { tb_page_remove(p2, tb); - invalidate_page_bitmap(p2); } tb =3D existing_tb; } @@ -1731,7 +1678,6 @@ tb_invalidate_phys_page_range__locked(struct page_col= lection *pages, #if !defined(CONFIG_USER_ONLY) /* if no code remaining, no need to continue to use slow writes */ if (!p->first_tb) { - invalidate_page_bitmap(p); tlb_unprotect_code(start); } #endif @@ -1827,24 +1773,8 @@ void tb_invalidate_phys_page_fast(struct page_collec= tion *pages, } =20 assert_page_locked(p); - if (!p->code_bitmap && - ++p->code_write_count >=3D SMC_BITMAP_USE_THRESHOLD) { - build_page_bitmap(p); - } - if (p->code_bitmap) { - unsigned int nr; - unsigned long b; - - nr =3D start & ~TARGET_PAGE_MASK; - b =3D p->code_bitmap[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG - 1)); - if (b & ((1 << len) - 1)) { - goto do_invalidate; - } - } else { - do_invalidate: - tb_invalidate_phys_page_range__locked(pages, p, start, start + len, - retaddr); - } + tb_invalidate_phys_page_range__locked(pages, p, start, start + len, + retaddr); } #else /* Called with mmap_lock held. If pc is not 0 then it indicates the --=20 2.34.1 From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664914207; cv=none; d=zohomail.com; s=zohoarc; b=QOcA6s9Be9u/BmfBGzb9BdhVqe02oelvvwz1ftbLdPStZLhFNLyRNlOBuc9DLyjoVk7+JC6+YfReEErTb4MsQu71p2n//OnU6fzj1hRRV+GZb4c8hYS8fqhGw2RGjQFCq9Nafc4aEBdqVkvBf1j0JhW1Rotp+rjsDQ3aeigCrIs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664914207; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cLUCkFTb6+JnLlWzn7HnttSYfDBpIhciH0RgPU16KNQ=; b=n0HvNO2ucs8OnKAe8zXUyOh2qTmxT6uO7bB/t3uUZoGkdkjPE94+HDRrbEd7GgsGqoDhT8PdFXDWwQCJIOBJ1ihhOK346OYW7g/sjS1W2mNY+YcUm5YlkWcyGmv1W1me+XIrQY0MideIa1JxrNN5TkNHPOf17m7gTOEJtBcXJ1E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664914207816245.27302974599797; Tue, 4 Oct 2022 13:10:07 -0700 (PDT) Received: from localhost ([::1]:43748 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofoEv-0002xX-RE for importer@patchew.org; Tue, 04 Oct 2022 16:10:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49318) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyM-0001rB-Hx for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:58 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:35421) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofnyJ-0000HH-Ow for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:58 -0400 Received: by mail-pf1-x42e.google.com with SMTP id i6so14043517pfb.2 for ; Tue, 04 Oct 2022 12:52:55 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.52.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:52:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=cLUCkFTb6+JnLlWzn7HnttSYfDBpIhciH0RgPU16KNQ=; b=o4mhEith8a9Amqr4WBxp4Mw/ryCl/lgfEXyPE6p2dGPqODJKVz6Zy4Sk0V8HJW24gn pz+0MCEMtIKsFqrYU6wViwm20J31xt58dIkbaw0eHtnPSh1PNZbvyCCz+Ezn460mtCKs Hf02F2p6v5non2QZXlwlkBRguStoQ1if/frt38kFp+H7CVCfkzJGqIkvJAZPPNZVtWD8 WpP/uez3k3VzhAk4DO8y4Oyh772HtAIcbdRNEZpZgyQKeCHLmZxo1g8hsaxA9VD1ZEw9 C1cRZz6cYWxxPZKtbDFdwHkMH36FFc1o+Bzqv8n8LKlRij4Xx3eLiKkg9XDGBfcg5xS/ Re8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=cLUCkFTb6+JnLlWzn7HnttSYfDBpIhciH0RgPU16KNQ=; b=clw8YwupA1Vy3AQFcZXGxZ00oDpCeADicnxzT2eHUiTTOBlRyDH7oml5rjrYiC4Y3p noBOD2fjHOgpTsXYXPsbzdYQejwAXxH9020TzPWrRUUJDNcwMv5V8HeMP4h1LpxIBc/h /QHMvEsf68Ne9n2hhxvioDbQzLQAhnyjIatdALfbdhWUmwt9zEl0mnU1hfrW8cuIeaMm KtekaAjYbcA9tXQnK3KIclTg4dUpxr/f/UP/ifbEkyjTg3N95Ad+rmMnpTIYeSOKBrUd OpQF7UH3QO1+Y9HNHKEb7yuQHZWjy6hLg54EvSCSPWynY7J+86ZnmYmYA43BprZBc7ce X1fw== X-Gm-Message-State: ACrzQf3g7GjmtDz54Bs6Pp8Fp7mT+PKLAR4V8LYxxisS3byMR+AaM6AU azHHLYVfabHkeVV/Japnr66HQZUxLU68Ng== X-Google-Smtp-Source: AMsMyM7FaXe8W1tJzNa6VshVMlzaKwQdPVSs2kajASgSgOh2JIC/D9qb1cgClNj0i35C2+b+0qKXgw== X-Received: by 2002:a62:ee17:0:b0:55b:b0d:bc9f with SMTP id e23-20020a62ee17000000b0055b0b0dbc9fmr26946604pfi.39.1664913174178; Tue, 04 Oct 2022 12:52:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 11/20] accel/tcg: Use bool for page_find_alloc Date: Tue, 4 Oct 2022 12:52:32 -0700 Message-Id: <20221004195241.46491-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664914209501100001 Bool is more appropriate type for the alloc parameter. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 59432dc558..ca685f6ede 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -465,7 +465,7 @@ void page_init(void) #endif } =20 -static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) +static PageDesc *page_find_alloc(tb_page_addr_t index, bool alloc) { PageDesc *pd; void **lp; @@ -533,11 +533,11 @@ static PageDesc *page_find_alloc(tb_page_addr_t index= , int alloc) =20 static inline PageDesc *page_find(tb_page_addr_t index) { - return page_find_alloc(index, 0); + return page_find_alloc(index, false); } =20 static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1, - PageDesc **ret_p2, tb_page_addr_t phys2, int al= loc); + PageDesc **ret_p2, tb_page_addr_t phys2, bool a= lloc); =20 /* In user-mode page locks aren't used; mmap_lock is enough */ #ifdef CONFIG_USER_ONLY @@ -651,7 +651,7 @@ static inline void page_unlock(PageDesc *pd) /* lock the page(s) of a TB in the correct acquisition order */ static inline void page_lock_tb(const TranslationBlock *tb) { - page_lock_pair(NULL, tb->page_addr[0], NULL, tb->page_addr[1], 0); + page_lock_pair(NULL, tb->page_addr[0], NULL, tb->page_addr[1], false); } =20 static inline void page_unlock_tb(const TranslationBlock *tb) @@ -840,7 +840,7 @@ void page_collection_unlock(struct page_collection *set) #endif /* !CONFIG_USER_ONLY */ =20 static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1, - PageDesc **ret_p2, tb_page_addr_t phys2, int al= loc) + PageDesc **ret_p2, tb_page_addr_t phys2, bool a= lloc) { PageDesc *p1, *p2; tb_page_addr_t page1; @@ -1290,7 +1290,7 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phy= s_pc, * Note that inserting into the hash table first isn't an option, since * we can only insert TBs that are fully initialized. */ - page_lock_pair(&p, phys_pc, &p2, phys_page2, 1); + page_lock_pair(&p, phys_pc, &p2, phys_page2, true); tb_page_add(p, tb, 0, phys_pc & TARGET_PAGE_MASK); if (p2) { tb_page_add(p2, tb, 1, phys_page2); @@ -2219,7 +2219,7 @@ void page_set_flags(target_ulong start, target_ulong = end, int flags) for (addr =3D start, len =3D end - start; len !=3D 0; len -=3D TARGET_PAGE_SIZE, addr +=3D TARGET_PAGE_SIZE) { - PageDesc *p =3D page_find_alloc(addr >> TARGET_PAGE_BITS, 1); + PageDesc *p =3D page_find_alloc(addr >> TARGET_PAGE_BITS, true); =20 /* If the write protection bit is set, then we invalidate the code inside. */ --=20 2.34.1 From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664914507; cv=none; d=zohomail.com; s=zohoarc; b=J4xpG9S/4fk85Hi6GllJBs1y3WtJ0aLIznA//Z2XDIaBRO6QIK99t2wcpBdg9s/boBwgc6+yPD+XXXApyiA21nxByfiO/v+/OA9PiXPOdQxz6tjM0Kr/JWKeGG+/2z0VUZgVR0NSiBJWo20+A97ItIz+nYz+OpOrFFopPRNOKG8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664914507; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Me0sYA03idIPAnR4K7d66qbwf2Tw0FB962wCcSsxCZU=; b=Wm7EXPgku2xHDtAF6mI6ICzTbUqEvn2EMUCoifbxzEXHuAnhis7uSs/0NOTYHH2qtGtjXOKgkeeJiLL2kHBPymf0qcuGy2JewJVucNa2vchUZiRyLAEnElIHisq0oRsVdvSaYGMBKL1kuoZsqwUmBW62MeQ3MlmX/POgzreZDgo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664914507829595.1857213258139; Tue, 4 Oct 2022 13:15:07 -0700 (PDT) Received: from localhost ([::1]:49310 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofoJl-0000aD-RK for importer@patchew.org; Tue, 04 Oct 2022 16:15:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49320) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyM-0001ss-WD for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:59 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:40531) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofnyK-0000Fs-9x for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:52:58 -0400 Received: by mail-pj1-x1033.google.com with SMTP id h8-20020a17090a054800b00205ccbae31eso19550174pjf.5 for ; Tue, 04 Oct 2022 12:52:55 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.52.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:52:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=Me0sYA03idIPAnR4K7d66qbwf2Tw0FB962wCcSsxCZU=; b=xTgXNB60QV1OW1aJH2i2rdagQWNfLdurK/jjOJTei6SEPx+nJgQXCcw90RotANBHXj ViDip2m62EiXzyZ3HjDzySdqgu9kfBjKb/UG8IAylbGtmDbufo+Bx+Mz/TH7JW7EQwR/ QU1QCYo80BNC9/uJ6mN4U8jvpJPi679r9xhXCiwW4L2x/v3I/EwFKsh/4GuJj8CGH4wc 1MUTYitcl66dadbQ5Cra50XVM2SzYQxdZlilxMG0nDR/a1AYt4T8TZNnb4dlMrvjZ+bV IRvb2ato83xII7mZMiRoztow2RpnrppLz8AuJ6nL3elLjbwkeZp+UXnN7r6/XdzdNx2R 1llg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=Me0sYA03idIPAnR4K7d66qbwf2Tw0FB962wCcSsxCZU=; b=ZWoCgvFkDYGUbnu9dNXjxUAUkcatlT7Ypp3+4oHuOk7UEa7G8vOfcOU7noBiUnJGZm VeHfCMYF8bKcJzjWhqnhhQqNPcIyCLTSLDwNMBbokW1o6Vt1OQjhsjavGWof7ZgMt+Z0 39FundKdzWRlOBNMEiNABJot+bwiVynGMxhrhzBLmKT89asKjQ2NN1y5uhxExXKtRWAd Eoh4gaZP5zd413T2mQHuPea2auyHEgq3TogS9IGK7K87PcLLBnPuZZ4R/jT3Xpw91Stg zDy1IQRmqPm6Sbp0Js4w51kvXiue0XSZNTdPp4WgP/GtAeRA2begs6kVy4cRWU7kRytR ITNw== X-Gm-Message-State: ACrzQf1mnxC1R3gAhGAim7yCvv2l8TPJdYpVtOtYag9I/JbqAN/l6w7T 4yo/VHTFOPoWtigXu/oPCqbxI/BU8yqPng== X-Google-Smtp-Source: AMsMyM7xy5WKdisHL+rymNhbGQ6Zv2vEwQuOdP6drOvq9wwMsBb+HShYePH+mfvkxE9PwSfcNDaBFw== X-Received: by 2002:a17:90a:4613:b0:20a:e03a:d292 with SMTP id w19-20020a17090a461300b0020ae03ad292mr1285151pjg.91.1664913175310; Tue, 04 Oct 2022 12:52:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 12/20] accel/tcg: Use DisasContextBase in plugin_gen_tb_start Date: Tue, 4 Oct 2022 12:52:33 -0700 Message-Id: <20221004195241.46491-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664914509850100001 Use the pc coming from db->pc_first rather than the TB. Use the cached host_addr rather than re-computing for the first page. We still need a separate lookup for the second page because it won't be computed for DisasContextBase until the translator actually performs a read from the page. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- include/exec/plugin-gen.h | 7 ++++--- accel/tcg/plugin-gen.c | 22 +++++++++++----------- accel/tcg/translator.c | 2 +- 3 files changed, 16 insertions(+), 15 deletions(-) diff --git a/include/exec/plugin-gen.h b/include/exec/plugin-gen.h index f92f169739..5004728c61 100644 --- a/include/exec/plugin-gen.h +++ b/include/exec/plugin-gen.h @@ -19,7 +19,8 @@ struct DisasContextBase; =20 #ifdef CONFIG_PLUGIN =20 -bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool s= upress); +bool plugin_gen_tb_start(CPUState *cpu, const struct DisasContextBase *db, + bool supress); void plugin_gen_tb_end(CPUState *cpu); void plugin_gen_insn_start(CPUState *cpu, const struct DisasContextBase *d= b); void plugin_gen_insn_end(void); @@ -48,8 +49,8 @@ static inline void plugin_insn_append(abi_ptr pc, const v= oid *from, size_t size) =20 #else /* !CONFIG_PLUGIN */ =20 -static inline -bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool s= upress) +static inline bool +plugin_gen_tb_start(CPUState *cpu, const struct DisasContextBase *db, bool= sup) { return false; } diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 3d0b101e34..80dff68934 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -852,7 +852,8 @@ static void plugin_gen_inject(const struct qemu_plugin_= tb *plugin_tb) pr_ops(); } =20 -bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool m= em_only) +bool plugin_gen_tb_start(CPUState *cpu, const DisasContextBase *db, + bool mem_only) { bool ret =3D false; =20 @@ -870,9 +871,9 @@ bool plugin_gen_tb_start(CPUState *cpu, const Translati= onBlock *tb, bool mem_onl =20 ret =3D true; =20 - ptb->vaddr =3D tb->pc; + ptb->vaddr =3D db->pc_first; ptb->vaddr2 =3D -1; - get_page_addr_code_hostp(cpu->env_ptr, tb->pc, &ptb->haddr1); + ptb->haddr1 =3D db->host_addr[0]; ptb->haddr2 =3D NULL; ptb->mem_only =3D mem_only; =20 @@ -898,16 +899,15 @@ void plugin_gen_insn_start(CPUState *cpu, const Disas= ContextBase *db) * Note that we skip this when haddr1 =3D=3D NULL, e.g. when we're * fetching instructions from a region not backed by RAM. */ - if (likely(ptb->haddr1 !=3D NULL && ptb->vaddr2 =3D=3D -1) && - unlikely((db->pc_next & TARGET_PAGE_MASK) !=3D - (db->pc_first & TARGET_PAGE_MASK))) { - get_page_addr_code_hostp(cpu->env_ptr, db->pc_next, - &ptb->haddr2); - ptb->vaddr2 =3D db->pc_next; - } - if (likely(ptb->vaddr2 =3D=3D -1)) { + if (ptb->haddr1 =3D=3D NULL) { + pinsn->haddr =3D NULL; + } else if (is_same_page(db, db->pc_next)) { pinsn->haddr =3D ptb->haddr1 + pinsn->vaddr - ptb->vaddr; } else { + if (ptb->vaddr2 =3D=3D -1) { + ptb->vaddr2 =3D TARGET_PAGE_ALIGN(db->pc_first); + get_page_addr_code_hostp(cpu->env_ptr, ptb->vaddr2, &ptb->hadd= r2); + } pinsn->haddr =3D ptb->haddr2 + pinsn->vaddr - ptb->vaddr2; } } diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index ca8a5f2d83..8e78fd7a9c 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -75,7 +75,7 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb,= int max_insns, ops->tb_start(db, cpu); tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ =20 - plugin_enabled =3D plugin_gen_tb_start(cpu, tb, cflags & CF_MEMI_ONLY); + plugin_enabled =3D plugin_gen_tb_start(cpu, db, cflags & CF_MEMI_ONLY); =20 while (true) { db->num_insns++; --=20 2.34.1 From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664915419; cv=none; d=zohomail.com; s=zohoarc; b=N0UPHXi8fLH3FpT8ugqtCCmDIw6xyonxXT4q3dybigNq/ZiLqbsuHntAhhgfaLVK7cpM03aAAJsHrY8GVZZbHb4cnpFEZI6NBCGWkVqTBLPrz7uw0EkpIvQzIxD6jiCSRZGLRcB1sHPPuZsqZBPC0SWAjUDG/L/8om4vnxIV+I8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664915419; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tAnjl9pfuDVCc8aWBS5RzIa+1h31pDabWO64Od8wikE=; b=O0KswXlzQotr2dKD1RPavOiusLkD+XOcYUooqhIilu77bV/z9tiHTUE7/f+Th6i92tki2fV6Ky8HL52kgbEbCJo00Ll07NEOxdAoaLCXh4ivAkUhqkOsKp6AUEyqe6eTGUOpnkC9Ni6k4evdboQC/Vw/6jdBXtzFm92EO1L8eeg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664915419400209.40988028777906; Tue, 4 Oct 2022 13:30:19 -0700 (PDT) Received: from localhost ([::1]:34696 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofoYU-0008CH-2b for importer@patchew.org; Tue, 04 Oct 2022 16:30:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49324) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyO-0001xm-MW for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:53:00 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:35679) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofnyM-0000Ha-OL for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:53:00 -0400 Received: by mail-pj1-x1035.google.com with SMTP id i7-20020a17090a65c700b0020ad9666a86so2818497pjs.0 for ; Tue, 04 Oct 2022 12:52:58 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.52.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:52:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=tAnjl9pfuDVCc8aWBS5RzIa+1h31pDabWO64Od8wikE=; b=kBQwLHlHbmtO5j7UF4khiDh0P8vKNpPeUetSInW7DF/OGtwurvguXxSp6TmbNS9E0n fOg2WdBPa2UofObO7IXhO1Y5f9eZKrp5l+2jFE85tRzUx8XbGpwwN6X5AQjQIQ4Fck2L UnJrdZ/L9ug7AzBnxs4PKjS+6s2tdPNxb9RRrWR+xYlLcF7vV+zAJfs2mtPh1WmlfzLx ENu2xKgktwGxozPYxG9mlpW8f1kVOIf1ut8VPL1AJ22AJb3fvhOzbKdiLgpiBSJeI63X LatEuRRyM2kg/S10e7mjN82Ng2JpKMabiKtp9/6GYsLIbMohhyZCqXn6mw5suYyYAiE1 2Q8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=tAnjl9pfuDVCc8aWBS5RzIa+1h31pDabWO64Od8wikE=; b=2hFp+SYUUzcirUiEH5wCnvyVdxQGvQZTD+duxS+PQ6X3hcgBr1TfawPw6iEoQ9253l /w7VBRb6DjURP4wfSr03/7rEyURJaB99lJSgOvkCsOCCl8Ce5g9gd9OnYFgs4wAE6PTU PkycAWspdRXgpwZRTTTtLWB7EwE65fkTe9PBZzN/tcPvoxEw4Y0Ehwd8UGbDtZsETgef 1cd5r7U7qy84ewQokDmC7jFW0I6pbl0ZNxM3wmNDBxoVBQ/lhR1l74PZLzfA+pp9Nx3A 5kbI+SqpFTSCX0SrAXwFfyldoRq8JL4zVtsTs8SposkVfM0kAIPK3UvB2jhLFfPaSGa8 iFMg== X-Gm-Message-State: ACrzQf09Z+j9g4Z30MDaXW4EIwxdglMnZEX3KXuzUwK5SRg89j1USiLE hKMeMBlrldhJ9TGgXHYzG7JFgzte5VKcXg== X-Google-Smtp-Source: AMsMyM64jAObDP11QSCeWGKt9E5N0piCENJT1XpYzVxwJNbpOdVyOOhdpEda2BK2QSpkAZxt/532qQ== X-Received: by 2002:a17:903:40cf:b0:17f:7d7e:95b0 with SMTP id t15-20020a17090340cf00b0017f7d7e95b0mr1744808pld.78.1664913176270; Tue, 04 Oct 2022 12:52:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 13/20] accel/tcg: Do not align tb->page_addr[0] Date: Tue, 4 Oct 2022 12:52:34 -0700 Message-Id: <20221004195241.46491-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664915420306100001 Let tb->page_addr[0] contain the address of the first byte of the translated block, rather than the address of the page containing the start of the translated block. We need to recover this value anyway at various points, and it is easier to discard a page offset when it is not needed, which happens naturally via the existing find_page shift. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 16 ++++++++-------- accel/tcg/cputlb.c | 3 ++- accel/tcg/translate-all.c | 9 +++++---- 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5f43b9769a..dd58a144a8 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -174,7 +174,7 @@ struct tb_desc { target_ulong pc; target_ulong cs_base; CPUArchState *env; - tb_page_addr_t phys_page1; + tb_page_addr_t page_addr0; uint32_t flags; uint32_t cflags; uint32_t trace_vcpu_dstate; @@ -186,7 +186,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) const struct tb_desc *desc =3D d; =20 if (tb->pc =3D=3D desc->pc && - tb->page_addr[0] =3D=3D desc->phys_page1 && + tb->page_addr[0] =3D=3D desc->page_addr0 && tb->cs_base =3D=3D desc->cs_base && tb->flags =3D=3D desc->flags && tb->trace_vcpu_dstate =3D=3D desc->trace_vcpu_dstate && @@ -195,8 +195,8 @@ static bool tb_lookup_cmp(const void *p, const void *d) if (tb->page_addr[1] =3D=3D -1) { return true; } else { - tb_page_addr_t phys_page2; - target_ulong virt_page2; + tb_page_addr_t phys_page1; + target_ulong virt_page1; =20 /* * We know that the first page matched, and an otherwise valid= TB @@ -207,9 +207,9 @@ static bool tb_lookup_cmp(const void *p, const void *d) * is different for the new TB. Therefore any exception raised * here by the faulting lookup is not premature. */ - virt_page2 =3D TARGET_PAGE_ALIGN(desc->pc); - phys_page2 =3D get_page_addr_code(desc->env, virt_page2); - if (tb->page_addr[1] =3D=3D phys_page2) { + virt_page1 =3D TARGET_PAGE_ALIGN(desc->pc); + phys_page1 =3D get_page_addr_code(desc->env, virt_page1); + if (tb->page_addr[1] =3D=3D phys_page1) { return true; } } @@ -235,7 +235,7 @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu= , target_ulong pc, if (phys_pc =3D=3D -1) { return NULL; } - desc.phys_page1 =3D phys_pc & TARGET_PAGE_MASK; + desc.page_addr0 =3D phys_pc; h =3D tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate); return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); } diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 361078471b..a0db2d32a8 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -951,7 +951,8 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUS= tate *src_cpu, can be detected */ void tlb_protect_code(ram_addr_t ram_addr) { - cpu_physical_memory_test_and_clear_dirty(ram_addr, TARGET_PAGE_SIZE, + cpu_physical_memory_test_and_clear_dirty(ram_addr & TARGET_PAGE_MASK, + TARGET_PAGE_SIZE, DIRTY_MEMORY_CODE); } =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index ca685f6ede..3a63113c41 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1167,7 +1167,7 @@ static void do_tb_phys_invalidate(TranslationBlock *t= b, bool rm_from_page_list) qemu_spin_unlock(&tb->jmp_lock); =20 /* remove the TB from the hash list */ - phys_pc =3D tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); + phys_pc =3D tb->page_addr[0]; h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags, tb->trace_vcpu_dstate); if (!qht_remove(&tb_ctx.htable, tb, h)) { @@ -1291,7 +1291,7 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phy= s_pc, * we can only insert TBs that are fully initialized. */ page_lock_pair(&p, phys_pc, &p2, phys_page2, true); - tb_page_add(p, tb, 0, phys_pc & TARGET_PAGE_MASK); + tb_page_add(p, tb, 0, phys_pc); if (p2) { tb_page_add(p2, tb, 1, phys_page2); } else { @@ -1644,11 +1644,12 @@ tb_invalidate_phys_page_range__locked(struct page_c= ollection *pages, if (n =3D=3D 0) { /* NOTE: tb_end may be after the end of the page, but it is not a problem */ - tb_start =3D tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); + tb_start =3D tb->page_addr[0]; tb_end =3D tb_start + tb->size; } else { tb_start =3D tb->page_addr[1]; - tb_end =3D tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK= ); + tb_end =3D tb_start + ((tb->page_addr[0] + tb->size) + & ~TARGET_PAGE_MASK); } if (!(tb_end <=3D start || tb_start >=3D end)) { #ifdef TARGET_HAS_PRECISE_SMC --=20 2.34.1 From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664914993; cv=none; d=zohomail.com; s=zohoarc; b=hyXxGyQ6WfdoUYypfLe6Bhcs5wUxSJE1ODzmwG91BUbJbgDJtey3siYdbRjMpPgHJ4/D19ANR+MJDMtIZC5xqUJJqjNGWZN8nsywJ4RmpoFHn9zgMRW+zud+fwns+OjJWoPSkC2TuCh0q4BBNOx0DVGJ2hyhw5vJazhotrX98po= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664914993; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ri8TJtGhCA+1GWqIBzEtqSJbIRN8JsEEU2ry8GkY8NY=; b=bPzgC9OdTSzZ40xg3qRwUnFIcWBJIOXjthpTd8IfDyGM+9lJk1bNfoVk2dkk6le4DPbkYpeeLkq4sMDaa9nEy9ATFaUbTSGw0D9MoRKeJQKxJR1nvektjl2SYZLhLm24MFNE4hlLT8SR2ZVBRq+nVa7zzg0Tk85BoK8RxAOy8oM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664914993087590.2772780444801; Tue, 4 Oct 2022 13:23:13 -0700 (PDT) Received: from localhost ([::1]:37188 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofoRb-0000DK-6r for importer@patchew.org; Tue, 04 Oct 2022 16:23:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49322) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyO-0001xU-Br for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:53:00 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:44723) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofnyM-0000Hc-Iz for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:53:00 -0400 Received: by mail-pf1-x42d.google.com with SMTP id v186so14021673pfv.11 for ; Tue, 04 Oct 2022 12:52:58 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.52.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:52:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=ri8TJtGhCA+1GWqIBzEtqSJbIRN8JsEEU2ry8GkY8NY=; b=DgYtTlCz3UIi5CoIdiD5K7+ZuBANtvf8w94/qo9sEaOsOwayc22kniAljAbm4RJxOP RR2di88C+GBgJOVEwmi5jRT2LQ9fxVM24NhaOIRpTCIJkCzXe5g6tFU0RZ/FnPD+9Bft l8EiDR4xRxkDleajYVSlHcXPSyqlNhWXSPYa43rLYfrqdS0YGy3L/j5YNKhBGNnq3cwn h+GUmvXx8ONEyOjNf8GT0Y5aJ7vtsjdzkGVKa29t9Qa+ZxHL7qyjDx6FRi7y+gCOjFJj xYkSlIo6scxMRMFap9OMBIRdTle8LZhF3eO0rkjZVS6N/V52Rt5R+NURABvo0YSclzrA Mbsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=ri8TJtGhCA+1GWqIBzEtqSJbIRN8JsEEU2ry8GkY8NY=; b=TEwwFg7U9W6U7IukNAewdW7ef1tNg3A/TIrSDPEe4hODJ5xbB1aSDBkjdL+ddGRJUT nXDtNcjP4e9UNJSmvAjBIyX9bNPaz/mfM5zENiZjs/2MWtN/VjGx7RvCxPsxRSha3psb qja9r4bLt4LesIFm+c8UMs4aSpbBUtr1GJAZ2Swr2Nb3DnlKi5WFFvjwSBuAgT/jfWXL L73CCPj9wVk93IJJsBZnQoPt1jbOSzLhcDMKzy/bByh7iMHCa5zI5XRmRS60iUc3qKaf tSUVEdOv6InJ8/tVRHYGYwhYXzeO61nuTwIcbWEGaO6+jiXA1SIQIqNJG+GFF9T3RIsi xn6g== X-Gm-Message-State: ACrzQf2oF1qLRDyhmLE+NsAH8k5qcW6wuHIutA7v7kLBOoKQJvtIQiA6 pZ0oKtMof3XHKN6pGdJzD8JqfRCVaRYMEA== X-Google-Smtp-Source: AMsMyM5m0tAIHhj66gk6RW1hqv2H4gMnASiClE0UJu1rhSQIvWd61ymliEaH9EZEtYFdCXEvIDf5/w== X-Received: by 2002:a63:4a1e:0:b0:438:fa59:c0f3 with SMTP id x30-20020a634a1e000000b00438fa59c0f3mr23911615pga.107.1664913177293; Tue, 04 Oct 2022 12:52:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 14/20] accel/tcg: Inline tb_flush_jmp_cache Date: Tue, 4 Oct 2022 12:52:35 -0700 Message-Id: <20221004195241.46491-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664914993869100001 This function has two users, who use it incompatibly. In tlb_flush_page_by_mmuidx_async_0, when flushing a single page, we need to flush exactly two pages. In tlb_flush_range_by_mmuidx_async_0, when flushing a range of pages, we need to flush N+1 pages. This avoids double-flushing of jmp cache pages in a range. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a0db2d32a8..c7909fb619 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -107,14 +107,6 @@ static void tb_jmp_cache_clear_page(CPUState *cpu, tar= get_ulong page_addr) } } =20 -static void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr) -{ - /* Discard jump cache entries for any tb which might potentially - overlap the flushed page. */ - tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE); - tb_jmp_cache_clear_page(cpu, addr); -} - /** * tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if nec= essary * @desc: The CPUTLBDesc portion of the TLB @@ -541,7 +533,12 @@ static void tlb_flush_page_by_mmuidx_async_0(CPUState = *cpu, } qemu_spin_unlock(&env_tlb(env)->c.lock); =20 - tb_flush_jmp_cache(cpu, addr); + /* + * Discard jump cache entries for any tb which might potentially + * overlap the flushed page, which includes the previous. + */ + tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE); + tb_jmp_cache_clear_page(cpu, addr); } =20 /** @@ -792,8 +789,14 @@ static void tlb_flush_range_by_mmuidx_async_0(CPUState= *cpu, return; } =20 - for (target_ulong i =3D 0; i < d.len; i +=3D TARGET_PAGE_SIZE) { - tb_flush_jmp_cache(cpu, d.addr + i); + /* + * Discard jump cache entries for any tb which might potentially + * overlap the flushed pages, which includes the previous. + */ + d.addr -=3D TARGET_PAGE_SIZE; + for (target_ulong i =3D 0, n =3D d.len / TARGET_PAGE_SIZE + 1; i < n; = i++) { + tb_jmp_cache_clear_page(cpu, d.addr); + d.addr +=3D TARGET_PAGE_SIZE; } } =20 --=20 2.34.1 From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664914608; cv=none; d=zohomail.com; s=zohoarc; b=fYjoPYwbn0d0VVlcaVcjgGSALTi/LcM8i/EOF3Sz4CDMmHexM087h6xfDK97vAbG06H8TC+k+hE+C7CHIxjczT7PJqqQuaKTgBatOAj/JHxVdm6tgx+gHBlLYiBwITdGtZyInYTizJwx+DYXt6mBD5lwZ6EJwpjX8ZMZEOeXh08= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664914608; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ecQCsvnTHICeRKHhQnmBF1bwYTnzG7vyEXDoUtOl6rE=; b=WXIgxBCJRot0Iy9KtQQa77e5gBMxr1XQ74sgrgn2XcrFzsaQV9a52h6Lsl235htIuzW78y7Viq+Jik9RdLPg7eCQJc3a05oC6YF3wpz18M7CMOtt6Iy8ombqxYmZUzYKMKjjg8nr9Ocoi2bgZ4Yts5WNoipmnagoW2vmHrj6XQc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664914608541388.66187334601966; Tue, 4 Oct 2022 13:16:48 -0700 (PDT) Received: from localhost ([::1]:35162 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofoLO-0002M7-8z for importer@patchew.org; Tue, 04 Oct 2022 16:16:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49326) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyP-000213-PL for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:53:01 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:33661) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofnyN-0000F3-2b for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:53:01 -0400 Received: by mail-pj1-x1034.google.com with SMTP id bu5-20020a17090aee4500b00202e9ca2182so1955081pjb.0 for ; Tue, 04 Oct 2022 12:52:58 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.52.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:52:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=ecQCsvnTHICeRKHhQnmBF1bwYTnzG7vyEXDoUtOl6rE=; b=qwMuAJjaY3exlpNxJFDfY4Y8mFw8KfwUilJ5EgPS9Y9ucvFjrHIEPDMTNP11RDsWez g/N88w+hNeDWN9bNx8Ogi5WVw3r0wfr12ecdG7IZaKqmfJU5TJ+nkOuDCR/p6VuNc03h aNkiltUcS36+lKAvMrMXB1RsUWSzhDkzzXFYV33KCQbcBv6jAlfKjQUhf+PAJrS7FoVm am1FwK/IQLE9EsXLYMNct0seGd2h3fhUAn1I+6mxlpta93aYEqcoN2ZiZGdLYtvfE+J+ YW0ORu8lFPiuQYLtPgrnxasnYzuq/nWixh6OF2RrB0BLomNilC7+zj1x/pTfQ8Og9ce1 A75g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=ecQCsvnTHICeRKHhQnmBF1bwYTnzG7vyEXDoUtOl6rE=; b=eanTl7wcqA8MIbfEb3aroTvdShq8lnlQ4R/3yO4yGx2FerEyh5RSmWbgRBvfrvrRdw 2yqb4fMFdo3obNnU9UGzBA0uCLGIF1ZUGJ1PbvhAbOJfJ7LpI0xN+VQXg+JwGfIUKuiu vLAr3z7UsTE8TOV6VS+LdfJZYJle8Nw2KQr2U5i2SudMRQI+Qc91BCeLYDj1N2P1eFeX YcZD38DrHxuBKn3yDetsDBX7qmkkut809FNi+1D6mbSVseZtEDoDipY9TJo32UM2BwlR A+3vhLk3mA62wke5QIhrAng8hE/2z9mqnZMSKJrebEVRpXTKYf7MoU15PwYxYG7g05UK PpBA== X-Gm-Message-State: ACrzQf04Nle9G5dofoKScs8NRC0Yq0PTR1hT6UJuJQ31so6Bpe9nP1gX Ec0MG2pP0zN9XqXTyF0xgVenDXQdYIaSUQ== X-Google-Smtp-Source: AMsMyM7TRLYUjOaHkI/pXE7SXkP+b65B+2lvDWVomZJeZmHrOZWPNiC2tKfLjqOy7bNNtA0q0ngBAg== X-Received: by 2002:a17:902:6546:b0:17f:7888:58b with SMTP id d6-20020a170902654600b0017f7888058bmr2838609pln.140.1664913178197; Tue, 04 Oct 2022 12:52:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 15/20] include/hw/core: Create struct CPUJumpCache Date: Tue, 4 Oct 2022 12:52:36 -0700 Message-Id: <20221004195241.46491-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664914610670100001 Wrap the bare TranslationBlock pointer into a structure. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- accel/tcg/tb-hash.h | 1 + accel/tcg/tb-jmp-cache.h | 24 ++++++++++++++++++++++++ include/exec/cpu-common.h | 1 + include/hw/core/cpu.h | 15 +-------------- include/qemu/typedefs.h | 1 + accel/stubs/tcg-stub.c | 4 ++++ accel/tcg/cpu-exec.c | 10 +++++++--- accel/tcg/cputlb.c | 9 +++++---- accel/tcg/translate-all.c | 28 +++++++++++++++++++++++++--- hw/core/cpu-common.c | 3 +-- plugins/core.c | 2 +- trace/control-target.c | 2 +- 12 files changed, 72 insertions(+), 28 deletions(-) create mode 100644 accel/tcg/tb-jmp-cache.h diff --git a/accel/tcg/tb-hash.h b/accel/tcg/tb-hash.h index 0a273d9605..83dc610e4c 100644 --- a/accel/tcg/tb-hash.h +++ b/accel/tcg/tb-hash.h @@ -23,6 +23,7 @@ #include "exec/cpu-defs.h" #include "exec/exec-all.h" #include "qemu/xxhash.h" +#include "tb-jmp-cache.h" =20 #ifdef CONFIG_SOFTMMU =20 diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h new file mode 100644 index 0000000000..2d8fbb1bfe --- /dev/null +++ b/accel/tcg/tb-jmp-cache.h @@ -0,0 +1,24 @@ +/* + * The per-CPU TranslationBlock jump cache. + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef ACCEL_TCG_TB_JMP_CACHE_H +#define ACCEL_TCG_TB_JMP_CACHE_H + +#define TB_JMP_CACHE_BITS 12 +#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) + +/* + * Accessed in parallel; all accesses to 'tb' must be atomic. + */ +struct CPUJumpCache { + struct { + TranslationBlock *tb; + } array[TB_JMP_CACHE_SIZE]; +}; + +#endif /* ACCEL_TCG_TB_JMP_CACHE_H */ diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index d909429427..c493510ee9 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -38,6 +38,7 @@ void cpu_list_unlock(void); unsigned int cpu_list_generation_id_get(void); =20 void tcg_flush_softmmu_tlb(CPUState *cs); +void tcg_flush_jmp_cache(CPUState *cs); =20 void tcg_iommu_init_notifier_list(CPUState *cpu); void tcg_iommu_free_notifier_list(CPUState *cpu); diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 009dc0d336..18ca701b44 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -236,9 +236,6 @@ struct kvm_run; struct hax_vcpu_state; struct hvf_vcpu_state; =20 -#define TB_JMP_CACHE_BITS 12 -#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) - /* work queue */ =20 /* The union type allows passing of 64 bit target pointers on 32 bit @@ -369,8 +366,7 @@ struct CPUState { CPUArchState *env_ptr; IcountDecr *icount_decr_ptr; =20 - /* Accessed in parallel; all accesses must be atomic */ - TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; + CPUJumpCache *tb_jmp_cache; =20 struct GDBRegisterState *gdb_regs; int gdb_num_regs; @@ -456,15 +452,6 @@ extern CPUTailQ cpus; =20 extern __thread CPUState *current_cpu; =20 -static inline void cpu_tb_jmp_cache_clear(CPUState *cpu) -{ - unsigned int i; - - for (i =3D 0; i < TB_JMP_CACHE_SIZE; i++) { - qatomic_set(&cpu->tb_jmp_cache[i], NULL); - } -} - /** * qemu_tcg_mttcg_enabled: * Check whether we are running MultiThread TCG or not. diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index a4aee238c7..5f95169827 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -41,6 +41,7 @@ typedef struct CoMutex CoMutex; typedef struct ConfidentialGuestSupport ConfidentialGuestSupport; typedef struct CPUAddressSpace CPUAddressSpace; typedef struct CPUArchState CPUArchState; +typedef struct CPUJumpCache CPUJumpCache; typedef struct CPUState CPUState; typedef struct CPUTLBEntryFull CPUTLBEntryFull; typedef struct DeviceListener DeviceListener; diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c index 6ce8a34228..c1b05767c0 100644 --- a/accel/stubs/tcg-stub.c +++ b/accel/stubs/tcg-stub.c @@ -21,6 +21,10 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) { } =20 +void tcg_flush_jmp_cache(CPUState *cpu) +{ +} + int probe_access_flags(CPUArchState *env, target_ulong addr, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index dd58a144a8..2d7e610ee2 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -42,6 +42,7 @@ #include "sysemu/replay.h" #include "sysemu/tcg.h" #include "exec/helper-proto.h" +#include "tb-jmp-cache.h" #include "tb-hash.h" #include "tb-context.h" #include "internal.h" @@ -252,7 +253,7 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu= , target_ulong pc, tcg_debug_assert(!(cflags & CF_INVALID)); =20 hash =3D tb_jmp_cache_hash_func(pc); - tb =3D qatomic_rcu_read(&cpu->tb_jmp_cache[hash]); + tb =3D qatomic_rcu_read(&cpu->tb_jmp_cache->array[hash].tb); =20 if (likely(tb && tb->pc =3D=3D pc && @@ -266,7 +267,7 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu= , target_ulong pc, if (tb =3D=3D NULL) { return NULL; } - qatomic_set(&cpu->tb_jmp_cache[hash], tb); + qatomic_set(&cpu->tb_jmp_cache->array[hash].tb, tb); return tb; } =20 @@ -987,6 +988,8 @@ int cpu_exec(CPUState *cpu) =20 tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb =3D=3D NULL) { + uint32_t h; + mmap_lock(); tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); mmap_unlock(); @@ -994,7 +997,8 @@ int cpu_exec(CPUState *cpu) * We add the TB in the virtual pc hash table * for the fast lookup */ - qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]= , tb); + h =3D tb_jmp_cache_hash_func(pc); + qatomic_set(&cpu->tb_jmp_cache->array[h].tb, tb); } =20 #ifndef CONFIG_USER_ONLY diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c7909fb619..6f1c00682b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -100,10 +100,11 @@ static void tlb_window_reset(CPUTLBDesc *desc, int64_= t ns, =20 static void tb_jmp_cache_clear_page(CPUState *cpu, target_ulong page_addr) { - unsigned int i, i0 =3D tb_jmp_cache_hash_page(page_addr); + int i, i0 =3D tb_jmp_cache_hash_page(page_addr); + CPUJumpCache *jc =3D cpu->tb_jmp_cache; =20 for (i =3D 0; i < TB_JMP_PAGE_SIZE; i++) { - qatomic_set(&cpu->tb_jmp_cache[i0 + i], NULL); + qatomic_set(&jc->array[i0 + i].tb, NULL); } } =20 @@ -356,7 +357,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cp= u, run_on_cpu_data data) =20 qemu_spin_unlock(&env_tlb(env)->c.lock); =20 - cpu_tb_jmp_cache_clear(cpu); + tcg_flush_jmp_cache(cpu); =20 if (to_clean =3D=3D ALL_MMUIDX_BITS) { qatomic_set(&env_tlb(env)->c.full_flush_count, @@ -785,7 +786,7 @@ static void tlb_flush_range_by_mmuidx_async_0(CPUState = *cpu, * longer to clear each entry individually than it will to clear it al= l. */ if (d.len >=3D (TARGET_PAGE_SIZE * TB_JMP_CACHE_SIZE)) { - cpu_tb_jmp_cache_clear(cpu); + tcg_flush_jmp_cache(cpu); return; } =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 3a63113c41..63ecc15236 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -58,6 +58,7 @@ #include "sysemu/tcg.h" #include "qapi/error.h" #include "hw/core/tcg-cpu-ops.h" +#include "tb-jmp-cache.h" #include "tb-hash.h" #include "tb-context.h" #include "internal.h" @@ -967,7 +968,7 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data = tb_flush_count) } =20 CPU_FOREACH(cpu) { - cpu_tb_jmp_cache_clear(cpu); + tcg_flush_jmp_cache(cpu); } =20 qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE); @@ -1187,8 +1188,9 @@ static void do_tb_phys_invalidate(TranslationBlock *t= b, bool rm_from_page_list) /* remove the TB from the hash list */ h =3D tb_jmp_cache_hash_func(tb->pc); CPU_FOREACH(cpu) { - if (qatomic_read(&cpu->tb_jmp_cache[h]) =3D=3D tb) { - qatomic_set(&cpu->tb_jmp_cache[h], NULL); + CPUJumpCache *jc =3D cpu->tb_jmp_cache; + if (qatomic_read(&jc->array[h].tb) =3D=3D tb) { + qatomic_set(&jc->array[h].tb, NULL); } } =20 @@ -2443,6 +2445,26 @@ int page_unprotect(target_ulong address, uintptr_t p= c) } #endif /* CONFIG_USER_ONLY */ =20 +/* + * Called by generic code at e.g. cpu reset after cpu creation, + * therefore we must be prepared to allocate the jump cache. + */ +void tcg_flush_jmp_cache(CPUState *cpu) +{ + CPUJumpCache *jc =3D cpu->tb_jmp_cache; + + if (likely(jc)) { + for (int i =3D 0; i < TB_JMP_CACHE_SIZE; i++) { + qatomic_set(&jc->array[i].tb, NULL); + } + } else { + /* This should happen once during realize, and thus never race. */ + jc =3D g_new0(CPUJumpCache, 1); + jc =3D qatomic_xchg(&cpu->tb_jmp_cache, jc); + assert(jc =3D=3D NULL); + } +} + /* This is a wrapper for common code that can not use CONFIG_SOFTMMU */ void tcg_flush_softmmu_tlb(CPUState *cs) { diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 9e3241b430..f9fdd46b9d 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -137,8 +137,7 @@ static void cpu_common_reset(DeviceState *dev) cpu->cflags_next_tb =3D -1; =20 if (tcg_enabled()) { - cpu_tb_jmp_cache_clear(cpu); - + tcg_flush_jmp_cache(cpu); tcg_flush_softmmu_tlb(cpu); } } diff --git a/plugins/core.c b/plugins/core.c index 792262da08..c3ae284994 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -56,7 +56,7 @@ struct qemu_plugin_ctx *plugin_id_to_ctx_locked(qemu_plug= in_id_t id) static void plugin_cpu_update__async(CPUState *cpu, run_on_cpu_data data) { bitmap_copy(cpu->plugin_mask, &data.host_ulong, QEMU_PLUGIN_EV_MAX); - cpu_tb_jmp_cache_clear(cpu); + tcg_flush_jmp_cache(cpu); } =20 static void plugin_cpu_update__locked(gpointer k, gpointer v, gpointer uda= ta) diff --git a/trace/control-target.c b/trace/control-target.c index 8418673c18..232c97a4a1 100644 --- a/trace/control-target.c +++ b/trace/control-target.c @@ -65,7 +65,7 @@ static void trace_event_synchronize_vcpu_state_dynamic( { bitmap_copy(vcpu->trace_dstate, vcpu->trace_dstate_delayed, CPU_TRACE_DSTATE_MAX_EVENTS); - cpu_tb_jmp_cache_clear(vcpu); + tcg_flush_jmp_cache(vcpu); } =20 void trace_event_set_vcpu_state_dynamic(CPUState *vcpu, --=20 2.34.1 From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664914122; cv=none; d=zohomail.com; s=zohoarc; b=PD9FW0sVZ/JwL2mT5oB3OxPbHLZ7ObKBARY91to2uCkJN+L6/O3dyCEs7oayryxMhS2ZiSoqPXbuFrHMR9zCbp8/lXcgYF5u94cNaZFxZRfOmX+UZqIIBkrqNAYlrzChqHWX+yVS4aFctx7W/stvZLrwiZ+xfmjlXuXsGtIbVFY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664914122; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ct0u9b3qDBsxUF0JVELTeHrR9q6ArXqosWhP8E36ZjU=; b=kSkJ8Nb1n0W3Oj8MWzncgl6sQXx9Ip0xZr3fBXwoUWo3RAlkgwKF58bsYpZVj1VIaKFrCc2ldxBf5Z16h8XxM+fheoenPaYuk9reEbSQX6xBTwH6pBFegEaivx2xSlJMlep5+sGVnRis/NHbYBp2s12R7me0a4qw7p5dO2JSh4U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664914122903169.8878243123945; Tue, 4 Oct 2022 13:08:42 -0700 (PDT) Received: from localhost ([::1]:56188 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofoDY-0000yf-PL for importer@patchew.org; Tue, 04 Oct 2022 16:08:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49332) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyS-00029P-HG for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:53:04 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:40641) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofnyO-0000IG-V6 for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:53:04 -0400 Received: by mail-pl1-x631.google.com with SMTP id b2so8669982plc.7 for ; Tue, 04 Oct 2022 12:53:00 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.52.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:52:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=ct0u9b3qDBsxUF0JVELTeHrR9q6ArXqosWhP8E36ZjU=; b=HYo/2r+m6bDg6ELdubsNjdgZ8BpJeefMzQfO55lzK+GhBOb1VtODgctNeWJdEW5eDL xUNPDF4tuMuqQaTwHxdMCWrwYARxNArnN/yzi8adKtl96p0Mzv88FmbeLINso4Bf4TA3 P6sf+sHHrsXiK9bQAuNRd1M5xtDC5ieeJSTmtfsYRxj21XYT3cpJhxN+ngJ3OqrW+TXF h+PjFE3zfipKqYc5YzjRdXzMcTGih1yIkbj9bLQHxD6xgOjnlM11I0X+ktVgW41Qyt/L abX1VQnYbCisuSvrVthcC0hw5JmZ4zS11wfLOj7TBwWPA/bFUyYhxbdXAPCxCCDCh/QW HQhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=ct0u9b3qDBsxUF0JVELTeHrR9q6ArXqosWhP8E36ZjU=; b=Gp1cjzkO67KZtRFGY5ZfE7zEZA+2aG96smbqwE9lFXFC/REZ67JnoTCxa997vHJIrT DAMtmDAKyVbJsArDMgY6qPM+XrPXG7wshjrc8/wBGI1e1Svx4LTFry2uGjZa2enYnx7M Kk4wjoSzoc/nj6oqLIPPKMrnqR17Cs/NTfjb0Ymaw8mSVKQUIgMr6///71iDTkUhAFJB 1AEUZrTHPDBXocoOjXTqZgbbG/BbfG/0qmiQE3yZmW4S3YS3YyU120oFcGIsLrsBOSvR bTn6tv+Zei2xE6QiEMVoFgqE+c4WVAhAjwexhKsndKRWOQswWu718DdmcWzACHHo6/jT kvIQ== X-Gm-Message-State: ACrzQf1kkInxMvr+YFe/A/OYcFVi6v1OmSAQELu1Ik3Hd8Qv5+/eUZyD Wniu+ylts/uxlDdpWogqBYo/n176Hsp9gA== X-Google-Smtp-Source: AMsMyM6cEFG/Z/EsVkyP/c6w/96tIo9KHVguYXVf9PcOMj8egcOzPCfPx+lBBMozJ/KJEgd/u/hxfA== X-Received: by 2002:a17:902:b194:b0:176:d229:83bd with SMTP id s20-20020a170902b19400b00176d22983bdmr27630526plr.174.1664913179367; Tue, 04 Oct 2022 12:52:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, Taylor Simpson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Mark Cave-Ayland , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Michael Rolnik , "Edgar E. Iglesias" , Song Gao , Xiaojuan Yang , Laurent Vivier , Jiaxun Yang , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , Yoshinori Sato , Bastian Koppelmann , Max Filippov , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PULL 16/20] hw/core: Add CPUClass.get_pc Date: Tue, 4 Oct 2022 12:52:37 -0700 Message-Id: <20221004195241.46491-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664914125806100003 Populate this new method for all targets. Always match the result that would be given by cpu_get_tb_cpu_state, as we will want these values to correspond in the logs. Reviewed-by: Taylor Simpson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Mark Cave-Ayland (target/sparc) Signed-off-by: Richard Henderson --- Cc: Eduardo Habkost (supporter:Machine core) Cc: Marcel Apfelbaum (supporter:Machine core) Cc: "Philippe Mathieu-Daud=C3=A9" (reviewer:Machine core) Cc: Yanan Wang (reviewer:Machine core) Cc: Michael Rolnik (maintainer:AVR TCG CPUs) Cc: "Edgar E. Iglesias" (maintainer:CRIS TCG CPU= s) Cc: Taylor Simpson (supporter:Hexagon TCG CPUs) Cc: Song Gao (maintainer:LoongArch TCG CPUs) Cc: Xiaojuan Yang (maintainer:LoongArch TCG CPUs) Cc: Laurent Vivier (maintainer:M68K TCG CPUs) Cc: Jiaxun Yang (reviewer:MIPS TCG CPUs) Cc: Aleksandar Rikalo (reviewer:MIPS TCG CPU= s) Cc: Chris Wulff (maintainer:NiosII TCG CPUs) Cc: Marek Vasut (maintainer:NiosII TCG CPUs) Cc: Stafford Horne (odd fixer:OpenRISC TCG CPUs) Cc: Yoshinori Sato (reviewer:RENESAS RX CPUs) Cc: Mark Cave-Ayland (maintainer:SPARC TCG = CPUs) Cc: Bastian Koppelmann (maintainer:TriCore= TCG CPUs) Cc: Max Filippov (maintainer:Xtensa TCG CPUs) Cc: qemu-arm@nongnu.org (open list:ARM TCG CPUs) Cc: qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs) Cc: qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Cc: qemu-s390x@nongnu.org (open list:S390 TCG CPUs) --- include/hw/core/cpu.h | 3 +++ target/alpha/cpu.c | 9 +++++++++ target/arm/cpu.c | 13 +++++++++++++ target/avr/cpu.c | 8 ++++++++ target/cris/cpu.c | 8 ++++++++ target/hexagon/cpu.c | 8 ++++++++ target/hppa/cpu.c | 8 ++++++++ target/i386/cpu.c | 9 +++++++++ target/loongarch/cpu.c | 9 +++++++++ target/m68k/cpu.c | 8 ++++++++ target/microblaze/cpu.c | 8 ++++++++ target/mips/cpu.c | 8 ++++++++ target/nios2/cpu.c | 9 +++++++++ target/openrisc/cpu.c | 8 ++++++++ target/ppc/cpu_init.c | 8 ++++++++ target/riscv/cpu.c | 13 +++++++++++++ target/rx/cpu.c | 8 ++++++++ target/s390x/cpu.c | 8 ++++++++ target/sh4/cpu.c | 8 ++++++++ target/sparc/cpu.c | 8 ++++++++ target/tricore/cpu.c | 9 +++++++++ target/xtensa/cpu.c | 8 ++++++++ 22 files changed, 186 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 18ca701b44..f9b58773f7 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -115,6 +115,8 @@ struct SysemuCPUOps; * If the target behaviour here is anything other than "set * the PC register to the value passed in" then the target must * also implement the synchronize_from_tb hook. + * @get_pc: Callback for getting the Program Counter register. + * As above, with the semantics of the target architecture. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_adjust_breakpoint: Callback for adjusting the address of a @@ -151,6 +153,7 @@ struct CPUClass { void (*dump_state)(CPUState *cpu, FILE *, int flags); int64_t (*get_arch_id)(CPUState *cpu); void (*set_pc)(CPUState *cpu, vaddr value); + vaddr (*get_pc)(CPUState *cpu); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index a8990d401b..979a629d59 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -33,6 +33,14 @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc =3D value; } =20 +static vaddr alpha_cpu_get_pc(CPUState *cs) +{ + AlphaCPU *cpu =3D ALPHA_CPU(cs); + + return cpu->env.pc; +} + + static bool alpha_cpu_has_work(CPUState *cs) { /* Here we are checking to see if the CPU should wake up from HALT. @@ -244,6 +252,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->has_work =3D alpha_cpu_has_work; cc->dump_state =3D alpha_cpu_dump_state; cc->set_pc =3D alpha_cpu_set_pc; + cc->get_pc =3D alpha_cpu_get_pc; cc->gdb_read_register =3D alpha_cpu_gdb_read_register; cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7ec3281da9..fa67ba6647 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -60,6 +60,18 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) } } =20 +static vaddr arm_cpu_get_pc(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + if (is_a64(env)) { + return env->pc; + } else { + return env->regs[15]; + } +} + #ifdef CONFIG_TCG void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) @@ -2172,6 +2184,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->has_work =3D arm_cpu_has_work; cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; + cc->get_pc =3D arm_cpu_get_pc; cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 05b992ff73..6900444d03 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -32,6 +32,13 @@ static void avr_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc_w =3D value / 2; /* internally PC points to words */ } =20 +static vaddr avr_cpu_get_pc(CPUState *cs) +{ + AVRCPU *cpu =3D AVR_CPU(cs); + + return cpu->env.pc_w * 2; +} + static bool avr_cpu_has_work(CPUState *cs) { AVRCPU *cpu =3D AVR_CPU(cs); @@ -214,6 +221,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->has_work =3D avr_cpu_has_work; cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; + cc->get_pc =3D avr_cpu_get_pc; dc->vmsd =3D &vms_avr_cpu; cc->sysemu_ops =3D &avr_sysemu_ops; cc->disas_set_info =3D avr_cpu_disas_set_info; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index ed6c781342..22f5c70f39 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -35,6 +35,13 @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc =3D value; } =20 +static vaddr cris_cpu_get_pc(CPUState *cs) +{ + CRISCPU *cpu =3D CRIS_CPU(cs); + + return cpu->env.pc; +} + static bool cris_cpu_has_work(CPUState *cs) { return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI= ); @@ -297,6 +304,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->has_work =3D cris_cpu_has_work; cc->dump_state =3D cris_cpu_dump_state; cc->set_pc =3D cris_cpu_set_pc; + cc->get_pc =3D cris_cpu_get_pc; cc->gdb_read_register =3D cris_cpu_gdb_read_register; cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index fa9bd702d6..04a497db5e 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -251,6 +251,13 @@ static void hexagon_cpu_set_pc(CPUState *cs, vaddr val= ue) env->gpr[HEX_REG_PC] =3D value; } =20 +static vaddr hexagon_cpu_get_pc(CPUState *cs) +{ + HexagonCPU *cpu =3D HEXAGON_CPU(cs); + CPUHexagonState *env =3D &cpu->env; + return env->gpr[HEX_REG_PC]; +} + static void hexagon_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -337,6 +344,7 @@ static void hexagon_cpu_class_init(ObjectClass *c, void= *data) cc->has_work =3D hexagon_cpu_has_work; cc->dump_state =3D hexagon_dump_state; cc->set_pc =3D hexagon_cpu_set_pc; + cc->get_pc =3D hexagon_cpu_get_pc; cc->gdb_read_register =3D hexagon_gdb_read_register; cc->gdb_write_register =3D hexagon_gdb_write_register; cc->gdb_num_core_regs =3D TOTAL_PER_THREAD_REGS + NUM_VREGS + NUM_QREG= S; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index a6f52caf14..e25d3db6d5 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -36,6 +36,13 @@ static void hppa_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.iaoq_b =3D value + 4; } =20 +static vaddr hppa_cpu_get_pc(CPUState *cs) +{ + HPPACPU *cpu =3D HPPA_CPU(cs); + + return cpu->env.iaoq_f; +} + static void hppa_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -168,6 +175,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->has_work =3D hppa_cpu_has_work; cc->dump_state =3D hppa_cpu_dump_state; cc->set_pc =3D hppa_cpu_set_pc; + cc->get_pc =3D hppa_cpu_get_pc; cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1db1278a59..ad623d91e4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6824,6 +6824,14 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.eip =3D value; } =20 +static vaddr x86_cpu_get_pc(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + + /* Match cpu_get_tb_cpu_state. */ + return cpu->env.eip + cpu->env.segs[R_CS].base; +} + int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) { X86CPU *cpu =3D X86_CPU(cs); @@ -7106,6 +7114,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->has_work =3D x86_cpu_has_work; cc->dump_state =3D x86_cpu_dump_state; cc->set_pc =3D x86_cpu_set_pc; + cc->get_pc =3D x86_cpu_get_pc; cc->gdb_read_register =3D x86_cpu_gdb_read_register; cc->gdb_write_register =3D x86_cpu_gdb_write_register; cc->get_arch_id =3D x86_cpu_get_arch_id; diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 941e2772bc..20a92ea56c 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -82,6 +82,14 @@ static void loongarch_cpu_set_pc(CPUState *cs, vaddr val= ue) env->pc =3D value; } =20 +static vaddr loongarch_cpu_get_pc(CPUState *cs) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + CPULoongArchState *env =3D &cpu->env; + + return env->pc; +} + #ifndef CONFIG_USER_ONLY #include "hw/loongarch/virt.h" =20 @@ -680,6 +688,7 @@ static void loongarch_cpu_class_init(ObjectClass *c, vo= id *data) cc->has_work =3D loongarch_cpu_has_work; cc->dump_state =3D loongarch_cpu_dump_state; cc->set_pc =3D loongarch_cpu_set_pc; + cc->get_pc =3D loongarch_cpu_get_pc; #ifndef CONFIG_USER_ONLY dc->vmsd =3D &vmstate_loongarch_cpu; cc->sysemu_ops =3D &loongarch_sysemu_ops; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 25d610db21..1e902e1ef0 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -31,6 +31,13 @@ static void m68k_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc =3D value; } =20 +static vaddr m68k_cpu_get_pc(CPUState *cs) +{ + M68kCPU *cpu =3D M68K_CPU(cs); + + return cpu->env.pc; +} + static bool m68k_cpu_has_work(CPUState *cs) { return cs->interrupt_request & CPU_INTERRUPT_HARD; @@ -540,6 +547,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->has_work =3D m68k_cpu_has_work; cc->dump_state =3D m68k_cpu_dump_state; cc->set_pc =3D m68k_cpu_set_pc; + cc->get_pc =3D m68k_cpu_get_pc; cc->gdb_read_register =3D m68k_cpu_gdb_read_register; cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index aed200dcff..73af51769e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -84,6 +84,13 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.iflags =3D 0; } =20 +static vaddr mb_cpu_get_pc(CPUState *cs) +{ + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + + return cpu->env.pc; +} + static void mb_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -391,6 +398,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) =20 cc->dump_state =3D mb_cpu_dump_state; cc->set_pc =3D mb_cpu_set_pc; + cc->get_pc =3D mb_cpu_get_pc; cc->gdb_read_register =3D mb_cpu_gdb_read_register; cc->gdb_write_register =3D mb_cpu_gdb_write_register; =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index c15c955367..da58eb8892 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -128,6 +128,13 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value) mips_env_set_pc(&cpu->env, value); } =20 +static vaddr mips_cpu_get_pc(CPUState *cs) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + + return cpu->env.active_tc.PC; +} + static bool mips_cpu_has_work(CPUState *cs) { MIPSCPU *cpu =3D MIPS_CPU(cs); @@ -557,6 +564,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->has_work =3D mips_cpu_has_work; cc->dump_state =3D mips_cpu_dump_state; cc->set_pc =3D mips_cpu_set_pc; + cc->get_pc =3D mips_cpu_get_pc; cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 19b2409974..2b28429c08 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -34,6 +34,14 @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value) env->pc =3D value; } =20 +static vaddr nios2_cpu_get_pc(CPUState *cs) +{ + Nios2CPU *cpu =3D NIOS2_CPU(cs); + CPUNios2State *env =3D &cpu->env; + + return env->pc; +} + static bool nios2_cpu_has_work(CPUState *cs) { return cs->interrupt_request & CPU_INTERRUPT_HARD; @@ -362,6 +370,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->has_work =3D nios2_cpu_has_work; cc->dump_state =3D nios2_cpu_dump_state; cc->set_pc =3D nios2_cpu_set_pc; + cc->get_pc =3D nios2_cpu_get_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &nios2_sysemu_ops; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index cb9f35f408..33cf717210 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -31,6 +31,13 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr valu= e) cpu->env.dflag =3D 0; } =20 +static vaddr openrisc_cpu_get_pc(CPUState *cs) +{ + OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); + + return cpu->env.pc; +} + static void openrisc_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -218,6 +225,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->has_work =3D openrisc_cpu_has_work; cc->dump_state =3D openrisc_cpu_dump_state; cc->set_pc =3D openrisc_cpu_set_pc; + cc->get_pc =3D openrisc_cpu_get_pc; cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 6e080ebda0..763a8431be 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7214,6 +7214,13 @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.nip =3D value; } =20 +static vaddr ppc_cpu_get_pc(CPUState *cs) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + + return cpu->env.nip; +} + static bool ppc_cpu_has_work(CPUState *cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); @@ -7472,6 +7479,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void = *data) cc->has_work =3D ppc_cpu_has_work; cc->dump_state =3D ppc_cpu_dump_state; cc->set_pc =3D ppc_cpu_set_pc; + cc->get_pc =3D ppc_cpu_get_pc; cc->gdb_read_register =3D ppc_cpu_gdb_read_register; cc->gdb_write_register =3D ppc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b29c88b9f0..6ca05c6eaf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -462,6 +462,18 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value) } } =20 +static vaddr riscv_cpu_get_pc(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + + /* Match cpu_get_tb_cpu_state. */ + if (env->xl =3D=3D MXL_RV32) { + return env->pc & UINT32_MAX; + } + return env->pc; +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -1154,6 +1166,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) cc->has_work =3D riscv_cpu_has_work; cc->dump_state =3D riscv_cpu_dump_state; cc->set_pc =3D riscv_cpu_set_pc; + cc->get_pc =3D riscv_cpu_get_pc; cc->gdb_read_register =3D riscv_cpu_gdb_read_register; cc->gdb_write_register =3D riscv_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 33; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index fb30080ac4..134b4b6bb6 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -32,6 +32,13 @@ static void rx_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc =3D value; } =20 +static vaddr rx_cpu_get_pc(CPUState *cs) +{ + RXCPU *cpu =3D RX_CPU(cs); + + return cpu->env.pc; +} + static void rx_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -208,6 +215,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) cc->has_work =3D rx_cpu_has_work; cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; + cc->get_pc =3D rx_cpu_get_pc; =20 #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &rx_sysemu_ops; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index c31bb2351f..df00040e95 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -88,6 +88,13 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.psw.addr =3D value; } =20 +static vaddr s390_cpu_get_pc(CPUState *cs) +{ + S390CPU *cpu =3D S390_CPU(cs); + + return cpu->env.psw.addr; +} + static bool s390_cpu_has_work(CPUState *cs) { S390CPU *cpu =3D S390_CPU(cs); @@ -297,6 +304,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->has_work =3D s390_cpu_has_work; cc->dump_state =3D s390_cpu_dump_state; cc->set_pc =3D s390_cpu_set_pc; + cc->get_pc =3D s390_cpu_get_pc; cc->gdb_read_register =3D s390_cpu_gdb_read_register; cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 06b2691dc4..4bafbf8596 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -34,6 +34,13 @@ static void superh_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc =3D value; } =20 +static vaddr superh_cpu_get_pc(CPUState *cs) +{ + SuperHCPU *cpu =3D SUPERH_CPU(cs); + + return cpu->env.pc; +} + static void superh_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -261,6 +268,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->has_work =3D superh_cpu_has_work; cc->dump_state =3D superh_cpu_dump_state; cc->set_pc =3D superh_cpu_set_pc; + cc->get_pc =3D superh_cpu_get_pc; cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 55268ed2a1..1b2afb0cb8 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -693,6 +693,13 @@ static void sparc_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.npc =3D value + 4; } =20 +static vaddr sparc_cpu_get_pc(CPUState *cs) +{ + SPARCCPU *cpu =3D SPARC_CPU(cs); + + return cpu->env.pc; +} + static void sparc_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -896,6 +903,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->memory_rw_debug =3D sparc_cpu_memory_rw_debug; #endif cc->set_pc =3D sparc_cpu_set_pc; + cc->get_pc =3D sparc_cpu_get_pc; cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index b95682b7f0..91b16bdefc 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -41,6 +41,14 @@ static void tricore_cpu_set_pc(CPUState *cs, vaddr value) env->PC =3D value & ~(target_ulong)1; } =20 +static vaddr tricore_cpu_get_pc(CPUState *cs) +{ + TriCoreCPU *cpu =3D TRICORE_CPU(cs); + CPUTriCoreState *env =3D &cpu->env; + + return env->PC; +} + static void tricore_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -176,6 +184,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) =20 cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; + cc->get_pc =3D tricore_cpu_get_pc; cc->sysemu_ops =3D &tricore_sysemu_ops; cc->tcg_ops =3D &tricore_tcg_ops; } diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index fd553fdfb5..cbbe0e84a2 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -44,6 +44,13 @@ static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc =3D value; } =20 +static vaddr xtensa_cpu_get_pc(CPUState *cs) +{ + XtensaCPU *cpu =3D XTENSA_CPU(cs); + + return cpu->env.pc; +} + static bool xtensa_cpu_has_work(CPUState *cs) { #ifndef CONFIG_USER_ONLY @@ -233,6 +240,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->has_work =3D xtensa_cpu_has_work; cc->dump_state =3D xtensa_cpu_dump_state; cc->set_pc =3D xtensa_cpu_set_pc; + cc->get_pc =3D xtensa_cpu_get_pc; cc->gdb_read_register =3D xtensa_cpu_gdb_read_register; cc->gdb_write_register =3D xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint =3D true; --=20 2.34.1 From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664915822; cv=none; d=zohomail.com; s=zohoarc; b=D8Nlc0omtYfE1WJH67vvJqgSlu21RGiBRQiPwGJ4BptevfVI2QmWGEzqqU7rtVCWmpJYIeoChBshsBsXbysRBKGkgWUZdbes4yodCBEd6gBDTvu05E0Zzq8MdFScbRmvc4mXdgMIA9XKQJ9GC3DU0KH8a+AvRSfUn7T0vKGF2Rg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664915822; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cdtAd+otCm47XoYCpODE7wQ+CTvzqkJ4M8W/26HxxK0=; b=egI+XAA7jYRQpxOVLwFyUyM8vNQk0SVaJ2O18gmliix1k/VBJAaoZ1cRL1UJ498LJtJb0WXNhwUawo1KjodebKH7NuBfWzK7cxcPoF8vwmRJDL9Z727W0d0QY7FV2+CKXIoJFPqEt9q1QwPYL2yXzac5T/EXb8r83k+V/H6tOng= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664915821992594.4770337528714; Tue, 4 Oct 2022 13:37:01 -0700 (PDT) Received: from localhost ([::1]:59870 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofoey-0006NZ-NE for importer@patchew.org; Tue, 04 Oct 2022 16:37:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51630) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyT-0002D4-Rb for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:53:06 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:37729) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofnyQ-0000If-3S for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:53:05 -0400 Received: by mail-pg1-x536.google.com with SMTP id bh13so13552442pgb.4 for ; Tue, 04 Oct 2022 12:53:01 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.52.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:52:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=cdtAd+otCm47XoYCpODE7wQ+CTvzqkJ4M8W/26HxxK0=; b=UtPLoUaCkK49syDrV68gmbPb7seON19qBOvff5d3OBeh1V3oixRx/xaG0a6ImztQ9u o+AAi+N83PELWhrRw7BpXpbySFZtae3kHSiwcY/11akoHkKuOEanttGlyKYR/Htze//q 3JdghFsJY3/ops979QbCU2FxfhQ00vt7X1GvLfu41D6vdgqxXXZwcLiEQVKUWru2i1Uu 6EBUFlhBAKzYFAxysejop+szJcJOsG5HYaNLO/El/AwamNhwkz8yOSKaCTwK73sYWEjQ sabbdpsYhJPrQHRlTq4QMDnmHEm9K8uuDQyh4XBlH9pFTwP4plC1rU4dulzjy1f3oY9X cr5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=cdtAd+otCm47XoYCpODE7wQ+CTvzqkJ4M8W/26HxxK0=; b=ym9cA4MkczLZFwZEYYgKrz47IKtENi9wayZ2fgv27Br60TINSFVOQXrdCpZvMkIhdm Ds6NLZEGueR+tmyl9FpWRY7+OCqkhGtuBx1WAqy3tiicy0PSa2sijIk+RhFjyrgGfTvy 7rWkwjZF0tHiSZ/PrRQd/8kOGIO9YN5X/C/g3aZ053//8BoU7BXrvcYrwSRtKa6eFQQu VR9IE9J+rLM8LH9Paa7pRNkqP7hhSv7kAcfqU/eV0iRRp5t12bWGV3A0GxeXVdiRD+Lj VFsU9KeNLiBn1+Gemx1MV83puppeGflIDdibweKheuNTDRGWXNjHpRyTDfQw0DvkPIBB d1fQ== X-Gm-Message-State: ACrzQf1hWtyrCT75vlBI2vqCEYunUgjGe1gk32gTA7/iFosKWpLuZ9Yg X6iiZde4prOENDxi5bEPZ6vqLMxVl/yW2A== X-Google-Smtp-Source: AMsMyM6g9rK51/PrLSXbg2YYs7JnkMebf2dWuXgWP7YltJ/OfdXVTJ6spnAYc6e+LjfEIyVKy+AOYw== X-Received: by 2002:a63:f709:0:b0:44f:6cba:3a4f with SMTP id x9-20020a63f709000000b0044f6cba3a4fmr9759454pgh.428.1664913180419; Tue, 04 Oct 2022 12:53:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 17/20] accel/tcg: Introduce tb_pc and log_pc Date: Tue, 4 Oct 2022 12:52:38 -0700 Message-Id: <20221004195241.46491-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664915823992100001 The availability of tb->pc will shortly be conditional. Introduce accessor functions to minimize ifdefs. Pass around a known pc to places like tcg_gen_code, where the caller must already have the value. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/internal.h | 6 ++++ include/exec/exec-all.h | 6 ++++ include/tcg/tcg.h | 2 +- accel/tcg/cpu-exec.c | 46 ++++++++++++++----------- accel/tcg/translate-all.c | 37 +++++++++++--------- target/arm/cpu.c | 4 +-- target/avr/cpu.c | 2 +- target/hexagon/cpu.c | 2 +- target/hppa/cpu.c | 4 +-- target/i386/tcg/tcg-cpu.c | 2 +- target/loongarch/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/tcg/exception.c | 2 +- target/mips/tcg/sysemu/special_helper.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 4 +-- target/rx/cpu.c | 2 +- target/sh4/cpu.c | 4 +-- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- tcg/tcg.c | 8 ++--- 21 files changed, 82 insertions(+), 61 deletions(-) diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h index 3092bfa964..a3875a3b5a 100644 --- a/accel/tcg/internal.h +++ b/accel/tcg/internal.h @@ -18,4 +18,10 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_= t retaddr); void page_init(void); void tb_htable_init(void); =20 +/* Return the current PC from CPU, which may be cached in TB. */ +static inline target_ulong log_pc(CPUState *cpu, const TranslationBlock *t= b) +{ + return tb_pc(tb); +} + #endif /* ACCEL_TCG_INTERNAL_H */ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index b1b920a713..7ea6026ba9 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -570,6 +570,12 @@ struct TranslationBlock { uintptr_t jmp_dest[2]; }; =20 +/* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */ +static inline target_ulong tb_pc(const TranslationBlock *tb) +{ + return tb->pc; +} + /* Hide the qatomic_read to make code a little easier on the eyes */ static inline uint32_t tb_cflags(const TranslationBlock *tb) { diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 26a70526f1..d84bae6e3f 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -840,7 +840,7 @@ void tcg_register_thread(void); void tcg_prologue_init(TCGContext *s); void tcg_func_start(TCGContext *s); =20 -int tcg_gen_code(TCGContext *s, TranslationBlock *tb); +int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_star= t); =20 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t siz= e); =20 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 2d7e610ee2..8b3f8435fb 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -186,7 +186,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) const TranslationBlock *tb =3D p; const struct tb_desc *desc =3D d; =20 - if (tb->pc =3D=3D desc->pc && + if (tb_pc(tb) =3D=3D desc->pc && tb->page_addr[0] =3D=3D desc->page_addr0 && tb->cs_base =3D=3D desc->cs_base && tb->flags =3D=3D desc->flags && @@ -271,12 +271,10 @@ static inline TranslationBlock *tb_lookup(CPUState *c= pu, target_ulong pc, return tb; } =20 -static inline void log_cpu_exec(target_ulong pc, CPUState *cpu, - const TranslationBlock *tb) +static void log_cpu_exec(target_ulong pc, CPUState *cpu, + const TranslationBlock *tb) { - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) - && qemu_log_in_addr_range(pc)) { - + if (qemu_log_in_addr_range(pc)) { qemu_log_mask(CPU_LOG_EXEC, "Trace %d: %p [" TARGET_FMT_lx "/" TARGET_FMT_lx "/%08x/%08x] %s\n", @@ -400,7 +398,9 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) return tcg_code_gen_epilogue; } =20 - log_cpu_exec(pc, cpu, tb); + if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) { + log_cpu_exec(pc, cpu, tb); + } =20 return tb->tc.ptr; } @@ -423,7 +423,9 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *= tb_exit) TranslationBlock *last_tb; const void *tb_ptr =3D itb->tc.ptr; =20 - log_cpu_exec(itb->pc, cpu, itb); + if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) { + log_cpu_exec(log_pc(cpu, itb), cpu, itb); + } =20 qemu_thread_jit_execute(); ret =3D tcg_qemu_tb_exec(env, tb_ptr); @@ -447,16 +449,20 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int= *tb_exit) * of the start of the TB. */ CPUClass *cc =3D CPU_GET_CLASS(cpu); - qemu_log_mask_and_addr(CPU_LOG_EXEC, last_tb->pc, - "Stopped execution of TB chain before %p [" - TARGET_FMT_lx "] %s\n", - last_tb->tc.ptr, last_tb->pc, - lookup_symbol(last_tb->pc)); + if (cc->tcg_ops->synchronize_from_tb) { cc->tcg_ops->synchronize_from_tb(cpu, last_tb); } else { assert(cc->set_pc); - cc->set_pc(cpu, last_tb->pc); + cc->set_pc(cpu, tb_pc(last_tb)); + } + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + target_ulong pc =3D log_pc(cpu, last_tb); + if (qemu_log_in_addr_range(pc)) { + qemu_log("Stopped execution of TB chain before %p [" + TARGET_FMT_lx "] %s\n", + last_tb->tc.ptr, pc, lookup_symbol(pc)); + } } } =20 @@ -598,11 +604,8 @@ static inline void tb_add_jump(TranslationBlock *tb, i= nt n, =20 qemu_spin_unlock(&tb_next->jmp_lock); =20 - qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, - "Linking TBs %p [" TARGET_FMT_lx - "] index %d -> %p [" TARGET_FMT_lx "]\n", - tb->tc.ptr, tb->pc, n, - tb_next->tc.ptr, tb_next->pc); + qemu_log_mask(CPU_LOG_EXEC, "Linking TBs %p index %d -> %p\n", + tb->tc.ptr, n, tb_next->tc.ptr); return; =20 out_unlock_next: @@ -848,11 +851,12 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, } =20 static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, + target_ulong pc, TranslationBlock **last_tb, int *tb_ex= it) { int32_t insns_left; =20 - trace_exec_tb(tb, tb->pc); + trace_exec_tb(tb, pc); tb =3D cpu_tb_exec(cpu, tb, tb_exit); if (*tb_exit !=3D TB_EXIT_REQUESTED) { *last_tb =3D tb; @@ -1017,7 +1021,7 @@ int cpu_exec(CPUState *cpu) tb_add_jump(last_tb, tb_exit, tb); } =20 - cpu_loop_exec_tb(cpu, tb, &last_tb, &tb_exit); + cpu_loop_exec_tb(cpu, tb, pc, &last_tb, &tb_exit); =20 /* Try to align the host and virtual clocks if the guest is in advance */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 63ecc15236..13c964dcd8 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -299,7 +299,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) =20 for (j =3D 0; j < TARGET_INSN_START_WORDS; ++j) { if (i =3D=3D 0) { - prev =3D (j =3D=3D 0 ? tb->pc : 0); + prev =3D (j =3D=3D 0 ? tb_pc(tb) : 0); } else { prev =3D tcg_ctx->gen_insn_data[i - 1][j]; } @@ -327,7 +327,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t searched_pc, bool reset_ico= unt) { - target_ulong data[TARGET_INSN_START_WORDS] =3D { tb->pc }; + target_ulong data[TARGET_INSN_START_WORDS] =3D { tb_pc(tb) }; uintptr_t host_pc =3D (uintptr_t)tb->tc.ptr; CPUArchState *env =3D cpu->env_ptr; const uint8_t *p =3D tb->tc.ptr + tb->tc.size; @@ -885,7 +885,7 @@ static bool tb_cmp(const void *ap, const void *bp) const TranslationBlock *a =3D ap; const TranslationBlock *b =3D bp; =20 - return a->pc =3D=3D b->pc && + return tb_pc(a) =3D=3D tb_pc(b) && a->cs_base =3D=3D b->cs_base && a->flags =3D=3D b->flags && (tb_cflags(a) & ~CF_INVALID) =3D=3D (tb_cflags(b) & ~CF_INVALID) && @@ -1013,9 +1013,10 @@ static void do_tb_invalidate_check(void *p, uint32_t= hash, void *userp) TranslationBlock *tb =3D p; target_ulong addr =3D *(target_ulong *)userp; =20 - if (!(addr + TARGET_PAGE_SIZE <=3D tb->pc || addr >=3D tb->pc + tb->si= ze)) { + if (!(addr + TARGET_PAGE_SIZE <=3D tb_pc(tb) || + addr >=3D tb_pc(tb) + tb->size)) { printf("ERROR invalidate: address=3D" TARGET_FMT_lx - " PC=3D%08lx size=3D%04x\n", addr, (long)tb->pc, tb->size); + " PC=3D%08lx size=3D%04x\n", addr, (long)tb_pc(tb), tb->siz= e); } } =20 @@ -1034,11 +1035,11 @@ static void do_tb_page_check(void *p, uint32_t hash= , void *userp) TranslationBlock *tb =3D p; int flags1, flags2; =20 - flags1 =3D page_get_flags(tb->pc); - flags2 =3D page_get_flags(tb->pc + tb->size - 1); + flags1 =3D page_get_flags(tb_pc(tb)); + flags2 =3D page_get_flags(tb_pc(tb) + tb->size - 1); if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { printf("ERROR page flags: PC=3D%08lx size=3D%04x f1=3D%x f2=3D%x\n= ", - (long)tb->pc, tb->size, flags1, flags2); + (long)tb_pc(tb), tb->size, flags1, flags2); } } =20 @@ -1169,7 +1170,7 @@ static void do_tb_phys_invalidate(TranslationBlock *t= b, bool rm_from_page_list) =20 /* remove the TB from the hash list */ phys_pc =3D tb->page_addr[0]; - h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags, + h =3D tb_hash_func(phys_pc, tb_pc(tb), tb->flags, orig_cflags, tb->trace_vcpu_dstate); if (!qht_remove(&tb_ctx.htable, tb, h)) { return; @@ -1301,7 +1302,7 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phy= s_pc, } =20 /* add in the hash table */ - h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags, + h =3D tb_hash_func(phys_pc, tb_pc(tb), tb->flags, tb->cflags, tb->trace_vcpu_dstate); qht_insert(&tb_ctx.htable, tb, h, &existing_tb); =20 @@ -1401,7 +1402,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->cpu =3D NULL; max_insns =3D tb->icount; =20 - trace_translate_block(tb, tb->pc, tb->tc.ptr); + trace_translate_block(tb, pc, tb->tc.ptr); =20 /* generate machine code */ tb->jmp_reset_offset[0] =3D TB_JMP_RESET_OFFSET_INVALID; @@ -1422,7 +1423,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, ti =3D profile_getclock(); #endif =20 - gen_code_size =3D tcg_gen_code(tcg_ctx, tb); + gen_code_size =3D tcg_gen_code(tcg_ctx, tb, pc); if (unlikely(gen_code_size < 0)) { error_return: switch (gen_code_size) { @@ -1478,7 +1479,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, =20 #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) && - qemu_log_in_addr_range(tb->pc)) { + qemu_log_in_addr_range(pc)) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { int code_size, data_size; @@ -1918,9 +1919,13 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retad= dr) */ cpu->cflags_next_tb =3D curr_cflags(cpu) | CF_MEMI_ONLY | CF_LAST_IO |= n; =20 - qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, - "cpu_io_recompile: rewound execution of TB to " - TARGET_FMT_lx "\n", tb->pc); + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + target_ulong pc =3D log_pc(cpu, tb); + if (qemu_log_in_addr_range(pc)) { + qemu_log("cpu_io_recompile: rewound execution of TB to " + TARGET_FMT_lx "\n", pc); + } + } =20 cpu_loop_exit_noexc(cpu); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index fa67ba6647..94ca6f163f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -84,9 +84,9 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, * never possible for an AArch64 TB to chain to an AArch32 TB. */ if (is_a64(env)) { - env->pc =3D tb->pc; + env->pc =3D tb_pc(tb); } else { - env->regs[15] =3D tb->pc; + env->regs[15] =3D tb_pc(tb); } } #endif /* CONFIG_TCG */ diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 6900444d03..0d2861179d 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -54,7 +54,7 @@ static void avr_cpu_synchronize_from_tb(CPUState *cs, AVRCPU *cpu =3D AVR_CPU(cs); CPUAVRState *env =3D &cpu->env; =20 - env->pc_w =3D tb->pc / 2; /* internally PC points to words */ + env->pc_w =3D tb_pc(tb) / 2; /* internally PC points to words */ } =20 static void avr_cpu_reset(DeviceState *ds) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 04a497db5e..fa6d722555 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -263,7 +263,7 @@ static void hexagon_cpu_synchronize_from_tb(CPUState *c= s, { HexagonCPU *cpu =3D HEXAGON_CPU(cs); CPUHexagonState *env =3D &cpu->env; - env->gpr[HEX_REG_PC] =3D tb->pc; + env->gpr[HEX_REG_PC] =3D tb_pc(tb); } =20 static bool hexagon_cpu_has_work(CPUState *cs) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index e25d3db6d5..e677ca09d4 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -49,7 +49,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, HPPACPU *cpu =3D HPPA_CPU(cs); =20 #ifdef CONFIG_USER_ONLY - cpu->env.iaoq_f =3D tb->pc; + cpu->env.iaoq_f =3D tb_pc(tb); cpu->env.iaoq_b =3D tb->cs_base; #else /* Recover the IAOQ values from the GVA + PRIV. */ @@ -59,7 +59,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, int32_t diff =3D cs_base; =20 cpu->env.iasq_f =3D iasq_f; - cpu->env.iaoq_f =3D (tb->pc & ~iasq_f) + priv; + cpu->env.iaoq_f =3D (tb_pc(tb) & ~iasq_f) + priv; if (diff) { cpu->env.iaoq_b =3D cpu->env.iaoq_f + diff; } diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index d3c2b8fb49..6cf14c83ff 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -51,7 +51,7 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, { X86CPU *cpu =3D X86_CPU(cs); =20 - cpu->env.eip =3D tb->pc - tb->cs_base; + cpu->env.eip =3D tb_pc(tb) - tb->cs_base; } =20 #ifndef CONFIG_USER_ONLY diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 20a92ea56c..1722ed2a4d 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -317,7 +317,7 @@ static void loongarch_cpu_synchronize_from_tb(CPUState = *cs, LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); CPULoongArchState *env =3D &cpu->env; =20 - env->pc =3D tb->pc; + env->pc =3D tb_pc(tb); } #endif /* CONFIG_TCG */ =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 73af51769e..c10b8ac029 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -96,7 +96,7 @@ static void mb_cpu_synchronize_from_tb(CPUState *cs, { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); =20 - cpu->env.pc =3D tb->pc; + cpu->env.pc =3D tb_pc(tb); cpu->env.iflags =3D tb->flags & IFLAGS_TB_MASK; } =20 diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c index 2bd77a61de..96e61170e6 100644 --- a/target/mips/tcg/exception.c +++ b/target/mips/tcg/exception.c @@ -82,7 +82,7 @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const Tra= nslationBlock *tb) MIPSCPU *cpu =3D MIPS_CPU(cs); CPUMIPSState *env =3D &cpu->env; =20 - env->active_tc.PC =3D tb->pc; + env->active_tc.PC =3D tb_pc(tb); env->hflags &=3D ~MIPS_HFLAG_BMASK; env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; } diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/syse= mu/special_helper.c index f4f8fe8afc..3c5f35c759 100644 --- a/target/mips/tcg/sysemu/special_helper.c +++ b/target/mips/tcg/sysemu/special_helper.c @@ -94,7 +94,7 @@ bool mips_io_recompile_replay_branch(CPUState *cs, const = TranslationBlock *tb) CPUMIPSState *env =3D &cpu->env; =20 if ((env->hflags & MIPS_HFLAG_BMASK) !=3D 0 - && env->active_tc.PC !=3D tb->pc) { + && env->active_tc.PC !=3D tb_pc(tb)) { env->active_tc.PC -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); env->hflags &=3D ~MIPS_HFLAG_BMASK; return true; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 33cf717210..f6fd437785 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -43,7 +43,7 @@ static void openrisc_cpu_synchronize_from_tb(CPUState *cs, { OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); =20 - cpu->env.pc =3D tb->pc; + cpu->env.pc =3D tb_pc(tb); } =20 =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6ca05c6eaf..e6d9c706bb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -482,9 +482,9 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); =20 if (xl =3D=3D MXL_RV32) { - env->pc =3D (int32_t)tb->pc; + env->pc =3D (int32_t)tb_pc(tb); } else { - env->pc =3D tb->pc; + env->pc =3D tb_pc(tb); } } =20 diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 134b4b6bb6..2f28099723 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -44,7 +44,7 @@ static void rx_cpu_synchronize_from_tb(CPUState *cs, { RXCPU *cpu =3D RX_CPU(cs); =20 - cpu->env.pc =3D tb->pc; + cpu->env.pc =3D tb_pc(tb); } =20 static bool rx_cpu_has_work(CPUState *cs) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 4bafbf8596..a65a66de43 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -46,7 +46,7 @@ static void superh_cpu_synchronize_from_tb(CPUState *cs, { SuperHCPU *cpu =3D SUPERH_CPU(cs); =20 - cpu->env.pc =3D tb->pc; + cpu->env.pc =3D tb_pc(tb); cpu->env.flags =3D tb->flags & TB_FLAG_ENVFLAGS_MASK; } =20 @@ -58,7 +58,7 @@ static bool superh_io_recompile_replay_branch(CPUState *c= s, CPUSH4State *env =3D &cpu->env; =20 if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) !=3D 0 - && env->pc !=3D tb->pc) { + && env->pc !=3D tb_pc(tb)) { env->pc -=3D 2; env->flags &=3D ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); return true; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 1b2afb0cb8..1f9ef7afd8 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -705,7 +705,7 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, { SPARCCPU *cpu =3D SPARC_CPU(cs); =20 - cpu->env.pc =3D tb->pc; + cpu->env.pc =3D tb_pc(tb); cpu->env.npc =3D tb->cs_base; } =20 diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 91b16bdefc..ab7a1e3a6d 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -55,7 +55,7 @@ static void tricore_cpu_synchronize_from_tb(CPUState *cs, TriCoreCPU *cpu =3D TRICORE_CPU(cs); CPUTriCoreState *env =3D &cpu->env; =20 - env->PC =3D tb->pc; + env->PC =3D tb_pc(tb); } =20 static void tricore_cpu_reset(DeviceState *dev) diff --git a/tcg/tcg.c b/tcg/tcg.c index 0f9cfe96f2..612a12f58f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -4188,7 +4188,7 @@ int64_t tcg_cpu_exec_time(void) #endif =20 =20 -int tcg_gen_code(TCGContext *s, TranslationBlock *tb) +int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_star= t) { #ifdef CONFIG_PROFILER TCGProfile *prof =3D &s->prof; @@ -4218,7 +4218,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) =20 #ifdef DEBUG_DISAS if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP) - && qemu_log_in_addr_range(tb->pc))) { + && qemu_log_in_addr_range(pc_start))) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { fprintf(logfile, "OP:\n"); @@ -4265,7 +4265,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) if (s->nb_indirects > 0) { #ifdef DEBUG_DISAS if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND) - && qemu_log_in_addr_range(tb->pc))) { + && qemu_log_in_addr_range(pc_start))) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { fprintf(logfile, "OP before indirect lowering:\n"); @@ -4288,7 +4288,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) =20 #ifdef DEBUG_DISAS if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT) - && qemu_log_in_addr_range(tb->pc))) { + && qemu_log_in_addr_range(pc_start))) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { fprintf(logfile, "OP after optimization and liveness analysis:= \n"); --=20 2.34.1 From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664915108; cv=none; d=zohomail.com; s=zohoarc; b=ORLfvyZgXVyR18NlOdXDgAR2I39e0SR2D5h8IkFeivFiL6lkipEura0vFljScbf/5YrD8/YkUGvhsD7uZEFybCO5Y8S/jNfJoobXfy9Yq0MtiLSo2rA64AiQkB7PmMQW8oSQn5kVj2E7EDRiYsq52ecMzxu7FSQw6hPu8JPAaQY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664915108; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GMseGoEdHDZJo9qfpjf4QS3EDnkmn8Necr0EbekFMeI=; b=Gns/RNT37CdXb3oNZNq7Srk2D0fLmi+Z+z4YyF4Ii/Cv+ZjquHYovlFDAW2qKBvC5I/8HxT3ekgzFKmsuLWQQuhcXqCYLelednmH+MdqGOUFLswstk4f8syGJ61GVe86MnYXur+AHMgi98x2nbsfE6IrJUcz5q3ETQpDmvepCBY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664915108120989.8356380877281; Tue, 4 Oct 2022 13:25:08 -0700 (PDT) Received: from localhost ([::1]:49344 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofoTR-0002kO-Qo for importer@patchew.org; Tue, 04 Oct 2022 16:25:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49336) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyT-0002CF-HL for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:53:05 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:43951) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofnyR-0000Is-4O for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:53:05 -0400 Received: by mail-pl1-x630.google.com with SMTP id z20so7029625plb.10 for ; Tue, 04 Oct 2022 12:53:02 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.53.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:53:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=GMseGoEdHDZJo9qfpjf4QS3EDnkmn8Necr0EbekFMeI=; b=NoMJ2No5sV2obLb+6Q1NhcIFmxNiVAv1shh/ao5lVROGp+UvtfJQqMgpFe/aq7zrVc LAB3DwflpNwK6nLjtzrx9ZXAgxXbFfCX+iveUnhAjgmB/56UAV6PLgxtKNE2ppbIPoWX JtHQ0UNsq0xvBgLCeRUF1WZLfYYv+aXeY97gBtYZgr9T59Zv/CH8HKflz25PHo9nB9wE 7D8b7VNnXCA0asWRmjQGa0oE3fpr5ai/a9FtBvR6RuGJ9fxDA4kylf2ukWKD5GQxFL58 jydwzzoUtgy9o+CVa6aWSW3nLWqyi9nXiEZ2zX/Rv+P05AltD4G1eOjyCDCBxa/M347O UmGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=GMseGoEdHDZJo9qfpjf4QS3EDnkmn8Necr0EbekFMeI=; b=cxVN8zLcyCoHWwUSrrY9fsw4s4WJemn0BxJ6Y5X/+CSQN2yQ5utxcVHKeLDkSqvT/U CgGaHaop4/yhhF93rUMXxAgRnvJzrkBsRb1U8Bfbp70xZUFKRjSIKlGz3dwpfqFSDujS dA9XZxpEm80wxc9zxdDJduRiC/sfjcMn4N8iHVMFyHTCiSskSGOFdbzSRPpVubumZRNR 0bAZ74nhsoqL0koOA6SdrhoH0eHxWGhyTzz76LypAM5BOeyo3ccxOq9YMLp2TIbjUdf6 C+9MxD1R0nLGeL1149zxef06DlLcQQtVSGC/tFAh7qtbmqi5ekyT68JhFn79E2FmQzG5 FuqA== X-Gm-Message-State: ACrzQf2ABTqjBj10TCfqfRXb8cG4r9u3JucuBnr6aVuUDlVlxA4DFKLB a7y69paNsQOTqeZKdgTNA2Tk50tLtLBAZQ== X-Google-Smtp-Source: AMsMyM53Cv3usJCTVSB59++tyfpjk/6Cgwt4uKkv1dlsyoEUKQ+3hipVdu7AxGPUHKF9HPDW1Hnjdg== X-Received: by 2002:a17:90b:1801:b0:202:7cf6:9f93 with SMTP id lw1-20020a17090b180100b002027cf69f93mr1289953pjb.170.1664913181461; Tue, 04 Oct 2022 12:53:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 18/20] accel/tcg: Introduce TARGET_TB_PCREL Date: Tue, 4 Oct 2022 12:52:39 -0700 Message-Id: <20221004195241.46491-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664915108419100001 Prepare for targets to be able to produce TBs that can run in more than one virtual context. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/internal.h | 4 +++ accel/tcg/tb-jmp-cache.h | 41 +++++++++++++++++++++++++ include/exec/cpu-defs.h | 3 ++ include/exec/exec-all.h | 32 ++++++++++++++++++-- accel/tcg/cpu-exec.c | 16 ++++++---- accel/tcg/translate-all.c | 64 ++++++++++++++++++++++++++------------- 6 files changed, 131 insertions(+), 29 deletions(-) diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h index a3875a3b5a..dc800fd485 100644 --- a/accel/tcg/internal.h +++ b/accel/tcg/internal.h @@ -21,7 +21,11 @@ void tb_htable_init(void); /* Return the current PC from CPU, which may be cached in TB. */ static inline target_ulong log_pc(CPUState *cpu, const TranslationBlock *t= b) { +#if TARGET_TB_PCREL + return cpu->cc->get_pc(cpu); +#else return tb_pc(tb); +#endif } =20 #endif /* ACCEL_TCG_INTERNAL_H */ diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h index 2d8fbb1bfe..ff5ffc8fc2 100644 --- a/accel/tcg/tb-jmp-cache.h +++ b/accel/tcg/tb-jmp-cache.h @@ -14,11 +14,52 @@ =20 /* * Accessed in parallel; all accesses to 'tb' must be atomic. + * For TARGET_TB_PCREL, accesses to 'pc' must be protected by + * a load_acquire/store_release to 'tb'. */ struct CPUJumpCache { struct { TranslationBlock *tb; +#if TARGET_TB_PCREL + target_ulong pc; +#endif } array[TB_JMP_CACHE_SIZE]; }; =20 +static inline TranslationBlock * +tb_jmp_cache_get_tb(CPUJumpCache *jc, uint32_t hash) +{ +#if TARGET_TB_PCREL + /* Use acquire to ensure current load of pc from jc. */ + return qatomic_load_acquire(&jc->array[hash].tb); +#else + /* Use rcu_read to ensure current load of pc from *tb. */ + return qatomic_rcu_read(&jc->array[hash].tb); +#endif +} + +static inline target_ulong +tb_jmp_cache_get_pc(CPUJumpCache *jc, uint32_t hash, TranslationBlock *tb) +{ +#if TARGET_TB_PCREL + return jc->array[hash].pc; +#else + return tb_pc(tb); +#endif +} + +static inline void +tb_jmp_cache_set(CPUJumpCache *jc, uint32_t hash, + TranslationBlock *tb, target_ulong pc) +{ +#if TARGET_TB_PCREL + jc->array[hash].pc =3D pc; + /* Use store_release on tb to ensure pc is written first. */ + qatomic_store_release(&jc->array[hash].tb, tb); +#else + /* Use the pc value already stored in tb->pc. */ + qatomic_set(&jc->array[hash].tb, tb); +#endif +} + #endif /* ACCEL_TCG_TB_JMP_CACHE_H */ diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 67239b4e5e..21309cf567 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -54,6 +54,9 @@ # error TARGET_PAGE_BITS must be defined in cpu-param.h # endif #endif +#ifndef TARGET_TB_PCREL +# define TARGET_TB_PCREL 0 +#endif =20 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) =20 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 7ea6026ba9..e5f8b224a5 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -496,8 +496,32 @@ struct tb_tc { }; =20 struct TranslationBlock { - target_ulong pc; /* simulated PC corresponding to this block (EIP + = CS base) */ - target_ulong cs_base; /* CS base for this block */ +#if !TARGET_TB_PCREL + /* + * Guest PC corresponding to this block. This must be the true + * virtual address. Therefore e.g. x86 stores EIP + CS_BASE, and + * targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or + * privilege, must store those bits elsewhere. + * + * If TARGET_TB_PCREL, the opcodes for the TranslationBlock are + * written such that the TB is associated only with the physical + * page and may be run in any virtual address context. In this case, + * PC must always be taken from ENV in a target-specific manner. + * Unwind information is taken as offsets from the page, to be + * deposited into the "current" PC. + */ + target_ulong pc; +#endif + + /* + * Target-specific data associated with the TranslationBlock, e.g.: + * x86: the original user, the Code Segment virtual base, + * arm: an extension of tb->flags, + * s390x: instruction data for EXECUTE, + * sparc: the next pc of the instruction queue (for delay slots). + */ + target_ulong cs_base; + uint32_t flags; /* flags defining in which context the code was genera= ted */ uint32_t cflags; /* compile flags */ =20 @@ -573,7 +597,11 @@ struct TranslationBlock { /* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */ static inline target_ulong tb_pc(const TranslationBlock *tb) { +#if TARGET_TB_PCREL + qemu_build_not_reached(); +#else return tb->pc; +#endif } =20 /* Hide the qatomic_read to make code a little easier on the eyes */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8b3f8435fb..f9e5cc9ba0 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -186,7 +186,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) const TranslationBlock *tb =3D p; const struct tb_desc *desc =3D d; =20 - if (tb_pc(tb) =3D=3D desc->pc && + if ((TARGET_TB_PCREL || tb_pc(tb) =3D=3D desc->pc) && tb->page_addr[0] =3D=3D desc->page_addr0 && tb->cs_base =3D=3D desc->cs_base && tb->flags =3D=3D desc->flags && @@ -237,7 +237,8 @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu= , target_ulong pc, return NULL; } desc.page_addr0 =3D phys_pc; - h =3D tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate); + h =3D tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : pc), + flags, cflags, *cpu->trace_dstate); return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); } =20 @@ -247,16 +248,18 @@ static inline TranslationBlock *tb_lookup(CPUState *c= pu, target_ulong pc, uint32_t flags, uint32_t cflags) { TranslationBlock *tb; + CPUJumpCache *jc; uint32_t hash; =20 /* we should never be trying to look up an INVALID tb */ tcg_debug_assert(!(cflags & CF_INVALID)); =20 hash =3D tb_jmp_cache_hash_func(pc); - tb =3D qatomic_rcu_read(&cpu->tb_jmp_cache->array[hash].tb); + jc =3D cpu->tb_jmp_cache; + tb =3D tb_jmp_cache_get_tb(jc, hash); =20 if (likely(tb && - tb->pc =3D=3D pc && + tb_jmp_cache_get_pc(jc, hash, tb) =3D=3D pc && tb->cs_base =3D=3D cs_base && tb->flags =3D=3D flags && tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate && @@ -267,7 +270,7 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu= , target_ulong pc, if (tb =3D=3D NULL) { return NULL; } - qatomic_set(&cpu->tb_jmp_cache->array[hash].tb, tb); + tb_jmp_cache_set(jc, hash, tb, pc); return tb; } =20 @@ -453,6 +456,7 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *= tb_exit) if (cc->tcg_ops->synchronize_from_tb) { cc->tcg_ops->synchronize_from_tb(cpu, last_tb); } else { + assert(!TARGET_TB_PCREL); assert(cc->set_pc); cc->set_pc(cpu, tb_pc(last_tb)); } @@ -1002,7 +1006,7 @@ int cpu_exec(CPUState *cpu) * for the fast lookup */ h =3D tb_jmp_cache_hash_func(pc); - qatomic_set(&cpu->tb_jmp_cache->array[h].tb, tb); + tb_jmp_cache_set(cpu->tb_jmp_cache, h, tb, pc); } =20 #ifndef CONFIG_USER_ONLY diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 13c964dcd8..4ed75a13e1 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -299,7 +299,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) =20 for (j =3D 0; j < TARGET_INSN_START_WORDS; ++j) { if (i =3D=3D 0) { - prev =3D (j =3D=3D 0 ? tb_pc(tb) : 0); + prev =3D (!TARGET_TB_PCREL && j =3D=3D 0 ? tb_pc(tb) : 0); } else { prev =3D tcg_ctx->gen_insn_data[i - 1][j]; } @@ -327,7 +327,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t searched_pc, bool reset_ico= unt) { - target_ulong data[TARGET_INSN_START_WORDS] =3D { tb_pc(tb) }; + target_ulong data[TARGET_INSN_START_WORDS]; uintptr_t host_pc =3D (uintptr_t)tb->tc.ptr; CPUArchState *env =3D cpu->env_ptr; const uint8_t *p =3D tb->tc.ptr + tb->tc.size; @@ -343,6 +343,11 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tr= anslationBlock *tb, return -1; } =20 + memset(data, 0, sizeof(data)); + if (!TARGET_TB_PCREL) { + data[0] =3D tb_pc(tb); + } + /* Reconstruct the stored insn data while looking for the point at which the end of the insn exceeds the searched_pc. */ for (i =3D 0; i < num_insns; ++i) { @@ -885,13 +890,13 @@ static bool tb_cmp(const void *ap, const void *bp) const TranslationBlock *a =3D ap; const TranslationBlock *b =3D bp; =20 - return tb_pc(a) =3D=3D tb_pc(b) && - a->cs_base =3D=3D b->cs_base && - a->flags =3D=3D b->flags && - (tb_cflags(a) & ~CF_INVALID) =3D=3D (tb_cflags(b) & ~CF_INVALID) && - a->trace_vcpu_dstate =3D=3D b->trace_vcpu_dstate && - a->page_addr[0] =3D=3D b->page_addr[0] && - a->page_addr[1] =3D=3D b->page_addr[1]; + return ((TARGET_TB_PCREL || tb_pc(a) =3D=3D tb_pc(b)) && + a->cs_base =3D=3D b->cs_base && + a->flags =3D=3D b->flags && + (tb_cflags(a) & ~CF_INVALID) =3D=3D (tb_cflags(b) & ~CF_INVALI= D) && + a->trace_vcpu_dstate =3D=3D b->trace_vcpu_dstate && + a->page_addr[0] =3D=3D b->page_addr[0] && + a->page_addr[1] =3D=3D b->page_addr[1]); } =20 void tb_htable_init(void) @@ -1148,6 +1153,28 @@ static inline void tb_jmp_unlink(TranslationBlock *d= est) qemu_spin_unlock(&dest->jmp_lock); } =20 +static void tb_jmp_cache_inval_tb(TranslationBlock *tb) +{ + CPUState *cpu; + + if (TARGET_TB_PCREL) { + /* A TB may be at any virtual address */ + CPU_FOREACH(cpu) { + tcg_flush_jmp_cache(cpu); + } + } else { + uint32_t h =3D tb_jmp_cache_hash_func(tb_pc(tb)); + + CPU_FOREACH(cpu) { + CPUJumpCache *jc =3D cpu->tb_jmp_cache; + + if (qatomic_read(&jc->array[h].tb) =3D=3D tb) { + qatomic_set(&jc->array[h].tb, NULL); + } + } + } +} + /* * In user-mode, call with mmap_lock held. * In !user-mode, if @rm_from_page_list is set, call with the TB's pages' @@ -1155,7 +1182,6 @@ static inline void tb_jmp_unlink(TranslationBlock *de= st) */ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_= list) { - CPUState *cpu; PageDesc *p; uint32_t h; tb_page_addr_t phys_pc; @@ -1170,8 +1196,8 @@ static void do_tb_phys_invalidate(TranslationBlock *t= b, bool rm_from_page_list) =20 /* remove the TB from the hash list */ phys_pc =3D tb->page_addr[0]; - h =3D tb_hash_func(phys_pc, tb_pc(tb), tb->flags, orig_cflags, - tb->trace_vcpu_dstate); + h =3D tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : tb_pc(tb)), + tb->flags, orig_cflags, tb->trace_vcpu_dstate); if (!qht_remove(&tb_ctx.htable, tb, h)) { return; } @@ -1187,13 +1213,7 @@ static void do_tb_phys_invalidate(TranslationBlock *= tb, bool rm_from_page_list) } =20 /* remove the TB from the hash list */ - h =3D tb_jmp_cache_hash_func(tb->pc); - CPU_FOREACH(cpu) { - CPUJumpCache *jc =3D cpu->tb_jmp_cache; - if (qatomic_read(&jc->array[h].tb) =3D=3D tb) { - qatomic_set(&jc->array[h].tb, NULL); - } - } + tb_jmp_cache_inval_tb(tb); =20 /* suppress this TB from the two jump lists */ tb_remove_from_jmp_list(tb, 0); @@ -1302,8 +1322,8 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phy= s_pc, } =20 /* add in the hash table */ - h =3D tb_hash_func(phys_pc, tb_pc(tb), tb->flags, tb->cflags, - tb->trace_vcpu_dstate); + h =3D tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : tb_pc(tb)), + tb->flags, tb->cflags, tb->trace_vcpu_dstate); qht_insert(&tb_ctx.htable, tb, h, &existing_tb); =20 /* remove TB from the page(s) if we couldn't insert it */ @@ -1373,7 +1393,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, =20 gen_code_buf =3D tcg_ctx->code_gen_ptr; tb->tc.ptr =3D tcg_splitwx_to_rx(gen_code_buf); +#if !TARGET_TB_PCREL tb->pc =3D pc; +#endif tb->cs_base =3D cs_base; tb->flags =3D flags; tb->cflags =3D cflags; --=20 2.34.1 From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664915261; cv=none; d=zohomail.com; s=zohoarc; b=aprID2k8veInjWgqURZVpcMtsF6qkFrucS0BXuCkrm5zeZr4JBjQS7uZjcB0gkE5kiEUz+FUpumvv6om/0t8b5WUJ50yRgXJ6ZDEOLa11r1W9Z57N5CNIz//JO0c+ZDjo2dFSZQHvyCV1gM5Hi60PV8BqbLfSHrGvUbgN2yY91I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664915261; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DJ375f2f0/rpFxGusvoYB185jN+EVbOYzd0NkFA5EM0=; b=HNYiZGX8sNy0ljmbHdpnQqIJY60HsitMMh94YhHiJa3z1Tb/h3lDZnCWmohUdemGbq1zbZEx7QO9XFzsKXnMEYdXn382JmdeQ2YTNRd4bkhOzB/2vYAJfl/6LYJ2SGweNKc3TL/ViUEGItELfUfpDADDkY0GvCcSP+N4i/+izYQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664915261352479.94791530700684; Tue, 4 Oct 2022 13:27:41 -0700 (PDT) Received: from localhost ([::1]:44874 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofoVw-0005Fi-9S for importer@patchew.org; Tue, 04 Oct 2022 16:27:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51632) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyU-0002DR-Eg for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:53:07 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:35346) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofnyR-0000J2-Uj for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:53:06 -0400 Received: by mail-pg1-x529.google.com with SMTP id j71so7399473pge.2 for ; Tue, 04 Oct 2022 12:53:03 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.53.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:53:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=DJ375f2f0/rpFxGusvoYB185jN+EVbOYzd0NkFA5EM0=; b=ZEsEgFjw4OVDPVJd6e/SCBU8fq5ZSkSOe5fpOQQa0JyHteqOlAB0Qg3SH1Ysnt2GEC gRZcCk3oMznYA0zh9CcUd/whi2wJKtj9ZKRFnGqyTfBl6S/t+tFdr2WAopKPS4Khluf5 YJ4vS+VfdnRewZ/Npibdk5PbOMgdviBTo0YQ3Ix93XWSd0zlBLXgVL6CkUXARP8CNpx0 DVw+gNNpnMXcahh6ctSli+iMBEH8Ev4yeX4D3ly76rwb7y2sq/Ewd5RvsuL227Z4qXKT CKje+d+0rUbAZeFiRaGHJvFW+aZktqyzyHGZdIx16l3bGgBxgWzlSc53u2h7iy5bIudh ZX/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=DJ375f2f0/rpFxGusvoYB185jN+EVbOYzd0NkFA5EM0=; b=cCGP5JHowjrarARcmNW4mzGnIW4sDCY9wQhwrlPi9o+ixldVjG6sKEit/W+DB53IpQ x5P1eaq81qxhzGKwshBpWg3uFKLfeJ6EE0lj3dldh8tNFY+IIW2JgGBCaLvQvHUKrQgb PcZiRX2Wbidq/UuT1TvI+XK3/ZcgpU7E1UYe8dZ7/GdpRaoDWXCCl6dvInC/Pgawx0yN 4nljZU8ZWZXKRDqyPHQxWWtcYa55aCNRquProI49lK3ci8gdEhF0r3ZKswly/U+/OoGe 0+mFRfYRUcNL4two/tOhShP/7Ll/9uBHtWTGe5+zldzvOkyYtieIhq60112cbP4SxeGz RrTg== X-Gm-Message-State: ACrzQf2Come4uJPr9WZvhH/9GZTorOAhFcOy+iM16d4jt6TMjlCJGo4q SZmw2us4YxcZqz0TX8ZAw0ie+UwpGlEvdw== X-Google-Smtp-Source: AMsMyM4Omh/DAsXxLFKSq+cDkkCMDAlku5C75tdBP6LL7npHzpQfysX8R6MPJnTuqfvUsJNWS1F3Ow== X-Received: by 2002:a65:6e0d:0:b0:42d:707c:94ee with SMTP id bd13-20020a656e0d000000b0042d707c94eemr24001410pgb.260.1664913182471; Tue, 04 Oct 2022 12:53:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, Leandro Lupori Subject: [PULL 19/20] tcg/ppc: Optimize 26-bit jumps Date: Tue, 4 Oct 2022 12:52:40 -0700 Message-Id: <20221004195241.46491-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664915262712100001 Content-Type: text/plain; charset="utf-8" From: Leandro Lupori PowerPC64 processors handle direct branches better than indirect ones, resulting in less stalled cycles and branch misses. However, PPC's tb_target_set_jmp_target() was only using direct branches for 16-bit jumps, while PowerPC64's unconditional branch instructions are able to handle displacements of up to 26 bits. To take advantage of this, now jumps whose displacements fit in between 17 and 26 bits are also converted to direct branches. Reviewed-by: Richard Henderson Signed-off-by: Leandro Lupori [rth: Expanded some commentary.] Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 119 +++++++++++++++++++++++++++++---------- 1 file changed, 88 insertions(+), 31 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 1cbd047ab3..e3dba47697 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1847,44 +1847,101 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) tcg_out32(s, insn); } =20 +static inline uint64_t make_pair(tcg_insn_unit i1, tcg_insn_unit i2) +{ + if (HOST_BIG_ENDIAN) { + return (uint64_t)i1 << 32 | i2; + } + return (uint64_t)i2 << 32 | i1; +} + +static inline void ppc64_replace2(uintptr_t rx, uintptr_t rw, + tcg_insn_unit i0, tcg_insn_unit i1) +{ +#if TCG_TARGET_REG_BITS =3D=3D 64 + qatomic_set((uint64_t *)rw, make_pair(i0, i1)); + flush_idcache_range(rx, rw, 8); +#else + qemu_build_not_reached(); +#endif +} + +static inline void ppc64_replace4(uintptr_t rx, uintptr_t rw, + tcg_insn_unit i0, tcg_insn_unit i1, + tcg_insn_unit i2, tcg_insn_unit i3) +{ + uint64_t p[2]; + + p[!HOST_BIG_ENDIAN] =3D make_pair(i0, i1); + p[HOST_BIG_ENDIAN] =3D make_pair(i2, i3); + + /* + * There's no convenient way to get the compiler to allocate a pair + * of registers at an even index, so copy into r6/r7 and clobber. + */ + asm("mr %%r6, %1\n\t" + "mr %%r7, %2\n\t" + "stq %%r6, %0" + : "=3DQ"(*(__int128 *)rw) : "r"(p[0]), "r"(p[1]) : "r6", "r7"); + flush_idcache_range(rx, rw, 16); +} + void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, uintptr_t jmp_rw, uintptr_t addr) { - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_insn_unit i1, i2; - intptr_t tb_diff =3D addr - tc_ptr; - intptr_t br_diff =3D addr - (jmp_rx + 4); - uint64_t pair; + tcg_insn_unit i0, i1, i2, i3; + intptr_t tb_diff =3D addr - tc_ptr; + intptr_t br_diff =3D addr - (jmp_rx + 4); + intptr_t lo, hi; =20 - /* This does not exercise the range of the branch, but we do - still need to be able to load the new value of TCG_REG_TB. - But this does still happen quite often. */ - if (tb_diff =3D=3D (int16_t)tb_diff) { - i1 =3D ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff); - i2 =3D B | (br_diff & 0x3fffffc); - } else { - intptr_t lo =3D (int16_t)tb_diff; - intptr_t hi =3D (int32_t)(tb_diff - lo); - assert(tb_diff =3D=3D hi + lo); - i1 =3D ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16); - i2 =3D ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo); - } -#if HOST_BIG_ENDIAN - pair =3D (uint64_t)i1 << 32 | i2; -#else - pair =3D (uint64_t)i2 << 32 | i1; -#endif - - /* As per the enclosing if, this is ppc64. Avoid the _Static_asse= rt - within qatomic_set that would fail to build a ppc32 host. */ - qatomic_set__nocheck((uint64_t *)jmp_rw, pair); - flush_idcache_range(jmp_rx, jmp_rw, 8); - } else { + if (TCG_TARGET_REG_BITS =3D=3D 32) { intptr_t diff =3D addr - jmp_rx; tcg_debug_assert(in_range_b(diff)); qatomic_set((uint32_t *)jmp_rw, B | (diff & 0x3fffffc)); flush_idcache_range(jmp_rx, jmp_rw, 4); + return; } + + /* + * For 16-bit displacements, we can use a single add + branch. + * This happens quite often. + */ + if (tb_diff =3D=3D (int16_t)tb_diff) { + i0 =3D ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff); + i1 =3D B | (br_diff & 0x3fffffc); + ppc64_replace2(jmp_rx, jmp_rw, i0, i1); + return; + } + + lo =3D (int16_t)tb_diff; + hi =3D (int32_t)(tb_diff - lo); + assert(tb_diff =3D=3D hi + lo); + i0 =3D ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16); + i1 =3D ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo); + + /* + * Without stq from 2.07, we can only update two insns, + * and those must be the ones that load the target address. + */ + if (!have_isa_2_07) { + ppc64_replace2(jmp_rx, jmp_rw, i0, i1); + return; + } + + /* + * For 26-bit displacements, we can use a direct branch. + * Otherwise we still need the indirect branch, which we + * must restore after a potential direct branch write. + */ + br_diff -=3D 4; + if (in_range_b(br_diff)) { + i2 =3D B | (br_diff & 0x3fffffc); + i3 =3D NOP; + } else { + i2 =3D MTSPR | RS(TCG_REG_TB) | CTR; + i3 =3D BCCTR | BO_ALWAYS; + } + ppc64_replace4(jmp_rx, jmp_rw, i0, i1, i2, i3); } =20 static void tcg_out_call_int(TCGContext *s, int lk, @@ -2574,8 +2631,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, if (s->tb_jmp_insn_offset) { /* Direct jump. */ if (TCG_TARGET_REG_BITS =3D=3D 64) { - /* Ensure the next insns are 8-byte aligned. */ - if ((uintptr_t)s->code_ptr & 7) { + /* Ensure the next insns are 8 or 16-byte aligned. */ + while ((uintptr_t)s->code_ptr & (have_isa_2_07 ? 15 : 7)) { tcg_out32(s, NOP); } s->tb_jmp_insn_offset[args[0]] =3D tcg_current_code_size(s= ); --=20 2.34.1 From nobody Mon May 13 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664915648; cv=none; d=zohomail.com; s=zohoarc; b=iMYIAKeApMTEAsZfg8pMeGuAQfVQrc2IoGbG1OurKxm+72ONCkCAcX23zKltbkd/5R5lEKgHgdvdyvY/hqqcDm7HgSbztXvHXKzukvM4cFZt7n6vLCk7u6w8RhC+HriaTs6TEc4jiH9BsbEYGDDbkgd+FPFMHhHai0LrxzFbuOQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664915648; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HLcUorCJlB4lSvVTCc9YU9rdFfxf313/xQ83iKPFDkY=; b=IMbmx4wPQCOn8o3qiUA1yeSOw/9oTWgHp6wYIof5u1EVt5SiJJuOsKqNK9ZsfE5XvNcAMZO09XE5wzgQTgfgIWrzuN+tdJupkVesG31T+yLI+2nTv1adI97nfG3RBvILtltV4GVoyMohCBScuYS+9VYbnAbra7m8+nRBfTZsYUk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664915648694730.4068469104973; Tue, 4 Oct 2022 13:34:08 -0700 (PDT) Received: from localhost ([::1]:56092 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofocB-0003f5-LU for importer@patchew.org; Tue, 04 Oct 2022 16:34:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51634) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofnyW-0002Ei-WD for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:53:10 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:38654) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofnyS-0000JM-R8 for qemu-devel@nongnu.org; Tue, 04 Oct 2022 15:53:07 -0400 Received: by mail-pl1-x630.google.com with SMTP id x1so13564547plv.5 for ; Tue, 04 Oct 2022 12:53:04 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id u23-20020a1709026e1700b00172973d3cd9sm9293406plk.55.2022.10.04.12.53.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 12:53:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=HLcUorCJlB4lSvVTCc9YU9rdFfxf313/xQ83iKPFDkY=; b=po5HvnpOQF1VJWF6Lx8qW00fMOq+Ut7aItfQtoLTDLAogxOzfphSqnD5f29rsXoMUb Kz8ChcYRvGIyHXWqWF2agoQ8aqQXnuKVZR8ra+BMOk75ZeaU4Pj0s9zEnubA2+REQnCt btZWNWka45fWGCtY431R3NkWcWkm/V3l2qmMCb/dqfaYvy6s+8nHeZV6XiYq76HbXT9Z GnIH3XkmhKE6jYHfOhOUjy49Eh6ypayc4AWuQyWaw6pjWkzM/61YRMj9FpnHCuMEl2lu 5TAxpnV84fOEJ4csO9S04Zh7l6moJKCvuMyegXSrztsZ4mlsRnCnVz6jd67r4cBN626r NHDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=HLcUorCJlB4lSvVTCc9YU9rdFfxf313/xQ83iKPFDkY=; b=KR4AGTPaT6MJDZDooO42EqHfDhg6KtrUzq40Ezd2tALPWtwxt7SwqBEOtnjx8NQ1Sz 8TqBuQAtTcZqQ/a+avBqgYRYFWb4FVeRh67RqFM9v7UofJTlr+50gr1BkZ+MIpgHj1V0 Fiv9zS6W2DHJyp+YjDjI+GXNCza6mFUniWOB5pZU1TfqBX56qgGu27i1O6JkleRW2dXB 6bkPiqHNVm76uUmPabQ8KIturxcVZZ8yzoD5g+AO+H99bh+USWsyGhojPqac0uCQZZrh /yj6yWtvdqP7TzzSC7x1yr6da4Nd7QZiK6Yw1qAiVpGCt/YXe34ugUCp2pxHRmB0GaPs SKOA== X-Gm-Message-State: ACrzQf2b2xTDE/kTMGD61CM6gecEgf/RzKVelgx68t+2fTEWWN/0ZaBc Pqszs5UfaWsznXqN9At9UrT8OuXJgNU07w== X-Google-Smtp-Source: AMsMyM7P94nVJT8XGC1m7L1Ax9ETrZwj3rxhEVcs4Tyr/HSsCOmpAwULBevE544qVhLX9JU/8gBMaA== X-Received: by 2002:a17:90a:fe13:b0:20a:8fc8:60ec with SMTP id ck19-20020a17090afe1300b0020a8fc860ecmr1314006pjb.69.1664913183440; Tue, 04 Oct 2022 12:53:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, Yoshinori Sato Subject: [PULL 20/20] target/sh4: Fix TB_FLAG_UNALIGN Date: Tue, 4 Oct 2022 12:52:41 -0700 Message-Id: <20221004195241.46491-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221004195241.46491-1-richard.henderson@linaro.org> References: <20221004195241.46491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664915650116100001 Content-Type: text/plain; charset="utf-8" The value previously chosen overlaps GUSA_MASK. Rename all DELAY_SLOT_* and GUSA_* defines to emphasize that they are included in TB_FLAGs. Add aliases for the FPSCR and SR bits that are included in TB_FLAGS, so that we don't accidentally reassign those bits. Fixes: 4da06fb3062 ("target/sh4: Implement prctl_unalign_sigbus") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/856 Reviewed-by: Yoshinori Sato Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 56 +++++++++++++------------ linux-user/sh4/signal.c | 6 +-- target/sh4/cpu.c | 6 +-- target/sh4/helper.c | 6 +-- target/sh4/translate.c | 90 ++++++++++++++++++++++------------------- 5 files changed, 88 insertions(+), 76 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 9f15ef913c..727b829598 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -78,26 +78,33 @@ #define FPSCR_RM_NEAREST (0 << 0) #define FPSCR_RM_ZERO (1 << 0) =20 -#define DELAY_SLOT_MASK 0x7 -#define DELAY_SLOT (1 << 0) -#define DELAY_SLOT_CONDITIONAL (1 << 1) -#define DELAY_SLOT_RTE (1 << 2) +#define TB_FLAG_DELAY_SLOT (1 << 0) +#define TB_FLAG_DELAY_SLOT_COND (1 << 1) +#define TB_FLAG_DELAY_SLOT_RTE (1 << 2) +#define TB_FLAG_PENDING_MOVCA (1 << 3) +#define TB_FLAG_GUSA_SHIFT 4 /* [11:4] */ +#define TB_FLAG_GUSA_EXCLUSIVE (1 << 12) +#define TB_FLAG_UNALIGN (1 << 13) +#define TB_FLAG_SR_FD (1 << SR_FD) /* 15 */ +#define TB_FLAG_FPSCR_PR FPSCR_PR /* 19 */ +#define TB_FLAG_FPSCR_SZ FPSCR_SZ /* 20 */ +#define TB_FLAG_FPSCR_FR FPSCR_FR /* 21 */ +#define TB_FLAG_SR_RB (1 << SR_RB) /* 29 */ +#define TB_FLAG_SR_MD (1 << SR_MD) /* 30 */ =20 -#define TB_FLAG_PENDING_MOVCA (1 << 3) -#define TB_FLAG_UNALIGN (1 << 4) - -#define GUSA_SHIFT 4 -#ifdef CONFIG_USER_ONLY -#define GUSA_EXCLUSIVE (1 << 12) -#define GUSA_MASK ((0xff << GUSA_SHIFT) | GUSA_EXCLUSIVE) -#else -/* Provide dummy versions of the above to allow tests against tbflags - to be elided while avoiding ifdefs. */ -#define GUSA_EXCLUSIVE 0 -#define GUSA_MASK 0 -#endif - -#define TB_FLAG_ENVFLAGS_MASK (DELAY_SLOT_MASK | GUSA_MASK) +#define TB_FLAG_DELAY_SLOT_MASK (TB_FLAG_DELAY_SLOT | \ + TB_FLAG_DELAY_SLOT_COND | \ + TB_FLAG_DELAY_SLOT_RTE) +#define TB_FLAG_GUSA_MASK ((0xff << TB_FLAG_GUSA_SHIFT) | \ + TB_FLAG_GUSA_EXCLUSIVE) +#define TB_FLAG_FPSCR_MASK (TB_FLAG_FPSCR_PR | \ + TB_FLAG_FPSCR_SZ | \ + TB_FLAG_FPSCR_FR) +#define TB_FLAG_SR_MASK (TB_FLAG_SR_FD | \ + TB_FLAG_SR_RB | \ + TB_FLAG_SR_MD) +#define TB_FLAG_ENVFLAGS_MASK (TB_FLAG_DELAY_SLOT_MASK | \ + TB_FLAG_GUSA_MASK) =20 typedef struct tlb_t { uint32_t vpn; /* virtual page number */ @@ -258,7 +265,7 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool= ifetch) { /* The instruction in a RTE delay slot is fetched in privileged mode, but executed in user mode. */ - if (ifetch && (env->flags & DELAY_SLOT_RTE)) { + if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) { return 0; } else { return (env->sr & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; @@ -366,11 +373,10 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *= env, target_ulong *pc, { *pc =3D env->pc; /* For a gUSA region, notice the end of the region. */ - *cs_base =3D env->flags & GUSA_MASK ? env->gregs[0] : 0; - *flags =3D env->flags /* TB_FLAG_ENVFLAGS_MASK: bits 0-2, 4-12 */ - | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-= 21 */ - | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-= 30 */ - | (env->sr & (1u << SR_FD)) /* Bit 15 */ + *cs_base =3D env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; + *flags =3D env->flags + | (env->fpscr & TB_FLAG_FPSCR_MASK) + | (env->sr & TB_FLAG_SR_MASK) | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ #ifdef CONFIG_USER_ONLY *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; diff --git a/linux-user/sh4/signal.c b/linux-user/sh4/signal.c index f6a18bc6b5..c4ba962708 100644 --- a/linux-user/sh4/signal.c +++ b/linux-user/sh4/signal.c @@ -161,7 +161,7 @@ static void restore_sigcontext(CPUSH4State *regs, struc= t target_sigcontext *sc) __get_user(regs->fpul, &sc->sc_fpul); =20 regs->tra =3D -1; /* disable syscall checks */ - regs->flags &=3D ~(DELAY_SLOT_MASK | GUSA_MASK); + regs->flags =3D 0; } =20 void setup_frame(int sig, struct target_sigaction *ka, @@ -199,7 +199,7 @@ void setup_frame(int sig, struct target_sigaction *ka, regs->gregs[5] =3D 0; regs->gregs[6] =3D frame_addr +=3D offsetof(typeof(*frame), sc); regs->pc =3D (unsigned long) ka->_sa_handler; - regs->flags &=3D ~(DELAY_SLOT_MASK | GUSA_MASK); + regs->flags &=3D ~(TB_FLAG_DELAY_SLOT_MASK | TB_FLAG_GUSA_MASK); =20 unlock_user_struct(frame, frame_addr, 1); return; @@ -251,7 +251,7 @@ void setup_rt_frame(int sig, struct target_sigaction *k= a, regs->gregs[5] =3D frame_addr + offsetof(typeof(*frame), info); regs->gregs[6] =3D frame_addr + offsetof(typeof(*frame), uc); regs->pc =3D (unsigned long) ka->_sa_handler; - regs->flags &=3D ~(DELAY_SLOT_MASK | GUSA_MASK); + regs->flags &=3D ~(TB_FLAG_DELAY_SLOT_MASK | TB_FLAG_GUSA_MASK); =20 unlock_user_struct(frame, frame_addr, 1); return; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index a65a66de43..56c50530da 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -47,7 +47,7 @@ static void superh_cpu_synchronize_from_tb(CPUState *cs, SuperHCPU *cpu =3D SUPERH_CPU(cs); =20 cpu->env.pc =3D tb_pc(tb); - cpu->env.flags =3D tb->flags & TB_FLAG_ENVFLAGS_MASK; + cpu->env.flags =3D tb->flags; } =20 #ifndef CONFIG_USER_ONLY @@ -57,10 +57,10 @@ static bool superh_io_recompile_replay_branch(CPUState = *cs, SuperHCPU *cpu =3D SUPERH_CPU(cs); CPUSH4State *env =3D &cpu->env; =20 - if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) !=3D 0 + if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND)) && env->pc !=3D tb_pc(tb)) { env->pc -=3D 2; - env->flags &=3D ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); + env->flags &=3D ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND); return true; } return false; diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 6a620e36fc..e02e7af607 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -147,11 +147,11 @@ void superh_cpu_do_interrupt(CPUState *cs) env->sr |=3D (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB); env->lock_addr =3D -1; =20 - if (env->flags & DELAY_SLOT_MASK) { + if (env->flags & TB_FLAG_DELAY_SLOT_MASK) { /* Branch instruction should be executed again before delay slot. = */ env->spc -=3D 2; /* Clear flags for exception/interrupt routine. */ - env->flags &=3D ~DELAY_SLOT_MASK; + env->flags &=3D ~TB_FLAG_DELAY_SLOT_MASK; } =20 if (do_exp) { @@ -786,7 +786,7 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interr= upt_request) CPUSH4State *env =3D &cpu->env; =20 /* Delay slots are indivisible, ignore interrupts */ - if (env->flags & DELAY_SLOT_MASK) { + if (env->flags & TB_FLAG_DELAY_SLOT_MASK) { return false; } else { superh_cpu_do_interrupt(cs); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 01056571c3..26231b2a5a 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -175,13 +175,13 @@ void superh_cpu_dump_state(CPUState *cs, FILE *f, int= flags) i, env->gregs[i], i + 1, env->gregs[i + 1], i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]); } - if (env->flags & DELAY_SLOT) { + if (env->flags & TB_FLAG_DELAY_SLOT) { qemu_printf("in delay slot (delayed_pc=3D0x%08x)\n", env->delayed_pc); - } else if (env->flags & DELAY_SLOT_CONDITIONAL) { + } else if (env->flags & TB_FLAG_DELAY_SLOT_COND) { qemu_printf("in conditional delay slot (delayed_pc=3D0x%08x)\n", env->delayed_pc); - } else if (env->flags & DELAY_SLOT_RTE) { + } else if (env->flags & TB_FLAG_DELAY_SLOT_RTE) { qemu_fprintf(f, "in rte delay slot (delayed_pc=3D0x%08x)\n", env->delayed_pc); } @@ -223,7 +223,7 @@ static inline void gen_save_cpu_state(DisasContext *ctx= , bool save_pc) =20 static inline bool use_exit_tb(DisasContext *ctx) { - return (ctx->tbflags & GUSA_EXCLUSIVE) !=3D 0; + return (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) !=3D 0; } =20 static bool use_goto_tb(DisasContext *ctx, target_ulong dest) @@ -276,12 +276,12 @@ static void gen_conditional_jump(DisasContext *ctx, t= arget_ulong dest, TCGLabel *l1 =3D gen_new_label(); TCGCond cond_not_taken =3D jump_if_true ? TCG_COND_EQ : TCG_COND_NE; =20 - if (ctx->tbflags & GUSA_EXCLUSIVE) { + if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) { /* When in an exclusive region, we must continue to the end. Therefore, exit the region on a taken branch, but otherwise fall through to the next instruction. */ tcg_gen_brcondi_i32(cond_not_taken, cpu_sr_t, 0, l1); - tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~GUSA_MASK); + tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~TB_FLAG_GUSA_MASK); /* Note that this won't actually use a goto_tb opcode because we disallow it in use_goto_tb, but it handles exit + singlestep. = */ gen_goto_tb(ctx, 0, dest); @@ -307,14 +307,14 @@ static void gen_delayed_conditional_jump(DisasContext= * ctx) tcg_gen_mov_i32(ds, cpu_delayed_cond); tcg_gen_discard_i32(cpu_delayed_cond); =20 - if (ctx->tbflags & GUSA_EXCLUSIVE) { + if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) { /* When in an exclusive region, we must continue to the end. Therefore, exit the region on a taken branch, but otherwise fall through to the next instruction. */ tcg_gen_brcondi_i32(TCG_COND_EQ, ds, 0, l1); =20 /* Leave the gUSA region. */ - tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~GUSA_MASK); + tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~TB_FLAG_GUSA_MASK); gen_jump(ctx); =20 gen_set_label(l1); @@ -361,8 +361,8 @@ static inline void gen_store_fpr64(DisasContext *ctx, T= CGv_i64 t, int reg) #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) =20 #define CHECK_NOT_DELAY_SLOT \ - if (ctx->envflags & DELAY_SLOT_MASK) { \ - goto do_illegal_slot; \ + if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) { \ + goto do_illegal_slot; \ } =20 #define CHECK_PRIVILEGED \ @@ -436,7 +436,7 @@ static void _decode_opc(DisasContext * ctx) case 0x000b: /* rts */ CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr); - ctx->envflags |=3D DELAY_SLOT; + ctx->envflags |=3D TB_FLAG_DELAY_SLOT; ctx->delayed_pc =3D (uint32_t) - 1; return; case 0x0028: /* clrmac */ @@ -458,7 +458,7 @@ static void _decode_opc(DisasContext * ctx) CHECK_NOT_DELAY_SLOT gen_write_sr(cpu_ssr); tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc); - ctx->envflags |=3D DELAY_SLOT_RTE; + ctx->envflags |=3D TB_FLAG_DELAY_SLOT_RTE; ctx->delayed_pc =3D (uint32_t) - 1; ctx->base.is_jmp =3D DISAS_STOP; return; @@ -513,12 +513,15 @@ static void _decode_opc(DisasContext * ctx) return; case 0xe000: /* mov #imm,Rn */ #ifdef CONFIG_USER_ONLY - /* Detect the start of a gUSA region. If so, update envflags - and end the TB. This will allow us to see the end of the - region (stored in R0) in the next TB. */ + /* + * Detect the start of a gUSA region (mov #-n, r15). + * If so, update envflags and end the TB. This will allow us + * to see the end of the region (stored in R0) in the next TB. + */ if (B11_8 =3D=3D 15 && B7_0s < 0 && (tb_cflags(ctx->base.tb) & CF_PARALLEL)) { - ctx->envflags =3D deposit32(ctx->envflags, GUSA_SHIFT, 8, B7_0= s); + ctx->envflags =3D + deposit32(ctx->envflags, TB_FLAG_GUSA_SHIFT, 8, B7_0s); ctx->base.is_jmp =3D DISAS_STOP; } #endif @@ -544,13 +547,13 @@ static void _decode_opc(DisasContext * ctx) case 0xa000: /* bra disp */ CHECK_NOT_DELAY_SLOT ctx->delayed_pc =3D ctx->base.pc_next + 4 + B11_0s * 2; - ctx->envflags |=3D DELAY_SLOT; + ctx->envflags |=3D TB_FLAG_DELAY_SLOT; return; case 0xb000: /* bsr disp */ CHECK_NOT_DELAY_SLOT tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4); ctx->delayed_pc =3D ctx->base.pc_next + 4 + B11_0s * 2; - ctx->envflags |=3D DELAY_SLOT; + ctx->envflags |=3D TB_FLAG_DELAY_SLOT; return; } =20 @@ -1194,7 +1197,7 @@ static void _decode_opc(DisasContext * ctx) CHECK_NOT_DELAY_SLOT tcg_gen_xori_i32(cpu_delayed_cond, cpu_sr_t, 1); ctx->delayed_pc =3D ctx->base.pc_next + 4 + B7_0s * 2; - ctx->envflags |=3D DELAY_SLOT_CONDITIONAL; + ctx->envflags |=3D TB_FLAG_DELAY_SLOT_COND; return; case 0x8900: /* bt label */ CHECK_NOT_DELAY_SLOT @@ -1204,7 +1207,7 @@ static void _decode_opc(DisasContext * ctx) CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_delayed_cond, cpu_sr_t); ctx->delayed_pc =3D ctx->base.pc_next + 4 + B7_0s * 2; - ctx->envflags |=3D DELAY_SLOT_CONDITIONAL; + ctx->envflags |=3D TB_FLAG_DELAY_SLOT_COND; return; case 0x8800: /* cmp/eq #imm,R0 */ tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(0), B7_0s); @@ -1388,14 +1391,14 @@ static void _decode_opc(DisasContext * ctx) case 0x0023: /* braf Rn */ CHECK_NOT_DELAY_SLOT tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->base.pc_next + 4= ); - ctx->envflags |=3D DELAY_SLOT; + ctx->envflags |=3D TB_FLAG_DELAY_SLOT; ctx->delayed_pc =3D (uint32_t) - 1; return; case 0x0003: /* bsrf Rn */ CHECK_NOT_DELAY_SLOT tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4); tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr); - ctx->envflags |=3D DELAY_SLOT; + ctx->envflags |=3D TB_FLAG_DELAY_SLOT; ctx->delayed_pc =3D (uint32_t) - 1; return; case 0x4015: /* cmp/pl Rn */ @@ -1411,14 +1414,14 @@ static void _decode_opc(DisasContext * ctx) case 0x402b: /* jmp @Rn */ CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); - ctx->envflags |=3D DELAY_SLOT; + ctx->envflags |=3D TB_FLAG_DELAY_SLOT; ctx->delayed_pc =3D (uint32_t) - 1; return; case 0x400b: /* jsr @Rn */ CHECK_NOT_DELAY_SLOT tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4); tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); - ctx->envflags |=3D DELAY_SLOT; + ctx->envflags |=3D TB_FLAG_DELAY_SLOT; ctx->delayed_pc =3D (uint32_t) - 1; return; case 0x400e: /* ldc Rm,SR */ @@ -1839,7 +1842,7 @@ static void _decode_opc(DisasContext * ctx) fflush(stderr); #endif do_illegal: - if (ctx->envflags & DELAY_SLOT_MASK) { + if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) { do_illegal_slot: gen_save_cpu_state(ctx, true); gen_helper_raise_slot_illegal_instruction(cpu_env); @@ -1852,7 +1855,7 @@ static void _decode_opc(DisasContext * ctx) =20 do_fpu_disabled: gen_save_cpu_state(ctx, true); - if (ctx->envflags & DELAY_SLOT_MASK) { + if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) { gen_helper_raise_slot_fpu_disable(cpu_env); } else { gen_helper_raise_fpu_disable(cpu_env); @@ -1867,23 +1870,23 @@ static void decode_opc(DisasContext * ctx) =20 _decode_opc(ctx); =20 - if (old_flags & DELAY_SLOT_MASK) { + if (old_flags & TB_FLAG_DELAY_SLOT_MASK) { /* go out of the delay slot */ - ctx->envflags &=3D ~DELAY_SLOT_MASK; + ctx->envflags &=3D ~TB_FLAG_DELAY_SLOT_MASK; =20 /* When in an exclusive region, we must continue to the end for conditional branches. */ - if (ctx->tbflags & GUSA_EXCLUSIVE - && old_flags & DELAY_SLOT_CONDITIONAL) { + if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE + && old_flags & TB_FLAG_DELAY_SLOT_COND) { gen_delayed_conditional_jump(ctx); return; } /* Otherwise this is probably an invalid gUSA region. Drop the GUSA bits so the next TB doesn't see them. */ - ctx->envflags &=3D ~GUSA_MASK; + ctx->envflags &=3D ~TB_FLAG_GUSA_MASK; =20 tcg_gen_movi_i32(cpu_flags, ctx->envflags); - if (old_flags & DELAY_SLOT_CONDITIONAL) { + if (old_flags & TB_FLAG_DELAY_SLOT_COND) { gen_delayed_conditional_jump(ctx); } else { gen_jump(ctx); @@ -2223,7 +2226,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4Stat= e *env) } =20 /* The entire region has been translated. */ - ctx->envflags &=3D ~GUSA_MASK; + ctx->envflags &=3D ~TB_FLAG_GUSA_MASK; ctx->base.pc_next =3D pc_end; ctx->base.num_insns +=3D max_insns - 1; return; @@ -2234,7 +2237,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4Stat= e *env) =20 /* Restart with the EXCLUSIVE bit set, within a TB run via cpu_exec_step_atomic holding the exclusive lock. */ - ctx->envflags |=3D GUSA_EXCLUSIVE; + ctx->envflags |=3D TB_FLAG_GUSA_EXCLUSIVE; gen_save_cpu_state(ctx, false); gen_helper_exclusive(cpu_env); ctx->base.is_jmp =3D DISAS_NORETURN; @@ -2267,17 +2270,19 @@ static void sh4_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) (tbflags & (1 << SR_RB))) * 0x10; ctx->fbank =3D tbflags & FPSCR_FR ? 0x10 : 0; =20 - if (tbflags & GUSA_MASK) { +#ifdef CONFIG_USER_ONLY + if (tbflags & TB_FLAG_GUSA_MASK) { + /* In gUSA exclusive region. */ uint32_t pc =3D ctx->base.pc_next; uint32_t pc_end =3D ctx->base.tb->cs_base; - int backup =3D sextract32(ctx->tbflags, GUSA_SHIFT, 8); + int backup =3D sextract32(ctx->tbflags, TB_FLAG_GUSA_SHIFT, 8); int max_insns =3D (pc_end - pc) / 2; =20 if (pc !=3D pc_end + backup || max_insns < 2) { /* This is a malformed gUSA region. Don't do anything special, since the interpreter is likely to get confused. */ - ctx->envflags &=3D ~GUSA_MASK; - } else if (tbflags & GUSA_EXCLUSIVE) { + ctx->envflags &=3D ~TB_FLAG_GUSA_MASK; + } else if (tbflags & TB_FLAG_GUSA_EXCLUSIVE) { /* Regardless of single-stepping or the end of the page, we must complete execution of the gUSA region while holding the exclusive lock. */ @@ -2285,6 +2290,7 @@ static void sh4_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) return; } } +#endif =20 /* Since the ISA is fixed-width, we can bound by the number of instructions remaining on the page. */ @@ -2309,8 +2315,8 @@ static void sh4_tr_translate_insn(DisasContextBase *d= cbase, CPUState *cs) DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 #ifdef CONFIG_USER_ONLY - if (unlikely(ctx->envflags & GUSA_MASK) - && !(ctx->envflags & GUSA_EXCLUSIVE)) { + if (unlikely(ctx->envflags & TB_FLAG_GUSA_MASK) + && !(ctx->envflags & TB_FLAG_GUSA_EXCLUSIVE)) { /* We're in an gUSA region, and we have not already fallen back on using an exclusive region. Attempt to parse the region into a single supported atomic operation. Failure @@ -2330,9 +2336,9 @@ static void sh4_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - if (ctx->tbflags & GUSA_EXCLUSIVE) { + if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) { /* Ending the region of exclusivity. Clear the bits. */ - ctx->envflags &=3D ~GUSA_MASK; + ctx->envflags &=3D ~TB_FLAG_GUSA_MASK; } =20 switch (ctx->base.is_jmp) { --=20 2.34.1