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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=shentey@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1664833942299100001 Content-Type: text/plain; charset="utf-8" Will allow e500 boards to access SD cards using just their own devices. Signed-off-by: Bernhard Beschow --- hw/sd/sdhci.c | 147 +++++++++++++++++++++++++++++++++++++++++- include/hw/sd/sdhci.h | 3 + 2 files changed, 149 insertions(+), 1 deletion(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 306070c872..ff92c6c4e5 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1369,6 +1369,7 @@ void sdhci_initfn(SDHCIState *s) s->transfer_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_tran= sfer, s); =20 s->io_ops =3D &sdhci_mmio_ops; + s->io_registers_map_size =3D SDHC_REGISTERS_MAP_SIZE; } =20 void sdhci_uninitfn(SDHCIState *s) @@ -1392,7 +1393,7 @@ void sdhci_common_realize(SDHCIState *s, Error **errp) s->fifo_buffer =3D g_malloc0(s->buf_maxsz); =20 memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci", - SDHC_REGISTERS_MAP_SIZE); + s->io_registers_map_size); } =20 void sdhci_common_unrealize(SDHCIState *s) @@ -1575,6 +1576,149 @@ static const TypeInfo sdhci_bus_info =3D { .class_init =3D sdhci_bus_class_init, }; =20 +/* --- qdev Freescale eSDHC --- */ + +/* Watermark Level Register */ +#define ESDHC_WML 0x44 + +/* Host Controller Capabilities Register 2 */ +#define ESDHC_CAPABILITIES_1 0x114 + +/* Control Register for DMA transfer */ +#define ESDHC_DMA_SYSCTL 0x40c + +#define ESDHC_REGISTERS_MAP_SIZE 0x410 + +static uint64_t esdhci_read(void *opaque, hwaddr offset, unsigned size) +{ + uint64_t ret; + + if (size !=3D 4) { + qemu_log_mask(LOG_GUEST_ERROR, "ESDHC rd_%ub @0x%02" HWADDR_PRIx + " wrong size\n", size, offset); + return 0; + } + + if (offset & 0x3) { + qemu_log_mask(LOG_GUEST_ERROR, "ESDHC rd_%ub @0x%02" HWADDR_PRIx + " unaligned\n", size, offset); + return 0; + } + + switch (offset) { + case SDHC_SYSAD: + case SDHC_BLKSIZE: + case SDHC_ARGUMENT: + case SDHC_TRNMOD: + case SDHC_RSPREG0: + case SDHC_RSPREG1: + case SDHC_RSPREG2: + case SDHC_RSPREG3: + case SDHC_BDATA: + case SDHC_PRNSTS: + case SDHC_HOSTCTL: + case SDHC_CLKCON: + case SDHC_NORINTSTS: + case SDHC_NORINTSTSEN: + case SDHC_NORINTSIGEN: + case SDHC_ACMD12ERRSTS: + case SDHC_CAPAB: + case SDHC_SLOT_INT_STATUS: + ret =3D sdhci_read(opaque, offset, size); + break; + + case ESDHC_WML: + case ESDHC_DMA_SYSCTL: + ret =3D 0; + qemu_log_mask(LOG_UNIMP, "ESDHC rd_%ub @0x%02" HWADDR_PRIx + " not implemented\n", size, offset); + break; + + default: + ret =3D 0; + qemu_log_mask(LOG_GUEST_ERROR, "ESDHC rd_%ub @0x%02" HWADDR_PRIx + " unknown offset\n", size, offset); + break; + } + + return ret; +} + +static void esdhci_write(void *opaque, hwaddr offset, uint64_t val, + unsigned size) +{ + if (size !=3D 4) { + qemu_log_mask(LOG_GUEST_ERROR, "ESDHC wr_%ub @0x%02" HWADDR_PRIx + " <- 0x%08lx wrong size\n", size, offset, val); + return; + } + + if (offset & 0x3) { + qemu_log_mask(LOG_GUEST_ERROR, "ESDHC wr_%ub @0x%02" HWADDR_PRIx + " <- 0x%08lx unaligned\n", size, offset, val); + return; + } + + switch (offset) { + case SDHC_SYSAD: + case SDHC_BLKSIZE: + case SDHC_ARGUMENT: + case SDHC_TRNMOD: + case SDHC_BDATA: + case SDHC_HOSTCTL: + case SDHC_CLKCON: + case SDHC_NORINTSTS: + case SDHC_NORINTSTSEN: + case SDHC_NORINTSIGEN: + case SDHC_FEAER: + sdhci_write(opaque, offset, val, size); + break; + + case ESDHC_WML: + case ESDHC_DMA_SYSCTL: + qemu_log_mask(LOG_UNIMP, "ESDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x= %08lx " + "not implemented\n", size, offset, val); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "ESDHC wr_%ub @0x%02" HWADDR_PRIx + " <- 0x%08lx unknown offset\n", size, offset, val); + break; + } +} + +static const MemoryRegionOps esdhc_mmio_ops =3D { + .read =3D esdhci_read, + .write =3D esdhci_write, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + .unaligned =3D false + }, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + +static void esdhci_init(Object *obj) +{ + DeviceState *dev =3D DEVICE(obj); + SDHCIState *s =3D SYSBUS_SDHCI(obj); + + s->io_ops =3D &esdhc_mmio_ops; + s->io_registers_map_size =3D ESDHC_REGISTERS_MAP_SIZE; + + /* + * Compatible with: + * - SD Host Controller Specification Version 2.0 Part A2 + */ + qdev_prop_set_uint8(dev, "sd-spec-version", 2); +} + +static const TypeInfo esdhc_info =3D { + .name =3D TYPE_FSL_ESDHC, + .parent =3D TYPE_SYSBUS_SDHCI, + .instance_init =3D esdhci_init, +}; + /* --- qdev i.MX eSDHC --- */ =20 #define USDHC_MIX_CTRL 0x48 @@ -1907,6 +2051,7 @@ static void sdhci_register_types(void) { type_register_static(&sdhci_sysbus_info); type_register_static(&sdhci_bus_info); + type_register_static(&esdhc_info); type_register_static(&imx_usdhc_info); type_register_static(&sdhci_s3c_info); } diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 01a64c5442..5b32e83eee 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -45,6 +45,7 @@ struct SDHCIState { AddressSpace *dma_as; MemoryRegion *dma_mr; const MemoryRegionOps *io_ops; + uint64_t io_registers_map_size; =20 QEMUTimer *insert_timer; /* timer for 'changing' sd card. */ QEMUTimer *transfer_timer; @@ -122,6 +123,8 @@ DECLARE_INSTANCE_CHECKER(SDHCIState, PCI_SDHCI, DECLARE_INSTANCE_CHECKER(SDHCIState, SYSBUS_SDHCI, TYPE_SYSBUS_SDHCI) =20 +#define TYPE_FSL_ESDHC "fsl-esdhc" + #define TYPE_IMX_USDHC "imx-usdhc" =20 #define TYPE_S3C_SDHCI "s3c-sdhci" --=20 2.37.3