From nobody Mon May 13 17:12:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664815184; cv=none; d=zohomail.com; s=zohoarc; b=M4vSVs6HnygCqDZhEOXdFJ+2Bnm8aRjIomZKdBd5Rqo16d/82UxyuAtzpOsEaVzyJrlazYOLaj3q2H9olauUE96yAXuZUOxaLDLBTaOWbGJ9G7QRUJ0NCs4I6m6Nt0rbjYdMVWe7v7JhEHvRP4eB7/8RcGn4yYTZaYRe2arf6bE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664815184; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jUmre8iVrWqfonZLosPQb1JFiAtPKqPnUADEzLUFRYs=; b=ZkWkvFRWc2fdOeL4qneHNLdKiDOAGbW9nENI32oviJrXlpefJFMo74R2AZCxx0/ipFODQGE8DWwJ72sw1JW0zZ9lCb/mn+T73B8n82KlRMcWmS/HcUQW60YK9Z4kzOmg1058Rpn1qo1p8N1vSLVyfBe2j208KtvpaJjYGbAC4uw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664815184780611.0909756568869; Mon, 3 Oct 2022 09:39:44 -0700 (PDT) Received: from localhost ([::1]:47622 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofOTn-0000eL-78 for importer@patchew.org; Mon, 03 Oct 2022 12:39:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60438) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofOE7-0007uP-BN for qemu-devel@nongnu.org; Mon, 03 Oct 2022 12:23:31 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:39873) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofODy-0000HY-PY for qemu-devel@nongnu.org; Mon, 03 Oct 2022 12:23:31 -0400 Received: by mail-wr1-x42f.google.com with SMTP id f11so14867890wrm.6 for ; Mon, 03 Oct 2022 09:23:21 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d62c2000000b0022afce9ea93sm9897856wrv.40.2022.10.03.09.23.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Oct 2022 09:23:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date; bh=jUmre8iVrWqfonZLosPQb1JFiAtPKqPnUADEzLUFRYs=; b=v12CywUSi62MZqRi7AoB76rw52nNtur+0YF+s+RcvF+E13IcRfMnx0L/Gjfjy9Kn4l qsZlvqdFLnzfC//unEUoi5BiEJQ54FXb809+JLUN7KqdyxAVEcYuveTda16g+09yG22t ph0HOIxm+un9uhOkvWA6jL1DlxORuDa+yABs0DB7ElmnJLVaXAUv8PSVCHWiedl1uLqz ow0gPH6/uOEKs3s2mcQImywBDG+KrOaAmwLGgAkvXVzPBWojAvDqhjndAEusOU90wqQz PWmJ3+z+yhVCIxSG9rItQVy015qbPGnDKbF3PpNXOuh+KkshSSqXf65918J0AiEs+HwT qHGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date; bh=jUmre8iVrWqfonZLosPQb1JFiAtPKqPnUADEzLUFRYs=; b=33GqOHZM6lTm3fE9XnaYkooIqflb11EtdEtP0MBi0HnPgEZ53BqRaLD7BjmjWhS/G6 o92CAk6IHPJVT0t8zwrAFi5Su7lB4Lllz/JSM1tZ2XPU4VI4CcruLRogIkMH4gzdK1tV Exwuhltu0+dLYO54b6eVbPMSrQMuCoa1UAMQ7ZhvmD1xD4GixLFoaZRCbZDaMJs44CqY fLaCn/5EhzF0O2Q2wf1F5pO33A9MkFTmSbqbv68SoFC754ICndx+o2M68YCd/gAzdGVi SqagrYI5su71kZ0k4f/pjDNf4BAxQuQkljtPyk/GNCBug9i/BokcpkV4MHz0h51sTfWX 9LUA== X-Gm-Message-State: ACrzQf25ttoyugtZn33JRkS7bpxZqrHdneXgFze4JXzy+T6YlzACtVhb v3eK7kel3JttFam8e7e3m4Ovf6Moyaltmw== X-Google-Smtp-Source: AMsMyM7Oiq1a8DihDjSBRaFxY3ut6K1TMWYB55DcnDYSrJNJhZKbmSkE0pPIFq4H92+hO9J9fB5fVg== X-Received: by 2002:a5d:598f:0:b0:22a:f74d:ae24 with SMTP id n15-20020a5d598f000000b0022af74dae24mr13568756wri.544.1664814198347; Mon, 03 Oct 2022 09:23:18 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 1/3] target/arm: Don't allow guest to use unimplemented granule sizes Date: Mon, 3 Oct 2022 17:23:13 +0100 Message-Id: <20221003162315.2833797-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221003162315.2833797-1-peter.maydell@linaro.org> References: <20221003162315.2833797-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664815185633100001 Content-Type: text/plain; charset="utf-8" Arm CPUs support some subset of the granule (page) sizes 4K, 16K and 64K. The guest selects the one it wants using bits in the TCR_ELx registers. If it tries to program these registers with a value that is either reserved or which requests a size that the CPU does not implement, the architecture requires that the CPU behaves as if the field was programmed to some size that has been implemented. Currently we don't implement this, and instead let the guest use any granule size, even if the CPU ID register fields say it isn't present. Make aa64_va_parameters() check against the supported granule size and force use of a different one if it is not implemented. (A subsequent commit will make ARMVAParameters use the new enum rather than the current pair of using16k/using64k bools.) Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- v1->v2: rename enum to ARMGranuleSize, put it in internals.h --- target/arm/cpu.h | 33 +++++++++++++ target/arm/internals.h | 9 ++++ target/arm/helper.c | 102 +++++++++++++++++++++++++++++++++++++---- 3 files changed, 136 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 33cdbc0143e..6d39d27378d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4103,6 +4103,39 @@ static inline bool isar_feature_aa64_tgran16_2_lpa2(= const ARMISARegisters *id) return t >=3D 3 || (t =3D=3D 0 && isar_feature_aa64_tgran16_lpa2(id)); } =20 +static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id) +{ + return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >=3D 0; +} + +static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >=3D 1; +} + +static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id) +{ + return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >=3D 0; +} + +static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id) +{ + unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); + return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran4(id)); +} + +static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id) +{ + unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); + return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran16(id)); +} + +static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) +{ + unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2); + return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran64(id)); +} + static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) !=3D 0; diff --git a/target/arm/internals.h b/target/arm/internals.h index 307a5965053..0727c7e4559 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1065,6 +1065,15 @@ static inline uint32_t aarch64_pstate_valid_mask(con= st ARMISARegisters *id) return valid; } =20 +/* Granule size (i.e. page size) */ +typedef enum ARMGranuleSize { + /* Same order as TG0 encoding */ + Gran4K, + Gran64K, + Gran16K, + GranInvalid, +} ARMGranuleSize; + /* * Parameters of a given virtual address, as extracted from the * translation control register (TCR) for a given regime. diff --git a/target/arm/helper.c b/target/arm/helper.c index b5dac651e75..41b8435deac 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10289,20 +10289,105 @@ static int aa64_va_parameter_tcma(uint64_t tcr, = ARMMMUIdx mmu_idx) } } =20 +static ARMGranuleSize tg0_to_gran_size(int tg) +{ + switch (tg) { + case 0: + return Gran4K; + case 1: + return Gran64K; + case 2: + return Gran16K; + default: + return GranInvalid; + } +} + +static ARMGranuleSize tg1_to_gran_size(int tg) +{ + switch (tg) { + case 1: + return Gran16K; + case 2: + return Gran4K; + case 3: + return Gran64K; + default: + return GranInvalid; + } +} + +static inline bool have4k(ARMCPU *cpu, bool stage2) +{ + return stage2 ? cpu_isar_feature(aa64_tgran4_2, cpu) + : cpu_isar_feature(aa64_tgran4, cpu); +} + +static inline bool have16k(ARMCPU *cpu, bool stage2) +{ + return stage2 ? cpu_isar_feature(aa64_tgran16_2, cpu) + : cpu_isar_feature(aa64_tgran16, cpu); +} + +static inline bool have64k(ARMCPU *cpu, bool stage2) +{ + return stage2 ? cpu_isar_feature(aa64_tgran64_2, cpu) + : cpu_isar_feature(aa64_tgran64, cpu); +} + +static ARMGranuleSize sanitize_gran_size(ARMCPU *cpu, ARMGranuleSize gran, + bool stage2) +{ + switch (gran) { + case Gran4K: + if (have4k(cpu, stage2)) { + return gran; + } + break; + case Gran16K: + if (have16k(cpu, stage2)) { + return gran; + } + break; + case Gran64K: + if (have64k(cpu, stage2)) { + return gran; + } + break; + case GranInvalid: + break; + } + /* + * If the guest selects a granule size that isn't implemented, + * the architecture requires that we behave as if it selected one + * that is (with an IMPDEF choice of which one to pick). We choose + * to implement the smallest supported granule size. + */ + if (have4k(cpu, stage2)) { + return Gran4K; + } + if (have16k(cpu, stage2)) { + return Gran16K; + } + assert(have64k(cpu, stage2)); + return Gran64K; +} + ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data) { uint64_t tcr =3D regime_tcr(env, mmu_idx); bool epd, hpd, using16k, using64k, tsz_oob, ds; int select, tsz, tbi, max_tsz, min_tsz, ps, sh; + ARMGranuleSize gran; ARMCPU *cpu =3D env_archcpu(env); + bool stage2 =3D mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMM= MUIdx_Stage2_S; =20 if (!regime_has_2_ranges(mmu_idx)) { select =3D 0; tsz =3D extract32(tcr, 0, 6); - using64k =3D extract32(tcr, 14, 1); - using16k =3D extract32(tcr, 15, 1); - if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_St= age2_S) { + gran =3D tg0_to_gran_size(extract32(tcr, 14, 2)); + if (stage2) { /* VTCR_EL2 */ hpd =3D false; } else { @@ -10320,16 +10405,13 @@ ARMVAParameters aa64_va_parameters(CPUARMState *e= nv, uint64_t va, select =3D extract64(va, 55, 1); if (!select) { tsz =3D extract32(tcr, 0, 6); + gran =3D tg0_to_gran_size(extract32(tcr, 14, 2)); epd =3D extract32(tcr, 7, 1); sh =3D extract32(tcr, 12, 2); - using64k =3D extract32(tcr, 14, 1); - using16k =3D extract32(tcr, 15, 1); hpd =3D extract64(tcr, 41, 1); } else { - int tg =3D extract32(tcr, 30, 2); - using16k =3D tg =3D=3D 1; - using64k =3D tg =3D=3D 3; tsz =3D extract32(tcr, 16, 6); + gran =3D tg1_to_gran_size(extract32(tcr, 30, 2)); epd =3D extract32(tcr, 23, 1); sh =3D extract32(tcr, 28, 2); hpd =3D extract64(tcr, 42, 1); @@ -10338,6 +10420,10 @@ ARMVAParameters aa64_va_parameters(CPUARMState *en= v, uint64_t va, ds =3D extract64(tcr, 59, 1); } =20 + gran =3D sanitize_gran_size(cpu, gran, stage2); + using64k =3D gran =3D=3D Gran64K; + using16k =3D gran =3D=3D Gran16K; + if (cpu_isar_feature(aa64_st, cpu)) { max_tsz =3D 48 - using64k; } else { --=20 2.25.1 From nobody Mon May 13 17:12:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664814707; cv=none; d=zohomail.com; s=zohoarc; b=ZDZBkas+gG0tfHdVc+JkWKpeSSoGNNH89MTu7557Li1CqIJYxiNa4PNmjbVaJKQgyqpwXpVIzRjz/N8EwqSXGv+oKo0r7VqKcC0ZUxUunkokiDmbs9y/dsYJz8tvG29Ta+F3eW1xKyoR24B4q8GlyGD+sTM/WpLhyjAZdYMARwI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664814707; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iLS80cjxzj2lzwffuWrbrnxfYmJ63GkptFKtPKF4mf8=; b=gdF7OoQX/61qBFVOzVv8XsQziqsfTYgwOiYbtWUzf9nQ12nqfi/dHmsdsPxtJngGp2fmrBJp7JAr0S4YQOydr9tL3NrOD+zzNg5cFxQ0pIEV1PhD5QShAYuIUqXey/DojmhFVsoy62u7OXuF0S8EyG3tjOUc3Z3h6Im9v+zEwOs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664814707112893.4025291192331; Mon, 3 Oct 2022 09:31:47 -0700 (PDT) Received: from localhost ([::1]:39240 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofOM6-00049i-2X for importer@patchew.org; Mon, 03 Oct 2022 12:31:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60442) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofOE8-0007vW-G4 for qemu-devel@nongnu.org; Mon, 03 Oct 2022 12:23:34 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:36648) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofODy-0000He-Pa for qemu-devel@nongnu.org; Mon, 03 Oct 2022 12:23:32 -0400 Received: by mail-wr1-x42b.google.com with SMTP id j7so12158384wrr.3 for ; Mon, 03 Oct 2022 09:23:21 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d62c2000000b0022afce9ea93sm9897856wrv.40.2022.10.03.09.23.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Oct 2022 09:23:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date; bh=iLS80cjxzj2lzwffuWrbrnxfYmJ63GkptFKtPKF4mf8=; b=crwwGU25GTQMMOV+aN1uk6LhaFVle8FSx2hJKe1U255cSYxMdSp9qQjJedTzEsQzsL YC1nQ+qhLFAyg4adBjjwYP1yUEdJzhmNRvBCaLQULJ6igSW3Tj+1MNkDZ3MTrfqauBSI ltPj4NCzw3l0+D2XZ5a+s+ebLVMn0VMClsHdbpomYek+pXhmPvzaGRiu8L+Y6q0RScm+ l77zH6+Bfj2v85VxX9O6uBPwc5vnGBfinz+U4RCH1oZu/sevClVF+Z4RMKaO33pcL3eM HimT8MrrNKDKtoP81QYmRouQMUfOsNgQxGidM3prsNgAKocvJzIVBnjb9cbXXDSBSAea Xzcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date; bh=iLS80cjxzj2lzwffuWrbrnxfYmJ63GkptFKtPKF4mf8=; b=K0i0lWvyVqZHnU+KP60tA4rXSnPnX9TTl9YPSv1PGKC/G26PUk+hvZnAiFh7ny1vLT hugMPg63aNqSarkN8hvJiSV3YweF4BMhNWtr/SYoe5NQORfODgTa951AQTWzFlzbbj0I O1jsf/D9oqO8w8a/PX6PzkdVfXDz2x4mRet9UziPBAj4Je+cgpWi+LYBWOYWmNY/5UDe zrr4cvou1NWhzHyquIUENQIrN4a9qz3bRKohsryywKiEZsA3A6id6lBZ0TFD/E4/7vMu ODyV06Q892H3vlvUq17xBqOnGicqILQ2jrKxaBJgiNRWR5Vb4kxlC4nazQx8nfzdbT0V YCoA== X-Gm-Message-State: ACrzQf1LrlsgulrmrUiPdmZ0fuwmQOmhBzjMcpEU/oa/fQXPcsPeC84z 0rAgKBxihUKuRIN9y++YuNZlWw== X-Google-Smtp-Source: AMsMyM5Mg6+Gt1rgwgp6NS9v0AIM8K85ZcgD3D9vd9a7zWOGAp1vC2iswC274EOlVb6rWinKx0h8Pw== X-Received: by 2002:a5d:59a5:0:b0:22e:37ab:ed7d with SMTP id p5-20020a5d59a5000000b0022e37abed7dmr4288607wrr.461.1664814199106; Mon, 03 Oct 2022 09:23:19 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 2/3] target/arm: Use ARMGranuleSize in ARMVAParameters Date: Mon, 3 Oct 2022 17:23:14 +0100 Message-Id: <20221003162315.2833797-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221003162315.2833797-1-peter.maydell@linaro.org> References: <20221003162315.2833797-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664814708413100001 Content-Type: text/plain; charset="utf-8" Now we have an enum for the granule size, use it in the ARMVAParameters struct instead of the using16k/using64k bools. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/internals.h | 23 +++++++++++++++++++++-- target/arm/helper.c | 39 ++++++++++++++++++++++++++++----------- target/arm/ptw.c | 8 +------- 3 files changed, 50 insertions(+), 20 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 0727c7e4559..95f654db3bc 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1074,6 +1074,26 @@ typedef enum ARMGranuleSize { GranInvalid, } ARMGranuleSize; =20 +/** + * arm_granule_bits: Return address size of the granule in bits + * + * Return the address size of the granule in bits. This corresponds + * to the pseudocode TGxGranuleBits(). + */ +static inline int arm_granule_bits(ARMGranuleSize gran) +{ + switch (gran) { + case Gran64K: + return 16; + case Gran16K: + return 14; + case Gran4K: + return 12; + default: + g_assert_not_reached(); + } +} + /* * Parameters of a given virtual address, as extracted from the * translation control register (TCR) for a given regime. @@ -1086,10 +1106,9 @@ typedef struct ARMVAParameters { bool tbi : 1; bool epd : 1; bool hpd : 1; - bool using16k : 1; - bool using64k : 1; bool tsz_oob : 1; /* tsz has been clamped to legal range */ bool ds : 1; + ARMGranuleSize gran : 2; } ARMVAParameters; =20 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, diff --git a/target/arm/helper.c b/target/arm/helper.c index 41b8435deac..484a2d54ab8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4487,6 +4487,24 @@ typedef struct { uint64_t length; } TLBIRange; =20 +static ARMGranuleSize tlbi_range_tg_to_gran_size(int tg) +{ + /* + * Note that the TLBI range TG field encoding differs from both + * TG0 and TG1 encodings. + */ + switch (tg) { + case 1: + return Gran4K; + case 2: + return Gran16K; + case 3: + return Gran64K; + default: + return GranInvalid; + } +} + static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, uint64_t value) { @@ -4495,17 +4513,19 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *e= nv, ARMMMUIdx mmuidx, uint64_t select =3D sextract64(value, 36, 1); ARMVAParameters param =3D aa64_va_parameters(env, select, mmuidx, true= ); TLBIRange ret =3D { }; + ARMGranuleSize gran; =20 page_size_granule =3D extract64(value, 46, 2); + gran =3D tlbi_range_tg_to_gran_size(page_size_granule); =20 /* The granule encoded in value must match the granule in use. */ - if (page_size_granule !=3D (param.using64k ? 3 : param.using16k ? 2 : = 1)) { + if (gran !=3D param.gran) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\= n", page_size_granule); return ret; } =20 - page_shift =3D (page_size_granule - 1) * 2 + 12; + page_shift =3D arm_granule_bits(gran); num =3D extract64(value, 39, 5); scale =3D extract64(value, 44, 2); exponent =3D (5 * scale) + 1; @@ -10377,7 +10397,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, ARMMMUIdx mmu_idx, bool data) { uint64_t tcr =3D regime_tcr(env, mmu_idx); - bool epd, hpd, using16k, using64k, tsz_oob, ds; + bool epd, hpd, tsz_oob, ds; int select, tsz, tbi, max_tsz, min_tsz, ps, sh; ARMGranuleSize gran; ARMCPU *cpu =3D env_archcpu(env); @@ -10421,11 +10441,9 @@ ARMVAParameters aa64_va_parameters(CPUARMState *en= v, uint64_t va, } =20 gran =3D sanitize_gran_size(cpu, gran, stage2); - using64k =3D gran =3D=3D Gran64K; - using16k =3D gran =3D=3D Gran16K; =20 if (cpu_isar_feature(aa64_st, cpu)) { - max_tsz =3D 48 - using64k; + max_tsz =3D 48 - (gran =3D=3D Gran64K); } else { max_tsz =3D 39; } @@ -10435,7 +10453,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, * adjust the effective value of DS, as documented. */ min_tsz =3D 16; - if (using64k) { + if (gran =3D=3D Gran64K) { if (cpu_isar_feature(aa64_lva, cpu)) { min_tsz =3D 12; } @@ -10444,14 +10462,14 @@ ARMVAParameters aa64_va_parameters(CPUARMState *e= nv, uint64_t va, switch (mmu_idx) { case ARMMMUIdx_Stage2: case ARMMMUIdx_Stage2_S: - if (using16k) { + if (gran =3D=3D Gran16K) { ds =3D cpu_isar_feature(aa64_tgran16_2_lpa2, cpu); } else { ds =3D cpu_isar_feature(aa64_tgran4_2_lpa2, cpu); } break; default: - if (using16k) { + if (gran =3D=3D Gran16K) { ds =3D cpu_isar_feature(aa64_tgran16_lpa2, cpu); } else { ds =3D cpu_isar_feature(aa64_tgran4_lpa2, cpu); @@ -10488,10 +10506,9 @@ ARMVAParameters aa64_va_parameters(CPUARMState *en= v, uint64_t va, .tbi =3D tbi, .epd =3D epd, .hpd =3D hpd, - .using16k =3D using16k, - .using64k =3D using64k, .tsz_oob =3D tsz_oob, .ds =3D ds, + .gran =3D gran, }; } =20 diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 2ddfc028abb..b0a780b38e2 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1048,13 +1048,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uin= t64_t address, } } =20 - if (param.using64k) { - stride =3D 13; - } else if (param.using16k) { - stride =3D 11; - } else { - stride =3D 9; - } + stride =3D arm_granule_bits(param.gran) - 3; =20 /* * Note that QEMU ignores shareability and cacheability attributes, --=20 2.25.1 From nobody Mon May 13 17:12:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664815583; cv=none; d=zohomail.com; s=zohoarc; b=mfyjOKCDBXBzXDcoilqjaK3nLVqhS4eyobn6EaVsXHgxx01GWkqR+V36fZf+E8qlqpO+n98s8aSKmKYkZJaIgsSqcd20C/E7+DZdrPQnD+KeGRUVu+CA6RmEDqaEY4KIRkgYuLX9ZSP9oZ+rJQUo+sXU0ZbWS9HpZXg/FCiKBbM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664815583; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Lbf7DgzaGFcfNvaM2KqWvg7D8B8oETdPLTVE9MwyWyA=; b=FQ8KNSdGwTDAfpULafMaqSFvIyyZfDtpZmiYz8ITBfrQw/u4jYenO2hs/SFBD2RdwusV3suNdeZxxhhD6Ma+70LX7xBCFbP6GBETWf2aJ8wzXjX54sFooN7It00psMT3MwxTUwAqyyHkOdsztvqtlb5V0uz9xyx+f86NvEIw9T0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664815583379532.0841096091451; Mon, 3 Oct 2022 09:46:23 -0700 (PDT) Received: from localhost ([::1]:36712 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ofOa9-0005gR-4x for importer@patchew.org; Mon, 03 Oct 2022 12:46:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60446) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ofOEA-0007vx-8M for qemu-devel@nongnu.org; Mon, 03 Oct 2022 12:23:34 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:39878) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ofODz-0000Hk-Ov for qemu-devel@nongnu.org; Mon, 03 Oct 2022 12:23:33 -0400 Received: by mail-wr1-x434.google.com with SMTP id f11so14867948wrm.6 for ; Mon, 03 Oct 2022 09:23:20 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d62c2000000b0022afce9ea93sm9897856wrv.40.2022.10.03.09.23.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Oct 2022 09:23:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date; bh=Lbf7DgzaGFcfNvaM2KqWvg7D8B8oETdPLTVE9MwyWyA=; b=Ztonl5fAaT/D1XIUjRAGtBLqZtEtQcOO1AcvFUMECHec08QSr81I/6drRHu7Vo04kZ TafWgLq/jo/oVeDQBhbq/+yjvy+neYzsDL1nhY9HshWoQ7H5YifBu/zrFDuVnTrArAyh dqgzyKH5AEu8pzIszOGakyk4M5TXQGU/uYEFw9pKVdD8K6oXAuJBRe94fWIC1cnN7Hzb 5JkCdreKWWSudhFlLBYT3av90wbwunr4PatY3yLslPOJ0sqPH2KU9RnofAAM8yAWwhiK mnWbcaGZMqYVbb8cW/MsYTvGxPr2KptdfHJ8JAoDjDunQs1wT3OobfAZTPvO/UZnp0ie VyMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date; bh=Lbf7DgzaGFcfNvaM2KqWvg7D8B8oETdPLTVE9MwyWyA=; b=64/bjjhpDt5qNZupHLgMHbzlVnZGEXSZpgq2kvmouCC6wP7rfE78eBoVZyCTCk73nz MKr/DVGL95vEZH2Gud25PQLSy8uNlIVVafgL5X92Ha/fmqHAkBEUVs9EjpjXGCQLcJSs eOPjEcsT2w5lJm3A8qAXnlWykadOD7WA2ek51vh03xP81nC2xgS5+MSLM/n9McFO3iIG yRKnadxy/JVCDq4bpUot48MiYLJ5S30pvVWcFFGuJfCK3SZjG9+lE1uQSpEygzzBuLx7 4IdK4zzDSb7g1PZIxYGHyeWyNiTKKxsi5/rC6RQjh9zNbesSDrXPamIpMuSM0vHZzpZI hKzQ== X-Gm-Message-State: ACrzQf0y70YzrCw+qeZoKFQdmPh3npmQmMXmrmqxFZp/X4Z0z0+i8XqD 33SRz/vHBdcfTIg3bucmxW1KOjugvkK1Ug== X-Google-Smtp-Source: AMsMyM7UkkYFU7thWBeE+K1/ByPF7FWvFlICQAxLaMBxEzw/tz9wN9Oz6zBlPyUQVD7PL0Y3PQpRZQ== X-Received: by 2002:adf:dbc3:0:b0:22a:d393:bd84 with SMTP id e3-20020adfdbc3000000b0022ad393bd84mr13600563wrj.626.1664814199791; Mon, 03 Oct 2022 09:23:19 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 3/3] docs/system/arm/emulation.rst: Report FEAT_GTG support Date: Mon, 3 Oct 2022 17:23:15 +0100 Message-Id: <20221003162315.2833797-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221003162315.2833797-1-peter.maydell@linaro.org> References: <20221003162315.2833797-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664815585014100001 Content-Type: text/plain; charset="utf-8" FEAT_GTG is a change tho the ID register ID_AA64MMFR0_EL1 so that it can report a different set of supported granule (page) sizes for stage 1 and stage 2 translation tables. As of commit c20281b2a5048 we already report the granule sizes that way for '-cpu max', and now we also correctly make attempts to use unimplemented granule sizes fail, so we can report the support of the feature in the documentation. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index be7bbffe595..cfb4b0768b0 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -31,6 +31,7 @@ the following architecture extensions: - FEAT_FRINTTS (Floating-point to integer instructions) - FEAT_FlagM (Flag manipulation instructions v2) - FEAT_FlagM2 (Enhancements to flag manipulation instructions) +- FEAT_GTG (Guest translation granule size) - FEAT_HCX (Support for the HCRX_EL2 register) - FEAT_HPDS (Hierarchical permission disables) - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) --=20 2.25.1