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([2a01:e0a:3cb:7bb0:5860:99c5:7ff3:cb36]) by smtp.gmail.com with ESMTPSA id z6-20020adfec86000000b0022b1d74dc56sm10040365wrn.79.2022.10.03.07.57.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Oct 2022 07:57:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date; bh=RV/X+WaJqNZO6nQexO9aMZi9OCWlE8Q3vDFCU19ehgg=; b=YcBNWgCzGgKluIVRv7kN/epE6GoK2NdrFIZeLZmi5o7vDBwZPVC4G+28FM+UF0Ne5D O9+5VywFmi035TNVRZKNGPyVGBdhYbNC9EB0kcrq7B5xEsF4s4XvGjjVk2cFqqkoL92O nh+U0eLxcpulGDcFJvkei4i0wnQauuY60cFAnvA8nLU0fTUQsr+xaQVqPpcWadV3ZJzW E70FE83xrow75jhRGdT58Wa9cwiU+8bSxdGjGfGR6CbWSQL31msxvCwl5ZwRE9INlIsl RDspmAZ7AJWaBEpxVONRr8863nAVOve7am22frKjLPSRxQk8RH3TUfq4fVVKJ4HPfhuQ LX3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date; bh=RV/X+WaJqNZO6nQexO9aMZi9OCWlE8Q3vDFCU19ehgg=; b=fOu58V9qBQHawlC6rHTCEE2QXkry2PWmzVjhNAgPvkzNfZ5rGRrv6wJs51SqFKdQfQ X/kdCPNw0UYB9mcg7LqXV6dH2jOwRMKCsI0EeTUTUgJEJ+POOYh4toyYWObqkTGN/rbQ N78OHKDGTdCHPgAHF6rSwxUAdnMPDlx5bohvY0PkNS9RplCgMSvb9Nk7XO110DJMO/9W jaljb53Dm0vxJV2TfskdAkRE613kjeLvhgNCf+x6BUJnHxpdsdmd2JX/Iyo9yFlmydwH f7WswE4wA5DoogkUYaIn74RQlW8vZP9XAo3ZlIuk6RNi7Vgj80hQ7lGbBNGJQXLtnAHo F+dg== X-Gm-Message-State: ACrzQf3Jrmt4t+5mPgEJF/sHgjC9Vko63/fKOlr3tKGjWHoPFDo0wXSm heuWL/HwDrsrYyFV8QJIJi+yLA== X-Google-Smtp-Source: AMsMyM7QW9KLxx1ok39dnt2to5KSw60xi9NAvZUh7CvtW7D3VgINZAFArT/GT0jl4RLkQngyEaBn3w== X-Received: by 2002:a5d:69c6:0:b0:22c:dbb2:d84 with SMTP id s6-20020a5d69c6000000b0022cdbb20d84mr12881189wrw.190.1664809029566; Mon, 03 Oct 2022 07:57:09 -0700 (PDT) From: Jerome Forissier To: Peter Maydell , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, Richard Henderson , Jerome Forissier , qemu-stable@nongnu.org Subject: [PATCH] hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3 Date: Mon, 3 Oct 2022 16:56:41 +0200 Message-Id: <20221003145641.1921467-1-jerome.forissier@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=jerome.forissier@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664809170749100001 Content-Type: text/plain; charset="utf-8" According to the Linux kernel booting.rst [1], CPTR_EL3.ESM and SCR_EL3.EnTP2 must be initialized to 1 when EL3 is present and FEAT_SME is advertised. This has to be taken care of when QEMU boots directly into the kernel (i.e., "-M virt,secure=3Don -cpu max -kernel Image"). Cc: qemu-stable@nongnu.org Fixes: 78cb9776662a ("target/arm: Enable SME for -cpu max") Link: [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.gi= t/tree/Documentation/arm64/booting.rst?h=3Dv6.0#n321 Signed-off-by: Jerome Forissier --- hw/arm/boot.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index ada2717f76..ee3858b673 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -763,6 +763,10 @@ static void do_cpu_reset(void *opaque) if (cpu_isar_feature(aa64_sve, cpu)) { env->cp15.cptr_el[3] |=3D R_CPTR_EL3_EZ_MASK; } + if (cpu_isar_feature(aa64_sme, cpu)) { + env->cp15.cptr_el[3] |=3D R_CPTR_EL3_ESM_MASK; + env->cp15.scr_el3 |=3D SCR_ENTP2; + } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); /* This hook is only supported for AArch32 currently: --=20 2.34.1