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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d12-20020a170902cecc00b0017732e4003bsm6108596plg.141.2022.10.02.21.14.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Oct 2022 21:14:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date; bh=F+mjQgSIAnozHseNrNKmVtq1cIhjeBBYAbGF2zpCiHk=; b=casen/B75ua/AN1X/YMfDM+FAcr5wke3RSjmNvTO3zcVlcjuixOQFb/vSQ+q3yU/6L 4/4SR8gFEnnci5HXxPUp1qs0I1iBhZvG0YU/BiCYQbXw9Ks5hUYkyMhR3oQ9jeA9zn9z 5yO0r6WHzd38+IMMr6foYTL1O4tPwZt86AP/bA6Bqm29oBbMsOzk3BZMcboWFTzDBKME CUXFxjiT9SMg+qdE3h+y8ZRXCmQAJzjZMRuDT2ZsWb+JxMjhDkWOn2qjfbZw0yqjRYxH B7HA/qCKFmFGbIYIbOkbX55OIJGlewufIg30yD3iTVHit/0zlr/I7i6U/lkRvzl1RhZ2 zDWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=F+mjQgSIAnozHseNrNKmVtq1cIhjeBBYAbGF2zpCiHk=; b=JSpq6gZO/lhZx0vz5bjzHwpYRAE40Nv6JFtjj4YxVzkzQNuqKMx4lzX5CRN+om0Zy4 VQLv2C/rWEX1A7FpMZOGc2rFeuhGP3/31gF0eliMY1hSo+rU6kH48Nb37HkyERL+bATY 6n6loMYZBPhKgENPkr6W6eswipzk4uNN3ExBJl8iYpdX7NgoBveze3Bkc56vN+XMVpcB LK2h44tuzGvSMnWL6Cx54vwTmcOcgE4lnogqrKJqU/3+5UYuXW6vNjpZl/80EfVBw0Us G80/dpdkNyUjWXTVaWj8qhrmFADJ5ytBN6c1uyplTeaB16nbkdD7FrlNh5W70S5FIV4/ HOEg== X-Gm-Message-State: ACrzQf2E673bBfkGcmrOpAuxaZ714YPI6lVsoKVePbuG7I9XhU9qO7+0 Nbab3Ww1rDlGI1r1FYcItnLLHttAGKFcVcNJ6BFnBHVpaXd0Ojblfg+kUMl78rdficVKFqCMyT3 s+gru3GHCkvVTzPIvAT8fzSTDNc+ILlAjG2zWmgtCi6OL30mSlhFSR3YhPpkyrKq2HJk= X-Google-Smtp-Source: AMsMyM6igbQ0Se816vi8zq5Px9W2pNLp3EF0yiD9tCWpm/16qcmmUvr7272YseSfpbErnWy6qcXo5Q== X-Received: by 2002:a05:6a00:24d2:b0:542:f6e3:e18d with SMTP id d18-20020a056a0024d200b00542f6e3e18dmr20397910pfv.36.1664770498221; Sun, 02 Oct 2022 21:14:58 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair Francis , Bin Meng , Palmer Dabbelt , chigot@adacore.com, Jim Shu Subject: [PATCH v3 2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field Date: Mon, 3 Oct 2022 04:14:40 +0000 Message-Id: <20221003041440.2320-3-jim.shu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221003041440.2320-1-jim.shu@sifive.com> References: <20221003041440.2320-1-jim.shu@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=jim.shu@sifive.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1664770764845100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" PLIC spec [1] requires interrupt source priority registers are WARL field and the number of supported priority is power-of-2 to simplify SW discovery. Existing QEMU RISC-V machine (e.g. shakti_c) don't strictly follow PLIC spec, whose number of supported priority is not power-of-2. Just change each bit of interrupt priority register to WARL field when the number of supported priority is power-of-2. [1] https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#in= terrupt-priorities Signed-off-by: Jim Shu Acked-by: Alistair Francis Reviewed-by: Cl=C3=A9ment Chigot --- hw/intc/sifive_plic.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index f864efa761..c2dfacf028 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -180,7 +180,15 @@ static void sifive_plic_write(void *opaque, hwaddr add= r, uint64_t value, if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) { uint32_t irq =3D ((addr - plic->priority_base) >> 2) + 1; =20 - if (value <=3D plic->num_priorities) { + if (((plic->num_priorities + 1) & plic->num_priorities) =3D=3D 0) { + /* + * if "num_priorities + 1" is power-of-2, make each register b= it of + * interrupt priority WARL (Write-Any-Read-Legal). Just filter + * out the access to unsupported priority bits. + */ + plic->source_priority[irq] =3D value % (plic->num_priorities += 1); + sifive_plic_update(plic); + } else if (value <=3D plic->num_priorities) { plic->source_priority[irq] =3D value; sifive_plic_update(plic); } @@ -207,7 +215,16 @@ static void sifive_plic_write(void *opaque, hwaddr add= r, uint64_t value, uint32_t contextid =3D (addr & (plic->context_stride - 1)); =20 if (contextid =3D=3D 0) { - if (value <=3D plic->num_priorities) { + if (((plic->num_priorities + 1) & plic->num_priorities) =3D=3D= 0) { + /* + * if "num_priorities + 1" is power-of-2, each register bi= t of + * interrupt priority is WARL (Write-Any-Read-Legal). Just + * filter out the access to unsupported priority bits. + */ + plic->target_priority[addrid] =3D value % + (plic->num_priorities + 1); + sifive_plic_update(plic); + } else if (value <=3D plic->num_priorities) { plic->target_priority[addrid] =3D value; sifive_plic_update(plic); } --=20 2.17.1