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([2605:ef80:8002:3cad:72cd:dd96:98f6:c3cf]) by smtp.gmail.com with ESMTPSA id 135-20020a62168d000000b0056025ccc3bbsm2749783pfw.146.2022.10.02.10.30.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Oct 2022 10:30:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=C37fm5yl+2DkUpxiktitev4JizHs4y6eTIlsxlfhyQs=; b=Ut6kFlI3ntQrQoSeU4PIH7CV2RWgfCDBzN1g7Zc2NR0yJbtpYTvYFk1xGIx6V6Cvpd lK0BJA6NVgfBHcDw74uvwM/l9HKVEaQzbUs2bG2eIO8Mwgy1OberRT1Hubckm1K2AMcE DShw9/HxJNw55jGqZp69x5fx2UOH9TR6GefijgFFUdtjF6oclN8T7S4v0Ep+PUGizaLh ljMCLQyWdAC7ORjt38IkMo1ZzpNB+WKJrvJGsds2EKkLEZBrPEPYPrGBTEr00PCZVCQR ZKtz1WEK9tW9mCVtGz1dlkX9rLEqIYy+P4DJB8ZpvvTJRIkOEvcXCPfpWZ2gQCFhQJqN dIIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=C37fm5yl+2DkUpxiktitev4JizHs4y6eTIlsxlfhyQs=; b=YwbK8ILCJUVx5iluXCDMfpprA8Pc+rex/+PjjXZU1mGVJh06Lt2t66774EiyX8AHcX 99gjbE/v72uoYYOzlvYCORi36srJia8AdyM1DJPY0kRvVmZtWCh0R+/isFKZ2im2ppQl 35T4eIO8HnHBb0BIlwwLUptpA4Eiikoej997rbVE4nViQOTaDEHyaaj+iPoOK/PEFgQR AhSBujRqI5aRScY/sFmQRKPwLj5BSfyoao7A16fBX1kVFqdVxD6hVxkptscFpuw5J4kW 9XDGWcB3qyPRriFkpYdSG03JwVsvMLFHTLzQQgJh5HVpQRY3ZAbd27rod4da90qebUHj teuw== X-Gm-Message-State: ACrzQf2yE3F1rC+Rc0+jxVeAZX4Yi0vAFiAXlgQVJhMbN2E83IEwIADF VAFuwSD+bLtlMnKW8yW4d0HTs65qtBUIag== X-Google-Smtp-Source: AMsMyM59PM1kF3QfLNJ5Slq4vAH4cHOSQvk2hUMeB+hegyl0344KHS0xw+J47xqNI6QIr7SH2CVw0g== X-Received: by 2002:a65:5a82:0:b0:446:8ff8:fd4d with SMTP id c2-20020a655a82000000b004468ff8fd4dmr6442135pgt.560.1664731841863; Sun, 02 Oct 2022 10:30:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 8/9] target/i386: Use atomic operations for pte updates Date: Sun, 2 Oct 2022 10:29:55 -0700 Message-Id: <20221002172956.265735-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221002172956.265735-1-richard.henderson@linaro.org> References: <20221002172956.265735-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664732622774100001 Content-Type: text/plain; charset="utf-8" Use probe_access_full in order to resolve to a host address, which then lets us use a host cmpxchg to update the pte. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/279 Signed-off-by: Richard Henderson --- target/i386/tcg/sysemu/excp_helper.c | 242 +++++++++++++++++++-------- 1 file changed, 168 insertions(+), 74 deletions(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index d6b7de6eea..e8457e9b21 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -27,8 +27,8 @@ typedef struct TranslateParams { target_ulong cr3; int pg_mode; int mmu_idx; + int ptw_idx; MMUAccessType access_type; - bool use_stage2; } TranslateParams; =20 typedef struct TranslateResult { @@ -50,43 +50,106 @@ typedef struct TranslateFault { TranslateFaultStage2 stage2; } TranslateFault; =20 -#define PTE_HPHYS(ADDR) \ - do { \ - if (in->use_stage2) { \ - nested_in.addr =3D (ADDR); \ - if (!mmu_translate(env, &nested_in, out, err)) { \ - err->stage2 =3D S2_GPT; \ - return false; \ - } \ - (ADDR) =3D out->paddr; \ - } \ - } while (0) +typedef struct PTETranslate { + CPUX86State *env; + TranslateFault *err; + int ptw_idx; + void *haddr; + hwaddr gaddr; +} PTETranslate; + +static bool ptw_translate(PTETranslate *inout, hwaddr addr) +{ + CPUTLBEntryFull *full; + int flags; + + inout->gaddr =3D addr; + flags =3D probe_access_full(inout->env, addr, MMU_DATA_STORE, + inout->ptw_idx, true, &inout->haddr, &full, = 0); + + if (unlikely(flags & TLB_INVALID_MASK)) { + TranslateFault *err =3D inout->err; + + assert(inout->ptw_idx =3D=3D MMU_NESTED_IDX); + err->exception_index =3D 0; /* unused */ + err->error_code =3D inout->env->error_code; + err->cr2 =3D addr; + err->stage2 =3D S2_GPT; + return false; + } + return true; +} + +static inline uint32_t ptw_ldl(const PTETranslate *in) +{ + if (likely(in->haddr)) { + return ldl_p(in->haddr); + } + return cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0); +} + +static inline uint64_t ptw_ldq(const PTETranslate *in) +{ + if (likely(in->haddr)) { + return ldq_p(in->haddr); + } + return cpu_ldq_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0); +} + +/* + * Note that we can use a 32-bit cmpxchg for all page table entries, + * even 64-bit ones, because PG_PRESENT_MASK, PG_ACCESSED_MASK and + * PG_DIRTY_MASK are all in the low 32 bits. + */ +static bool ptw_setl_slow(const PTETranslate *in, uint32_t old, uint32_t n= ew) +{ + uint32_t cmp; + + /* Does x86 really perform a rmw cycle on mmio for ptw? */ + start_exclusive(); + cmp =3D cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0); + if (cmp =3D=3D old) { + cpu_stl_mmuidx_ra(in->env, in->gaddr, new, in->ptw_idx, 0); + } + end_exclusive(); + return cmp =3D=3D old; +} + +static inline bool ptw_setl(const PTETranslate *in, uint32_t old, uint32_t= set) +{ + if (set & ~old) { + uint32_t new =3D old | set; + if (likely(in->haddr)) { + old =3D cpu_to_le32(old); + new =3D cpu_to_le32(new); + return qatomic_cmpxchg((uint32_t *)in->haddr, old, new) =3D=3D= old; + } + return ptw_setl_slow(in, old, new); + } + return true; +} =20 static bool mmu_translate(CPUX86State *env, const TranslateParams *in, TranslateResult *out, TranslateFault *err) { - TranslateParams nested_in =3D { - /* Use store for page table entries, to allow A/D flag updates. */ - .access_type =3D MMU_DATA_STORE, - .cr3 =3D env->nested_cr3, - .pg_mode =3D env->nested_pg_mode, - .mmu_idx =3D MMU_USER_IDX, - .use_stage2 =3D false, - }; - - CPUState *cs =3D env_cpu(env); - X86CPU *cpu =3D env_archcpu(env); const int32_t a20_mask =3D x86_get_a20_mask(env); const target_ulong addr =3D in->addr; const int pg_mode =3D in->pg_mode; const bool is_user =3D (in->mmu_idx =3D=3D MMU_USER_IDX); const MMUAccessType access_type =3D in->access_type; - uint64_t ptep, pte; + uint64_t ptep, pte, rsvd_mask; + PTETranslate pte_trans =3D { + .env =3D env, + .err =3D err, + .ptw_idx =3D in->ptw_idx, + }; hwaddr pte_addr; - uint64_t rsvd_mask =3D PG_ADDRESS_MASK & ~MAKE_64BIT_MASK(0, cpu->phys= _bits); uint32_t pkr; int page_size; =20 + restart_all: + rsvd_mask =3D ~MAKE_64BIT_MASK(0, env_archcpu(env)->phys_bits); + rsvd_mask &=3D PG_ADDRESS_MASK; if (!(pg_mode & PG_MODE_NXE)) { rsvd_mask |=3D PG_NX_MASK; } @@ -100,17 +163,19 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, */ pte_addr =3D ((in->cr3 & ~0xfff) + (((addr >> 48) & 0x1ff) << 3)) & a20_mask; - PTE_HPHYS(pte_addr); - pte =3D x86_ldq_phys(cs, pte_addr); + if (!ptw_translate(&pte_trans, pte_addr)) { + return false; + } + restart_5: + pte =3D ptw_ldq(&pte_trans); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } if (pte & (rsvd_mask | PG_PSE_MASK)) { goto do_fault_rsvd; } - if (!(pte & PG_ACCESSED_MASK)) { - pte |=3D PG_ACCESSED_MASK; - x86_stl_phys_notdirty(cs, pte_addr, pte); + if (!ptw_setl(&pte_trans, pte, PG_ACCESSED_MASK)) { + goto restart_5; } ptep =3D pte ^ PG_NX_MASK; } else { @@ -123,17 +188,19 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, */ pte_addr =3D ((pte & PG_ADDRESS_MASK) + (((addr >> 39) & 0x1ff) << 3)) & a20_mask; - PTE_HPHYS(pte_addr); - pte =3D x86_ldq_phys(cs, pte_addr); + if (!ptw_translate(&pte_trans, pte_addr)) { + return false; + } + restart_4: + pte =3D ptw_ldq(&pte_trans); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } if (pte & (rsvd_mask | PG_PSE_MASK)) { goto do_fault_rsvd; } - if (!(pte & PG_ACCESSED_MASK)) { - pte |=3D PG_ACCESSED_MASK; - x86_stl_phys_notdirty(cs, pte_addr, pte); + if (!ptw_setl(&pte_trans, pte, PG_ACCESSED_MASK)) { + goto restart_4; } ptep &=3D pte ^ PG_NX_MASK; =20 @@ -142,19 +209,21 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, */ pte_addr =3D ((pte & PG_ADDRESS_MASK) + (((addr >> 30) & 0x1ff) << 3)) & a20_mask; - PTE_HPHYS(pte_addr); - pte =3D x86_ldq_phys(cs, pte_addr); + if (!ptw_translate(&pte_trans, pte_addr)) { + return false; + } + restart_3_lma: + pte =3D ptw_ldq(&pte_trans); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } if (pte & rsvd_mask) { goto do_fault_rsvd; } - ptep &=3D pte ^ PG_NX_MASK; - if (!(pte & PG_ACCESSED_MASK)) { - pte |=3D PG_ACCESSED_MASK; - x86_stl_phys_notdirty(cs, pte_addr, pte); + if (!ptw_setl(&pte_trans, pte, PG_ACCESSED_MASK)) { + goto restart_3_lma; } + ptep &=3D pte ^ PG_NX_MASK; if (pte & PG_PSE_MASK) { /* 1 GB page */ page_size =3D 1024 * 1024 * 1024; @@ -167,15 +236,21 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, * Page table level 3 */ pte_addr =3D ((in->cr3 & ~0x1f) + ((addr >> 27) & 0x18)) & a20= _mask; - PTE_HPHYS(pte_addr); - pte =3D x86_ldq_phys(cs, pte_addr); + if (!ptw_translate(&pte_trans, pte_addr)) { + return false; + } + rsvd_mask |=3D PG_HI_USER_MASK; + restart_3_nolma: + pte =3D ptw_ldq(&pte_trans); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } - rsvd_mask |=3D PG_HI_USER_MASK; if (pte & (rsvd_mask | PG_NX_MASK)) { goto do_fault_rsvd; } + if (!ptw_setl(&pte_trans, pte, PG_ACCESSED_MASK)) { + goto restart_3_nolma; + } ptep =3D PG_NX_MASK | PG_USER_MASK | PG_RW_MASK; } =20 @@ -184,32 +259,37 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, */ pte_addr =3D ((pte & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) << 3)) & a20_mask; - PTE_HPHYS(pte_addr); - pte =3D x86_ldq_phys(cs, pte_addr); + if (!ptw_translate(&pte_trans, pte_addr)) { + return false; + } + restart_2_pae: + pte =3D ptw_ldq(&pte_trans); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } if (pte & rsvd_mask) { goto do_fault_rsvd; } - ptep &=3D pte ^ PG_NX_MASK; if (pte & PG_PSE_MASK) { /* 2 MB page */ page_size =3D 2048 * 1024; + ptep &=3D pte ^ PG_NX_MASK; goto do_check_protect; } - if (!(pte & PG_ACCESSED_MASK)) { - pte |=3D PG_ACCESSED_MASK; - x86_stl_phys_notdirty(cs, pte_addr, pte); + if (!ptw_setl(&pte_trans, pte, PG_ACCESSED_MASK)) { + goto restart_2_pae; } + ptep &=3D pte ^ PG_NX_MASK; =20 /* * Page table level 1 */ pte_addr =3D ((pte & PG_ADDRESS_MASK) + (((addr >> 12) & 0x1ff) << 3)) & a20_mask; - PTE_HPHYS(pte_addr); - pte =3D x86_ldq_phys(cs, pte_addr); + if (!ptw_translate(&pte_trans, pte_addr)) { + return false; + } + pte =3D ptw_ldq(&pte_trans); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -224,8 +304,11 @@ static bool mmu_translate(CPUX86State *env, const Tran= slateParams *in, * Page table level 2 */ pte_addr =3D ((in->cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_m= ask; - PTE_HPHYS(pte_addr); - pte =3D x86_ldl_phys(cs, pte_addr); + if (!ptw_translate(&pte_trans, pte_addr)) { + return false; + } + restart_2_nopae: + pte =3D ptw_ldl(&pte_trans); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -242,17 +325,18 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, rsvd_mask =3D 0x200000; goto do_check_protect_pse36; } - if (!(pte & PG_ACCESSED_MASK)) { - pte |=3D PG_ACCESSED_MASK; - x86_stl_phys_notdirty(cs, pte_addr, pte); + if (!ptw_setl(&pte_trans, pte, PG_ACCESSED_MASK)) { + goto restart_2_nopae; } =20 /* * Page table level 1 */ pte_addr =3D ((pte & ~0xfffu) + ((addr >> 10) & 0xffc)) & a20_mask; - PTE_HPHYS(pte_addr); - pte =3D x86_ldl_phys(cs, pte_addr); + if (!ptw_translate(&pte_trans, pte_addr)) { + return false; + } + pte =3D ptw_ldl(&pte_trans); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -319,27 +403,35 @@ do_check_protect_pse36: uint32_t set =3D PG_ACCESSED_MASK; if (access_type =3D=3D MMU_DATA_STORE) { set |=3D PG_DIRTY_MASK; + } else if (!(pte & PG_DIRTY_MASK)) { + /* + * Only set write access if already dirty... + * otherwise wait for dirty access. + */ + prot &=3D ~PAGE_WRITE; } - if (set & ~pte) { - pte |=3D set; - x86_stl_phys_notdirty(cs, pte_addr, pte); + if (!ptw_setl(&pte_trans, pte, set)) { + /* + * We can arrive here from any of 3 levels and 2 formats. + * The only safe thing is to restart the entire lookup. + */ + goto restart_all; } } =20 - if (!(pte & PG_DIRTY_MASK)) { - /* only set write access if already dirty... otherwise wait - for dirty access */ - assert(access_type !=3D MMU_DATA_STORE); - prot &=3D ~PAGE_WRITE; - } - /* align to page_size */ out->paddr =3D (pte & a20_mask & PG_ADDRESS_MASK & ~(page_size - 1)) | (addr & (page_size - 1)); =20 - if (in->use_stage2) { - nested_in.addr =3D out->paddr; - nested_in.access_type =3D access_type; + if (in->ptw_idx =3D=3D MMU_NESTED_IDX) { + TranslateParams nested_in =3D { + .addr =3D out->paddr, + .access_type =3D access_type, + .cr3 =3D env->nested_cr3, + .pg_mode =3D env->nested_pg_mode, + .mmu_idx =3D MMU_USER_IDX, + .ptw_idx =3D MMU_PHYS_IDX, + }; =20 if (!mmu_translate(env, &nested_in, out, err)) { err->stage2 =3D S2_GPA; @@ -436,7 +528,7 @@ static bool get_physical_address(CPUX86State *env, vadd= r addr, in.cr3 =3D env->nested_cr3; in.pg_mode =3D env->nested_pg_mode; in.mmu_idx =3D MMU_USER_IDX; - in.use_stage2 =3D false; + in.ptw_idx =3D MMU_PHYS_IDX; =20 if (!mmu_translate(env, &in, out, err)) { err->stage2 =3D S2_GPA; @@ -449,7 +541,7 @@ static bool get_physical_address(CPUX86State *env, vadd= r addr, default: in.cr3 =3D env->cr[3]; in.mmu_idx =3D mmu_idx; - in.use_stage2 =3D use_stage2; + in.ptw_idx =3D use_stage2 ? MMU_NESTED_IDX : MMU_PHYS_IDX; in.pg_mode =3D get_pg_mode(env); =20 if (likely(in.pg_mode)) { @@ -504,6 +596,8 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int siz= e, } =20 if (probe) { + /* This will be used if recursing for stage2 translation. */ + env->error_code =3D err.error_code; return false; } =20 --=20 2.34.1