From nobody Sat May 11 23:55:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664731988; cv=none; d=zohomail.com; s=zohoarc; b=P91CE5iaztM6882OfsMPt6ywt6aw0C44HZb+3fmlfW114kmA/nXDHkDvtToggtTzzXYp7vfFL8SiAEWye8/5FYQIyTKwwpWZ7NcHFFQE8Qc2UC5RgyVPOJhRGBJEPIlP7HeotmmaemTrv+X80liuWCpanOs29VbBVXgZhi3FU7k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664731988; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=D7KYNabvnNZChlZWMiOVnXqz2ASnpJf3GCFatgE5ov8=; b=CAKzDDICQVHrPBb7dyEk066aXSrc6WcxBMbnkaRYawjQIwQ+Vw3AIAb99ovmzP0iauHDQRuqSawrVwEkYwOGwEDLZowIJvRtYJN2ZPl0ssLVTKId6gDeJgS93VdPIhput2wErihI2YymaGQ21rRH0v2/1cr928bWBR2sFx5EPB8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664731988476523.7443391959605; Sun, 2 Oct 2022 10:33:08 -0700 (PDT) Received: from localhost ([::1]:40364 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1of2pv-0007fT-8k for importer@patchew.org; Sun, 02 Oct 2022 13:33:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44322) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1of2nO-0005SX-OZ for qemu-devel@nongnu.org; Sun, 02 Oct 2022 13:30:43 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:35527) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1of2nM-0006BB-MT for qemu-devel@nongnu.org; Sun, 02 Oct 2022 13:30:30 -0400 Received: by mail-pf1-x436.google.com with SMTP id i6so8409126pfb.2 for ; Sun, 02 Oct 2022 10:30:28 -0700 (PDT) Received: from stoup.. ([2605:ef80:8002:3cad:72cd:dd96:98f6:c3cf]) by smtp.gmail.com with ESMTPSA id 135-20020a62168d000000b0056025ccc3bbsm2749783pfw.146.2022.10.02.10.30.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Oct 2022 10:30:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=D7KYNabvnNZChlZWMiOVnXqz2ASnpJf3GCFatgE5ov8=; b=M2lE7HctTwIGVIvrFgxBA/1gzsFGcI4H4ycyZ9grYJc8lnsQqHiVcT0MHWnUJG90vE ft6ORPuYTRixiEm3HvOvRvda13pPMUxzkMMcCdnnBP001BYyetl1MaOh7U4f9IeI+Sw4 T7OICAFVjkiu7HDkvPZVaJG75nc9hc9t4RhN5m5ufpo+ikK1kl7hMUSucVO2fKMFcIgI PFBtEwj1WEDN08LPrRQVBGEV0vhL4pnwcVG2FUK0xJKle6OemJcuebI1G0ZWcozoCAds VuX6O5DLbMroYySJCrAD0vPKgDHpjeQJAR4UpfqlDFRpKjsFwWqW+JB4TtB9TUoa686A zv7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=D7KYNabvnNZChlZWMiOVnXqz2ASnpJf3GCFatgE5ov8=; b=pZYpVCJFrPn1auOYhsTu0xE2OkdCqmdiuKBuK1UgXOYgWSEfsZl60LiD+yn3d5kk1a w/gMJOL5eGcWaxXSf0nBpS1Gl3Cp+clES52vlrIMIahgjf1h3iJ5/7KEaD2Hn3ddXWq6 fq0+BWrZOpCd+uxZ0AXJ0RUkU92HMrT2GPIYa/pPgTTqBaU4T3m1IORmoJ+k0jyxNWpH 7rOFAnaH3VeULsKKuF7o9HI0FtbvpBWJlQN2VIWgmPWBgTCQkhqy3M//Fs2GAIQ5VXZG VCtFjsQSwMAWrEkx+U3vzAuvEWZ1nVFDuKKzVlgGVHDOEpFqvejrSaiP2S7px3T0y68n 4HBA== X-Gm-Message-State: ACrzQf0EcpIHyMw+6G/htlFJOcKPJ+lrCJn09rJvFIz7MgQ9MHvrNo9t +hIUACoTx4q5LpAd3UEofcNo9k/8mpwu9Q== X-Google-Smtp-Source: AMsMyM6iKU/tMyBmVCA3SXsOTZ94Yr1TdFu61pCJatd+mZus9rhGy9h9do4RRIx3/p7X5of3zWOcsg== X-Received: by 2002:a65:6c08:0:b0:448:c216:fe9 with SMTP id y8-20020a656c08000000b00448c2160fe9mr5715598pgu.243.1664731827193; Sun, 02 Oct 2022 10:30:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 1/9] target/i386: Use MMUAccessType across excp_helper.c Date: Sun, 2 Oct 2022 10:29:48 -0700 Message-Id: <20221002172956.265735-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221002172956.265735-1-richard.henderson@linaro.org> References: <20221002172956.265735-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664731990661100001 Content-Type: text/plain; charset="utf-8" Replace int is_write1 and magic numbers with the proper MMUAccessType access_type and enumerators. Signed-off-by: Richard Henderson --- target/i386/tcg/sysemu/excp_helper.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index 796dc2a1f3..eee59aa977 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -30,8 +30,10 @@ typedef hwaddr (*MMUTranslateFunc)(CPUState *cs, hwaddr = gphys, MMUAccessType acc #define GET_HPHYS(cs, gpa, access_type, prot) \ (get_hphys_func ? get_hphys_func(cs, gpa, access_type, prot) : gpa) =20 -static int mmu_translate(CPUState *cs, hwaddr addr, MMUTranslateFunc get_h= phys_func, - uint64_t cr3, int is_write1, int mmu_idx, int pg_= mode, +static int mmu_translate(CPUState *cs, hwaddr addr, + MMUTranslateFunc get_hphys_func, + uint64_t cr3, MMUAccessType access_type, + int mmu_idx, int pg_mode, hwaddr *xlat, int *page_size, int *prot) { X86CPU *cpu =3D X86_CPU(cs); @@ -40,13 +42,13 @@ static int mmu_translate(CPUState *cs, hwaddr addr, MMU= TranslateFunc get_hphys_f int32_t a20_mask; target_ulong pde_addr, pte_addr; int error_code =3D 0; - int is_dirty, is_write, is_user; + bool is_dirty, is_write, is_user; uint64_t rsvd_mask =3D PG_ADDRESS_MASK & ~MAKE_64BIT_MASK(0, cpu->phys= _bits); uint32_t page_offset; uint32_t pkr; =20 is_user =3D (mmu_idx =3D=3D MMU_USER_IDX); - is_write =3D is_write1 & 1; + is_write =3D (access_type =3D=3D MMU_DATA_STORE); a20_mask =3D x86_get_a20_mask(env); =20 if (!(pg_mode & PG_MODE_NXE)) { @@ -264,14 +266,14 @@ do_check_protect_pse36: } =20 *prot &=3D pkr_prot; - if ((pkr_prot & (1 << is_write1)) =3D=3D 0) { - assert(is_write1 !=3D 2); + if ((pkr_prot & (1 << access_type)) =3D=3D 0) { + assert(access_type !=3D MMU_INST_FETCH); error_code |=3D PG_ERROR_PK_MASK; goto do_fault_protect; } } =20 - if ((*prot & (1 << is_write1)) =3D=3D 0) { + if ((*prot & (1 << access_type)) =3D=3D 0) { goto do_fault_protect; } =20 @@ -297,7 +299,7 @@ do_check_protect_pse36: /* align to page_size */ pte &=3D PG_ADDRESS_MASK & ~(*page_size - 1); page_offset =3D addr & (*page_size - 1); - *xlat =3D GET_HPHYS(cs, pte + page_offset, is_write1, prot); + *xlat =3D GET_HPHYS(cs, pte + page_offset, access_type, prot); return PG_ERROR_OK; =20 do_fault_rsvd: @@ -308,7 +310,7 @@ do_check_protect_pse36: error_code |=3D (is_write << PG_ERROR_W_BIT); if (is_user) error_code |=3D PG_ERROR_U_MASK; - if (is_write1 =3D=3D 2 && + if (access_type =3D=3D MMU_INST_FETCH && ((pg_mode & PG_MODE_NXE) || (pg_mode & PG_MODE_SMEP))) error_code |=3D PG_ERROR_I_D_MASK; return error_code; @@ -353,7 +355,7 @@ hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessT= ype access_type, * 1 =3D generate PF fault */ static int handle_mmu_fault(CPUState *cs, vaddr addr, int size, - int is_write1, int mmu_idx) + MMUAccessType access_type, int mmu_idx) { X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; @@ -365,7 +367,7 @@ static int handle_mmu_fault(CPUState *cs, vaddr addr, i= nt size, =20 #if defined(DEBUG_MMU) printf("MMU fault: addr=3D%" VADDR_PRIx " w=3D%d mmu=3D%d eip=3D" TARG= ET_FMT_lx "\n", - addr, is_write1, mmu_idx, env->eip); + addr, access_type, mmu_idx, env->eip); #endif =20 if (!(env->cr[0] & CR0_PG_MASK)) { @@ -393,7 +395,7 @@ static int handle_mmu_fault(CPUState *cs, vaddr addr, i= nt size, } } =20 - error_code =3D mmu_translate(cs, addr, get_hphys, env->cr[3], is_w= rite1, + error_code =3D mmu_translate(cs, addr, get_hphys, env->cr[3], acce= ss_type, mmu_idx, pg_mode, &paddr, &page_size, &prot); } @@ -404,7 +406,7 @@ static int handle_mmu_fault(CPUState *cs, vaddr addr, i= nt size, vaddr =3D addr & TARGET_PAGE_MASK; paddr &=3D TARGET_PAGE_MASK; =20 - assert(prot & (1 << is_write1)); + assert(prot & (1 << access_type)); tlb_set_page_with_attrs(cs, vaddr, paddr, cpu_get_mem_attrs(env), prot, mmu_idx, page_size); return 0; --=20 2.34.1 From nobody Sat May 11 23:55:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2605:ef80:8002:3cad:72cd:dd96:98f6:c3cf]) by smtp.gmail.com with ESMTPSA id 135-20020a62168d000000b0056025ccc3bbsm2749783pfw.146.2022.10.02.10.30.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Oct 2022 10:30:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=LEJVqUhskGeG1MhK0CsszCgPcQtH98gJ6ePcJwlk5nI=; b=hKE4l0sJZz6bYHI/i6Knryi1tN7ogOk8v7KTDoT/fXQF6wJT+H8+rZW3lTABjkzZ/S nWDfzsYO/iPbpg4w68bvadMIdkmRvL6hmXpJL9v0X1GS+S9eh39Ykhsbk0uf7AjG8MgY e20wQ9dbfue194RXIaLlwgsUJPSABvjZTr5KkoQpmAFItyJ+7hSLEDXL9jcdVHLhUi7k s+vL0hqLsxE5LL+oTKy5p0L/hr5aqOm2ZscfMRNWpAewgpZkXl9TtQtHTTPaZMeW4D+N lqfnmQrZN3eilUxP2xxDjgVogRR+k+b6e9pM2HQAXy/7bNFchB3TxjTfNxbb3CEWK9kD q2iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=LEJVqUhskGeG1MhK0CsszCgPcQtH98gJ6ePcJwlk5nI=; b=EiuwJRXUEj3oJAjJMm9vQPKZ4dXWiFLgKoMQ0d1ytupnDH8jVkXZ0q4Q60/bF8FXtR hDtEz60N1JYfaTO9YMfK+KgSOgw10nazr6dOaQ5bvBB7PCFKs8KOfZRG8fhESKGeOG59 56M5GYO2sBXWx8dYLPY7Sd+u+8hxe5DZqyKCG1J1SNn1nevEWtT6/kwoViXMUbuLXuHO gqv68ORQ0zE3JcKes5iuNv9A/pj7yzehAM7/ajSR6g+LO9nAxbRKuDaxbSRWOHNxRMbi brixxt3KCB7ocW5wO9zbFwEpy2PJnV+Qni0zBCPX+/Gh5WO/XNHOWfnHocJU8btzknVm dvWQ== X-Gm-Message-State: ACrzQf2psC76SfgOeR3Vg2gWi10Q3YICRGVG1gwkgoUKfClcBmUgrEfi BoCH9lJN19BxY7rUMf3Pdj0AJNOT5ke5Bg== X-Google-Smtp-Source: AMsMyM4w8QPLe1UipWTPOkXignppZhXEM2GrKtbyc3OaEJpAxTvsa7BR74Rg037iTyko0mhgwUzhjg== X-Received: by 2002:a17:902:db0a:b0:178:32b9:6f51 with SMTP id m10-20020a170902db0a00b0017832b96f51mr18270766plx.145.1664731829294; Sun, 02 Oct 2022 10:30:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 2/9] target/i386: Direct call get_hphys from mmu_translate Date: Sun, 2 Oct 2022 10:29:49 -0700 Message-Id: <20221002172956.265735-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221002172956.265735-1-richard.henderson@linaro.org> References: <20221002172956.265735-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664732371510100001 Content-Type: text/plain; charset="utf-8" Use a boolean to control the call to get_hphys instead of passing a null function pointer. Signed-off-by: Richard Henderson --- target/i386/tcg/sysemu/excp_helper.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index eee59aa977..c9f6afba29 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -24,14 +24,10 @@ =20 #define PG_ERROR_OK (-1) =20 -typedef hwaddr (*MMUTranslateFunc)(CPUState *cs, hwaddr gphys, MMUAccessTy= pe access_type, - int *prot); - #define GET_HPHYS(cs, gpa, access_type, prot) \ - (get_hphys_func ? get_hphys_func(cs, gpa, access_type, prot) : gpa) + (use_stage2 ? get_hphys(cs, gpa, access_type, prot) : gpa) =20 -static int mmu_translate(CPUState *cs, hwaddr addr, - MMUTranslateFunc get_hphys_func, +static int mmu_translate(CPUState *cs, hwaddr addr, bool use_stage2, uint64_t cr3, MMUAccessType access_type, int mmu_idx, int pg_mode, hwaddr *xlat, int *page_size, int *prot) @@ -329,7 +325,7 @@ hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessT= ype access_type, return gphys; } =20 - exit_info_1 =3D mmu_translate(cs, gphys, NULL, env->nested_cr3, + exit_info_1 =3D mmu_translate(cs, gphys, false, env->nested_cr3, access_type, MMU_USER_IDX, env->nested_pg_m= ode, &hphys, &page_size, &next_prot); if (exit_info_1 =3D=3D PG_ERROR_OK) { @@ -395,7 +391,7 @@ static int handle_mmu_fault(CPUState *cs, vaddr addr, i= nt size, } } =20 - error_code =3D mmu_translate(cs, addr, get_hphys, env->cr[3], acce= ss_type, + error_code =3D mmu_translate(cs, addr, true, env->cr[3], access_ty= pe, mmu_idx, pg_mode, &paddr, &page_size, &prot); } --=20 2.34.1 From nobody Sat May 11 23:55:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664732231; cv=none; d=zohomail.com; s=zohoarc; b=gVbSQLzd1G4qjEMVGedeN+pp3A+UDPYBeq4WehHexlBTWN+gI6xr7+3Dp7Ri2HdqWY+XNbdIboCtjxuRykyKApiQsi9GSXdHkTOhHaGAvvsmQLMIW6Y4H05Y1HzpPJ2M4Re/+VYhTsd67Vpk9vjvAAw2mjjR4kc3DMGYPC19FUQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664732231; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eSyXIPxnSfJv4KTx45fDzIMqON6eUhifkXEE6zOJl1g=; b=SqsPx0H4KS/Pz9xjjYA5pWM/X/QOaiCQvjy+Wiecq5V+XDrdiDqlnIM2ukDmd3qK0vjl/LaEYG8VNk2qM6a2sff0/EZdzVnESQ48Pt4jGS8Y5dBqHSJhDCWLqyINw5EOAVC5qDUmPwFjnF54RvSAH3OpL0ybwol4XZcjKtKqnsw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664732231583794.5040399268089; Sun, 2 Oct 2022 10:37:11 -0700 (PDT) Received: from localhost ([::1]:44972 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1of2tp-0006bu-H5 for importer@patchew.org; Sun, 02 Oct 2022 13:37:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59414) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1of2nV-0005Sh-Vc for qemu-devel@nongnu.org; Sun, 02 Oct 2022 13:30:43 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:33561) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1of2nR-0006BU-BX for qemu-devel@nongnu.org; Sun, 02 Oct 2022 13:30:35 -0400 Received: by mail-pf1-x435.google.com with SMTP id w2so8416099pfb.0 for ; Sun, 02 Oct 2022 10:30:32 -0700 (PDT) Received: from stoup.. ([2605:ef80:8002:3cad:72cd:dd96:98f6:c3cf]) by smtp.gmail.com with ESMTPSA id 135-20020a62168d000000b0056025ccc3bbsm2749783pfw.146.2022.10.02.10.30.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Oct 2022 10:30:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=eSyXIPxnSfJv4KTx45fDzIMqON6eUhifkXEE6zOJl1g=; b=f+Gbo3Kw6k0QJo64zpVfkQKzAv3UfpbzFHoYGxveykErr9INc5L1RM6hj1DJnmjpn/ 85ZguURDEYRuqh6bXUVsL78VM5HuhrxCAjKCuqbXm/N7MUpv2z9Pw4eYm5NZL9TPgrx4 Von1pXCORU7j4IUZoGTwjWaCmFbFCIArB03aGRj5R514MnwR2GsYEoL1O+tyxhI0xtEH L6BZ6Il8Sd50PQdzUUXLcvojq/Bth/BM4FvIwerUfxDGBsTOXsjFxfplOXcGWfznKmMp W0Xb061Hz6spZOm6XAZfkHkO9NnFfR0pID+bh52lt3qHs2gnIfLAIloafOBPYqXkcH+Y t6WA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=eSyXIPxnSfJv4KTx45fDzIMqON6eUhifkXEE6zOJl1g=; b=wuG2kF4BFnZHXU593aXcGH/a7YwO2b/M7p2AlJRHOC9fCUoXtcqYIuVxSRff0A8uA9 qfziz18LWtOqvDcrK5/5fnlJxNRlLv9nfrTt6Qs9RKJQneA3lQ+T3pkLxZ9+kEnYPdJu wNGBVOkNcqzRtQTs9BiIWV/2en4bN6VFDapBfPjkbvwJjV/FDFU1jGdnKWW8joIMQWJK 3E1vpjvdiNpYUYYjvchFtZMXxFBx4//1IvTlsv68yYtXm/xmGh3wrapOknx3zwIhog+l Z8iKpuiLQSz9fOS34qOwMqdS0EjlNSIBSOYAoYoO4snrHNTMOvkPyOd7b+DHSSK51YJn 6/Bw== X-Gm-Message-State: ACrzQf0JpSKSonyR4FYmwxF5hZ0j2HsBuk2nXgtxLV3/XU4IzEIyRT44 33N/kjchQ9zruvm8CapI8h2dXQfUakQ7pw== X-Google-Smtp-Source: AMsMyM5MmdhSxFz/y1hl9R2lKoXGSj1uGHccRMib8SMCQ9l1KFoyYHrJrWfDXyXlDcfwVv921tnbHg== X-Received: by 2002:a05:6a00:e8f:b0:536:c98e:8307 with SMTP id bo15-20020a056a000e8f00b00536c98e8307mr18919574pfb.73.1664731831694; Sun, 02 Oct 2022 10:30:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 3/9] target/i386: Introduce structures for mmu_translate Date: Sun, 2 Oct 2022 10:29:50 -0700 Message-Id: <20221002172956.265735-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221002172956.265735-1-richard.henderson@linaro.org> References: <20221002172956.265735-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664732232257100001 Content-Type: text/plain; charset="utf-8" Create TranslateParams for inputs, TranslateResults for successful outputs, and TranslateFault for error outputs; return true on success. Move stage1 error paths from handle_mmu_fault to x86_cpu_tlb_fill; reorg the rest of handle_mmu_fault into get_physical_address. Signed-off-by: Richard Henderson --- target/i386/tcg/sysemu/excp_helper.c | 322 ++++++++++++++------------- 1 file changed, 171 insertions(+), 151 deletions(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index c9f6afba29..00ce4cf253 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -22,30 +22,45 @@ #include "exec/exec-all.h" #include "tcg/helper-tcg.h" =20 -#define PG_ERROR_OK (-1) +typedef struct TranslateParams { + target_ulong addr; + target_ulong cr3; + int pg_mode; + int mmu_idx; + MMUAccessType access_type; + bool use_stage2; +} TranslateParams; + +typedef struct TranslateResult { + hwaddr paddr; + int prot; + int page_size; +} TranslateResult; + +typedef struct TranslateFault { + int exception_index; + int error_code; + target_ulong cr2; +} TranslateFault; =20 #define GET_HPHYS(cs, gpa, access_type, prot) \ - (use_stage2 ? get_hphys(cs, gpa, access_type, prot) : gpa) + (in->use_stage2 ? get_hphys(cs, gpa, access_type, prot) : gpa) =20 -static int mmu_translate(CPUState *cs, hwaddr addr, bool use_stage2, - uint64_t cr3, MMUAccessType access_type, - int mmu_idx, int pg_mode, - hwaddr *xlat, int *page_size, int *prot) +static bool mmu_translate(CPUX86State *env, const TranslateParams *in, + TranslateResult *out, TranslateFault *err) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUState *cs =3D env_cpu(env); + X86CPU *cpu =3D env_archcpu(env); + const int32_t a20_mask =3D x86_get_a20_mask(env); + const target_ulong addr =3D in->addr; + const int pg_mode =3D in->pg_mode; + const bool is_user =3D (in->mmu_idx =3D=3D MMU_USER_IDX); + const MMUAccessType access_type =3D in->access_type; uint64_t ptep, pte; - int32_t a20_mask; - target_ulong pde_addr, pte_addr; - int error_code =3D 0; - bool is_dirty, is_write, is_user; + hwaddr pde_addr, pte_addr; uint64_t rsvd_mask =3D PG_ADDRESS_MASK & ~MAKE_64BIT_MASK(0, cpu->phys= _bits); - uint32_t page_offset; uint32_t pkr; - - is_user =3D (mmu_idx =3D=3D MMU_USER_IDX); - is_write =3D (access_type =3D=3D MMU_DATA_STORE); - a20_mask =3D x86_get_a20_mask(env); + int page_size; =20 if (!(pg_mode & PG_MODE_NXE)) { rsvd_mask |=3D PG_NX_MASK; @@ -62,7 +77,7 @@ static int mmu_translate(CPUState *cs, hwaddr addr, bool = use_stage2, uint64_t pml4e_addr, pml4e; =20 if (la57) { - pml5e_addr =3D ((cr3 & ~0xfff) + + pml5e_addr =3D ((in->cr3 & ~0xfff) + (((addr >> 48) & 0x1ff) << 3)) & a20_mask; pml5e_addr =3D GET_HPHYS(cs, pml5e_addr, MMU_DATA_STORE, N= ULL); pml5e =3D x86_ldq_phys(cs, pml5e_addr); @@ -78,7 +93,7 @@ static int mmu_translate(CPUState *cs, hwaddr addr, bool = use_stage2, } ptep =3D pml5e ^ PG_NX_MASK; } else { - pml5e =3D cr3; + pml5e =3D in->cr3; ptep =3D PG_NX_MASK | PG_USER_MASK | PG_RW_MASK; } =20 @@ -114,7 +129,7 @@ static int mmu_translate(CPUState *cs, hwaddr addr, boo= l use_stage2, } if (pdpe & PG_PSE_MASK) { /* 1 GB page */ - *page_size =3D 1024 * 1024 * 1024; + page_size =3D 1024 * 1024 * 1024; pte_addr =3D pdpe_addr; pte =3D pdpe; goto do_check_protect; @@ -123,7 +138,7 @@ static int mmu_translate(CPUState *cs, hwaddr addr, boo= l use_stage2, #endif { /* XXX: load them when cr3 is loaded ? */ - pdpe_addr =3D ((cr3 & ~0x1f) + ((addr >> 27) & 0x18)) & + pdpe_addr =3D ((in->cr3 & ~0x1f) + ((addr >> 27) & 0x18)) & a20_mask; pdpe_addr =3D GET_HPHYS(cs, pdpe_addr, MMU_DATA_STORE, NULL); pdpe =3D x86_ldq_phys(cs, pdpe_addr); @@ -150,7 +165,7 @@ static int mmu_translate(CPUState *cs, hwaddr addr, boo= l use_stage2, ptep &=3D pde ^ PG_NX_MASK; if (pde & PG_PSE_MASK) { /* 2 MB page */ - *page_size =3D 2048 * 1024; + page_size =3D 2048 * 1024; pte_addr =3D pde_addr; pte =3D pde; goto do_check_protect; @@ -172,12 +187,12 @@ static int mmu_translate(CPUState *cs, hwaddr addr, b= ool use_stage2, } /* combine pde and pte nx, user and rw protections */ ptep &=3D pte ^ PG_NX_MASK; - *page_size =3D 4096; + page_size =3D 4096; } else { uint32_t pde; =20 /* page directory entry */ - pde_addr =3D ((cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) & + pde_addr =3D ((in->cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_mask; pde_addr =3D GET_HPHYS(cs, pde_addr, MMU_DATA_STORE, NULL); pde =3D x86_ldl_phys(cs, pde_addr); @@ -188,7 +203,7 @@ static int mmu_translate(CPUState *cs, hwaddr addr, boo= l use_stage2, =20 /* if PSE bit is set, then we use a 4MB page */ if ((pde & PG_PSE_MASK) && (pg_mode & PG_MODE_PSE)) { - *page_size =3D 4096 * 1024; + page_size =3D 4096 * 1024; pte_addr =3D pde_addr; =20 /* Bits 20-13 provide bits 39-32 of the address, bit 21 is res= erved. @@ -214,12 +229,12 @@ static int mmu_translate(CPUState *cs, hwaddr addr, b= ool use_stage2, } /* combine pde and pte user and rw protections */ ptep &=3D pte | PG_NX_MASK; - *page_size =3D 4096; + page_size =3D 4096; rsvd_mask =3D 0; } =20 do_check_protect: - rsvd_mask |=3D (*page_size - 1) & PG_ADDRESS_MASK & ~PG_PSE_PAT_MASK; + rsvd_mask |=3D (page_size - 1) & PG_ADDRESS_MASK & ~PG_PSE_PAT_MASK; do_check_protect_pse36: if (pte & rsvd_mask) { goto do_fault_rsvd; @@ -231,17 +246,17 @@ do_check_protect_pse36: goto do_fault_protect; } =20 - *prot =3D 0; - if (mmu_idx !=3D MMU_KSMAP_IDX || !(ptep & PG_USER_MASK)) { - *prot |=3D PAGE_READ; + int prot =3D 0; + if (in->mmu_idx !=3D MMU_KSMAP_IDX || !(ptep & PG_USER_MASK)) { + prot |=3D PAGE_READ; if ((ptep & PG_RW_MASK) || !(is_user || (pg_mode & PG_MODE_WP))) { - *prot |=3D PAGE_WRITE; + prot |=3D PAGE_WRITE; } } if (!(ptep & PG_NX_MASK) && - (mmu_idx =3D=3D MMU_USER_IDX || + (is_user || !((pg_mode & PG_MODE_SMEP) && (ptep & PG_USER_MASK)))) { - *prot |=3D PAGE_EXEC; + prot |=3D PAGE_EXEC; } =20 if (ptep & PG_USER_MASK) { @@ -260,164 +275,151 @@ do_check_protect_pse36: } else if (pkr_wd && (is_user || (pg_mode & PG_MODE_WP))) { pkr_prot &=3D ~PAGE_WRITE; } - - *prot &=3D pkr_prot; if ((pkr_prot & (1 << access_type)) =3D=3D 0) { - assert(access_type !=3D MMU_INST_FETCH); - error_code |=3D PG_ERROR_PK_MASK; - goto do_fault_protect; + goto do_fault_pk_protect; } + prot &=3D pkr_prot; } =20 - if ((*prot & (1 << access_type)) =3D=3D 0) { + if ((prot & (1 << access_type)) =3D=3D 0) { goto do_fault_protect; } =20 /* yes, it can! */ - is_dirty =3D is_write && !(pte & PG_DIRTY_MASK); - if (!(pte & PG_ACCESSED_MASK) || is_dirty) { - pte |=3D PG_ACCESSED_MASK; - if (is_dirty) { - pte |=3D PG_DIRTY_MASK; + { + uint32_t set =3D PG_ACCESSED_MASK; + if (access_type =3D=3D MMU_DATA_STORE) { + set |=3D PG_DIRTY_MASK; + } + if (set & ~pte) { + pte |=3D set; + x86_stl_phys_notdirty(cs, pte_addr, pte); } - x86_stl_phys_notdirty(cs, pte_addr, pte); } =20 if (!(pte & PG_DIRTY_MASK)) { /* only set write access if already dirty... otherwise wait for dirty access */ - assert(!is_write); - *prot &=3D ~PAGE_WRITE; + assert(access_type !=3D MMU_DATA_STORE); + prot &=3D ~PAGE_WRITE; } - - pte =3D pte & a20_mask; + out->prot =3D prot; + out->page_size =3D page_size; =20 /* align to page_size */ - pte &=3D PG_ADDRESS_MASK & ~(*page_size - 1); - page_offset =3D addr & (*page_size - 1); - *xlat =3D GET_HPHYS(cs, pte + page_offset, access_type, prot); - return PG_ERROR_OK; + out->paddr =3D (pte & a20_mask & PG_ADDRESS_MASK & ~(page_size - 1)) + | (addr & (page_size - 1)); + out->paddr =3D GET_HPHYS(cs, out->paddr, access_type, &out->prot); + return true; =20 + int error_code; do_fault_rsvd: - error_code |=3D PG_ERROR_RSVD_MASK; + error_code =3D PG_ERROR_RSVD_MASK; + goto do_fault_cont; do_fault_protect: - error_code |=3D PG_ERROR_P_MASK; + error_code =3D PG_ERROR_P_MASK; + goto do_fault_cont; + do_fault_pk_protect: + assert(access_type !=3D MMU_INST_FETCH); + error_code =3D PG_ERROR_PK_MASK | PG_ERROR_P_MASK; + goto do_fault_cont; do_fault: - error_code |=3D (is_write << PG_ERROR_W_BIT); - if (is_user) + error_code =3D 0; + do_fault_cont: + if (is_user) { error_code |=3D PG_ERROR_U_MASK; - if (access_type =3D=3D MMU_INST_FETCH && - ((pg_mode & PG_MODE_NXE) || (pg_mode & PG_MODE_SMEP))) - error_code |=3D PG_ERROR_I_D_MASK; - return error_code; + } + switch (access_type) { + case MMU_DATA_LOAD: + break; + case MMU_DATA_STORE: + error_code |=3D PG_ERROR_W_MASK; + break; + case MMU_INST_FETCH: + if (pg_mode & (PG_MODE_NXE | PG_MODE_SMEP)) { + error_code |=3D PG_ERROR_I_D_MASK; + } + break; + } + err->exception_index =3D EXCP0E_PAGE; + err->error_code =3D error_code; + err->cr2 =3D addr; + return false; } =20 hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type, - int *prot) + int *prot) { CPUX86State *env =3D &X86_CPU(cs)->env; - uint64_t exit_info_1; - int page_size; - int next_prot; - hwaddr hphys; =20 if (likely(!(env->hflags2 & HF2_NPT_MASK))) { return gphys; - } + } else { + TranslateParams in =3D { + .addr =3D gphys, + .cr3 =3D env->nested_cr3, + .pg_mode =3D env->nested_pg_mode, + .mmu_idx =3D MMU_USER_IDX, + .access_type =3D access_type, + .use_stage2 =3D false, + }; + TranslateResult out; + TranslateFault err; + uint64_t exit_info_1; =20 - exit_info_1 =3D mmu_translate(cs, gphys, false, env->nested_cr3, - access_type, MMU_USER_IDX, env->nested_pg_m= ode, - &hphys, &page_size, &next_prot); - if (exit_info_1 =3D=3D PG_ERROR_OK) { - if (prot) { - *prot &=3D next_prot; + if (mmu_translate(env, &in, &out, &err)) { + if (prot) { + *prot &=3D out.prot; + } + return out.paddr; } - return hphys; - } =20 - x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.exit_inf= o_2), - gphys); - if (prot) { - exit_info_1 |=3D SVM_NPTEXIT_GPA; - } else { /* page table access */ - exit_info_1 |=3D SVM_NPTEXIT_GPT; + x86_stq_phys(cs, env->vm_vmcb + + offsetof(struct vmcb, control.exit_info_2), gphys); + exit_info_1 =3D err.error_code + | (prot ? SVM_NPTEXIT_GPA : SVM_NPTEXIT_GPT); + cpu_vmexit(env, SVM_EXIT_NPF, exit_info_1, env->retaddr); } - cpu_vmexit(env, SVM_EXIT_NPF, exit_info_1, env->retaddr); } =20 -/* return value: - * -1 =3D cannot handle fault - * 0 =3D nothing more to do - * 1 =3D generate PF fault - */ -static int handle_mmu_fault(CPUState *cs, vaddr addr, int size, - MMUAccessType access_type, int mmu_idx) +static bool get_physical_address(CPUX86State *env, vaddr addr, + MMUAccessType access_type, int mmu_idx, + TranslateResult *out, TranslateFault *err) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - int error_code =3D PG_ERROR_OK; - int pg_mode, prot, page_size; - int32_t a20_mask; - hwaddr paddr; - hwaddr vaddr; - -#if defined(DEBUG_MMU) - printf("MMU fault: addr=3D%" VADDR_PRIx " w=3D%d mmu=3D%d eip=3D" TARG= ET_FMT_lx "\n", - addr, access_type, mmu_idx, env->eip); -#endif - if (!(env->cr[0] & CR0_PG_MASK)) { - a20_mask =3D x86_get_a20_mask(env); - paddr =3D addr & a20_mask; + out->paddr =3D addr & x86_get_a20_mask(env); + #ifdef TARGET_X86_64 if (!(env->hflags & HF_LMA_MASK)) { /* Without long mode we can only address 32bits in real mode */ - paddr =3D (uint32_t)paddr; + out->paddr =3D (uint32_t)out->paddr; } #endif - prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - page_size =3D 4096; + out->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + out->page_size =3D TARGET_PAGE_SIZE; + return true; } else { - pg_mode =3D get_pg_mode(env); - if (pg_mode & PG_MODE_LMA) { - int32_t sext; + TranslateParams in =3D { + .addr =3D addr, + .cr3 =3D env->cr[3], + .pg_mode =3D get_pg_mode(env), + .mmu_idx =3D mmu_idx, + .access_type =3D access_type, + .use_stage2 =3D true + }; =20 + if (in.pg_mode & PG_MODE_LMA) { /* test virtual address sign extension */ - sext =3D (int64_t)addr >> (pg_mode & PG_MODE_LA57 ? 56 : 47); + int shift =3D in.pg_mode & PG_MODE_LA57 ? 56 : 47; + int64_t sext =3D (int64_t)addr >> shift; if (sext !=3D 0 && sext !=3D -1) { - env->error_code =3D 0; - cs->exception_index =3D EXCP0D_GPF; - return 1; + err->exception_index =3D EXCP0D_GPF; + err->error_code =3D 0; + err->cr2 =3D addr; + return false; } } - - error_code =3D mmu_translate(cs, addr, true, env->cr[3], access_ty= pe, - mmu_idx, pg_mode, - &paddr, &page_size, &prot); - } - - if (error_code =3D=3D PG_ERROR_OK) { - /* Even if 4MB pages, we map only one 4KB page in the cache to - avoid filling it too fast */ - vaddr =3D addr & TARGET_PAGE_MASK; - paddr &=3D TARGET_PAGE_MASK; - - assert(prot & (1 << access_type)); - tlb_set_page_with_attrs(cs, vaddr, paddr, cpu_get_mem_attrs(env), - prot, mmu_idx, page_size); - return 0; - } else { - if (env->intercept_exceptions & (1 << EXCP0E_PAGE)) { - /* cr2 is not modified in case of exceptions */ - x86_stq_phys(cs, - env->vm_vmcb + offsetof(struct vmcb, control.exit_inf= o_2), - addr); - } else { - env->cr[2] =3D addr; - } - env->error_code =3D error_code; - cs->exception_index =3D EXCP0E_PAGE; - return 1; + return mmu_translate(env, &in, out, err); } } =20 @@ -425,17 +427,35 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int s= ize, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + CPUX86State *env =3D cs->env_ptr; + TranslateResult out; + TranslateFault err; =20 - env->retaddr =3D retaddr; - if (handle_mmu_fault(cs, addr, size, access_type, mmu_idx)) { - /* FIXME: On error in get_hphys we have already jumped out. */ - g_assert(!probe); - raise_exception_err_ra(env, cs->exception_index, - env->error_code, retaddr); + if (get_physical_address(env, addr, access_type, mmu_idx, &out, &err))= { + /* + * Even if 4MB pages, we map only one 4KB page in the cache to + * avoid filling it too fast. + */ + assert(out.prot & (1 << access_type)); + tlb_set_page_with_attrs(cs, addr & TARGET_PAGE_MASK, + out.paddr & TARGET_PAGE_MASK, + cpu_get_mem_attrs(env), + out.prot, mmu_idx, out.page_size); + return true; } - return true; + + /* FIXME: On error in get_hphys we have already jumped out. */ + g_assert(!probe); + + if (env->intercept_exceptions & (1 << err.exception_index)) { + /* cr2 is not modified in case of exceptions */ + x86_stq_phys(cs, env->vm_vmcb + + offsetof(struct vmcb, control.exit_info_2), + err.cr2); + } else { + env->cr[2] =3D err.cr2; + } + raise_exception_err_ra(env, err.exception_index, err.error_code, retad= dr); } =20 G_NORETURN void x86_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, --=20 2.34.1 From nobody Sat May 11 23:55:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664732462; cv=none; d=zohomail.com; s=zohoarc; b=PlEqyXz8xqbQwPQuY2K0OcrBy/NXvCU/XBwoJx64KgPjtk+8OmIsC7SeWH/rDGfTP+M+EXdCVi7bC5Vm61mni02PDIw1i7nR+TXhAmyoSy11CDgGNe8DoGvYD1msnOgukjNPRo+uZLp8ipHlj7zYYuGteH8bEc1ZPHSsag/Uceo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664732462; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([2605:ef80:8002:3cad:72cd:dd96:98f6:c3cf]) by smtp.gmail.com with ESMTPSA id 135-20020a62168d000000b0056025ccc3bbsm2749783pfw.146.2022.10.02.10.30.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Oct 2022 10:30:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=T8uWtBP3TZO6X3XhGgQrKyuC5IL3sIGd/gd8Mwr3t5A=; b=gdnpXsQwP2Zz4uU7G4xib6P+/8iqrRFcqnnOzRVlfo0jad+Ow+PWObSIoXoBw5/ExN gRxHXGM1cFg1IGGfavP4CWyX1iFpcTaYivnXzh+PPbzlA5jldBHRQ2CTsZdMXZS3uHew aAiXq6DAW/Zaw9xwvjmnkbs5gt1hWgSDv1r0Y8AlyXccCQ5sFat7Kt5v2FrMvMWmBR4X nJiCD+j3HQV6BT7G68TX7U2+sM2fmOcRrgoWiCzv7mDyeJGdxIPOspyAhRx8xiPcKR2k QEpD7jGZJe11ZNTrf7RJuX5Vecf8GwpMFMri/N+aSOXZocm/P+JIerSOrOPyJAl38c32 DCvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=T8uWtBP3TZO6X3XhGgQrKyuC5IL3sIGd/gd8Mwr3t5A=; b=fRmi6vnnaFDSvY2Mm1I3+pNAQACu0qVxZfR6t75JFFBSO+Te8jREtJVdflbSWHiWgI LGkLdWAd4/XFV7rOrGGNw9VE9YIxiyI7Yo90vxVVlzqru9khIIGbmDFotVWKRKjcj6hS 2nSWAOCmuPphOg1rw48dTWORCuGrG/TzjhWJNAGe5CIFvAbKNscNzWLMqkRzVj01+mTz R508uPrDkd+43hLb+4JfvmzvQULXhzz2mEE3PYizMlUscXOyV/5GLIteGT5uUREs4fBk k3v9qyPIKryBlI4zp/hmOB/lQAXMnbfS+s5ZfY7jrFR5mrZ1IPHBsk4VChigK/bqjAiD jgsA== X-Gm-Message-State: ACrzQf1Eq5ykDtOM3rca2jWLnXSdUErikD5GOZntzevpStJ/reux4BLE bjnOAWS/hidaPrgRz3eLqSVWqHHKSuivbg== X-Google-Smtp-Source: AMsMyM6Ppshro29vaIdbl9Hxjr1TyhbCMoGwYFMDUY7PrPICYvjkhA0yFy/QQsNdq4wrAMjPzhnpnQ== X-Received: by 2002:a05:6a00:1f05:b0:540:6552:dfbf with SMTP id be5-20020a056a001f0500b005406552dfbfmr18860159pfb.65.1664731833706; Sun, 02 Oct 2022 10:30:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 4/9] target/i386: Reorg GET_HPHYS Date: Sun, 2 Oct 2022 10:29:51 -0700 Message-Id: <20221002172956.265735-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221002172956.265735-1-richard.henderson@linaro.org> References: <20221002172956.265735-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664732463841100001 Content-Type: text/plain; charset="utf-8" Replace with PTE_HPHYS for the page table walk, and a direct call to mmu_translate for the final stage2 translation. Hoist the check for HF2_NPT_MASK out to get_physical_address, which avoids the recursive call when stage2 is disabled. We can now return all the way out to x86_cpu_tlb_fill before raising an exception, which means probe works. Signed-off-by: Richard Henderson --- target/i386/tcg/sysemu/excp_helper.c | 123 +++++++++++++++++++++------ 1 file changed, 95 insertions(+), 28 deletions(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index 00ce4cf253..816b307547 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -37,18 +37,43 @@ typedef struct TranslateResult { int page_size; } TranslateResult; =20 +typedef enum TranslateFaultStage2 { + S2_NONE, + S2_GPA, + S2_GPT, +} TranslateFaultStage2; + typedef struct TranslateFault { int exception_index; int error_code; target_ulong cr2; + TranslateFaultStage2 stage2; } TranslateFault; =20 -#define GET_HPHYS(cs, gpa, access_type, prot) \ - (in->use_stage2 ? get_hphys(cs, gpa, access_type, prot) : gpa) +#define PTE_HPHYS(ADDR) \ + do { \ + if (in->use_stage2) { \ + nested_in.addr =3D (ADDR); \ + if (!mmu_translate(env, &nested_in, out, err)) { \ + err->stage2 =3D S2_GPT; \ + return false; \ + } \ + (ADDR) =3D out->paddr; \ + } \ + } while (0) =20 static bool mmu_translate(CPUX86State *env, const TranslateParams *in, TranslateResult *out, TranslateFault *err) { + TranslateParams nested_in =3D { + /* Use store for page table entries, to allow A/D flag updates. */ + .access_type =3D MMU_DATA_STORE, + .cr3 =3D env->nested_cr3, + .pg_mode =3D env->nested_pg_mode, + .mmu_idx =3D MMU_USER_IDX, + .use_stage2 =3D false, + }; + CPUState *cs =3D env_cpu(env); X86CPU *cpu =3D env_archcpu(env); const int32_t a20_mask =3D x86_get_a20_mask(env); @@ -79,7 +104,7 @@ static bool mmu_translate(CPUX86State *env, const Transl= ateParams *in, if (la57) { pml5e_addr =3D ((in->cr3 & ~0xfff) + (((addr >> 48) & 0x1ff) << 3)) & a20_mask; - pml5e_addr =3D GET_HPHYS(cs, pml5e_addr, MMU_DATA_STORE, N= ULL); + PTE_HPHYS(pml5e_addr); pml5e =3D x86_ldq_phys(cs, pml5e_addr); if (!(pml5e & PG_PRESENT_MASK)) { goto do_fault; @@ -99,7 +124,7 @@ static bool mmu_translate(CPUX86State *env, const Transl= ateParams *in, =20 pml4e_addr =3D ((pml5e & PG_ADDRESS_MASK) + (((addr >> 39) & 0x1ff) << 3)) & a20_mask; - pml4e_addr =3D GET_HPHYS(cs, pml4e_addr, MMU_DATA_STORE, NULL); + PTE_HPHYS(pml4e_addr); pml4e =3D x86_ldq_phys(cs, pml4e_addr); if (!(pml4e & PG_PRESENT_MASK)) { goto do_fault; @@ -114,7 +139,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, ptep &=3D pml4e ^ PG_NX_MASK; pdpe_addr =3D ((pml4e & PG_ADDRESS_MASK) + (((addr >> 30) & 0x= 1ff) << 3)) & a20_mask; - pdpe_addr =3D GET_HPHYS(cs, pdpe_addr, MMU_DATA_STORE, NULL); + PTE_HPHYS(pdpe_addr); pdpe =3D x86_ldq_phys(cs, pdpe_addr); if (!(pdpe & PG_PRESENT_MASK)) { goto do_fault; @@ -140,7 +165,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* XXX: load them when cr3 is loaded ? */ pdpe_addr =3D ((in->cr3 & ~0x1f) + ((addr >> 27) & 0x18)) & a20_mask; - pdpe_addr =3D GET_HPHYS(cs, pdpe_addr, MMU_DATA_STORE, NULL); + PTE_HPHYS(pdpe_addr); pdpe =3D x86_ldq_phys(cs, pdpe_addr); if (!(pdpe & PG_PRESENT_MASK)) { goto do_fault; @@ -154,7 +179,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, =20 pde_addr =3D ((pdpe & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) <= < 3)) & a20_mask; - pde_addr =3D GET_HPHYS(cs, pde_addr, MMU_DATA_STORE, NULL); + PTE_HPHYS(pde_addr); pde =3D x86_ldq_phys(cs, pde_addr); if (!(pde & PG_PRESENT_MASK)) { goto do_fault; @@ -177,7 +202,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, } pte_addr =3D ((pde & PG_ADDRESS_MASK) + (((addr >> 12) & 0x1ff) <<= 3)) & a20_mask; - pte_addr =3D GET_HPHYS(cs, pte_addr, MMU_DATA_STORE, NULL); + PTE_HPHYS(pte_addr); pte =3D x86_ldq_phys(cs, pte_addr); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; @@ -194,7 +219,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* page directory entry */ pde_addr =3D ((in->cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_mask; - pde_addr =3D GET_HPHYS(cs, pde_addr, MMU_DATA_STORE, NULL); + PTE_HPHYS(pde_addr); pde =3D x86_ldl_phys(cs, pde_addr); if (!(pde & PG_PRESENT_MASK)) { goto do_fault; @@ -222,7 +247,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* page directory entry */ pte_addr =3D ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & a20_mask; - pte_addr =3D GET_HPHYS(cs, pte_addr, MMU_DATA_STORE, NULL); + PTE_HPHYS(pte_addr); pte =3D x86_ldl_phys(cs, pte_addr); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; @@ -303,13 +328,31 @@ do_check_protect_pse36: assert(access_type !=3D MMU_DATA_STORE); prot &=3D ~PAGE_WRITE; } - out->prot =3D prot; - out->page_size =3D page_size; =20 /* align to page_size */ out->paddr =3D (pte & a20_mask & PG_ADDRESS_MASK & ~(page_size - 1)) | (addr & (page_size - 1)); - out->paddr =3D GET_HPHYS(cs, out->paddr, access_type, &out->prot); + + if (in->use_stage2) { + nested_in.addr =3D out->paddr; + nested_in.access_type =3D access_type; + + if (!mmu_translate(env, &nested_in, out, err)) { + err->stage2 =3D S2_GPA; + return false; + } + + /* Merge stage1 & stage2 protection bits. */ + prot &=3D out->prot; + + /* Re-verify resulting protection. */ + if ((prot & (1 << access_type)) =3D=3D 0) { + goto do_fault_protect; + } + } + + out->prot =3D prot; + out->page_size =3D page_size; return true; =20 int error_code; @@ -344,13 +387,36 @@ do_check_protect_pse36: err->exception_index =3D EXCP0E_PAGE; err->error_code =3D error_code; err->cr2 =3D addr; + err->stage2 =3D S2_NONE; return false; } =20 +static G_NORETURN void raise_stage2(CPUX86State *env, TranslateFault *err, + uintptr_t retaddr) +{ + uint64_t exit_info_1 =3D err->error_code; + + switch (err->stage2) { + case S2_GPT: + exit_info_1 |=3D SVM_NPTEXIT_GPT; + break; + case S2_GPA: + exit_info_1 |=3D SVM_NPTEXIT_GPA; + break; + default: + g_assert_not_reached(); + } + + x86_stq_phys(env_cpu(env), + env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2), + err->cr2); + cpu_vmexit(env, SVM_EXIT_NPF, exit_info_1, retaddr); +} + hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type, int *prot) { - CPUX86State *env =3D &X86_CPU(cs)->env; + CPUX86State *env =3D cs->env_ptr; =20 if (likely(!(env->hflags2 & HF2_NPT_MASK))) { return gphys; @@ -365,20 +431,16 @@ hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAcces= sType access_type, }; TranslateResult out; TranslateFault err; - uint64_t exit_info_1; =20 - if (mmu_translate(env, &in, &out, &err)) { - if (prot) { - *prot &=3D out.prot; - } - return out.paddr; + if (!mmu_translate(env, &in, &out, &err)) { + err.stage2 =3D prot ? SVM_NPTEXIT_GPA : SVM_NPTEXIT_GPT; + raise_stage2(env, &err, env->retaddr); } =20 - x86_stq_phys(cs, env->vm_vmcb + - offsetof(struct vmcb, control.exit_info_2), gphys); - exit_info_1 =3D err.error_code - | (prot ? SVM_NPTEXIT_GPA : SVM_NPTEXIT_GPT); - cpu_vmexit(env, SVM_EXIT_NPF, exit_info_1, env->retaddr); + if (prot) { + *prot &=3D out.prot; + } + return out.paddr; } } =20 @@ -405,7 +467,7 @@ static bool get_physical_address(CPUX86State *env, vadd= r addr, .pg_mode =3D get_pg_mode(env), .mmu_idx =3D mmu_idx, .access_type =3D access_type, - .use_stage2 =3D true + .use_stage2 =3D env->hflags2 & HF2_NPT_MASK, }; =20 if (in.pg_mode & PG_MODE_LMA) { @@ -444,8 +506,13 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int si= ze, return true; } =20 - /* FIXME: On error in get_hphys we have already jumped out. */ - g_assert(!probe); + if (probe) { + return false; + } + + if (err.stage2 !=3D S2_NONE) { + raise_stage2(env, &err, retaddr); + } =20 if (env->intercept_exceptions & (1 << err.exception_index)) { /* cr2 is not modified in case of exceptions */ --=20 2.34.1 From nobody Sat May 11 23:55:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664732252; cv=none; d=zohomail.com; s=zohoarc; b=W+gqdmr5GOvZqRa+hJUs2tQRJkOoUVAbWs+5YdxouffbKPnGKU7BaWctd8spNoMoiiolQgUB0gNLuL6laQfNme84QUK8v3DCdKFLG/fNmRjgOx5BacVnBU1ZsqVLTA0tTviFJYr4lcBN5gojLPQFfZzY0KNM43morP5oeL2+TBA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664732252; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8xeA2rOgse1n4eSQHAkt+kpvv0Pcr9kLnEHTHU5z+Ak=; b=OVObQzuiNkVIubfdlIW51ysrkYHIftwBx3oHMOsOrxvC6qcUqywinH9PfM2hcWZFgrMzwlYuCT/E/rfj7IhmBy6dThhXJHEsgj2Kx2Ab0WH9hPu3ts/gWi1HKEYLCXSaNfl6FBj32fG2qAoivCAPFreLA2qptrFo2LSXGL9pUhU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664732252312181.49299772234588; Sun, 2 Oct 2022 10:37:32 -0700 (PDT) Received: from localhost ([::1]:42966 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1of2uB-0007cN-Be for importer@patchew.org; Sun, 02 Oct 2022 13:37:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59416) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1of2nX-0005Si-Jk for qemu-devel@nongnu.org; Sun, 02 Oct 2022 13:30:43 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:40615) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1of2nV-0006Bk-Mz for qemu-devel@nongnu.org; Sun, 02 Oct 2022 13:30:39 -0400 Received: by mail-pj1-x102f.google.com with SMTP id h8-20020a17090a054800b00205ccbae31eso13366461pjf.5 for ; Sun, 02 Oct 2022 10:30:36 -0700 (PDT) Received: from stoup.. ([2605:ef80:8002:3cad:72cd:dd96:98f6:c3cf]) by smtp.gmail.com with ESMTPSA id 135-20020a62168d000000b0056025ccc3bbsm2749783pfw.146.2022.10.02.10.30.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Oct 2022 10:30:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=8xeA2rOgse1n4eSQHAkt+kpvv0Pcr9kLnEHTHU5z+Ak=; b=tZjk9ECuK2UPYrCjgWWw0LHv5oQD43xAITwpk7sV/StsqlI6EfZyJJECZtc869F8Ik K8TaozFzcuOeAX7kMY8Ee0o+YSLFbtI5696VrayD1ikVjzZy0nuS4VisCfJjXKGTNLNX XLYdQeN6snkhEmeSEvepPSOhSwUkpcVb1rsbMJm+f3OYg5+kL9udHeo+0ONA4t6SCa8s AFp/zcivYIAf/jgEF5YFUH8UCFTd2rInXp3XSYlx/tPp6Yn9zNjp/JxvzchgBjoSKblD l9lwggJf/MBTTJyRD7CNe7pdlZvmTiK7Ds+erFhxswcCIhRlZbtCsZZikz3AxMKiJS8w /cKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=8xeA2rOgse1n4eSQHAkt+kpvv0Pcr9kLnEHTHU5z+Ak=; b=uFpDq3SoaL3eqlckeN8YWXOeMmtohhN3Xab0Qb3d+D6mEGWkvG3jOww3l+vKHwo7p9 QIo6o8SOa1GSrm+jiBle5536z8lEgSCBaimJdtAvArKQk5ULlEERniutVfVAuIEB4llg HauCkS7B+EPcMwxMiaR5OL4eSs+9Dj+Wb1YyixiYH5Bz5R9Q7H+hgramSAA2laM18SCq gFHhk5tqVXuM35KMObWrM5Oa3aU9b7Cd8A5JRLfjrq4f1x+6RkIZI9ZH5oLc+0Yirebq 5kNkr9UTM9MkcoERlYsn6qUmXPKp8zIpbn/R6Ia8lVBCmMEMlDBgKQ4nEoQxVoJhijyQ buEg== X-Gm-Message-State: ACrzQf3jra9KXdL5cuQhOJAqcE3mqXBL3XcKyLpZwwMIo+WTWf68bV40 DF6TAtXveK56GMilXGfUJSr8Gvvelw0ZUw== X-Google-Smtp-Source: AMsMyM6qgJeBxvuMZpFb4EQChgvAKf98Ah21x1FZn4OzPF9g6QgpaiQDuAE5vs/YopXQTmRPLIuQFw== X-Received: by 2002:a17:90a:1096:b0:202:c5a9:bf1e with SMTP id c22-20020a17090a109600b00202c5a9bf1emr8567887pja.3.1664731835683; Sun, 02 Oct 2022 10:30:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 5/9] target/i386: Add MMU_PHYS_IDX and MMU_NESTED_IDX Date: Sun, 2 Oct 2022 10:29:52 -0700 Message-Id: <20221002172956.265735-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221002172956.265735-1-richard.henderson@linaro.org> References: <20221002172956.265735-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664732254292100001 Content-Type: text/plain; charset="utf-8" These new mmu indexes will be helpful for improving paging and code throughout the target. Signed-off-by: Richard Henderson --- target/i386/cpu-param.h | 2 +- target/i386/cpu.h | 3 + target/i386/tcg/sysemu/excp_helper.c | 82 ++++++++++++++++++---------- target/i386/tcg/sysemu/svm_helper.c | 3 + 4 files changed, 60 insertions(+), 30 deletions(-) diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index 9740bd7abd..abad52af20 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -23,6 +23,6 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif #define TARGET_PAGE_BITS 12 -#define NB_MMU_MODES 3 +#define NB_MMU_MODES 5 =20 #endif diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 82004b65b9..9a40b54ae5 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2144,6 +2144,9 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define MMU_KSMAP_IDX 0 #define MMU_USER_IDX 1 #define MMU_KNOSMAP_IDX 2 +#define MMU_NESTED_IDX 3 +#define MMU_PHYS_IDX 4 + static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) { return (env->hflags & HF_CPL_MASK) =3D=3D 3 ? MMU_USER_IDX : diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index 816b307547..494dc6d00c 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -448,41 +448,65 @@ static bool get_physical_address(CPUX86State *env, va= ddr addr, MMUAccessType access_type, int mmu_idx, TranslateResult *out, TranslateFault *err) { - if (!(env->cr[0] & CR0_PG_MASK)) { - out->paddr =3D addr & x86_get_a20_mask(env); + TranslateParams in; + bool use_stage2 =3D env->hflags2 & HF2_NPT_MASK; =20 -#ifdef TARGET_X86_64 - if (!(env->hflags & HF_LMA_MASK)) { - /* Without long mode we can only address 32bits in real mode */ - out->paddr =3D (uint32_t)out->paddr; - } -#endif - out->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - out->page_size =3D TARGET_PAGE_SIZE; - return true; - } else { - TranslateParams in =3D { - .addr =3D addr, - .cr3 =3D env->cr[3], - .pg_mode =3D get_pg_mode(env), - .mmu_idx =3D mmu_idx, - .access_type =3D access_type, - .use_stage2 =3D env->hflags2 & HF2_NPT_MASK, - }; + in.addr =3D addr; + in.access_type =3D access_type; =20 - if (in.pg_mode & PG_MODE_LMA) { - /* test virtual address sign extension */ - int shift =3D in.pg_mode & PG_MODE_LA57 ? 56 : 47; - int64_t sext =3D (int64_t)addr >> shift; - if (sext !=3D 0 && sext !=3D -1) { - err->exception_index =3D EXCP0D_GPF; - err->error_code =3D 0; - err->cr2 =3D addr; + switch (mmu_idx) { + case MMU_PHYS_IDX: + break; + + case MMU_NESTED_IDX: + if (likely(use_stage2)) { + in.cr3 =3D env->nested_cr3; + in.pg_mode =3D env->nested_pg_mode; + in.mmu_idx =3D MMU_USER_IDX; + in.use_stage2 =3D false; + + if (!mmu_translate(env, &in, out, err)) { + err->stage2 =3D S2_GPA; return false; } + return true; } - return mmu_translate(env, &in, out, err); + break; + + default: + in.cr3 =3D env->cr[3]; + in.mmu_idx =3D mmu_idx; + in.use_stage2 =3D use_stage2; + in.pg_mode =3D get_pg_mode(env); + + if (likely(in.pg_mode)) { + if (in.pg_mode & PG_MODE_LMA) { + /* test virtual address sign extension */ + int shift =3D in.pg_mode & PG_MODE_LA57 ? 56 : 47; + int64_t sext =3D (int64_t)addr >> shift; + if (sext !=3D 0 && sext !=3D -1) { + err->exception_index =3D EXCP0D_GPF; + err->error_code =3D 0; + err->cr2 =3D addr; + return false; + } + } + return mmu_translate(env, &in, out, err); + } + break; } + + /* Translation disabled. */ + out->paddr =3D addr & x86_get_a20_mask(env); +#ifdef TARGET_X86_64 + if (!(env->hflags & HF_LMA_MASK)) { + /* Without long mode we can only address 32bits in real mode */ + out->paddr =3D (uint32_t)out->paddr; + } +#endif + out->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + out->page_size =3D TARGET_PAGE_SIZE; + return true; } =20 bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/s= vm_helper.c index 2b6f450af9..85b7741d94 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -271,6 +271,8 @@ void helper_vmrun(CPUX86State *env, int aflag, int next= _eip_addend) env->hflags2 |=3D HF2_NPT_MASK; =20 env->nested_pg_mode =3D get_pg_mode(env) & PG_MODE_SVM_MASK; + + tlb_flush_by_mmuidx(cs, 1 << MMU_NESTED_IDX); } =20 /* enable intercepts */ @@ -720,6 +722,7 @@ void do_vmexit(CPUX86State *env) env->vm_vmcb + offsetof(struct vmcb, control.int_state), = 0); } env->hflags2 &=3D ~HF2_NPT_MASK; + tlb_flush_by_mmuidx(cs, 1 << MMU_NESTED_IDX); =20 /* Save the VM state in the vmcb */ svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.es), --=20 2.34.1 From nobody Sat May 11 23:55:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664732101; cv=none; d=zohomail.com; s=zohoarc; b=Fteq+aTJtg0mG51RuMJjSo6votmU/mK9rbLGjVY4MItzFjD9IdKTSjDtGD6Mv3aLH2ZQpQEqEF8+QqLOBoNuMw6+h471ebNsbSkEJg66y20SMzhPkAsAlu24kK9jY6V0EPUmrtJSwYRWTt88SIdKNom5o57Y/zL4RLPGbocVNxw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664732101; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mA/6AxMDVCI5iP1gqwmW0DujQCJiMlB/8O7xo0e5vos=; b=eV+02UF91SiF4TAVL0C4xY6C3asuYtWLV1qBIpnsDRTp1SPWRF6fdry1gntD4KaMbMUHOz9syxQuCrXHyf/BNaggzibtkwW60kgvh97G488CdKGSCwzVgbJIxPlauxF9FEFAaS4kAncIUopQNP25EwPU/tD+O68BXCQP4IiV2Uc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664732101099484.4902681830788; Sun, 2 Oct 2022 10:35:01 -0700 (PDT) Received: from localhost ([::1]:53400 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1of2rj-0002BN-Nh for importer@patchew.org; Sun, 02 Oct 2022 13:34:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59420) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1of2nZ-0005Sn-NS for qemu-devel@nongnu.org; Sun, 02 Oct 2022 13:30:43 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:41765) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1of2nW-0006CJ-Vk for qemu-devel@nongnu.org; Sun, 02 Oct 2022 13:30:41 -0400 Received: by mail-pj1-x102d.google.com with SMTP id x32-20020a17090a38a300b00209dced49cfso5631201pjb.0 for ; Sun, 02 Oct 2022 10:30:38 -0700 (PDT) Received: from stoup.. ([2605:ef80:8002:3cad:72cd:dd96:98f6:c3cf]) by smtp.gmail.com with ESMTPSA id 135-20020a62168d000000b0056025ccc3bbsm2749783pfw.146.2022.10.02.10.30.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Oct 2022 10:30:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=mA/6AxMDVCI5iP1gqwmW0DujQCJiMlB/8O7xo0e5vos=; b=qjl1E3wj1Xz7mszB9+N60Mc+YblUTTNQmxA1mTl5jGFuNjcbc59jrTz6cGg69Q2hBi aBapz1JdKJO+rzhBJITVpPRAOoR9nCIURx6LYLUlBj4oESFaBP9odosfjJROtdV2rkLM xZ1QpBsW0wBwAAYQps0bp/T+PUGW7RdJVP3Q1Dsb9chrvKCklRp0Txi77vGd3mjHAv/T 4ZaVVAhpM+Nq9/IoHgZ/gqcuRiTMkPO+G4oGo9JmPOIz6cVoFszFH2yjni8oRVNyH4bZ nWFohZbmBs4V0SWRAy8G7IBxUhqyyBE/73ofhYEviVy60NEQgGKXOOBz550tRBrRfr/W VRzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=mA/6AxMDVCI5iP1gqwmW0DujQCJiMlB/8O7xo0e5vos=; b=BOyw5WoBCrqwd4NkFxEdlqnjdhPu9P3fdP5JKPnNknHavMXZkDJPgsjuAUwlYV+uWc vOI2LfrXq/oLBpDvZN+D7NULPpgbpgdgX4jev02mfAdpvgK3cSwg0jYcvvpRSwOqpUZv Dina/zL/avjWxEnroEfiZeTeuMUo71qaxe7QeZgVQBV9q+sy3+mLJyqsMUhG71DSq9SD FwIOzIsRcJQGoxoPG3cNwTAxLPkkRPpPsxJwAZpmh5AurKbp+duXm0+Ga0rWaVIbvV8Z dkZ5l1VUJfK8vMqy2yd0FkpJb8aDKUYiNJ/ET6YUa8mES49X6vEzMOfGTWVzekTP+9Hy EyeQ== X-Gm-Message-State: ACrzQf0/Bq1gvRWneKlOIXCi9XvQ52IaCLJcXpm6x8vFEQjkwx81qZMF 73awNWGy5ktczH1kU4BOlwSyAK9ZlwjL5g== X-Google-Smtp-Source: AMsMyM4fzaaa26N/Jf39Q/Y4/r8Zac9c+gXwfZKVmYm0mZYxIMiA812u6Lj9Igqe2gYwJMP1LRS8TQ== X-Received: by 2002:a17:902:7c0d:b0:178:a6ca:1dbc with SMTP id x13-20020a1709027c0d00b00178a6ca1dbcmr18801341pll.115.1664731837480; Sun, 02 Oct 2022 10:30:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 6/9] target/i386: Use MMU_NESTED_IDX for vmload/vmsave Date: Sun, 2 Oct 2022 10:29:53 -0700 Message-Id: <20221002172956.265735-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221002172956.265735-1-richard.henderson@linaro.org> References: <20221002172956.265735-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664732103245100001 Content-Type: text/plain; charset="utf-8" Use MMU_NESTED_IDX for each memory access, rather than just a single translation to physical. Adjust svm_save_seg and svm_load_seg to pass in mmu_idx. This removes the last use of get_hphys so remove it. Signed-off-by: Richard Henderson --- target/i386/cpu.h | 2 - target/i386/tcg/sysemu/excp_helper.c | 31 ---- target/i386/tcg/sysemu/svm_helper.c | 231 +++++++++++++++------------ 3 files changed, 126 insertions(+), 138 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9a40b54ae5..10a5e79774 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2381,8 +2381,6 @@ static inline bool ctl_has_irq(CPUX86State *env) return (env->int_ctl & V_IRQ_MASK) && (int_prio >=3D tpr); } =20 -hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type, - int *prot); #if defined(TARGET_X86_64) && \ defined(CONFIG_USER_ONLY) && \ defined(CONFIG_LINUX) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index 494dc6d00c..86b3014196 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -413,37 +413,6 @@ static G_NORETURN void raise_stage2(CPUX86State *env, = TranslateFault *err, cpu_vmexit(env, SVM_EXIT_NPF, exit_info_1, retaddr); } =20 -hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type, - int *prot) -{ - CPUX86State *env =3D cs->env_ptr; - - if (likely(!(env->hflags2 & HF2_NPT_MASK))) { - return gphys; - } else { - TranslateParams in =3D { - .addr =3D gphys, - .cr3 =3D env->nested_cr3, - .pg_mode =3D env->nested_pg_mode, - .mmu_idx =3D MMU_USER_IDX, - .access_type =3D access_type, - .use_stage2 =3D false, - }; - TranslateResult out; - TranslateFault err; - - if (!mmu_translate(env, &in, &out, &err)) { - err.stage2 =3D prot ? SVM_NPTEXIT_GPA : SVM_NPTEXIT_GPT; - raise_stage2(env, &err, env->retaddr); - } - - if (prot) { - *prot &=3D out.prot; - } - return out.paddr; - } -} - static bool get_physical_address(CPUX86State *env, vaddr addr, MMUAccessType access_type, int mmu_idx, TranslateResult *out, TranslateFault *err) diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/s= vm_helper.c index 85b7741d94..8e88567399 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -27,19 +27,19 @@ =20 /* Secure Virtual Machine helpers */ =20 -static inline void svm_save_seg(CPUX86State *env, hwaddr addr, - const SegmentCache *sc) +static void svm_save_seg(CPUX86State *env, int mmu_idx, hwaddr addr, + const SegmentCache *sc) { - CPUState *cs =3D env_cpu(env); - - x86_stw_phys(cs, addr + offsetof(struct vmcb_seg, selector), - sc->selector); - x86_stq_phys(cs, addr + offsetof(struct vmcb_seg, base), - sc->base); - x86_stl_phys(cs, addr + offsetof(struct vmcb_seg, limit), - sc->limit); - x86_stw_phys(cs, addr + offsetof(struct vmcb_seg, attrib), - ((sc->flags >> 8) & 0xff) | ((sc->flags >> 12) & 0x0f00)); + cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector), + sc->selector, mmu_idx, 0); + cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base), + sc->base, mmu_idx, 0); + cpu_stl_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit), + sc->limit, mmu_idx, 0); + cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib), + ((sc->flags >> 8) & 0xff) + | ((sc->flags >> 12) & 0x0f00), + mmu_idx, 0); } =20 /* @@ -52,29 +52,36 @@ static inline void svm_canonicalization(CPUX86State *en= v, target_ulong *seg_base *seg_base =3D ((((long) *seg_base) << shift_amt) >> shift_amt); } =20 -static inline void svm_load_seg(CPUX86State *env, hwaddr addr, - SegmentCache *sc) +static void svm_load_seg(CPUX86State *env, int mmu_idx, hwaddr addr, + SegmentCache *sc) { - CPUState *cs =3D env_cpu(env); unsigned int flags; =20 - sc->selector =3D x86_lduw_phys(cs, - addr + offsetof(struct vmcb_seg, selector)); - sc->base =3D x86_ldq_phys(cs, addr + offsetof(struct vmcb_seg, base)); - sc->limit =3D x86_ldl_phys(cs, addr + offsetof(struct vmcb_seg, limit)= ); - flags =3D x86_lduw_phys(cs, addr + offsetof(struct vmcb_seg, attrib)); + sc->selector =3D + cpu_lduw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector), + mmu_idx, 0); + sc->base =3D + cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base), + mmu_idx, 0); + sc->limit =3D + cpu_ldl_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit), + mmu_idx, 0); + flags =3D + cpu_lduw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib), + mmu_idx, 0); sc->flags =3D ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12); + svm_canonicalization(env, &sc->base); } =20 -static inline void svm_load_seg_cache(CPUX86State *env, hwaddr addr, - int seg_reg) +static void svm_load_seg_cache(CPUX86State *env, int mmu_idx, + hwaddr addr, int seg_reg) { - SegmentCache sc1, *sc =3D &sc1; + SegmentCache sc; =20 - svm_load_seg(env, addr, sc); - cpu_x86_load_seg_cache(env, seg_reg, sc->selector, - sc->base, sc->limit, sc->flags); + svm_load_seg(env, mmu_idx, addr, &sc); + cpu_x86_load_seg_cache(env, seg_reg, sc.selector, + sc.base, sc.limit, sc.flags); } =20 static inline bool is_efer_invalid_state (CPUX86State *env) @@ -199,13 +206,17 @@ void helper_vmrun(CPUX86State *env, int aflag, int ne= xt_eip_addend) env->vm_hsave + offsetof(struct vmcb, save.rflags), cpu_compute_eflags(env)); =20 - svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.es), + svm_save_seg(env, MMU_PHYS_IDX, + env->vm_hsave + offsetof(struct vmcb, save.es), &env->segs[R_ES]); - svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.cs), + svm_save_seg(env, MMU_PHYS_IDX, + env->vm_hsave + offsetof(struct vmcb, save.cs), &env->segs[R_CS]); - svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.ss), + svm_save_seg(env, MMU_PHYS_IDX, + env->vm_hsave + offsetof(struct vmcb, save.ss), &env->segs[R_SS]); - svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.ds), + svm_save_seg(env, MMU_PHYS_IDX, + env->vm_hsave + offsetof(struct vmcb, save.ds), &env->segs[R_DS]); =20 x86_stq_phys(cs, env->vm_hsave + offsetof(struct vmcb, save.rip), @@ -325,18 +336,18 @@ void helper_vmrun(CPUX86State *env, int aflag, int ne= xt_eip_addend) save.rflags)), ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); =20 - svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.es), - R_ES); - svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.cs), - R_CS); - svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.ss), - R_SS); - svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.ds), - R_DS); - svm_load_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.idtr), - &env->idt); - svm_load_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.gdtr), - &env->gdt); + svm_load_seg_cache(env, MMU_PHYS_IDX, + env->vm_vmcb + offsetof(struct vmcb, save.es), R_ES= ); + svm_load_seg_cache(env, MMU_PHYS_IDX, + env->vm_vmcb + offsetof(struct vmcb, save.cs), R_CS= ); + svm_load_seg_cache(env, MMU_PHYS_IDX, + env->vm_vmcb + offsetof(struct vmcb, save.ss), R_SS= ); + svm_load_seg_cache(env, MMU_PHYS_IDX, + env->vm_vmcb + offsetof(struct vmcb, save.ds), R_DS= ); + svm_load_seg(env, MMU_PHYS_IDX, + env->vm_vmcb + offsetof(struct vmcb, save.idtr), &env->id= t); + svm_load_seg(env, MMU_PHYS_IDX, + env->vm_vmcb + offsetof(struct vmcb, save.gdtr), &env->gd= t); =20 env->eip =3D x86_ldq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, save.rip)); @@ -451,9 +462,8 @@ void helper_vmmcall(CPUX86State *env) =20 void helper_vmload(CPUX86State *env, int aflag) { - CPUState *cs =3D env_cpu(env); + int mmu_idx =3D MMU_PHYS_IDX; target_ulong addr; - int prot; =20 cpu_svm_check_intercept_param(env, SVM_EXIT_VMLOAD, 0, GETPC()); =20 @@ -464,43 +474,52 @@ void helper_vmload(CPUX86State *env, int aflag) } =20 if (virtual_vm_load_save_enabled(env, SVM_EXIT_VMLOAD, GETPC())) { - addr =3D get_hphys(cs, addr, MMU_DATA_LOAD, &prot); + mmu_idx =3D MMU_NESTED_IDX; } =20 - qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmload! " TARGET_FMT_lx - "\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n", - addr, x86_ldq_phys(cs, addr + offsetof(struct vmcb, - save.fs.base)), - env->segs[R_FS].base); - - svm_load_seg_cache(env, addr + offsetof(struct vmcb, save.fs), R_FS); - svm_load_seg_cache(env, addr + offsetof(struct vmcb, save.gs), R_GS); - svm_load_seg(env, addr + offsetof(struct vmcb, save.tr), &env->tr); - svm_load_seg(env, addr + offsetof(struct vmcb, save.ldtr), &env->ldt); + svm_load_seg_cache(env, mmu_idx, + addr + offsetof(struct vmcb, save.fs), R_FS); + svm_load_seg_cache(env, mmu_idx, + addr + offsetof(struct vmcb, save.gs), R_GS); + svm_load_seg(env, mmu_idx, + addr + offsetof(struct vmcb, save.tr), &env->tr); + svm_load_seg(env, mmu_idx, + addr + offsetof(struct vmcb, save.ldtr), &env->ldt); =20 #ifdef TARGET_X86_64 - env->kernelgsbase =3D x86_ldq_phys(cs, addr + offsetof(struct vmcb, - save.kernel_gs_base)); - env->lstar =3D x86_ldq_phys(cs, addr + offsetof(struct vmcb, save.lsta= r)); - env->cstar =3D x86_ldq_phys(cs, addr + offsetof(struct vmcb, save.csta= r)); - env->fmask =3D x86_ldq_phys(cs, addr + offsetof(struct vmcb, save.sfma= sk)); + env->kernelgsbase =3D + cpu_ldq_mmuidx_ra(env, + addr + offsetof(struct vmcb, save.kernel_gs_base= ), + mmu_idx, 0); + env->lstar =3D + cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar), + mmu_idx, 0); + env->cstar =3D + cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar), + mmu_idx, 0); + env->fmask =3D + cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask), + mmu_idx, 0); svm_canonicalization(env, &env->kernelgsbase); #endif - env->star =3D x86_ldq_phys(cs, addr + offsetof(struct vmcb, save.star)= ); - env->sysenter_cs =3D x86_ldq_phys(cs, - addr + offsetof(struct vmcb, save.sysenter= _cs)); - env->sysenter_esp =3D x86_ldq_phys(cs, addr + offsetof(struct vmcb, - save.sysenter_esp)); - env->sysenter_eip =3D x86_ldq_phys(cs, addr + offsetof(struct vmcb, - save.sysenter_eip)); - + env->star =3D + cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star), + mmu_idx, 0); + env->sysenter_cs =3D + cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_= cs), + mmu_idx, 0); + env->sysenter_esp =3D + cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_= esp), + mmu_idx, 0); + env->sysenter_eip =3D + cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_= eip), + mmu_idx, 0); } =20 void helper_vmsave(CPUX86State *env, int aflag) { - CPUState *cs =3D env_cpu(env); + int mmu_idx =3D MMU_PHYS_IDX; target_ulong addr; - int prot; =20 cpu_svm_check_intercept_param(env, SVM_EXIT_VMSAVE, 0, GETPC()); =20 @@ -511,38 +530,36 @@ void helper_vmsave(CPUX86State *env, int aflag) } =20 if (virtual_vm_load_save_enabled(env, SVM_EXIT_VMSAVE, GETPC())) { - addr =3D get_hphys(cs, addr, MMU_DATA_STORE, &prot); + mmu_idx =3D MMU_NESTED_IDX; } =20 - qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmsave! " TARGET_FMT_lx - "\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n", - addr, x86_ldq_phys(cs, - addr + offsetof(struct vmcb, save.fs.base= )), - env->segs[R_FS].base); - - svm_save_seg(env, addr + offsetof(struct vmcb, save.fs), + svm_save_seg(env, mmu_idx, addr + offsetof(struct vmcb, save.fs), &env->segs[R_FS]); - svm_save_seg(env, addr + offsetof(struct vmcb, save.gs), + svm_save_seg(env, mmu_idx, addr + offsetof(struct vmcb, save.gs), &env->segs[R_GS]); - svm_save_seg(env, addr + offsetof(struct vmcb, save.tr), + svm_save_seg(env, mmu_idx, addr + offsetof(struct vmcb, save.tr), &env->tr); - svm_save_seg(env, addr + offsetof(struct vmcb, save.ldtr), + svm_save_seg(env, mmu_idx, addr + offsetof(struct vmcb, save.ldtr), &env->ldt); =20 #ifdef TARGET_X86_64 - x86_stq_phys(cs, addr + offsetof(struct vmcb, save.kernel_gs_base), - env->kernelgsbase); - x86_stq_phys(cs, addr + offsetof(struct vmcb, save.lstar), env->lstar); - x86_stq_phys(cs, addr + offsetof(struct vmcb, save.cstar), env->cstar); - x86_stq_phys(cs, addr + offsetof(struct vmcb, save.sfmask), env->fmask= ); + cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.kernel_gs_bas= e), + env->kernelgsbase, mmu_idx, 0); + cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar), + env->lstar, mmu_idx, 0); + cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar), + env->cstar, mmu_idx, 0); + cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask), + env->fmask, mmu_idx, 0); #endif - x86_stq_phys(cs, addr + offsetof(struct vmcb, save.star), env->star); - x86_stq_phys(cs, - addr + offsetof(struct vmcb, save.sysenter_cs), env->sysenter= _cs); - x86_stq_phys(cs, addr + offsetof(struct vmcb, save.sysenter_esp), - env->sysenter_esp); - x86_stq_phys(cs, addr + offsetof(struct vmcb, save.sysenter_eip), - env->sysenter_eip); + cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star), + env->star, mmu_idx, 0); + cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_cs), + env->sysenter_cs, mmu_idx, 0); + cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_esp), + env->sysenter_esp, mmu_idx, 0); + cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_eip), + env->sysenter_eip, mmu_idx, 0); } =20 void helper_stgi(CPUX86State *env) @@ -725,13 +742,17 @@ void do_vmexit(CPUX86State *env) tlb_flush_by_mmuidx(cs, 1 << MMU_NESTED_IDX); =20 /* Save the VM state in the vmcb */ - svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.es), + svm_save_seg(env, MMU_PHYS_IDX, + env->vm_vmcb + offsetof(struct vmcb, save.es), &env->segs[R_ES]); - svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.cs), + svm_save_seg(env, MMU_PHYS_IDX, + env->vm_vmcb + offsetof(struct vmcb, save.cs), &env->segs[R_CS]); - svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.ss), + svm_save_seg(env, MMU_PHYS_IDX, + env->vm_vmcb + offsetof(struct vmcb, save.ss), &env->segs[R_SS]); - svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.ds), + svm_save_seg(env, MMU_PHYS_IDX, + env->vm_vmcb + offsetof(struct vmcb, save.ds), &env->segs[R_DS]); =20 x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, save.gdtr.base), @@ -812,14 +833,14 @@ void do_vmexit(CPUX86State *env) ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK | VM_MASK)); =20 - svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.es), - R_ES); - svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.cs), - R_CS); - svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.ss), - R_SS); - svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.ds), - R_DS); + svm_load_seg_cache(env, MMU_PHYS_IDX, + env->vm_hsave + offsetof(struct vmcb, save.es), R_E= S); + svm_load_seg_cache(env, MMU_PHYS_IDX, + env->vm_hsave + offsetof(struct vmcb, save.cs), R_C= S); + svm_load_seg_cache(env, MMU_PHYS_IDX, + env->vm_hsave + offsetof(struct vmcb, save.ss), R_S= S); + svm_load_seg_cache(env, MMU_PHYS_IDX, + env->vm_hsave + offsetof(struct vmcb, save.ds), R_D= S); =20 env->eip =3D x86_ldq_phys(cs, env->vm_hsave + offsetof(struct vmcb, save.rip)); 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Standardize on pte/pte_addr for all levels. Signed-off-by: Richard Henderson --- target/i386/tcg/sysemu/excp_helper.c | 178 ++++++++++++++------------- 1 file changed, 91 insertions(+), 87 deletions(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index 86b3014196..d6b7de6eea 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -82,7 +82,7 @@ static bool mmu_translate(CPUX86State *env, const Transla= teParams *in, const bool is_user =3D (in->mmu_idx =3D=3D MMU_USER_IDX); const MMUAccessType access_type =3D in->access_type; uint64_t ptep, pte; - hwaddr pde_addr, pte_addr; + hwaddr pte_addr; uint64_t rsvd_mask =3D PG_ADDRESS_MASK & ~MAKE_64BIT_MASK(0, cpu->phys= _bits); uint32_t pkr; int page_size; @@ -92,116 +92,122 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, } =20 if (pg_mode & PG_MODE_PAE) { - uint64_t pde, pdpe; - target_ulong pdpe_addr; - #ifdef TARGET_X86_64 if (pg_mode & PG_MODE_LMA) { - bool la57 =3D pg_mode & PG_MODE_LA57; - uint64_t pml5e_addr, pml5e; - uint64_t pml4e_addr, pml4e; - - if (la57) { - pml5e_addr =3D ((in->cr3 & ~0xfff) + - (((addr >> 48) & 0x1ff) << 3)) & a20_mask; - PTE_HPHYS(pml5e_addr); - pml5e =3D x86_ldq_phys(cs, pml5e_addr); - if (!(pml5e & PG_PRESENT_MASK)) { + if (pg_mode & PG_MODE_LA57) { + /* + * Page table level 5 + */ + pte_addr =3D ((in->cr3 & ~0xfff) + + (((addr >> 48) & 0x1ff) << 3)) & a20_mask; + PTE_HPHYS(pte_addr); + pte =3D x86_ldq_phys(cs, pte_addr); + if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } - if (pml5e & (rsvd_mask | PG_PSE_MASK)) { + if (pte & (rsvd_mask | PG_PSE_MASK)) { goto do_fault_rsvd; } - if (!(pml5e & PG_ACCESSED_MASK)) { - pml5e |=3D PG_ACCESSED_MASK; - x86_stl_phys_notdirty(cs, pml5e_addr, pml5e); + if (!(pte & PG_ACCESSED_MASK)) { + pte |=3D PG_ACCESSED_MASK; + x86_stl_phys_notdirty(cs, pte_addr, pte); } - ptep =3D pml5e ^ PG_NX_MASK; + ptep =3D pte ^ PG_NX_MASK; } else { - pml5e =3D in->cr3; + pte =3D in->cr3; ptep =3D PG_NX_MASK | PG_USER_MASK | PG_RW_MASK; } =20 - pml4e_addr =3D ((pml5e & PG_ADDRESS_MASK) + - (((addr >> 39) & 0x1ff) << 3)) & a20_mask; - PTE_HPHYS(pml4e_addr); - pml4e =3D x86_ldq_phys(cs, pml4e_addr); - if (!(pml4e & PG_PRESENT_MASK)) { + /* + * Page table level 4 + */ + pte_addr =3D ((pte & PG_ADDRESS_MASK) + + (((addr >> 39) & 0x1ff) << 3)) & a20_mask; + PTE_HPHYS(pte_addr); + pte =3D x86_ldq_phys(cs, pte_addr); + if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } - if (pml4e & (rsvd_mask | PG_PSE_MASK)) { + if (pte & (rsvd_mask | PG_PSE_MASK)) { goto do_fault_rsvd; } - if (!(pml4e & PG_ACCESSED_MASK)) { - pml4e |=3D PG_ACCESSED_MASK; - x86_stl_phys_notdirty(cs, pml4e_addr, pml4e); + if (!(pte & PG_ACCESSED_MASK)) { + pte |=3D PG_ACCESSED_MASK; + x86_stl_phys_notdirty(cs, pte_addr, pte); } - ptep &=3D pml4e ^ PG_NX_MASK; - pdpe_addr =3D ((pml4e & PG_ADDRESS_MASK) + (((addr >> 30) & 0x= 1ff) << 3)) & - a20_mask; - PTE_HPHYS(pdpe_addr); - pdpe =3D x86_ldq_phys(cs, pdpe_addr); - if (!(pdpe & PG_PRESENT_MASK)) { + ptep &=3D pte ^ PG_NX_MASK; + + /* + * Page table level 3 + */ + pte_addr =3D ((pte & PG_ADDRESS_MASK) + + (((addr >> 30) & 0x1ff) << 3)) & a20_mask; + PTE_HPHYS(pte_addr); + pte =3D x86_ldq_phys(cs, pte_addr); + if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } - if (pdpe & rsvd_mask) { + if (pte & rsvd_mask) { goto do_fault_rsvd; } - ptep &=3D pdpe ^ PG_NX_MASK; - if (!(pdpe & PG_ACCESSED_MASK)) { - pdpe |=3D PG_ACCESSED_MASK; - x86_stl_phys_notdirty(cs, pdpe_addr, pdpe); + ptep &=3D pte ^ PG_NX_MASK; + if (!(pte & PG_ACCESSED_MASK)) { + pte |=3D PG_ACCESSED_MASK; + x86_stl_phys_notdirty(cs, pte_addr, pte); } - if (pdpe & PG_PSE_MASK) { + if (pte & PG_PSE_MASK) { /* 1 GB page */ page_size =3D 1024 * 1024 * 1024; - pte_addr =3D pdpe_addr; - pte =3D pdpe; goto do_check_protect; } } else #endif { - /* XXX: load them when cr3 is loaded ? */ - pdpe_addr =3D ((in->cr3 & ~0x1f) + ((addr >> 27) & 0x18)) & - a20_mask; - PTE_HPHYS(pdpe_addr); - pdpe =3D x86_ldq_phys(cs, pdpe_addr); - if (!(pdpe & PG_PRESENT_MASK)) { + /* + * Page table level 3 + */ + pte_addr =3D ((in->cr3 & ~0x1f) + ((addr >> 27) & 0x18)) & a20= _mask; + PTE_HPHYS(pte_addr); + pte =3D x86_ldq_phys(cs, pte_addr); + if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } rsvd_mask |=3D PG_HI_USER_MASK; - if (pdpe & (rsvd_mask | PG_NX_MASK)) { + if (pte & (rsvd_mask | PG_NX_MASK)) { goto do_fault_rsvd; } ptep =3D PG_NX_MASK | PG_USER_MASK | PG_RW_MASK; } =20 - pde_addr =3D ((pdpe & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) <= < 3)) & - a20_mask; - PTE_HPHYS(pde_addr); - pde =3D x86_ldq_phys(cs, pde_addr); - if (!(pde & PG_PRESENT_MASK)) { + /* + * Page table level 2 + */ + pte_addr =3D ((pte & PG_ADDRESS_MASK) + + (((addr >> 21) & 0x1ff) << 3)) & a20_mask; + PTE_HPHYS(pte_addr); + pte =3D x86_ldq_phys(cs, pte_addr); + if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } - if (pde & rsvd_mask) { + if (pte & rsvd_mask) { goto do_fault_rsvd; } - ptep &=3D pde ^ PG_NX_MASK; - if (pde & PG_PSE_MASK) { + ptep &=3D pte ^ PG_NX_MASK; + if (pte & PG_PSE_MASK) { /* 2 MB page */ page_size =3D 2048 * 1024; - pte_addr =3D pde_addr; - pte =3D pde; goto do_check_protect; } - /* 4 KB page */ - if (!(pde & PG_ACCESSED_MASK)) { - pde |=3D PG_ACCESSED_MASK; - x86_stl_phys_notdirty(cs, pde_addr, pde); + if (!(pte & PG_ACCESSED_MASK)) { + pte |=3D PG_ACCESSED_MASK; + x86_stl_phys_notdirty(cs, pte_addr, pte); } - pte_addr =3D ((pde & PG_ADDRESS_MASK) + (((addr >> 12) & 0x1ff) <<= 3)) & - a20_mask; + + /* + * Page table level 1 + */ + pte_addr =3D ((pte & PG_ADDRESS_MASK) + + (((addr >> 12) & 0x1ff) << 3)) & a20_mask; PTE_HPHYS(pte_addr); pte =3D x86_ldq_phys(cs, pte_addr); if (!(pte & PG_PRESENT_MASK)) { @@ -214,39 +220,37 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, ptep &=3D pte ^ PG_NX_MASK; page_size =3D 4096; } else { - uint32_t pde; - - /* page directory entry */ - pde_addr =3D ((in->cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) & - a20_mask; - PTE_HPHYS(pde_addr); - pde =3D x86_ldl_phys(cs, pde_addr); - if (!(pde & PG_PRESENT_MASK)) { + /* + * Page table level 2 + */ + pte_addr =3D ((in->cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_m= ask; + PTE_HPHYS(pte_addr); + pte =3D x86_ldl_phys(cs, pte_addr); + if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } - ptep =3D pde | PG_NX_MASK; + ptep =3D pte | PG_NX_MASK; =20 /* if PSE bit is set, then we use a 4MB page */ - if ((pde & PG_PSE_MASK) && (pg_mode & PG_MODE_PSE)) { + if ((pte & PG_PSE_MASK) && (pg_mode & PG_MODE_PSE)) { page_size =3D 4096 * 1024; - pte_addr =3D pde_addr; - - /* Bits 20-13 provide bits 39-32 of the address, bit 21 is res= erved. + /* + * Bits 20-13 provide bits 39-32 of the address, bit 21 is res= erved. * Leave bits 20-13 in place for setting accessed/dirty bits b= elow. */ - pte =3D pde | ((pde & 0x1fe000LL) << (32 - 13)); + pte =3D (uint32_t)pte | ((pte & 0x1fe000LL) << (32 - 13)); rsvd_mask =3D 0x200000; goto do_check_protect_pse36; } - - if (!(pde & PG_ACCESSED_MASK)) { - pde |=3D PG_ACCESSED_MASK; - x86_stl_phys_notdirty(cs, pde_addr, pde); + if (!(pte & PG_ACCESSED_MASK)) { + pte |=3D PG_ACCESSED_MASK; + x86_stl_phys_notdirty(cs, pte_addr, pte); } =20 - /* page directory entry */ - pte_addr =3D ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & - a20_mask; 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Resolves: https://gitlab.com/qemu-project/qemu/-/issues/279 Signed-off-by: Richard Henderson --- target/i386/tcg/sysemu/excp_helper.c | 242 +++++++++++++++++++-------- 1 file changed, 168 insertions(+), 74 deletions(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index d6b7de6eea..e8457e9b21 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -27,8 +27,8 @@ typedef struct TranslateParams { target_ulong cr3; int pg_mode; int mmu_idx; + int ptw_idx; MMUAccessType access_type; - bool use_stage2; } TranslateParams; =20 typedef struct TranslateResult { @@ -50,43 +50,106 @@ typedef struct TranslateFault { TranslateFaultStage2 stage2; } TranslateFault; =20 -#define PTE_HPHYS(ADDR) \ - do { \ - if (in->use_stage2) { \ - nested_in.addr =3D (ADDR); \ - if (!mmu_translate(env, &nested_in, out, err)) { \ - err->stage2 =3D S2_GPT; \ - return false; \ - } \ - (ADDR) =3D out->paddr; \ - } \ - } while (0) +typedef struct PTETranslate { + CPUX86State *env; + TranslateFault *err; + int ptw_idx; + void *haddr; + hwaddr gaddr; +} PTETranslate; + +static bool ptw_translate(PTETranslate *inout, hwaddr addr) +{ + CPUTLBEntryFull *full; + int flags; + + inout->gaddr =3D addr; + flags =3D probe_access_full(inout->env, addr, MMU_DATA_STORE, + inout->ptw_idx, true, &inout->haddr, &full, = 0); + + if (unlikely(flags & TLB_INVALID_MASK)) { + TranslateFault *err =3D inout->err; + + assert(inout->ptw_idx =3D=3D MMU_NESTED_IDX); + err->exception_index =3D 0; /* unused */ + err->error_code =3D inout->env->error_code; + err->cr2 =3D addr; + err->stage2 =3D S2_GPT; + return false; + } + return true; +} + +static inline uint32_t ptw_ldl(const PTETranslate *in) +{ + if (likely(in->haddr)) { + return ldl_p(in->haddr); + } + return cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0); +} + +static inline uint64_t ptw_ldq(const PTETranslate *in) +{ + if (likely(in->haddr)) { + return ldq_p(in->haddr); + } + return cpu_ldq_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0); +} + +/* + * Note that we can use a 32-bit cmpxchg for all page table entries, + * even 64-bit ones, because PG_PRESENT_MASK, PG_ACCESSED_MASK and + * PG_DIRTY_MASK are all in the low 32 bits. + */ +static bool ptw_setl_slow(const PTETranslate *in, uint32_t old, uint32_t n= ew) +{ + uint32_t cmp; + + /* Does x86 really perform a rmw cycle on mmio for ptw? */ + start_exclusive(); + cmp =3D cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0); + if (cmp =3D=3D old) { + cpu_stl_mmuidx_ra(in->env, in->gaddr, new, in->ptw_idx, 0); + } + end_exclusive(); + return cmp =3D=3D old; +} + +static inline bool ptw_setl(const PTETranslate *in, uint32_t old, uint32_t= set) +{ + if (set & ~old) { + uint32_t new =3D old | set; + if (likely(in->haddr)) { + old =3D cpu_to_le32(old); + new =3D cpu_to_le32(new); + return qatomic_cmpxchg((uint32_t *)in->haddr, old, new) =3D=3D= old; + } + return ptw_setl_slow(in, old, new); + } + return true; +} =20 static bool mmu_translate(CPUX86State *env, const TranslateParams *in, TranslateResult *out, TranslateFault *err) { - TranslateParams nested_in =3D { - /* Use store for page table entries, to allow A/D flag updates. */ - .access_type =3D MMU_DATA_STORE, - .cr3 =3D env->nested_cr3, - .pg_mode =3D env->nested_pg_mode, - .mmu_idx =3D MMU_USER_IDX, - .use_stage2 =3D false, - }; - - CPUState *cs =3D env_cpu(env); - X86CPU *cpu =3D env_archcpu(env); const int32_t a20_mask =3D x86_get_a20_mask(env); const target_ulong addr =3D in->addr; const int pg_mode =3D in->pg_mode; const bool is_user =3D (in->mmu_idx =3D=3D MMU_USER_IDX); const MMUAccessType access_type =3D in->access_type; - uint64_t ptep, pte; + uint64_t ptep, pte, rsvd_mask; + PTETranslate pte_trans =3D { + .env =3D env, + .err =3D err, + .ptw_idx =3D in->ptw_idx, + }; hwaddr pte_addr; - uint64_t rsvd_mask =3D PG_ADDRESS_MASK & ~MAKE_64BIT_MASK(0, cpu->phys= _bits); uint32_t pkr; int page_size; =20 + restart_all: + rsvd_mask =3D ~MAKE_64BIT_MASK(0, env_archcpu(env)->phys_bits); + rsvd_mask &=3D PG_ADDRESS_MASK; if (!(pg_mode & PG_MODE_NXE)) { rsvd_mask |=3D PG_NX_MASK; } @@ -100,17 +163,19 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, */ pte_addr =3D ((in->cr3 & ~0xfff) + (((addr >> 48) & 0x1ff) << 3)) & a20_mask; - PTE_HPHYS(pte_addr); - pte =3D x86_ldq_phys(cs, pte_addr); + if (!ptw_translate(&pte_trans, pte_addr)) { + return false; + } + restart_5: + pte =3D ptw_ldq(&pte_trans); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } if (pte & (rsvd_mask | PG_PSE_MASK)) { goto do_fault_rsvd; } - if (!(pte & PG_ACCESSED_MASK)) { - pte |=3D PG_ACCESSED_MASK; - x86_stl_phys_notdirty(cs, pte_addr, pte); + if (!ptw_setl(&pte_trans, pte, PG_ACCESSED_MASK)) { + goto restart_5; } ptep =3D pte ^ PG_NX_MASK; } else { @@ -123,17 +188,19 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, */ pte_addr =3D ((pte & PG_ADDRESS_MASK) + (((addr >> 39) & 0x1ff) << 3)) & a20_mask; - PTE_HPHYS(pte_addr); - pte =3D x86_ldq_phys(cs, pte_addr); + if (!ptw_translate(&pte_trans, pte_addr)) { + return false; + } + restart_4: + pte =3D ptw_ldq(&pte_trans); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } if (pte & (rsvd_mask | PG_PSE_MASK)) { goto do_fault_rsvd; } - if (!(pte & PG_ACCESSED_MASK)) { - pte |=3D PG_ACCESSED_MASK; - x86_stl_phys_notdirty(cs, pte_addr, pte); + if (!ptw_setl(&pte_trans, pte, PG_ACCESSED_MASK)) { + goto restart_4; } ptep &=3D pte ^ PG_NX_MASK; =20 @@ -142,19 +209,21 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, */ pte_addr =3D ((pte & PG_ADDRESS_MASK) + (((addr >> 30) & 0x1ff) << 3)) & a20_mask; - PTE_HPHYS(pte_addr); - pte =3D x86_ldq_phys(cs, pte_addr); + if (!ptw_translate(&pte_trans, pte_addr)) { + return false; + } + restart_3_lma: + pte =3D ptw_ldq(&pte_trans); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } if (pte & rsvd_mask) { goto do_fault_rsvd; } - ptep &=3D pte ^ PG_NX_MASK; - if (!(pte & PG_ACCESSED_MASK)) { - pte |=3D PG_ACCESSED_MASK; - x86_stl_phys_notdirty(cs, pte_addr, pte); + if (!ptw_setl(&pte_trans, pte, PG_ACCESSED_MASK)) { + goto restart_3_lma; } + ptep &=3D pte ^ PG_NX_MASK; if (pte & PG_PSE_MASK) { /* 1 GB page */ page_size =3D 1024 * 1024 * 1024; @@ -167,15 +236,21 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, * Page table level 3 */ pte_addr =3D ((in->cr3 & ~0x1f) + ((addr >> 27) & 0x18)) & a20= _mask; - PTE_HPHYS(pte_addr); - pte =3D x86_ldq_phys(cs, pte_addr); + if (!ptw_translate(&pte_trans, pte_addr)) { + return false; + } + rsvd_mask |=3D PG_HI_USER_MASK; + restart_3_nolma: + pte =3D ptw_ldq(&pte_trans); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } - rsvd_mask |=3D PG_HI_USER_MASK; if (pte & (rsvd_mask | PG_NX_MASK)) { goto do_fault_rsvd; } + if (!ptw_setl(&pte_trans, pte, PG_ACCESSED_MASK)) { + goto restart_3_nolma; + } ptep =3D PG_NX_MASK | PG_USER_MASK | PG_RW_MASK; } =20 @@ -184,32 +259,37 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, */ pte_addr =3D ((pte & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) << 3)) & a20_mask; - PTE_HPHYS(pte_addr); - pte =3D x86_ldq_phys(cs, pte_addr); + if (!ptw_translate(&pte_trans, pte_addr)) { + return false; + } + restart_2_pae: + pte =3D ptw_ldq(&pte_trans); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } if (pte & rsvd_mask) { goto do_fault_rsvd; } - ptep &=3D pte ^ PG_NX_MASK; if (pte & PG_PSE_MASK) { /* 2 MB page */ page_size =3D 2048 * 1024; + ptep &=3D pte ^ PG_NX_MASK; goto do_check_protect; } - if (!(pte & PG_ACCESSED_MASK)) { - pte |=3D PG_ACCESSED_MASK; - x86_stl_phys_notdirty(cs, pte_addr, pte); + if (!ptw_setl(&pte_trans, pte, PG_ACCESSED_MASK)) { + goto restart_2_pae; } + ptep &=3D pte ^ PG_NX_MASK; =20 /* * Page table level 1 */ pte_addr =3D ((pte & PG_ADDRESS_MASK) + (((addr >> 12) & 0x1ff) << 3)) & a20_mask; - PTE_HPHYS(pte_addr); - pte =3D x86_ldq_phys(cs, pte_addr); + if (!ptw_translate(&pte_trans, pte_addr)) { + return false; + } + pte =3D ptw_ldq(&pte_trans); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -224,8 +304,11 @@ static bool mmu_translate(CPUX86State *env, const Tran= slateParams *in, * Page table level 2 */ pte_addr =3D ((in->cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_m= ask; - PTE_HPHYS(pte_addr); - pte =3D x86_ldl_phys(cs, pte_addr); + if (!ptw_translate(&pte_trans, pte_addr)) { + return false; + } + restart_2_nopae: + pte =3D ptw_ldl(&pte_trans); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -242,17 +325,18 @@ static bool mmu_translate(CPUX86State *env, const Tra= nslateParams *in, rsvd_mask =3D 0x200000; goto do_check_protect_pse36; } - if (!(pte & PG_ACCESSED_MASK)) { - pte |=3D PG_ACCESSED_MASK; - x86_stl_phys_notdirty(cs, pte_addr, pte); + if (!ptw_setl(&pte_trans, pte, PG_ACCESSED_MASK)) { + goto restart_2_nopae; } =20 /* * Page table level 1 */ pte_addr =3D ((pte & ~0xfffu) + ((addr >> 10) & 0xffc)) & a20_mask; - PTE_HPHYS(pte_addr); - pte =3D x86_ldl_phys(cs, pte_addr); + if (!ptw_translate(&pte_trans, pte_addr)) { + return false; + } + pte =3D ptw_ldl(&pte_trans); if (!(pte & PG_PRESENT_MASK)) { goto do_fault; } @@ -319,27 +403,35 @@ do_check_protect_pse36: uint32_t set =3D PG_ACCESSED_MASK; if (access_type =3D=3D MMU_DATA_STORE) { set |=3D PG_DIRTY_MASK; + } else if (!(pte & PG_DIRTY_MASK)) { + /* + * Only set write access if already dirty... + * otherwise wait for dirty access. + */ + prot &=3D ~PAGE_WRITE; } - if (set & ~pte) { - pte |=3D set; - x86_stl_phys_notdirty(cs, pte_addr, pte); + if (!ptw_setl(&pte_trans, pte, set)) { + /* + * We can arrive here from any of 3 levels and 2 formats. + * The only safe thing is to restart the entire lookup. + */ + goto restart_all; } } =20 - if (!(pte & PG_DIRTY_MASK)) { - /* only set write access if already dirty... otherwise wait - for dirty access */ - assert(access_type !=3D MMU_DATA_STORE); - prot &=3D ~PAGE_WRITE; - } - /* align to page_size */ out->paddr =3D (pte & a20_mask & PG_ADDRESS_MASK & ~(page_size - 1)) | (addr & (page_size - 1)); =20 - if (in->use_stage2) { - nested_in.addr =3D out->paddr; - nested_in.access_type =3D access_type; + if (in->ptw_idx =3D=3D MMU_NESTED_IDX) { + TranslateParams nested_in =3D { + .addr =3D out->paddr, + .access_type =3D access_type, + .cr3 =3D env->nested_cr3, + .pg_mode =3D env->nested_pg_mode, + .mmu_idx =3D MMU_USER_IDX, + .ptw_idx =3D MMU_PHYS_IDX, + }; =20 if (!mmu_translate(env, &nested_in, out, err)) { err->stage2 =3D S2_GPA; @@ -436,7 +528,7 @@ static bool get_physical_address(CPUX86State *env, vadd= r addr, in.cr3 =3D env->nested_cr3; in.pg_mode =3D env->nested_pg_mode; in.mmu_idx =3D MMU_USER_IDX; - in.use_stage2 =3D false; + in.ptw_idx =3D MMU_PHYS_IDX; =20 if (!mmu_translate(env, &in, out, err)) { err->stage2 =3D S2_GPA; @@ -449,7 +541,7 @@ static bool get_physical_address(CPUX86State *env, vadd= r addr, default: in.cr3 =3D env->cr[3]; in.mmu_idx =3D mmu_idx; - in.use_stage2 =3D use_stage2; + in.ptw_idx =3D use_stage2 ? MMU_NESTED_IDX : MMU_PHYS_IDX; in.pg_mode =3D get_pg_mode(env); =20 if (likely(in.pg_mode)) { @@ -504,6 +596,8 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int siz= e, } =20 if (probe) { + /* This will be used if recursing for stage2 translation. */ + env->error_code =3D err.error_code; return false; } =20 --=20 2.34.1 From nobody Sat May 11 23:55:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664732639; cv=none; d=zohomail.com; s=zohoarc; b=lsXjBFq8QxGPKkQLSdesOeHcAu9NeMrFKz5swStl7cTfxZdP0t0MfAuA+v2oraZ9MaRwtV3F9tkHvfgpTr0+bxYMbh3PhzFbgyu5qakTL8pxuX+E4gJQM/u2WzdyxdGC1i7Jf/l3KBFTZklb7hUJ3P4kVXVbVS5OtKx0VuUsrzA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664732639; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=D0hniRphEJcjKKIvbS4Fy3DBAta1qY7jOe+vkMzXYeQ=; b=cKCnrqSNql0IW/N54dk1QYo5rTH8k25mi2pIbDkm0VHo+IYjmKcteS50TCQ9CruHxtF461DB7cS525+rWs0C8YitP2ttgyIG7Uu47EyiI1m9LCHJpRtEa3aP+9C5md1WkDS/lJwl0xOZdUDOZ2ourC0PD9JwPbYWnxFLwReLUyo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664732639969691.037175450432; Sun, 2 Oct 2022 10:43:59 -0700 (PDT) Received: from localhost ([::1]:49784 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1of30R-0008HQ-0T for importer@patchew.org; Sun, 02 Oct 2022 13:43:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57038) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1of2ne-0005VU-J4 for qemu-devel@nongnu.org; Sun, 02 Oct 2022 13:30:47 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:43643) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1of2nc-0006BH-UU for qemu-devel@nongnu.org; Sun, 02 Oct 2022 13:30:46 -0400 Received: by mail-pl1-x62a.google.com with SMTP id z20so1371319plb.10 for ; Sun, 02 Oct 2022 10:30:44 -0700 (PDT) Received: from stoup.. ([2605:ef80:8002:3cad:72cd:dd96:98f6:c3cf]) by smtp.gmail.com with ESMTPSA id 135-20020a62168d000000b0056025ccc3bbsm2749783pfw.146.2022.10.02.10.30.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Oct 2022 10:30:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=D0hniRphEJcjKKIvbS4Fy3DBAta1qY7jOe+vkMzXYeQ=; b=z5AyP6nKX8goP7XUWqYqX6MFobpaM1j0TE4LIzJcuyBmhLaZqlDIJG6mu5NMTkFMif eYYEQXUU5DLliKf9pKv1B4Oj7RUEiyr0lUaKLtwaHcdypCx2rVgSjqeUjaPNNKSiXXqU blQ/O+FGeJc7HriPaaPaurUFZthofAHWlFM7s4TBIv1/I3Oiomyt+meM3Kt4B3rJefch 283in8Mdeanm2NUdnZGXITIIcfh2N4FViY/gsgYAJuGsXayBnL2nw0RHavAXpHGBcot2 zgL8CCY8wq+FVVVadT2shxqRj2fCeX18Sg+EjzzM4hVeCbOb+VIjmoV9MMuXf/68O4Lx Bl4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=D0hniRphEJcjKKIvbS4Fy3DBAta1qY7jOe+vkMzXYeQ=; b=5zsGSlkAlzs8lJbiU0+tt0k5DAWDHx4XGmZn2wRLdmv8Xl6xF7rXpT3Y9XqTodffyY bC/ZyraiGZ/kJEMvRbdDXNyEBqRsBf027bKyWKkGqTG/qeDkJ3VTtTDTDKBK2waiRsaE ET91Xh4/ra1+XHB7xnHUE5eXCIjYWt9kO/6vhj8vMxDgRnT+fEMCJ5Awa/KPfoGxfC5o u3FbeDMRSNg4qCRCsfcIab479WnuEpWoPhYWwK+muia1Mq7z62gZ4EdB0VQo46JmzWco Zf7dVDubu4SqNtSLAB6wXguHOhz5Slv8UPl8ZoHIBHtaiPfoStXAW0PvDu53PxS7trZ4 +m8g== X-Gm-Message-State: ACrzQf0sku9wMKm81X+1BMUy7zDDE6IvhkCDtTz22tqJ1xhDQ4Scck8b uPHvnLxIl4f56UQJ9c1W4dBL95tiUKqwgA== X-Google-Smtp-Source: AMsMyM4a9VUqawBqM4VHPOX3SpNRG1LXvhUguiJa1Vk/ixXfHKACV9kACB1U2WhZdImv7seku1xfRA== X-Received: by 2002:a17:902:ab11:b0:178:23f5:3718 with SMTP id ik17-20020a170902ab1100b0017823f53718mr18795649plb.96.1664731843798; Sun, 02 Oct 2022 10:30:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 9/9] target/i386: Use probe_access_full for final stage2 translation Date: Sun, 2 Oct 2022 10:29:56 -0700 Message-Id: <20221002172956.265735-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221002172956.265735-1-richard.henderson@linaro.org> References: <20221002172956.265735-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664732640830100001 Content-Type: text/plain; charset="utf-8" Rather than recurse directly on mmu_translate, go through the same softmmu lookup that we did for the page table walk. This centralizes all knowledge of MMU_NESTED_IDX, with respect to setup of TranslationParams, to get_physical_address. Signed-off-by: Richard Henderson --- target/i386/tcg/sysemu/excp_helper.c | 40 +++++++++++++++++++--------- 1 file changed, 27 insertions(+), 13 deletions(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index e8457e9b21..d51b5d7431 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -143,7 +143,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, .err =3D err, .ptw_idx =3D in->ptw_idx, }; - hwaddr pte_addr; + hwaddr pte_addr, paddr; uint32_t pkr; int page_size; =20 @@ -420,33 +420,47 @@ do_check_protect_pse36: } =20 /* align to page_size */ - out->paddr =3D (pte & a20_mask & PG_ADDRESS_MASK & ~(page_size - 1)) - | (addr & (page_size - 1)); + paddr =3D (pte & a20_mask & PG_ADDRESS_MASK & ~(page_size - 1)) + | (addr & (page_size - 1)); =20 if (in->ptw_idx =3D=3D MMU_NESTED_IDX) { - TranslateParams nested_in =3D { - .addr =3D out->paddr, - .access_type =3D access_type, - .cr3 =3D env->nested_cr3, - .pg_mode =3D env->nested_pg_mode, - .mmu_idx =3D MMU_USER_IDX, - .ptw_idx =3D MMU_PHYS_IDX, - }; + CPUTLBEntryFull *full; + int flags, nested_page_size; =20 - if (!mmu_translate(env, &nested_in, out, err)) { + flags =3D probe_access_full(env, paddr, access_type, + MMU_NESTED_IDX, true, + &pte_trans.haddr, &full, 0); + if (unlikely(flags & TLB_INVALID_MASK)) { + err->exception_index =3D 0; /* unused */ + err->error_code =3D env->error_code; + err->cr2 =3D paddr; err->stage2 =3D S2_GPA; return false; } =20 /* Merge stage1 & stage2 protection bits. */ - prot &=3D out->prot; + prot &=3D full->prot; =20 /* Re-verify resulting protection. */ if ((prot & (1 << access_type)) =3D=3D 0) { goto do_fault_protect; } + + /* Merge stage1 & stage2 addresses to final physical address. */ + nested_page_size =3D 1 << full->lg_page_size; + paddr =3D (full->phys_addr & ~(nested_page_size - 1)) + | (paddr & (nested_page_size - 1)); + + /* + * Use the larger of stage1 & stage2 page sizes, so that + * invalidation works. + */ + if (nested_page_size > page_size) { + page_size =3D nested_page_size; + } } =20 + out->paddr =3D paddr; out->prot =3D prot; out->page_size =3D page_size; return true; --=20 2.34.1