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([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.23.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:23:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=6Tnfc5rXfCku9MasFsfztuydoPYwIjiauClakmhLN0A=; b=EvjkrmHCJzh9pvhJhXid6iFFNxK7GGiyvCnoXwsWpuW4aUVEsYpMrWxs5WtQBz1C9u Vk98uNPVRXH6i+p97Kq1Mgf98xA2wM5rInMUMp4M1zesAM2H/6bcmzaofMKgMCkhDIGE LMnFxx15UHjyAaHqiCOqVMOxEIQ+CNPDEks1+/4g49F2GYUtNKqo/FFYuwS/U8Lvf3Hm J2G8s9xvHLv2RvnHYou/CxkmCZcfYqpJtiF1q1gRxtXg1CIjdgQyXgxspqXWmMmn0QKi J/EeWoOvsz8wq0Sc0wvCxLdM+i54uZC1wkqMe8mIdhaFc8u+yIl8QFkey4NXNRRqduvn xIVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=6Tnfc5rXfCku9MasFsfztuydoPYwIjiauClakmhLN0A=; b=VVP51IixSrzzUQe2YPEH2Llw9sLg2+1a79m01j8LhpLQSeiEVKk2dW3lpG3M4roIXv v5O32V1WWJ0wIltdPp0glSjQ45elkOwjSaefOj6qkkDG+67B9rBKu+3E4iygbv8/Qdd8 ccvWALuhu9rlH1v+0icEIupA1AxWI5tMroBtUZFJXcivvTMXSB1PChG/ndZS1zAYnmlu Iudnf1tu1K3j8ALDPb8SyA4ams022mYBm6UkFjqL8AVJ75X9XNd32RcdPI/CZhHqZ9j7 fxmZ0SF3gDNHgryv8x7nv6FOCCKG11jLVrDQFir6tgUyYWu2ZQLnRbh1oQW9fjzzgy3E BDsQ== X-Gm-Message-State: ACrzQf1ZkxEml9sFB5cw4rO4wJbfHsg8/PcXxjkI4UgqYw3/YMxILC0K Z0SefOxBsP9Q/FWZzdDQbwNhZ8AJi8BmwA== X-Google-Smtp-Source: AMsMyM61PU8VMEVdykE/halpW/Vjok+sDU1/X3s1JOeI2blWYnTwXe/ZZHBaUA7b/HbrY/qGC6Qq6Q== X-Received: by 2002:a05:622a:1c7:b0:35d:4a61:f2c7 with SMTP id t7-20020a05622a01c700b0035d4a61f2c7mr10802438qtw.578.1664641417854; Sat, 01 Oct 2022 09:23:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v3 06/42] target/arm: Add is_secure parameter to v7m_read_half_insn Date: Sat, 1 Oct 2022 09:22:42 -0700 Message-Id: <20221001162318.153420-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::831; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x831.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664641777983100001 Remove the use of regime_is_secure from v7m_read_half_insn, using the new parameter instead. As it happens, both callers pass true, propagated from the argument to arm_v7m_mmu_idx_for_secstate which created the mmu_idx argument, but that is a detail of v7m_handle_execute_nsc we need not expose to the callee. Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/m_helper.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 5ee4ee15b3..203ba411f6 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -1981,7 +1981,7 @@ static bool do_v7m_function_return(ARMCPU *cpu) return true; } =20 -static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, +static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure, uint32_t addr, uint16_t *insn) { /* @@ -2003,8 +2003,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, ARMMMUFaultInfo fi =3D {}; MemTxResult txres; =20 - v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, - regime_is_secure(env, mmu_idx), &sattrs); + v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, secure, &sattr= s); if (!sattrs.nsc || sattrs.ns) { /* * This must be the second half of the insn, and it straddles a @@ -2109,7 +2108,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) /* We want to do the MPU lookup as secure; work out what mmu_idx that = is */ mmu_idx =3D arm_v7m_mmu_idx_for_secstate(env, true); =20 - if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) { + if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15], &insn)) { return false; } =20 @@ -2125,7 +2124,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) goto gen_invep; } =20 - if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) { + if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15] + 2, &insn))= { return false; } =20 --=20 2.34.1