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([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.23.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:23:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=9SScwWFtisnAsN/gqU42XTsbKaa8LapqZEtG7W5lUds=; b=WDhhg8CYqKrrfbcDfM2mbSd2sZbhjaHTU5eyEx09ElS/0wx/B+LfvPdjEzm0gSc3fa u+GBoMNK6f/Tj1UNroYzbnTK1XrXgUrtYnKvdW2Lgmdjzrx/Pvg5gE6qM80hs4DCR6KU NmwrvJl2Kow1b9Pn1qwVRva6qj+lpuH7yYMZIHzbS03FrIfN9PfxGLfXV2v8Idltio+H vLA6xZns1LFYXBnNw5soaQbfkVSICGluWQebkbt9RVMIZWVUA9acrEYzPmN3AUWCyhK/ HR9Id9DIGEMwQwLqHCFzUOUyqEzJAE/t59CsMTGVkOsOM9x1KRQDBpcUDqcawvFUNdt0 B0lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=9SScwWFtisnAsN/gqU42XTsbKaa8LapqZEtG7W5lUds=; b=Iok1VAuVXSOL3p9MvRQuhwI57JsKnewO1lKpfI9dr+SNWc7DU9JofH3PixbNUY320h OncuzBrk1EQbaqvzL7Bjmw0Ejh6j/kUoqPzrulMjKg+QbIJig2A7HVVRD4GPPH17xQtu tUyB1YCw4pt1WBPJZJv86Zq0n43Kkjzr+uYyAhlSw/zy04DK9tyJHdGqbtz18Wf/iMVh hSxDYisP2f+EO35DRjFUCJK626FNQr+V2X9KOPXPI4i6q59yO9NMJM8Ih8ObHmS0bu6m Xs7eY2N5M0RFEyku8aabvuH6xAgh1yM0dLs+37I77dQfBon7RUaNJSjEJz5FZH3AnLO8 4o+w== X-Gm-Message-State: ACrzQf1qqgeTMOfNRDY2m/yahRL5u1c88nhT2aGY+U7UEex7i6zZZbjk awzjZcFdi+DCjNZSt8pkAXDvdiouZibfNQ== X-Google-Smtp-Source: AMsMyM7xRw5t6uLkNoUSHtBD/6ofNKsW72eY+PU2GtmvtIuyNAt/UpuKDlVdlKAAUWmrlnJxifbTZw== X-Received: by 2002:ac8:5790:0:b0:35b:fd92:6fb8 with SMTP id v16-20020ac85790000000b0035bfd926fb8mr10742059qta.53.1664641424338; Sat, 01 Oct 2022 09:23:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 09/42] target/arm: Add is_secure parameter to do_ats_write Date: Sat, 1 Oct 2022 09:22:45 -0700 Message-Id: <20221001162318.153420-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::835; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x835.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664642071781100001 Content-Type: text/plain; charset="utf-8" Use get_phys_addr_with_secure directly. For a-profile, this is the one place where the value of is_secure may not equal arm_is_secure(env). Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 772218f0d2..3adeb4cab4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3188,7 +3188,8 @@ static CPAccessResult ats_access(CPUARMState *env, co= nst ARMCPRegInfo *ri, =20 #ifdef CONFIG_TCG static uint64_t do_ats_write(CPUARMState *env, uint64_t value, - MMUAccessType access_type, ARMMMUIdx mmu_idx) + MMUAccessType access_type, ARMMMUIdx mmu_idx, + bool is_secure) { bool ret; uint64_t par64; @@ -3196,7 +3197,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, ARMMMUFaultInfo fi =3D {}; GetPhysAddrResult res =3D {}; =20 - ret =3D get_phys_addr(env, value, access_type, mmu_idx, &res, &fi); + ret =3D get_phys_addr_with_secure(env, value, access_type, mmu_idx, + is_secure, &res, &fi); =20 /* * ATS operations only do S1 or S1+S2 translations, so we never @@ -3368,6 +3370,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) switch (el) { case 3: mmu_idx =3D ARMMMUIdx_SE3; + secure =3D true; break; case 2: g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ @@ -3389,6 +3392,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) switch (el) { case 3: mmu_idx =3D ARMMMUIdx_SE10_0; + secure =3D true; break; case 2: g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ @@ -3404,16 +3408,18 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) case 4: /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ mmu_idx =3D ARMMMUIdx_E10_1; + secure =3D false; break; case 6: /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ mmu_idx =3D ARMMMUIdx_E10_0; + secure =3D false; break; default: g_assert_not_reached(); } =20 - par64 =3D do_ats_write(env, value, access_type, mmu_idx); + par64 =3D do_ats_write(env, value, access_type, mmu_idx, secure); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); #else @@ -3429,7 +3435,8 @@ static void ats1h_write(CPUARMState *env, const ARMCP= RegInfo *ri, MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; uint64_t par64; =20 - par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2); + /* There is no SecureEL2 for AArch32. */ + par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2, false); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); #else @@ -3472,6 +3479,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx =3D ARMMMUIdx_SE3; + secure =3D true; break; default: g_assert_not_reached(); @@ -3490,7 +3498,8 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, g_assert_not_reached(); } =20 - env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, mmu_idx); + env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, + mmu_idx, secure); #else /* Handled by hardware accelerator. */ g_assert_not_reached(); --=20 2.34.1