From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664641578; cv=none; d=zohomail.com; s=zohoarc; b=RLE7b1lMTolJFxQG+iwA4IjwlStJHRQX0X9C6DY/SUMrTSxup9Twit7sLQjwgRrxxJDoe8cF/HoDDmkk/gDV+UY7PdSmmJ3C+yUMyBF6tKqZKfP94nvigOdMzpI2BI4/jL/lgngzhpRbsvT/Ffpfd1Sk9Mmv1nIVjGgQUqZCQpI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664641578; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sUrjBJ7dwQzpr5dWkCg6Vpf21komKkvxoPfjuiTQD48=; b=Ih/6EmTWlpvGWYo2jUvyccEoWTbBV+o8IwMgjkMOYzG1qPlQYsi3gsG/kWmuLpCOP7BoHyGQrC93dkJOecdBzbedz+Bsgc0oQ/KWe4jrhMLMwUS9SCFsh2QfqiKbeAVy8lPPlQFrAkaXZvBaA8hHFcYIFrbANvVFHP765srCpHk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664641578498760.021270307285; Sat, 1 Oct 2022 09:26:18 -0700 (PDT) Received: from localhost ([::1]:55224 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefJg-0001YI-8N for importer@patchew.org; Sat, 01 Oct 2022 12:26:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38962) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefGy-0006GI-KC for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:23:28 -0400 Received: from mail-qt1-x82e.google.com ([2607:f8b0:4864:20::82e]:42726) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefGw-0006DO-Ul for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:23:28 -0400 Received: by mail-qt1-x82e.google.com with SMTP id w2so4334795qtv.9 for ; Sat, 01 Oct 2022 09:23:26 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.23.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:23:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=sUrjBJ7dwQzpr5dWkCg6Vpf21komKkvxoPfjuiTQD48=; b=YqMh1wM8B6us+FgC9F+Y0msBRmrQt9992KTMWlqh0DIfeCSsH2RaKRHxX4GHO1B2KP YBSzOpDuIl9chCQiyY0l2tysMreZRfuxE+LKR6BtRopSCN2uNgyzD65/XpYC2w2xLfq0 FIloio4N2J7DtHgBw45C5cRWWr15dXoSCufl549CTqLNttieMHNapW609i9jCVSDJGwl 7zS2z4NJc6RCDgkLTwqbv2ykps/8HROGUf3EIyvDXXDSqwWcT7VCZ2JzIbhpqcK9cJpG 5f4k59riCZxkg/fMCyzMpTkHknHTm9TvUPPINpef1CUyb4g971sldbKKSHbIVT+AUPsC Mbkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=sUrjBJ7dwQzpr5dWkCg6Vpf21komKkvxoPfjuiTQD48=; b=zoP+e+6IrndmO2TcWoiHs158biLFY5gEhajQ8tBwQl+h+svfzJDcRm8rwEAs3YMk4g EQ1hAr+ItT0aBxq697CV4+/bnEDOvVTY7wu0X2mu4ww4cr3Ugc2kVML5Cm51OgWZ355N 69UCG4URdFUSlwc/sGZGVcoMgqmjR15G6LHfibnXvyNv2vTBP9xMbw1+r6ICreIjdkwC Gd3VULsD/3+Gwd0vjre/4xas/fNwwWpr+EI5JFnMI+mP8AWXzVwSKLyfVm2yRf+lcJmr ESbmPYhAEFAAapnJ+MJ3Pbs/+kQilDnBowZRUYyVIidujbce37JmYjIaV7ZNoAYCnFWA 9bWg== X-Gm-Message-State: ACrzQf0eYj7oSEXkp5ODtaTsuNXequDe7isE9zMnBTuaCfscT7eFo2pk vgIBZjniHd8LWajzP4y11sVQ0TsZf8mA7w== X-Google-Smtp-Source: AMsMyM6Jtn8WNNY+4rgtKTSBlcaICjKXRMP+HW5sCeAEHq4YLxWfAni7vbLFJFUiS7my7dpjf8p8gA== X-Received: by 2002:a05:622a:2c8:b0:35d:4b4d:57b0 with SMTP id a8-20020a05622a02c800b0035d4b4d57b0mr11032021qtx.307.1664641405917; Sat, 01 Oct 2022 09:23:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 01/42] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr Date: Sat, 1 Oct 2022 09:22:37 -0700 Message-Id: <20221001162318.153420-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82e; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664641578890100001 Content-Type: text/plain; charset="utf-8" The starting security state comes with the translation regime, not the current state of arm_is_secure_below_el3(). Create a new local variable, s2walk_secure, which does not need to be written back to result->attrs.secure -- we compute that value later, after the S2 walk is complete. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v3: Do not modify ipa_secure, per review. --- target/arm/ptw.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 2ddfc028ab..b8c494ad9f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2298,7 +2298,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, hwaddr ipa; int s1_prot; int ret; - bool ipa_secure; + bool ipa_secure, s2walk_secure; ARMCacheAttrs cacheattrs1; ARMMMUIdx s2_mmu_idx; bool is_el0; @@ -2313,17 +2313,17 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, =20 ipa =3D result->phys; ipa_secure =3D result->attrs.secure; - if (arm_is_secure_below_el3(env)) { - if (ipa_secure) { - result->attrs.secure =3D !(env->cp15.vstcr_el2 & VSTCR= _SW); - } else { - result->attrs.secure =3D !(env->cp15.vtcr_el2 & VTCR_N= SW); - } + if (is_secure) { + /* Select TCR based on the NS bit from the S1 walk. */ + s2walk_secure =3D !(ipa_secure + ? env->cp15.vstcr_el2 & VSTCR_SW + : env->cp15.vtcr_el2 & VTCR_NSW); } else { assert(!ipa_secure); + s2walk_secure =3D false; } =20 - s2_mmu_idx =3D (result->attrs.secure + s2_mmu_idx =3D (s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2); is_el0 =3D mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D AR= MMMUIdx_SE10_0; =20 @@ -2366,7 +2366,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, result->cacheattrs); =20 /* Check if IPA translates to secure or non-secure PA space. */ - if (arm_is_secure_below_el3(env)) { + if (is_secure) { if (ipa_secure) { result->attrs.secure =3D !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)); --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664641717; cv=none; d=zohomail.com; s=zohoarc; b=QBOHoFev64hGy6y3BKHM7hAdt3zRf0xALfmYjhVlQHC/gDoDG99VBEHSCTppCyhFNAZNWghj9+rt/Tm+qTSZtg69sWtidcL4EvUlVk7q2oQ9V3O1YBq+bI+Ir0ZkaJoH5iuVuH3rqneGuYTJZF/duDlOL1nxLkvxm4nJN7+EQLY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664641717; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=t773ZS2LkVFwCoSMRlKqTFzA/pnkk1Ts0faFvUW3ikE=; b=OlaXuPh1KwoMjlUhVmIX633ebMtx2IGKqQiLbmARzZJ/RohTP2oEEy01ohahbY1ecHODh6qg9QDRbHg/k/iImv+aY3yrZ0kgbzm2cSKp+XJfTfeqHrwx7O/NLDIGqPDcfUUhfV3U6108DH4JTyE0gSY0Tccd1qz6jLCFOJ8wA80= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664641717567167.29216597557945; Sat, 1 Oct 2022 09:28:37 -0700 (PDT) Received: from localhost ([::1]:56100 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefLv-000778-Iv for importer@patchew.org; Sat, 01 Oct 2022 12:28:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38968) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefH2-0006RC-Vq for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:23:33 -0400 Received: from mail-qt1-x82a.google.com ([2607:f8b0:4864:20::82a]:45762) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefGz-0006Dr-7e for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:23:32 -0400 Received: by mail-qt1-x82a.google.com with SMTP id r20so4337968qtn.12 for ; Sat, 01 Oct 2022 09:23:28 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.23.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:23:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=t773ZS2LkVFwCoSMRlKqTFzA/pnkk1Ts0faFvUW3ikE=; b=fIcAYeOm9YcTeJK2gY64bWOaHy2X6wPoM0G/auDpVHgwHzrxfWiKO3WQ5cEpR41pDY VdBbzyCXqZLMxpPwhYJ1vf0y8dnwqOjBGgIxGJX2l71ciMRnaCyqo68Ru5EhwCg90u3P mO0eNEYs/7xYobvwDohnYjTUcE82i3tn6BtRT/rMdrqfktXHyfq6DiV/Ntpz8XCAIxtx 2KOOEXZ+Yh7p6Y3hO/8XT0JYBxSrQQ814nkl0dqDwRjhd9FKrRgMr1L7zN0O6GZyV5At jzBoct6crLtJ/HTjjWMaElcjuk+OfSfohYmD/94vyDoUmp2BfqSXcakijraOx7pq5VKI bPvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=t773ZS2LkVFwCoSMRlKqTFzA/pnkk1Ts0faFvUW3ikE=; b=8Itl1rA+pXQHsOx3g0souOhYOvJYNUTSjz35a/lDxh6N0hpVsswwnpa4/mqtaOyuDW gw4f/yhZAOiTPB7soZ1Oa69jyspJdhv0QZhqns5RLNyUmlgeqqeD68VOBkEM40ljGrcA FybDdmTXYYl3T25thXVmHm0HyyqOzhd9SWPOrrgo/NTAAVe3S444YSsfFs4VcIwzt4AS I8Y6sC8fcS+wy6luUyLQ91JZcQB1Zyr+rvRj1iI8t//T/pL2MSM+17zpfJBb6095IudV uUArYbMNqv2DvBC0vBwECbkEfrHXPqWDE3pSk5mAD8rhKbC6w47TjQXWdWcxuVkJdf57 sgpQ== X-Gm-Message-State: ACrzQf2FYnwQmUSoAc54AZ0oe7faKDK0XQ6d9fImFwrNVKIigIJ0Pito ET8PXBNe+ZIO6fmdXSHpB5n7UDpV3OfM8A== X-Google-Smtp-Source: AMsMyM7rkAEob9HL5X4HOg85wvfWn2u/ZfZaY2uLvL3HqJSYBOE/LBrVXuop7qRvCfPWQV+wJXEyFA== X-Received: by 2002:ac8:5a86:0:b0:35c:d85f:915e with SMTP id c6-20020ac85a86000000b0035cd85f915emr11130479qtc.19.1664641408261; Sat, 01 Oct 2022 09:23:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v3 02/42] target/arm: Add is_secure parameter to get_phys_addr_lpae Date: Sat, 1 Oct 2022 09:22:38 -0700 Message-Id: <20221001162318.153420-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82a; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664641719640100001 Remove the use of regime_is_secure from get_phys_addr_lpae, using the new parameter instead. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- v3: Update to use s2walk_secure. --- target/arm/ptw.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b8c494ad9f..b7c999ffce 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -16,8 +16,8 @@ =20 static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, - bool s1_is_el0, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) + bool is_secure, bool s1_is_el0, + GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) __attribute__((nonnull)); =20 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. = */ @@ -207,8 +207,8 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, GetPhysAddrResult s2 =3D {}; int ret; =20 - ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, f= alse, - &s2, fi); + ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, + *is_secure, false, &s2, fi); if (ret) { assert(fi->type !=3D ARMFault_None); fi->s2addr =3D addr; @@ -965,8 +965,8 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa6= 4, int level, */ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, - bool s1_is_el0, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) + bool is_secure, bool s1_is_el0, + GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) { ARMCPU *cpu =3D env_archcpu(env); /* Read an LPAE long-descriptor translation table. */ @@ -1183,7 +1183,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, * remain non-secure. We implement this by just ORing in the NSTable/NS * bits at each step. */ - tableattrs =3D regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); + tableattrs =3D is_secure ? 0 : (1 << 4); for (;;) { uint64_t descriptor; bool nstable; @@ -2337,7 +2337,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, memset(result, 0, sizeof(*result)); =20 ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, - is_el0, result, fi); + s2walk_secure, is_el0, result, fi); fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ @@ -2505,8 +2505,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, } =20 if (regime_using_lpae_format(env, mmu_idx)) { - return get_phys_addr_lpae(env, address, access_type, mmu_idx, fals= e, - result, fi); + return get_phys_addr_lpae(env, address, access_type, mmu_idx, + is_secure, false, result, fi); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, is_secure, result, fi); --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664641589; cv=none; d=zohomail.com; s=zohoarc; b=LE4lzmts9d5KhnnTopKARbIE5EzZ1lfBiS6IfuZ56xHp/UY/EBWHxYp5Fr1vTD/JgE9qYNUVHRf2f/YizhrDsh8E3ZBx8Nkr/awnxmPvOjXaXOtXecPqok1oSb4F3Wf5Ko2FbOoJkav8I1ZiBpmfEb2OxARY/x6XzBvTr2TUV+s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664641589; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4KPhpY52J+00g3rHXmwrM1G3yOLaxgKqSa5cCKMMs9A=; b=m9Hk1CICst/39qixffiWkZZnnux2q1BXUS5E4E1NeiinSxVZ2hC2deLPQIPaJBibGlKHg5eLrKrAyMOXVJsy3erp/fivsRaQZ+8gKOONfWnI1Jcmhv8e9mba8ZaesIadWJMOIEPSLtEa/qJJl3fgmkirq1mmERL5XMcsW/048yY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664641588999796.4372302146318; Sat, 1 Oct 2022 09:26:28 -0700 (PDT) Received: from localhost ([::1]:33626 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefJr-0001jp-Nn for importer@patchew.org; Sat, 01 Oct 2022 12:26:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38972) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefH4-0006Um-00 for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:23:34 -0400 Received: from mail-qk1-x72e.google.com ([2607:f8b0:4864:20::72e]:44922) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefH2-0006E9-E3 for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:23:33 -0400 Received: by mail-qk1-x72e.google.com with SMTP id y2so4533095qkl.11 for ; Sat, 01 Oct 2022 09:23:31 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.23.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:23:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=4KPhpY52J+00g3rHXmwrM1G3yOLaxgKqSa5cCKMMs9A=; b=u9Wvim0cMQjf9esrozY6ssOA+U9vwHLZPGfHv57i3jsrfPtwL84T1AueH/E+xQNZXH 6tPsMJfuMJybXISYCK/c7WHNA9KBSO/OBhQ30qQfc8VBobhjwn/975FVMS0odocg1voq H+jJVFO0UNb1UO1MQNkTL+V3fgxlDy0ucMC2eVqh7sdX/JoR2fSHdLbYDD20YYMc/dqL DHb9qSu+aO7tFYh5wHHHB2ByehveodQSbl9cvW8iaYhYiFX5XTXlh2pmI7Y8jcnlpNvh C0SJRzl705cqqmFUJ98k4hz6P9vmO1vDFTx2ap+xFUs1F9/AbYYZ8V6JTcPmmeVlxyI4 KR9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=4KPhpY52J+00g3rHXmwrM1G3yOLaxgKqSa5cCKMMs9A=; b=DQFIeklWAwT38sI3caXOX5MeER9UxwGgaG7z/0jUfENG3pyMMZ6jMIrBQ/5H0vnfrs diZvNY+9FrJjKG9Rem46qUD5mBxm3nK//Q90QAEoOFfURdcI1A5MyjZEaqbh4eNhrfEg 8Rs1aCG0oUmUCc05F5LoskL8GOXsXzxFQ7Xm22Au/8Qm1Vd1vbEmIhKFI1Ygac7qGq/L OYRK4AlxHgYMm4MFZbHT5uV7JOvX8LSFMP5j4Ebdoz3Q1X1qKRn1toVQxjuAZssMhlZO fbH88W/OZlwG3WyyA7Il/ZBm8ZinjhYzS3DXUhRml7KsnrWjAhq8C3QfdIxEaS4CdWQl W8Ng== X-Gm-Message-State: ACrzQf0vDcFzT3evRcRnOjDwBsj/jQrvf5MmZN8TnAQhprckI+1RNDb9 ts9X99R2gftx1C7HIsbkWJnQs4z2WK3fMQ== X-Google-Smtp-Source: AMsMyM7d3KMroM72iCxdgS6nrHqJ36NM5Ekdtq8wyEbcR2mXq+pdpEPoUG5QSctM/P2shDib+EpW4Q== X-Received: by 2002:a37:c443:0:b0:6ce:191a:bb60 with SMTP id h3-20020a37c443000000b006ce191abb60mr9577433qkm.53.1664641410360; Sat, 01 Oct 2022 09:23:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 03/42] target/arm: Fix S2 disabled check in S1_ptw_translate Date: Sat, 1 Oct 2022 09:22:39 -0700 Message-Id: <20221001162318.153420-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72e; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664641590827100001 Content-Type: text/plain; charset="utf-8" Pass the correct stage2 mmu_idx to regime_translation_disabled, which we computed afterward. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v3: Move earlier in the patch set. --- target/arm/ptw.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b7c999ffce..5192418c0e 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -200,10 +200,10 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, hwaddr addr, bool *is_secure, ARMMMUFaultInfo *fi) { + ARMMMUIdx s2_mmu_idx =3D *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_S= tage2; + if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { - ARMMMUIdx s2_mmu_idx =3D *is_secure ? ARMMMUIdx_Stage2_S - : ARMMMUIdx_Stage2; + !regime_translation_disabled(env, s2_mmu_idx)) { GetPhysAddrResult s2 =3D {}; int ret; =20 --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664641554; cv=none; d=zohomail.com; s=zohoarc; b=UFp4LW1GGiIG69aiy7jYT7xzZd9jcPJoIp8VKH7DPoqKZC6nse9FEkyIZAGdDlsCLVVXEYni7APhwbm61AsOAW2WaRiWUSMolW/i6hST/W0Q4/4pNuWZfUfEUprhCRGD/Yb3caRx9KreYW0m/ynuXmZnOQIK9Mt48r3b6gC9h58= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664641554; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1FqO/N9pjgiiBZnjptWqpBsjNoDh4nF55unoVGGZ15E=; b=f3E91PTjo3YMTgTkstxF5DdAW5du5EpZrJg89Wk1iEOQZUQciYVCsFVV0wO7qxPetv2Zr05+QplKjNkz5/zOMYDBzgqoVFYSuxxRGEOu07IIIkmiUd3pfBI3S6r1fHS47qFbmLxCvm4jijafkCg/S512rZgLCKWXm/FDAdo3Pvk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16646415541998.72478567711255; Sat, 1 Oct 2022 09:25:54 -0700 (PDT) Received: from localhost ([::1]:50460 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefJH-0001GJ-Om for importer@patchew.org; Sat, 01 Oct 2022 12:25:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38974) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefH5-0006WJ-FX for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:23:35 -0400 Received: from mail-qt1-x832.google.com ([2607:f8b0:4864:20::832]:47038) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefH3-0006EV-UL for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:23:35 -0400 Received: by mail-qt1-x832.google.com with SMTP id b23so4322506qtr.13 for ; Sat, 01 Oct 2022 09:23:33 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.23.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:23:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=1FqO/N9pjgiiBZnjptWqpBsjNoDh4nF55unoVGGZ15E=; b=J9r8uic4TB2HoXqNDO4naBMrtbWQ/HlsKOqMLd+y1haOoDBx1uPXVhc8CimtzJVhCm Jv0dz9l6xhLtKJ2l/7ktGrrK1Z00Bk88H17VL9pKAFYUNdf+K+e+FQiiU5toSaI9by6t AS7W+pF+Rhhe9wCB6Y3eAP3XH0EGU8xHx8S6Yyy+XUG106C5C+UaihATPfzCl/9vACAJ gz+x6ikWD26iqHs+AaYxXvBCglBGV1iduFEoVF9dxFrThmLK0FrUXmCJ91QOf1iAay91 n9dg5XBVWKQGpqg2WbLtHShZZ8YE75Yvi8d4dXLTJHwkeDn3lyRAZEyeqP22Vb4a69W4 uFSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=1FqO/N9pjgiiBZnjptWqpBsjNoDh4nF55unoVGGZ15E=; b=T/zGNuOr5s3I5KviCPe7r/5quC4H+gto6b0lgQWagEvZh872PAbIrBbVrfQlOQHlmq 6SIxVzcR54FgRzeLyB8ouOhQIFcEKQNgPhnMX/zeGaI4t3pDLdDzuqdrxp/alsqtSZlO cjjEDur5dtofodxrAHGLePqcUOpB+aRjOQSXLkonCDrYuKz2nhbM1epVpu/AcKhMXE2z h7aPd8xH4PaQ613pqCqaGrVB62QeMmAi45spekNdNISwc0hh/27oPdKX0Rui9/fYP3eW 7wIAQRnXZog+zdOcxJh6lMvslohSajo6asZfGtHeOlS0wmc5nDYbi3f2LcLSfs0tDHei QRcA== X-Gm-Message-State: ACrzQf2KJ6e9Jruy2EiXpD5dox+t/78wECbYcYFkLH7+Cq0mL2Mw14Uv nUCzRBTA/YByOfqA2+ofkJoy57DJYn+x0g== X-Google-Smtp-Source: AMsMyM6hmDWSAB6weAcqCD4pSBfsr2WeVFqZI49VpInu9i4S7mmoCswPfh7eI9rU0+P+m3+7fh0ClA== X-Received: by 2002:a05:622a:111:b0:35d:51e8:9620 with SMTP id u17-20020a05622a011100b0035d51e89620mr11160539qtw.172.1664641412784; Sat, 01 Oct 2022 09:23:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v3 04/42] target/arm: Add is_secure parameter to regime_translation_disabled Date: Sat, 1 Oct 2022 09:22:40 -0700 Message-Id: <20221001162318.153420-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::832; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x832.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664641554786100001 Remove the use of regime_is_secure from regime_translation_disabled, using the new parameter instead. This fixes a bug in S1_ptw_translate and get_phys_addr where we had passed ARMMMUIdx_Stage2 and not ARMMMUIdx_Stage2_S to determine if Stage2 is disabled, affecting FEAT_SEL2. Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/ptw.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5192418c0e..f9b7c316d0 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -131,12 +131,13 @@ static uint64_t regime_ttbr(CPUARMState *env, ARMMMUI= dx mmu_idx, int ttbrn) } =20 /* Return true if the specified stage of address translation is disabled */ -static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_id= x) +static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_id= x, + bool is_secure) { uint64_t hcr_el2; =20 if (arm_feature(env, ARM_FEATURE_M)) { - switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & + switch (env->v7m.mpu_ctrl[is_secure] & (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK= )) { case R_V7M_MPU_CTRL_ENABLE_MASK: /* Enabled, but not for HardFault and NMI */ @@ -163,7 +164,7 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx) =20 if (hcr_el2 & HCR_TGE) { /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ - if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) =3D= =3D 1) { + if (!is_secure && regime_el(env, mmu_idx) =3D=3D 1) { return true; } } @@ -203,7 +204,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, ARMMMUIdx s2_mmu_idx =3D *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_S= tage2; =20 if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, s2_mmu_idx)) { + !regime_translation_disabled(env, s2_mmu_idx, *is_secure)) { GetPhysAddrResult s2 =3D {}; int ret; =20 @@ -1357,7 +1358,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, ui= nt32_t address, uint32_t base; bool is_user =3D regime_is_user(env, mmu_idx); =20 - if (regime_translation_disabled(env, mmu_idx)) { + if (regime_translation_disabled(env, mmu_idx, is_secure)) { /* MPU disabled. */ result->phys =3D address; result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -1521,7 +1522,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, result->page_size =3D TARGET_PAGE_SIZE; result->prot =3D 0; =20 - if (regime_translation_disabled(env, mmu_idx) || + if (regime_translation_disabled(env, mmu_idx, secure) || m_is_ppb_region(env, address)) { /* * MPU disabled or M profile PPB access: use default memory map. @@ -1733,7 +1734,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, * are done in arm_v7m_load_vector(), which always does a direct * read using address_space_ldl(), rather than going via this function. */ - if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ + if (regime_translation_disabled(env, mmu_idx, secure)) { /* MPU disabl= ed */ hit =3D true; } else if (m_is_ppb_region(env, address)) { hit =3D true; @@ -2307,7 +2308,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, result, fi); =20 /* If S1 fails or S2 is disabled, return early. */ - if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2))= { + if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, + is_secure)) { return ret; } =20 @@ -2438,7 +2440,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, =20 /* Definitely a real MMU, not an MPU */ =20 - if (regime_translation_disabled(env, mmu_idx)) { + if (regime_translation_disabled(env, mmu_idx, is_secure)) { uint64_t hcr; uint8_t memattr; =20 --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664641773; cv=none; d=zohomail.com; s=zohoarc; b=BamRxSKdN49LKU6xTMaTQ4v7usdqDddoOfJTwOS13k5ZtTL8plHvShJrWt0Ad733l8DS8Ht0gaSGCjD6HZsetpTsNr/Ux3Scs2mbCJyCkvMw0yE+Ls9OWGWWGqnzdjgmCK1S4g6fnhHv+AlGwvM1U8qGSPhe0HDtscHOWZhaYAc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664641773; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yMwwAQATpt9Zz9/JT2D65VdUDyPtcQpJeVsrKct0TfU=; b=GUAPlC0zp1zKKdG+X2zj0t7i1rVk8GeA1EK0Jpm+TXjgD+0UPibA8sNpW33abk49YY4tOe2/8Q4HCjcUhohhxFf+tkmxTuqkH8MWYr2OnylO/LIz3jF9zpTkMaFV8ooU0wJaxvTI9vXfk2QF58W4ooT1VAkb1d8wwoyRKOGafTU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664641773517628.75671647725; Sat, 1 Oct 2022 09:29:33 -0700 (PDT) Received: from localhost ([::1]:46668 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefMp-0007r1-VK for importer@patchew.org; Sat, 01 Oct 2022 12:29:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59200) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefH8-0006ZK-J0 for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:23:39 -0400 Received: from mail-qk1-x729.google.com ([2607:f8b0:4864:20::729]:34404) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefH6-0006F8-OS for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:23:38 -0400 Received: by mail-qk1-x729.google.com with SMTP id g2so4548539qkk.1 for ; Sat, 01 Oct 2022 09:23:35 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.23.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:23:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=yMwwAQATpt9Zz9/JT2D65VdUDyPtcQpJeVsrKct0TfU=; b=yAYBdS8XMhhzHwF2PrGhZuK/m6ZrpzRybrMdH8EdU53pA9Kb8G+Z5r3SGgiU/BSAKx bR3iUbp/L9yQMXlBv94nCuRv23r46XbdcyNImoVfcSV5w7CG2W1d/0bwY9KEjjQWZ+h6 REm9hUOsDnzUQsyatGuUcFV9MAC9TGfg4BLo0ypUcOeq65vIKHgZmc8IBye91FT1azA/ VNxHoY70T3RW3fAcrYlkkHUa1FtYLAjzIqoHc8QsefwiHD5XYkRCHRQAr9Z99Ne2gvEp r2T3aXBMItUeb6Wr0q+wjt0k9T2mb3lCVGmIx5n4UrAK8X0JNPyrSGqCeJoq9gE0HXFs ozGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=yMwwAQATpt9Zz9/JT2D65VdUDyPtcQpJeVsrKct0TfU=; b=5IphiIpqYSbnuxtah1ZfCpeNBh19gTHT23dSIcG4WZcCOI0TQ1BqvF9UOQ7mFVunby kjw5LYhqdPAKDD8No+XIKKOIYFcGLhT7vqSJpLw9tCAYx+D3g6HNiu6j3z1YdYlPcyKv 2evEWdFuz99b/Ukg66E51ZxOtTmwYsQw1FHjCEy/cjqLBXEWk71gaLaHZxwtjTK41yYY WPkinbOlWweKAlDFaxo9ex4yYtWvLeSm3/hfnIWLNtTAy2j4EkKLO66gUzirN0r4jRWM l8Wovv7M4b2Nl/ot0xiAVMcpQuh8YUkw+jJrS2PyoxgSio5SntZ+6i3eaaW0aUXVBpYd sMOQ== X-Gm-Message-State: ACrzQf1tFKNZIRy6CTUODcgKrHcLT7w+OWSuolNxvynp5UiPKJjdgSN+ cGJgOcAkFAahB+WfWTqwOa25pISnEqDHiA== X-Google-Smtp-Source: AMsMyM6/G63eDLYU7mv+cfaz4mxVGMYDAanWTNn5KEBPWtUn6otoMz1lNl5xPX74tpZXE1Dv+yMR/g== X-Received: by 2002:a05:620a:4515:b0:6ce:7335:4e77 with SMTP id t21-20020a05620a451500b006ce73354e77mr9886130qkp.507.1664641415130; Sat, 01 Oct 2022 09:23:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 05/42] target/arm: Split out get_phys_addr_with_secure Date: Sat, 1 Oct 2022 09:22:41 -0700 Message-Id: <20221001162318.153420-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::729; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x729.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664641774027100001 Content-Type: text/plain; charset="utf-8" Retain the existing get_phys_addr interface using the security state derived from mmu_idx. Move the kerneldoc comments to the header file where they belong. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Move the kerneldoc to internals.h --- target/arm/internals.h | 40 ++++++++++++++++++++++++++++++++++++++ target/arm/ptw.c | 44 ++++++++++++++---------------------------- 2 files changed, 55 insertions(+), 29 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 307a596505..3524d11dc5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1145,6 +1145,46 @@ typedef struct GetPhysAddrResult { ARMCacheAttrs cacheattrs; } GetPhysAddrResult; =20 +/** + * get_phys_addr_with_secure: get the physical address for a virtual addre= ss + * @env: CPUARMState + * @address: virtual address to get physical address for + * @access_type: 0 for read, 1 for write, 2 for execute + * @mmu_idx: MMU index indicating required translation regime + * @is_secure: security state for the access + * @result: set on translation success. + * @fi: set to fault info if the translation fails + * + * Find the physical address corresponding to the given virtual address, + * by doing a translation table walk on MMU based systems or using the + * MPU state on MPU based systems. + * + * Returns false if the translation was successful. Otherwise, phys_ptr, a= ttrs, + * prot and page_size may not be filled in, and the populated fsr value pr= ovides + * information on why the translation aborted, in the format of a + * DFSR/IFSR fault register, with the following caveats: + * * we honour the short vs long DFSR format differences. + * * the WnR bit is never set (the caller must do this). + * * for PSMAv5 based systems we don't bother to return a full FSR format + * value. + */ +bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, bool is_secure, + GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) + __attribute__((nonnull)); + +/** + * get_phys_addr: get the physical address for a virtual address + * @env: CPUARMState + * @address: virtual address to get physical address for + * @access_type: 0 for read, 1 for write, 2 for execute + * @mmu_idx: MMU index indicating required translation regime + * @result: set on translation success. + * @fi: set to fault info if the translation fails + * + * Similarly, but use the security regime of @mmu_idx. + */ bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index f9b7c316d0..542111f99e 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2260,35 +2260,12 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState= *env, return ret; } =20 -/** - * get_phys_addr - get the physical address for this virtual address - * - * Find the physical address corresponding to the given virtual address, - * by doing a translation table walk on MMU based systems or using the - * MPU state on MPU based systems. - * - * Returns false if the translation was successful. Otherwise, phys_ptr, a= ttrs, - * prot and page_size may not be filled in, and the populated fsr value pr= ovides - * information on why the translation aborted, in the format of a - * DFSR/IFSR fault register, with the following caveats: - * * we honour the short vs long DFSR format differences. - * * the WnR bit is never set (the caller must do this). - * * for PSMAv5 based systems we don't bother to return a full FSR format - * value. - * - * @env: CPUARMState - * @address: virtual address to get physical address for - * @access_type: 0 for read, 1 for write, 2 for execute - * @mmu_idx: MMU index indicating required translation regime - * @result: set on translation success. - * @fi: set to fault info if the translation fails - */ -bool get_phys_addr(CPUARMState *env, target_ulong address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, ARMMMUFaultInfo *fi) +bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_id= x, + bool is_secure, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) { ARMMMUIdx s1_mmu_idx =3D stage_1_mmu_idx(mmu_idx); - bool is_secure =3D regime_is_secure(env, mmu_idx); =20 if (mmu_idx !=3D s1_mmu_idx) { /* @@ -2304,8 +2281,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, ARMMMUIdx s2_mmu_idx; bool is_el0; =20 - ret =3D get_phys_addr(env, address, access_type, s1_mmu_idx, - result, fi); + ret =3D get_phys_addr_with_secure(env, address, access_type, + s1_mmu_idx, is_secure, result,= fi); =20 /* If S1 fails or S2 is disabled, return early. */ if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, @@ -2518,6 +2495,15 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, } } =20 +bool get_phys_addr(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) +{ + return get_phys_addr_with_secure(env, address, access_type, mmu_idx, + regime_is_secure(env, mmu_idx), + result, fi); +} + hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664641777; cv=none; d=zohomail.com; s=zohoarc; b=av2EMdjU3PRPu//Xp6HtwRpb5sy1mrC9MyliI2TtXlGJ+TUy9WprHPccHGL9sdfqW2kq396mIPmFwAhjMdj7rIoEcC+5E+CTjP0PZkTJ1S3FwSnNPOmr8UyA4AR4P1p7+j6Qq49MSddcLjPVh9i2VamOjQ2oh7uX518v/1lhuS0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664641777; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6Tnfc5rXfCku9MasFsfztuydoPYwIjiauClakmhLN0A=; b=DLBqXS7P1JltpNGvp0SMlL5aRL1Bl9SRaUfT/h2w1EsRgEFgdKgVMWw499xoC/JmyiUyOrYOnj9RCXhJC7PMJV/SfVAVHDKRilNDLD1zl8qccY5PEvZkEZ4OI/kgY23qgrWkNTLzIbLQgFYTKD0Q6zOhsRYcFnVKAaveNO3jPTo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664641777267207.03842504225895; Sat, 1 Oct 2022 09:29:37 -0700 (PDT) Received: from localhost ([::1]:46676 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefMu-0007yV-6u for importer@patchew.org; Sat, 01 Oct 2022 12:29:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59206) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefHB-0006d0-Hc for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:23:41 -0400 Received: from mail-qt1-x831.google.com ([2607:f8b0:4864:20::831]:40490) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefH8-0006DP-GT for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:23:40 -0400 Received: by mail-qt1-x831.google.com with SMTP id cj27so4336523qtb.7 for ; Sat, 01 Oct 2022 09:23:38 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.23.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:23:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=6Tnfc5rXfCku9MasFsfztuydoPYwIjiauClakmhLN0A=; b=EvjkrmHCJzh9pvhJhXid6iFFNxK7GGiyvCnoXwsWpuW4aUVEsYpMrWxs5WtQBz1C9u Vk98uNPVRXH6i+p97Kq1Mgf98xA2wM5rInMUMp4M1zesAM2H/6bcmzaofMKgMCkhDIGE LMnFxx15UHjyAaHqiCOqVMOxEIQ+CNPDEks1+/4g49F2GYUtNKqo/FFYuwS/U8Lvf3Hm J2G8s9xvHLv2RvnHYou/CxkmCZcfYqpJtiF1q1gRxtXg1CIjdgQyXgxspqXWmMmn0QKi J/EeWoOvsz8wq0Sc0wvCxLdM+i54uZC1wkqMe8mIdhaFc8u+yIl8QFkey4NXNRRqduvn xIVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=6Tnfc5rXfCku9MasFsfztuydoPYwIjiauClakmhLN0A=; b=VVP51IixSrzzUQe2YPEH2Llw9sLg2+1a79m01j8LhpLQSeiEVKk2dW3lpG3M4roIXv v5O32V1WWJ0wIltdPp0glSjQ45elkOwjSaefOj6qkkDG+67B9rBKu+3E4iygbv8/Qdd8 ccvWALuhu9rlH1v+0icEIupA1AxWI5tMroBtUZFJXcivvTMXSB1PChG/ndZS1zAYnmlu Iudnf1tu1K3j8ALDPb8SyA4ams022mYBm6UkFjqL8AVJ75X9XNd32RcdPI/CZhHqZ9j7 fxmZ0SF3gDNHgryv8x7nv6FOCCKG11jLVrDQFir6tgUyYWu2ZQLnRbh1oQW9fjzzgy3E BDsQ== X-Gm-Message-State: ACrzQf1ZkxEml9sFB5cw4rO4wJbfHsg8/PcXxjkI4UgqYw3/YMxILC0K Z0SefOxBsP9Q/FWZzdDQbwNhZ8AJi8BmwA== X-Google-Smtp-Source: AMsMyM61PU8VMEVdykE/halpW/Vjok+sDU1/X3s1JOeI2blWYnTwXe/ZZHBaUA7b/HbrY/qGC6Qq6Q== X-Received: by 2002:a05:622a:1c7:b0:35d:4a61:f2c7 with SMTP id t7-20020a05622a01c700b0035d4a61f2c7mr10802438qtw.578.1664641417854; Sat, 01 Oct 2022 09:23:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v3 06/42] target/arm: Add is_secure parameter to v7m_read_half_insn Date: Sat, 1 Oct 2022 09:22:42 -0700 Message-Id: <20221001162318.153420-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::831; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x831.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664641777983100001 Remove the use of regime_is_secure from v7m_read_half_insn, using the new parameter instead. As it happens, both callers pass true, propagated from the argument to arm_v7m_mmu_idx_for_secstate which created the mmu_idx argument, but that is a detail of v7m_handle_execute_nsc we need not expose to the callee. Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/m_helper.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 5ee4ee15b3..203ba411f6 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -1981,7 +1981,7 @@ static bool do_v7m_function_return(ARMCPU *cpu) return true; } =20 -static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, +static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure, uint32_t addr, uint16_t *insn) { /* @@ -2003,8 +2003,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, ARMMMUFaultInfo fi =3D {}; MemTxResult txres; =20 - v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, - regime_is_secure(env, mmu_idx), &sattrs); + v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, secure, &sattr= s); if (!sattrs.nsc || sattrs.ns) { /* * This must be the second half of the insn, and it straddles a @@ -2109,7 +2108,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) /* We want to do the MPU lookup as secure; work out what mmu_idx that = is */ mmu_idx =3D arm_v7m_mmu_idx_for_secstate(env, true); =20 - if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) { + if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15], &insn)) { return false; } =20 @@ -2125,7 +2124,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) goto gen_invep; } =20 - if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) { + if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15] + 2, &insn))= { return false; } =20 --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664641761; cv=none; d=zohomail.com; s=zohoarc; b=JOKsEY/mZIHPPeoTU7MwWBtPNshJ5WD+Qob/99wcvy2OegH2tblUOq/y+TbeXT+WpSMi6IKtK3X6QKsCTwHqjxW1XI9FfIrKozOd73U/xe01Pjge2A3z0koHDp5fiVCxCBbhZiVUsRPZHEjQDKK8XFoCyPdAtRQbBq4bHVKW3wk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664641761; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9IDKhGDW8UhVUT6RQq69U/ovNhvqqaoZDY9SKNRcNWM=; b=HqOVHC2Abbm+X3cP/dHD43ymLvYPZeGrG3aIYZvjJ2+g7eGn2lSZETi/VEw2NOxJb13uEudmsFV97K1MZp02NL0Bg5orlSoKRs2NisMdH87C7qjT+bR0EDXqtLELO8l/KYktWBGICkRQ7we5p4hjEGBYw2CMQbORMxsReRRawdw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664641761170433.3893668287991; Sat, 1 Oct 2022 09:29:21 -0700 (PDT) Received: from localhost ([::1]:46658 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefMe-0007mL-89 for importer@patchew.org; Sat, 01 Oct 2022 12:29:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34976) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefHH-0006iz-4J for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:23:48 -0400 Received: from mail-qv1-xf34.google.com ([2607:f8b0:4864:20::f34]:39770) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefHB-0006DC-Ay for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:23:46 -0400 Received: by mail-qv1-xf34.google.com with SMTP id z18so4439053qvn.6 for ; Sat, 01 Oct 2022 09:23:40 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.23.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:23:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=9IDKhGDW8UhVUT6RQq69U/ovNhvqqaoZDY9SKNRcNWM=; b=Ch/eTdlmb9zwMTZnqdq4L/CL/P/3ersfsm8/4/W3I2vRNztAgx/DEL1a1Rzhppx7K5 +w4vcW4miapZVPQeZzFbTZbvAlqDFuO1mQa3IPQMMKiFyW2zmRiUJh2bwEyVuSlt2zXm C/9zki4sQgZwC4cwG4XYHQEnizoXRehTu9G90IWSzWzmPmSPXL50Tn4yXtpU3xxO6M4+ WtBM6X4wzj3USpOKa8ogF0kHsKgV7cO03+7d1jlSt8WLdAfEdSAHyxkg4Ly7CAekEY1l DS6VJOG8FcrhHnQO1RRM9+xiS0hqkYkREXC/keAEinC6v3L3W99QSBFwJM0mj5tiypM/ MDFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=9IDKhGDW8UhVUT6RQq69U/ovNhvqqaoZDY9SKNRcNWM=; b=Nnqn8h1npdvaVQRmJo2G+6GCFh7NAcTXslLF778YZHiYJ6gdaebv1j7s0O2Vs0sAbz fWKuKoOs1Y8JZX53KQFnR0Rx+HAPID98BidH0BJ4DvkOn5Y8mLQx2A1y9TFvqJhLUwfA qBP/KUwclOMt1xBJKCEK2oQYMuoy6ArX37XdsPPGYKxbkbAZ7I7gYQGzriU3AwV6e94/ 7mVgxDQBh9FjxaruZ1EkadLmkxxxvVhh6aeta+9XToudDct8KwwAyrwDMnfboeNdfPYf abVXEEgzyHu3c+JAkRpzfz84nSZ6pxefWI+dKTwt3+YqjMvyFXJdCJCro5rotGkB7hTb TeUA== X-Gm-Message-State: ACrzQf2vZwsWDMpIZjxLzZWiZKFaxvfbVusR1QdLpcRkxACnORAd1BI+ WfivEXKvVBpSI7J6TJO6yII7ADzhiFnDow== X-Google-Smtp-Source: AMsMyM4XtKSU83az55GinbzmrhemIM2ElAJGHSZ63YyDr28BHyf8xuVogL4LYNyL32cO2QCv/IOvLg== X-Received: by 2002:a05:6214:ac1:b0:4af:9cdb:e4f with SMTP id g1-20020a0562140ac100b004af9cdb0e4fmr11173180qvi.40.1664641420130; Sat, 01 Oct 2022 09:23:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 07/42] target/arm: Add TBFLAG_M32.SECURE Date: Sat, 1 Oct 2022 09:22:43 -0700 Message-Id: <20221001162318.153420-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f34; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664641761931100001 Content-Type: text/plain; charset="utf-8" Remove the use of regime_is_secure from arm_tr_init_disas_context. Instead, provide the value of v8m_secure directly from tb_flags. Rather than use regime_is_secure, use the env->v7m.secure directly, as per arm_mmu_idx_el. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/helper.c | 4 ++++ target/arm/translate.c | 3 +-- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 33cdbc0143..790328c598 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3197,6 +3197,8 @@ FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* No= t cached. */ FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ +/* Set if in secure mode */ +FIELD(TBFLAG_M32, SECURE, 6, 1) =20 /* * Bit usage when in AArch64 state diff --git a/target/arm/helper.c b/target/arm/helper.c index b5dac651e7..772218f0d2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10935,6 +10935,10 @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMStat= e *env, int fp_el, DP_TBFLAG_M32(flags, STACKCHECK, 1); } =20 + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) { + DP_TBFLAG_M32(flags, SECURE, 1); + } + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 5aaccbbf71..ac647e0262 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9351,8 +9351,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) dc->vfp_enabled =3D 1; dc->be_data =3D MO_TE; dc->v7m_handler_mode =3D EX_TBFLAG_M32(tb_flags, HANDLER); - dc->v8m_secure =3D arm_feature(env, ARM_FEATURE_M_SECURITY) && - regime_is_secure(env, dc->mmu_idx); + dc->v8m_secure =3D EX_TBFLAG_M32(tb_flags, SECURE); dc->v8m_stackcheck =3D EX_TBFLAG_M32(tb_flags, STACKCHECK); dc->v8m_fpccr_s_wrong =3D EX_TBFLAG_M32(tb_flags, FPCCR_S_WRONG); dc->v7m_new_fp_ctxt_needed =3D --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664642061; cv=none; d=zohomail.com; s=zohoarc; b=M3uVaDGJSLpS5FIh3dpQUkqNbdBipHfxMaTdOO26OtViOil2kbhWBv9f4/6dn1HWBVjuipZ0qIfIJILbPvNNBJfML6dxe9+ufeADN0sAxJBXlvB9wQLFiaFe2ryrYE5IaAuCgUgaLlXQYh7LfaXQeskfbUJaUlW5RUOPxgJRGzI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664642061; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=05f/pRTmfbp1ZrlM5+i+EnCZM40Ehp5l9D83IpJHRPk=; b=CPhRSbeLKwB1E+uHP6gldHZWRZ9YH/XgHX9kTEnvQ4dKPbZac+lRF+qoE1a/zJg+Y3796+uoXckjFlWI8kKqeqREz8gPsRxpEd8BU16GNbZBC4AE687NDKPomE0HKfkKGEbnmF/4F61EpLWyXDeRWYtdgAJTMVHua9IpgAsOtXM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166464206103965.37970077131047; Sat, 1 Oct 2022 09:34:21 -0700 (PDT) Received: from localhost ([::1]:40352 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefRT-0004sx-L4 for importer@patchew.org; Sat, 01 Oct 2022 12:34:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34978) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefHI-0006jT-DD for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:23:56 -0400 Received: from mail-qk1-x72b.google.com ([2607:f8b0:4864:20::72b]:35586) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefHD-0006GB-SJ for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:23:48 -0400 Received: by mail-qk1-x72b.google.com with SMTP id u28so4541760qku.2 for ; Sat, 01 Oct 2022 09:23:43 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.23.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:23:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=05f/pRTmfbp1ZrlM5+i+EnCZM40Ehp5l9D83IpJHRPk=; b=zxpKqWa+hznlM2ZjOZBZoCOxoLdu8sd6U9Q0GrxUgOVUka+ZxWgnP+ZF68U1H/DioN jloc7IPFjFZPgjQyOOygsGj0DGOXROYbn+8TSN5Ir6et3AKDlDHKGU4SI5Q2Aic9IF8F 4GqzVpXr9F3kcpExgJfsGypFmukYDHuvIw2+bIhGZFVMK49naFwV3YZn2XqRdSv/52lO 9vl5SyL0TpJdo5KJHWqGdhPxjiHmXaYz4Lwu01K1QPaiFSgG4KoNWL5ZHPMpUcmG/sn6 2nKEeZ/g9tAO7zr6boRj1SdH15CbKtI5BAetrLWKq6KlNLwJP9fmQUEeLsdqqVnLm0P1 bsnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=05f/pRTmfbp1ZrlM5+i+EnCZM40Ehp5l9D83IpJHRPk=; b=RACVbvwK2vusp+UcCeAaFdSraQQK8Cwgy39rvLbGaF9jMbK0XT8HpxlznAZNiXFkJa riA6kdpWMN33aX0IFE9i4dWvxwV2T3IttUE82gf9PxMi1raY/l6jiA7WIF+lnTTT7WE3 TuPE2EkwQTyAItIloFo6WuWUfJECwqUdVvsC7UM3r2nXLMGfT1X49kFvyIlv/Eelzol4 8enMmxzgiR2xuwnn1xyAFQo862j8F04yZpipggSTcQ7VaCr7DVPLoAFi2uu110jV7ELt clDSYRIGqA1Xg5uQ+h3z1S7EdDw45urqhRpGNSVFG9m9e5fTcrvGCW1FJOL3Jei7a2p1 g23Q== X-Gm-Message-State: ACrzQf192cYboKnNDc+3fRQqWrvpGN7NEeC7EnY9RulrIYI863BRdvBf FAQ11IEmiqzREut+gzStpIsnOP2nw8Dkew== X-Google-Smtp-Source: AMsMyM4Z28IxvH8HHcbltDH0zoiVD1jCkFJWoGJyudxMQaw9VS+RNs2tjcGGEqxUeG7DuCFBCD6mpQ== X-Received: by 2002:a05:620a:2490:b0:6ce:4054:ca14 with SMTP id i16-20020a05620a249000b006ce4054ca14mr9750361qkn.62.1664641422364; Sat, 01 Oct 2022 09:23:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 08/42] target/arm: Merge regime_is_secure into get_phys_addr Date: Sat, 1 Oct 2022 09:22:44 -0700 Message-Id: <20221001162318.153420-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72b; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664642061872100001 Content-Type: text/plain; charset="utf-8" This is the last use of regime_is_secure; remove it entirely before changing the layout of ARMMMUIdx. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 42 ---------------------------------------- target/arm/ptw.c | 44 ++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 42 insertions(+), 44 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 3524d11dc5..14428730d4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -670,48 +670,6 @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_i= dx) } } =20 -/* Return true if this address translation regime is secure */ -static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_E10_0: - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_E20_0: - case ARMMMUIdx_E20_2: - case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_Stage1_E1: - case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_E2: - case ARMMMUIdx_Stage2: - case ARMMMUIdx_MPrivNegPri: - case ARMMMUIdx_MUserNegPri: - case ARMMMUIdx_MPriv: - case ARMMMUIdx_MUser: - return false; - case ARMMMUIdx_SE3: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: - case ARMMMUIdx_Stage1_SE0: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: - case ARMMMUIdx_SE2: - case ARMMMUIdx_Stage2_S: - case ARMMMUIdx_MSPrivNegPri: - case ARMMMUIdx_MSUserNegPri: - case ARMMMUIdx_MSPriv: - case ARMMMUIdx_MSUser: - return true; - default: - g_assert_not_reached(); - } -} - static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 542111f99e..9454ee9df5 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2499,9 +2499,49 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, MMUAccessType access_type, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { + bool is_secure; + + switch (mmu_idx) { + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: + case ARMMMUIdx_E2: + case ARMMMUIdx_Stage2: + case ARMMMUIdx_MPrivNegPri: + case ARMMMUIdx_MUserNegPri: + case ARMMMUIdx_MPriv: + case ARMMMUIdx_MUser: + is_secure =3D false; + break; + case ARMMMUIdx_SE3: + case ARMMMUIdx_SE10_0: + case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: + case ARMMMUIdx_SE20_0: + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: + case ARMMMUIdx_Stage1_SE0: + case ARMMMUIdx_Stage1_SE1: + case ARMMMUIdx_Stage1_SE1_PAN: + case ARMMMUIdx_SE2: + case ARMMMUIdx_Stage2_S: + case ARMMMUIdx_MSPrivNegPri: + case ARMMMUIdx_MSUserNegPri: + case ARMMMUIdx_MSPriv: + case ARMMMUIdx_MSUser: + is_secure =3D true; + break; + default: + g_assert_not_reached(); + } return get_phys_addr_with_secure(env, address, access_type, mmu_idx, - regime_is_secure(env, mmu_idx), - result, fi); + is_secure, result, fi); } =20 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.23.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:23:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=9SScwWFtisnAsN/gqU42XTsbKaa8LapqZEtG7W5lUds=; b=WDhhg8CYqKrrfbcDfM2mbSd2sZbhjaHTU5eyEx09ElS/0wx/B+LfvPdjEzm0gSc3fa u+GBoMNK6f/Tj1UNroYzbnTK1XrXgUrtYnKvdW2Lgmdjzrx/Pvg5gE6qM80hs4DCR6KU NmwrvJl2Kow1b9Pn1qwVRva6qj+lpuH7yYMZIHzbS03FrIfN9PfxGLfXV2v8Idltio+H vLA6xZns1LFYXBnNw5soaQbfkVSICGluWQebkbt9RVMIZWVUA9acrEYzPmN3AUWCyhK/ HR9Id9DIGEMwQwLqHCFzUOUyqEzJAE/t59CsMTGVkOsOM9x1KRQDBpcUDqcawvFUNdt0 B0lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=9SScwWFtisnAsN/gqU42XTsbKaa8LapqZEtG7W5lUds=; b=Iok1VAuVXSOL3p9MvRQuhwI57JsKnewO1lKpfI9dr+SNWc7DU9JofH3PixbNUY320h OncuzBrk1EQbaqvzL7Bjmw0Ejh6j/kUoqPzrulMjKg+QbIJig2A7HVVRD4GPPH17xQtu tUyB1YCw4pt1WBPJZJv86Zq0n43Kkjzr+uYyAhlSw/zy04DK9tyJHdGqbtz18Wf/iMVh hSxDYisP2f+EO35DRjFUCJK626FNQr+V2X9KOPXPI4i6q59yO9NMJM8Ih8ObHmS0bu6m Xs7eY2N5M0RFEyku8aabvuH6xAgh1yM0dLs+37I77dQfBon7RUaNJSjEJz5FZH3AnLO8 4o+w== X-Gm-Message-State: ACrzQf1qqgeTMOfNRDY2m/yahRL5u1c88nhT2aGY+U7UEex7i6zZZbjk awzjZcFdi+DCjNZSt8pkAXDvdiouZibfNQ== X-Google-Smtp-Source: AMsMyM7xRw5t6uLkNoUSHtBD/6ofNKsW72eY+PU2GtmvtIuyNAt/UpuKDlVdlKAAUWmrlnJxifbTZw== X-Received: by 2002:ac8:5790:0:b0:35b:fd92:6fb8 with SMTP id v16-20020ac85790000000b0035bfd926fb8mr10742059qta.53.1664641424338; Sat, 01 Oct 2022 09:23:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 09/42] target/arm: Add is_secure parameter to do_ats_write Date: Sat, 1 Oct 2022 09:22:45 -0700 Message-Id: <20221001162318.153420-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::835; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x835.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664642071781100001 Content-Type: text/plain; charset="utf-8" Use get_phys_addr_with_secure directly. For a-profile, this is the one place where the value of is_secure may not equal arm_is_secure(env). Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 772218f0d2..3adeb4cab4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3188,7 +3188,8 @@ static CPAccessResult ats_access(CPUARMState *env, co= nst ARMCPRegInfo *ri, =20 #ifdef CONFIG_TCG static uint64_t do_ats_write(CPUARMState *env, uint64_t value, - MMUAccessType access_type, ARMMMUIdx mmu_idx) + MMUAccessType access_type, ARMMMUIdx mmu_idx, + bool is_secure) { bool ret; uint64_t par64; @@ -3196,7 +3197,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, ARMMMUFaultInfo fi =3D {}; GetPhysAddrResult res =3D {}; =20 - ret =3D get_phys_addr(env, value, access_type, mmu_idx, &res, &fi); + ret =3D get_phys_addr_with_secure(env, value, access_type, mmu_idx, + is_secure, &res, &fi); =20 /* * ATS operations only do S1 or S1+S2 translations, so we never @@ -3368,6 +3370,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) switch (el) { case 3: mmu_idx =3D ARMMMUIdx_SE3; + secure =3D true; break; case 2: g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ @@ -3389,6 +3392,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) switch (el) { case 3: mmu_idx =3D ARMMMUIdx_SE10_0; + secure =3D true; break; case 2: g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ @@ -3404,16 +3408,18 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) case 4: /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ mmu_idx =3D ARMMMUIdx_E10_1; + secure =3D false; break; case 6: /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ mmu_idx =3D ARMMMUIdx_E10_0; + secure =3D false; break; default: g_assert_not_reached(); } =20 - par64 =3D do_ats_write(env, value, access_type, mmu_idx); + par64 =3D do_ats_write(env, value, access_type, mmu_idx, secure); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); #else @@ -3429,7 +3435,8 @@ static void ats1h_write(CPUARMState *env, const ARMCP= RegInfo *ri, MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; uint64_t par64; =20 - par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2); + /* There is no SecureEL2 for AArch32. */ + par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2, false); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); #else @@ -3472,6 +3479,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx =3D ARMMMUIdx_SE3; + secure =3D true; break; default: g_assert_not_reached(); @@ -3490,7 +3498,8 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, g_assert_not_reached(); } =20 - env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, mmu_idx); + env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, + mmu_idx, secure); #else /* Handled by hardware accelerator. */ g_assert_not_reached(); --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664642203; cv=none; d=zohomail.com; s=zohoarc; b=Qnj0PMgrMQwGeFPV3anA9dJfcOPCWRcnmuyeerC/7tiVuXOE1urpxG21RI/BQTy5RqYl723BlV/Nm2HKcuQ9Pbx18kCnJSpfhA4PlLYMDcbfhDKTD/87FkHjkn6KLxdpnbngcvTREWECTHSFccw54s1A4G60Iil4robU0o7Umzc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664642203; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NhD7x7BDC4Q6yQBaenWmMvXEkO2Pazp20fQO9O98iHY=; b=giBkeYE025Dj/ntvq6g/oDqPCu4v9cKDSrvw95wHM3tcRZVM2NiC4zZJ8QOVIVQ9fqkhvxDW6N0yl9F8gbSl+M2Gi8rPMfUBicVTffHBlKe2ROfXkf2E/Rmgn1c5W1YFTwRIMET8qpG2YNC1OJWYw3TlnZF4TKBWCplj3S8r7J8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664642203376423.5428783833462; Sat, 1 Oct 2022 09:36:43 -0700 (PDT) Received: from localhost ([::1]:39380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefTm-00079n-1c for importer@patchew.org; Sat, 01 Oct 2022 12:36:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33430) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefHV-0006kQ-GJ for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:05 -0400 Received: from mail-qk1-x72a.google.com ([2607:f8b0:4864:20::72a]:40618) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefHM-0006Gc-OA for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:23:56 -0400 Received: by mail-qk1-x72a.google.com with SMTP id c19so4532112qkm.7 for ; Sat, 01 Oct 2022 09:23:48 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.23.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:23:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=NhD7x7BDC4Q6yQBaenWmMvXEkO2Pazp20fQO9O98iHY=; b=vXtLrQ/DfoZ+zx5DheQ05Pb2za6gz2FZBt2EVdEerJL+KwOG5XTo/GzmqHdaHi2EsZ aDyW41w4jga1H+DErgaUgvM+Ttmn867sZjPP8PnbATV2NNOgWwBTKTv1X9d/5SzbYxUx lAPxblhpvy9LmHqJ60ot6aGvfQY7DxBXuDrZ4KbyEsNxXYgBq5yTAIyzHJbyQjETbSkb qhAPvELjKLu0/ZSDF3o5ZgihB8FuZtbQHS1IqVDKUImILx8YlEf8wDREvBZm06wcERbh 8d53szYgXiU3BtzHod0Zefw8LDQ6C/hn6QoOr83ooPRFJJWuAO2a5IvQG2FXrIUIvjRu VchQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=NhD7x7BDC4Q6yQBaenWmMvXEkO2Pazp20fQO9O98iHY=; b=WtVtleFucruFPWg01CNBqj5yFPYZeOcKey8SErRw2qiwLsATbd8DHYUz6O/2G5Fw2Z gmm3HZl3xQyOS3ivMT4h95f9pW5fwm9myfieuQkRaDXA7vR4pmOqvqH+ctL4aR1Dd2jU duAGePfvM5LcAaY9CHnVoM8U6DufE3rSTgUCcwX4TXAfdD7r1hgWdMu3FRgIj9dOZQsi zEK71TVAkr91X4j+B9t9O9eEaJhKvnuVskfFsSGRywp6jquv3xwTQu1e/ReykPPRqDv3 35BB6k2au9A0Gar52z6WNmbReo9L+e5IzeVPbctawBjaSdU9220Hwn1brSe8r8t2ywpV WQbA== X-Gm-Message-State: ACrzQf1G72WFPN/p/d9K8MibbVVvHSn3yJr+veSEMjtzN7r7nD5QNnSm 5w7hnQgZmtb5Yb99kBhmsbSaNtU3RjgKzw== X-Google-Smtp-Source: AMsMyM56ePGVHBIKhQV+2/My/6jrRCXcS9NlCYcjbOwUz2I/21b7hSdvPD9qXK56yqKehHlJFzTZYg== X-Received: by 2002:a05:620a:271b:b0:6cd:fd1f:7472 with SMTP id b27-20020a05620a271b00b006cdfd1f7472mr9652232qkp.142.1664641427686; Sat, 01 Oct 2022 09:23:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 10/42] target/arm: Fold secure and non-secure a-profile mmu indexes Date: Sat, 1 Oct 2022 09:22:46 -0700 Message-Id: <20221001162318.153420-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72a; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664642204638100001 Content-Type: text/plain; charset="utf-8" For a-profile aarch64, which does not bank system registers, it takes quite a lot of code to switch between security states. In the process, registers such as TCR_EL{1,2} must be swapped, which in itself requires the flushing of softmmu tlbs. Therefore it doesn't buy us anything to separate tlbs by security state. Retain the distinction between Stage2 and Stage2_S. This will be important as we implement FEAT_RME, and do not wish to add a third set of mmu indexes for Realm state. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 72 +++++++------------ target/arm/internals.h | 31 +------- target/arm/helper.c | 144 +++++++++++++------------------------ target/arm/ptw.c | 25 ++----- target/arm/translate-a64.c | 8 --- target/arm/translate.c | 6 +- 7 files changed, 85 insertions(+), 203 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 68ffb12427..08681828ac 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -32,6 +32,6 @@ # define TARGET_PAGE_BITS_MIN 10 #endif =20 -#define NB_MMU_MODES 15 +#define NB_MMU_MODES 8 =20 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 790328c598..6475dc0cfd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2878,26 +2878,27 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_s= ync); * table over and over. * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access * Never (PAN) bit within PSTATE. + * 7. we fold together the secure and non-secure regimes for A-profile, + * because there are no banked system registers for aarch64, so the + * process of switching between secure and non-secure is + * already heavyweight. * * This gives us the following list of cases: * - * NS EL0 EL1&0 stage 1+2 (aka NS PL0) - * NS EL1 EL1&0 stage 1+2 (aka NS PL1) - * NS EL1 EL1&0 stage 1+2 +PAN - * NS EL0 EL2&0 - * NS EL2 EL2&0 - * NS EL2 EL2&0 +PAN - * NS EL2 (aka NS PL2) - * S EL0 EL1&0 (aka S PL0) - * S EL1 EL1&0 (not used if EL3 is 32 bit) - * S EL1 EL1&0 +PAN - * S EL3 (aka S PL1) + * EL0 EL1&0 stage 1+2 (aka NS PL0) + * EL1 EL1&0 stage 1+2 (aka NS PL1) + * EL1 EL1&0 stage 1+2 +PAN + * EL0 EL2&0 + * EL2 EL2&0 + * EL2 EL2&0 +PAN + * EL2 (aka NS PL2) + * EL3 (aka S PL1) * - * for a total of 11 different mmu_idx. + * for a total of 8 different mmu_idx. * * R profile CPUs have an MPU, but can use the same set of MMU indexes - * as A profile. They only need to distinguish NS EL0 and NS EL1 (and - * NS EL2 if we ever model a Cortex-R52). + * as A profile. They only need to distinguish EL0 and EL1 (and + * EL2 if we ever model a Cortex-R52). * * M profile CPUs are rather different as they do not have a true MMU. * They have the following different MMU indexes: @@ -2936,9 +2937,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_syn= c); #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ #define ARM_MMU_IDX_M 0x40 /* M profile */ =20 -/* Meanings of the bits for A profile mmu idx values */ -#define ARM_MMU_IDX_A_NS 0x8 - /* Meanings of the bits for M profile mmu idx values */ #define ARM_MMU_IDX_M_PRIV 0x1 #define ARM_MMU_IDX_M_NEGPRI 0x2 @@ -2952,22 +2950,14 @@ typedef enum ARMMMUIdx { /* * A-profile. */ - ARMMMUIdx_SE10_0 =3D 0 | ARM_MMU_IDX_A, - ARMMMUIdx_SE20_0 =3D 1 | ARM_MMU_IDX_A, - ARMMMUIdx_SE10_1 =3D 2 | ARM_MMU_IDX_A, - ARMMMUIdx_SE20_2 =3D 3 | ARM_MMU_IDX_A, - ARMMMUIdx_SE10_1_PAN =3D 4 | ARM_MMU_IDX_A, - ARMMMUIdx_SE20_2_PAN =3D 5 | ARM_MMU_IDX_A, - ARMMMUIdx_SE2 =3D 6 | ARM_MMU_IDX_A, - ARMMMUIdx_SE3 =3D 7 | ARM_MMU_IDX_A, - - ARMMMUIdx_E10_0 =3D ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E20_0 =3D ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E10_1 =3D ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E20_2 =3D ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E10_1_PAN =3D ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E20_2_PAN =3D ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E2 =3D ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS, + ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_0 =3D 1 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1 =3D 2 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2 =3D 3 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1_PAN =3D 4 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2_PAN =3D 5 | ARM_MMU_IDX_A, + ARMMMUIdx_E2 =3D 6 | ARM_MMU_IDX_A, + ARMMMUIdx_E3 =3D 7 | ARM_MMU_IDX_A, =20 /* * These are not allocated TLBs and are used only for AT system @@ -2976,9 +2966,6 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1_PAN =3D 2 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage1_SE0 =3D 3 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage1_SE1 =3D 4 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage1_SE1_PAN =3D 5 | ARM_MMU_IDX_NOTLB, /* * Not allocated a TLB: used only for second stage of an S12 page * table walk, or for descriptor loads during first stage of an S1 @@ -2986,8 +2973,8 @@ typedef enum ARMMMUIdx { * then various TLB flush insns which currently are no-ops or flush * only stage 1 MMU indexes will need to change to flush stage 2. */ - ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage2_S =3D 7 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage2 =3D 3 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage2_S =3D 4 | ARM_MMU_IDX_NOTLB, =20 /* * M-profile. @@ -3017,14 +3004,7 @@ typedef enum ARMMMUIdxBit { TO_CORE_BIT(E2), TO_CORE_BIT(E20_2), TO_CORE_BIT(E20_2_PAN), - TO_CORE_BIT(SE10_0), - TO_CORE_BIT(SE20_0), - TO_CORE_BIT(SE10_1), - TO_CORE_BIT(SE20_2), - TO_CORE_BIT(SE10_1_PAN), - TO_CORE_BIT(SE20_2_PAN), - TO_CORE_BIT(SE2), - TO_CORE_BIT(SE3), + TO_CORE_BIT(E3), =20 TO_CORE_BIT(MUser), TO_CORE_BIT(MPriv), diff --git a/target/arm/internals.h b/target/arm/internals.h index 14428730d4..b509d70851 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -649,21 +649,12 @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_= idx) case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_Stage1_SE0: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: return true; default: return false; @@ -674,11 +665,8 @@ static inline bool regime_is_pan(CPUARMState *env, ARM= MMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_Stage1_SE1_PAN: case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE10_1_PAN: - case ARMMMUIdx_SE20_2_PAN: return true; default: return false; @@ -689,30 +677,20 @@ static inline bool regime_is_pan(CPUARMState *env, AR= MMMUIdx mmu_idx) static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_Stage2: case ARMMMUIdx_Stage2_S: - case ARMMMUIdx_SE2: case ARMMMUIdx_E2: return 2; - case ARMMMUIdx_SE3: + case ARMMMUIdx_E3: return 3; - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_Stage1_SE0: - return arm_el_is_aa64(env, 3) ? 1 : 3; - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: + case ARMMMUIdx_E10_0: case ARMMMUIdx_Stage1_E0: + return arm_el_is_aa64(env, 3) || !arm_is_secure_below_el3(env) ? 1= : 3; case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: - case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_MPrivNegPri: @@ -954,9 +932,6 @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx= mmu_idx) case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_Stage1_SE0: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: return true; default: return false; diff --git a/target/arm/helper.c b/target/arm/helper.c index 3adeb4cab4..0fd0c73092 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1754,6 +1754,7 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) /* Begin with base v8.0 state. */ uint32_t valid_mask =3D 0x3fff; ARMCPU *cpu =3D env_archcpu(env); + uint64_t changed; =20 /* * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset alw= ays @@ -1813,7 +1814,22 @@ static void scr_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) =20 /* Clear all-context RES0 bits. */ value &=3D valid_mask; - raw_write(env, ri, value); + changed =3D env->cp15.scr_el3 ^ value; + env->cp15.scr_el3 =3D value; + + /* + * If SCR_EL3.NS changes, i.e. arm_is_secure_below_el3, then + * we must invalidate all TLBs below EL3. + */ + if (changed & SCR_NS) { + tlb_flush_by_mmuidx(env_cpu(env), (ARMMMUIdxBit_E10_0 | + ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E2)); + } } =20 static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri) @@ -2644,9 +2660,6 @@ static int gt_phys_redir_timeridx(CPUARMState *env) case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: return GTIMER_HYP; default: return GTIMER_PHYS; @@ -2659,9 +2672,6 @@ static int gt_virt_redir_timeridx(CPUARMState *env) case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: return GTIMER_HYPVIRT; default: return GTIMER_VIRT; @@ -3369,7 +3379,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP= */ switch (el) { case 3: - mmu_idx =3D ARMMMUIdx_SE3; + mmu_idx =3D ARMMMUIdx_E3; secure =3D true; break; case 2: @@ -3377,10 +3387,9 @@ static void ats_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) /* fall through */ case 1: if (ri->crm =3D=3D 9 && (env->uncached_cpsr & CPSR_PAN)) { - mmu_idx =3D (secure ? ARMMMUIdx_Stage1_SE1_PAN - : ARMMMUIdx_Stage1_E1_PAN); + mmu_idx =3D ARMMMUIdx_Stage1_E1_PAN; } else { - mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stag= e1_E1; + mmu_idx =3D ARMMMUIdx_Stage1_E1; } break; default: @@ -3391,7 +3400,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ switch (el) { case 3: - mmu_idx =3D ARMMMUIdx_SE10_0; + mmu_idx =3D ARMMMUIdx_E10_0; secure =3D true; break; case 2: @@ -3399,7 +3408,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) mmu_idx =3D ARMMMUIdx_Stage1_E0; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E= 0; + mmu_idx =3D ARMMMUIdx_Stage1_E0; break; default: g_assert_not_reached(); @@ -3468,17 +3477,16 @@ static void ats_write64(CPUARMState *env, const ARM= CPRegInfo *ri, switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ if (ri->crm =3D=3D 9 && (env->pstate & PSTATE_PAN)) { - mmu_idx =3D (secure ? ARMMMUIdx_Stage1_SE1_PAN - : ARMMMUIdx_Stage1_E1_PAN); + mmu_idx =3D ARMMMUIdx_Stage1_E1_PAN; } else { - mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stag= e1_E1; + mmu_idx =3D ARMMMUIdx_Stage1_E1; } break; case 4: /* AT S1E2R, AT S1E2W */ - mmu_idx =3D secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2; + mmu_idx =3D ARMMMUIdx_E2; break; case 6: /* AT S1E3R, AT S1E3W */ - mmu_idx =3D ARMMMUIdx_SE3; + mmu_idx =3D ARMMMUIdx_E3; secure =3D true; break; default: @@ -3486,13 +3494,13 @@ static void ats_write64(CPUARMState *env, const ARM= CPRegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0; + mmu_idx =3D ARMMMUIdx_Stage1_E0; break; case 4: /* AT S12E1R, AT S12E1W */ - mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1; + mmu_idx =3D ARMMMUIdx_E10_1; break; case 6: /* AT S12E0R, AT S12E0W */ - mmu_idx =3D secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0; + mmu_idx =3D ARMMMUIdx_E10_0; break; default: g_assert_not_reached(); @@ -3762,11 +3770,6 @@ static void vmsa_tcr_ttbr_el2_write(CPUARMState *env= , const ARMCPRegInfo *ri, uint16_t mask =3D ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_2_PAN | ARMMMUIdxBit_E20_0; - - if (arm_is_secure_below_el3(env)) { - mask >>=3D ARM_MMU_IDX_A_NS; - } - tlb_flush_by_mmuidx(env_cpu(env), mask); } raw_write(env, ri, value); @@ -3786,11 +3789,6 @@ static void vttbr_write(CPUARMState *env, const ARMC= PRegInfo *ri, uint16_t mask =3D ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0; - - if (arm_is_secure_below_el3(env)) { - mask >>=3D ARM_MMU_IDX_A_NS; - } - tlb_flush_by_mmuidx(cs, mask); raw_write(env, ri, value); } @@ -4261,11 +4259,6 @@ static int vae1_tlbmask(CPUARMState *env) ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0; } - - if (arm_is_secure_below_el3(env)) { - mask >>=3D ARM_MMU_IDX_A_NS; - } - return mask; } =20 @@ -4292,10 +4285,6 @@ static int vae1_tlbbits(CPUARMState *env, uint64_t a= ddr) mmu_idx =3D ARMMMUIdx_E10_0; } =20 - if (arm_is_secure_below_el3(env)) { - mmu_idx &=3D ~ARM_MMU_IDX_A_NS; - } - return tlbbits_for_regime(env, mmu_idx, addr); } =20 @@ -4328,30 +4317,17 @@ static int alle1_tlbmask(CPUARMState *env) * stage 2 translations, whereas most other scopes only invalidate * stage 1 translations. */ - if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE10_1 | - ARMMMUIdxBit_SE10_1_PAN | - ARMMMUIdxBit_SE10_0; - } else { - return ARMMMUIdxBit_E10_1 | - ARMMMUIdxBit_E10_1_PAN | - ARMMMUIdxBit_E10_0; - } + return (ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0); } =20 static int e2_tlbmask(CPUARMState *env) { - if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE20_0 | - ARMMMUIdxBit_SE20_2 | - ARMMMUIdxBit_SE20_2_PAN | - ARMMMUIdxBit_SE2; - } else { - return ARMMMUIdxBit_E20_0 | - ARMMMUIdxBit_E20_2 | - ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E2; - } + return (ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4378,7 +4354,7 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E3); } =20 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4404,7 +4380,7 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env,= const ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E3); } =20 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4432,7 +4408,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E3); } =20 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -4471,12 +4447,10 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env= , const ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - bool secure =3D arm_is_secure_below_el3(env); - int mask =3D secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; - int bits =3D tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUId= x_E2, - pageaddr); + int bits =3D tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr); =20 - tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits= ); + tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + ARMMMUIdxBit_E2, bits); } =20 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -4484,10 +4458,10 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env= , const ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - int bits =3D tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr); + int bits =3D tlbbits_for_regime(env, ARMMMUIdx_E3, pageaddr); =20 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_SE3, bits); + ARMMMUIdxBit_E3, bits); } =20 #ifdef TARGET_AARCH64 @@ -4593,8 +4567,7 @@ static void tlbi_aa64_rvae1is_write(CPUARMState *env, =20 static int vae2_tlbmask(CPUARMState *env) { - return (arm_is_secure_below_el3(env) - ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2); + return ARMMMUIdxBit_E2; } =20 static void tlbi_aa64_rvae2_write(CPUARMState *env, @@ -4640,8 +4613,7 @@ static void tlbi_aa64_rvae3_write(CPUARMState *env, * flush-last-level-only. */ =20 - do_rvae_write(env, value, ARMMMUIdxBit_SE3, - tlb_force_broadcast(env)); + do_rvae_write(env, value, ARMMMUIdxBit_E3, tlb_force_broadcast(env)); } =20 static void tlbi_aa64_rvae3is_write(CPUARMState *env, @@ -4655,7 +4627,7 @@ static void tlbi_aa64_rvae3is_write(CPUARMState *env, * flush-last-level-only or inner/outer specific flushes. */ =20 - do_rvae_write(env, value, ARMMMUIdxBit_SE3, true); + do_rvae_write(env, value, ARMMMUIdxBit_E3, true); } #endif =20 @@ -10258,8 +10230,7 @@ uint64_t arm_sctlr(CPUARMState *env, int el) /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ if (el =3D=3D 0) { ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, 0); - el =3D (mmu_idx =3D=3D ARMMMUIdx_E20_0 || mmu_idx =3D=3D ARMMMUIdx= _SE20_0) - ? 2 : 1; + el =3D mmu_idx =3D=3D ARMMMUIdx_E20_0 ? 2 : 1; } return env->cp15.sctlr_el[el]; } @@ -10803,22 +10774,15 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_E10_0: case ARMMMUIdx_E20_0: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE20_0: return 0; case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: return 1; case ARMMMUIdx_E2: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE2: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: return 2; - case ARMMMUIdx_SE3: + case ARMMMUIdx_E3: return 3; default: g_assert_not_reached(); @@ -10871,15 +10835,11 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) } break; case 3: - return ARMMMUIdx_SE3; + return ARMMMUIdx_E3; default: g_assert_not_reached(); } =20 - if (arm_is_secure_below_el3(env)) { - idx &=3D ~ARM_MMU_IDX_A_NS; - } - return idx; } =20 @@ -11082,15 +11042,11 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMSta= te *env, int el, int fp_el, switch (mmu_idx) { case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: /* TODO: ARMv8.3-NV */ DP_TBFLAG_A64(flags, UNPRIV, 1); break; case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: /* * Note that EL20_2 is gated by HCR_EL2.E2H =3D=3D 1, but EL20= _0 is * gated by HCR_EL2. =3D=3D '11', and so is LDTR. diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9454ee9df5..9be11f1673 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -65,12 +65,6 @@ unsigned int arm_pamax(ARMCPU *cpu) ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_SE10_0: - return ARMMMUIdx_Stage1_SE0; - case ARMMMUIdx_SE10_1: - return ARMMMUIdx_Stage1_SE1; - case ARMMMUIdx_SE10_1_PAN: - return ARMMMUIdx_Stage1_SE1_PAN; case ARMMMUIdx_E10_0: return ARMMMUIdx_Stage1_E0; case ARMMMUIdx_E10_1: @@ -95,11 +89,8 @@ static bool regime_translation_big_endian(CPUARMState *e= nv, ARMMMUIdx mmu_idx) static bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_SE10_0: case ARMMMUIdx_E20_0: - case ARMMMUIdx_SE20_0: case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_Stage1_SE0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: case ARMMMUIdx_MUserNegPri: @@ -2304,7 +2295,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, =20 s2_mmu_idx =3D (s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2); - is_el0 =3D mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D AR= MMMUIdx_SE10_0; + is_el0 =3D mmu_idx =3D=3D ARMMMUIdx_E10_0; =20 /* * S1 is done, now do S2 translation. @@ -2512,6 +2503,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E2: + is_secure =3D arm_is_secure_below_el3(env); + break; case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: @@ -2519,17 +2512,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, case ARMMMUIdx_MUser: is_secure =3D false; break; - case ARMMMUIdx_SE3: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: - case ARMMMUIdx_Stage1_SE0: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: - case ARMMMUIdx_SE2: + case ARMMMUIdx_E3: case ARMMMUIdx_Stage2_S: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 78b2d91ed4..5b67375f4e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -111,14 +111,6 @@ static int get_a64_user_mem_index(DisasContext *s) case ARMMMUIdx_E20_2_PAN: useridx =3D ARMMMUIdx_E20_0; break; - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - useridx =3D ARMMMUIdx_SE10_0; - break; - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: - useridx =3D ARMMMUIdx_SE20_0; - break; default: g_assert_not_reached(); } diff --git a/target/arm/translate.c b/target/arm/translate.c index ac647e0262..2f72afe019 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -237,16 +237,12 @@ static inline int get_a32_user_mem_index(DisasContext= *s) * otherwise, access as if at PL0. */ switch (s->mmu_idx) { + case ARMMMUIdx_E3: case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */ case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: return arm_to_core_mmu_idx(ARMMMUIdx_E10_0); - case ARMMMUIdx_SE3: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0); case ARMMMUIdx_MUser: case ARMMMUIdx_MPriv: return arm_to_core_mmu_idx(ARMMMUIdx_MUser); --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664642223; cv=none; d=zohomail.com; s=zohoarc; b=Jc97AbvxGPztjz+OLTVRO4CLhFPMxHJCaF+vsEsFAOOg73wHi8Z4PTdamQOGBqZrhAu5TT+o3UjKEook1DABhyzGhlO3NHhJGULdPYz/revfft1xjEyMttZMzRtKz45ul8rSemLQ2y3pOYpq0In6zvT/uvoJhAOHZd2lW8w7WyA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664642223; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YUgoT+b6fWGQnaxpAgaCymNUj0JMoRjdbdEo3IB0Hrw=; b=m3f+R7rUDDV9sYuQOz+nc5knYCWYPFsstnd4HZIFkrSsbbEtte/MtMiu7pGQOdaYCpVoXn65Au3MbT/CJYScgGD8K4g0KMJOw3IuRbWwiAng6CDFjdrKh3vorwTfzeWRkh0J+dAKgTFL0vj/4XRGitIiWssjh2RBB6Z2vjMebaQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166464222349048.273995241183684; Sat, 1 Oct 2022 09:37:03 -0700 (PDT) Received: from localhost ([::1]:39382 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefU6-0007Gn-Av for importer@patchew.org; Sat, 01 Oct 2022 12:37:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33444) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefHW-0006kY-9h for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:05 -0400 Received: from mail-qk1-x734.google.com ([2607:f8b0:4864:20::734]:38557) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefHO-0006Gl-DI for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:23:58 -0400 Received: by mail-qk1-x734.google.com with SMTP id 3so4547875qka.5 for ; Sat, 01 Oct 2022 09:23:50 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.23.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:23:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=YUgoT+b6fWGQnaxpAgaCymNUj0JMoRjdbdEo3IB0Hrw=; b=nMZYSGKjI7zFJxikM0HB+50DbcvuJSECCb1K5gTS3hd7piNpaXDi0aduszmqjp4CQ9 1YwSngP2WKtuRB4HEdYqc0BlD5PvyQ0BMQht6uDXYOxS3KALEhdDfu0PUpd+9N6uGViS s0b6nHozQ8bKCtX9WjXrqh4FBVgJR/o4oksrBAY4Vh1dnAWP0TQSE6qXY2z6p4t6S34m eHJvtUf6HNro2+vYHF+RHupka1YB3hsUNXQRk9eka2Yn2mQbi+QGZyjvTWv+RaadpQP9 //YClP1Lelx76oCJ+q5ozdFHF0PsBSsN2Y9LGyhrFbjfRRHFeZUKxrAlANWqGX+u9K/D 0+3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=YUgoT+b6fWGQnaxpAgaCymNUj0JMoRjdbdEo3IB0Hrw=; b=QrVCME/+YxkkotARIM4WJ7A04RDnJXF1WtRtuPeN0V8qvT7IKydF8stu+XlgOnbfwg 0R2dA4Keul4g7D9Pf19RPH/UMVLLp1AolRMZuQY3JqYU3cojxXrypIaTiwRQI3u2muAq 6rix1gcHnD1IxJ4uES/WrVy54q2A/gzbJOdNIOmrRxbGZjMRtyl+WjmILTk3ls1yrfxv 5P+O4/UjEqzDdrxBbSnutUW1Lh/8vwHJOeH6/T0YhJCiVMgklXGi34042VKXQm2vzNH/ j6L6fVq1q50c77E50reaE5E8w+JStQQOkaB3MD98GclnseZeSpT6jg4lpY+DmVNMwv9M M1ug== X-Gm-Message-State: ACrzQf1uKbxbQMTJ9vxZVXplLLSls2UGqNGaRD+9//0/59OHxgSfdcX0 2UmjrIVJfhZf+eXQ7PzaVSUqcwXxH6iiCg== X-Google-Smtp-Source: AMsMyM5TpbzgT98bO0zlNNSPUIGpouyd2A2kHZEFdwdzPE3/ZnOQojwkNJOqXqjLoKFl440E14l6jQ== X-Received: by 2002:a37:38d:0:b0:6cd:fd39:10e5 with SMTP id 135-20020a37038d000000b006cdfd3910e5mr9535242qkd.784.1664641430025; Sat, 01 Oct 2022 09:23:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 11/42] target/arm: Reorg regime_translation_disabled Date: Sat, 1 Oct 2022 09:22:47 -0700 Message-Id: <20221001162318.153420-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::734; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x734.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664642224757100001 Content-Type: text/plain; charset="utf-8" Use a switch on mmu_idx for the a-profile indexes, instead of three different if's vs regime_el and arm_mmu_idx_is_stage1_of_2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9be11f1673..2875ea881c 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -148,21 +148,39 @@ static bool regime_translation_disabled(CPUARMState *= env, ARMMMUIdx mmu_idx, =20 hcr_el2 =3D arm_hcr_el2_eff(env); =20 - if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { + switch (mmu_idx) { + case ARMMMUIdx_Stage2: + case ARMMMUIdx_Stage2_S: /* HCR.DC means HCR.VM behaves as 1 */ return (hcr_el2 & (HCR_DC | HCR_VM)) =3D=3D 0; - } =20 - if (hcr_el2 & HCR_TGE) { + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ - if (!is_secure && regime_el(env, mmu_idx) =3D=3D 1) { + if (!is_secure && (hcr_el2 & HCR_TGE)) { return true; } - } + break; =20 - if ((hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: /* HCR.DC means SCTLR_EL1.M behaves as 0 */ - return true; + if (hcr_el2 & HCR_DC) { + return true; + } + break; + + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_E2: + case ARMMMUIdx_E3: + break; + + default: + g_assert_not_reached(); } =20 return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664642452; cv=none; d=zohomail.com; s=zohoarc; b=iYn3rAupaQ5uOGE6JESR9O5+D5RvQoLJfZJeImcftoXo0VnV9f6LbpmpIfr1ag94t13F25QPDOqhQbywXWkhL5ZzzTiqKQN0mRkSK9SEwLDoOpdHb9ZiFu990MY/YCDsgr3VZGs7x6vYllLqn1fxdiZfK1GxkOpGpgMYCDbkE/M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664642452; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XPPHU0lTWthT7ltYYV7t26jbrDU+bNcf6qqSn2mwNC8=; b=RT8OcKY9MjyMeTwBD8smwFdM9dcdl+Tw7tBWONf6PeFwiiAuNRBsVMgP0nGicS5mlrPhWS/29QKvRp3be480h0YuYA0EsSXcfyQgitXgiOYtLGKADCLxlzY8VNcyt3KXUwBd45Bxv6iY/VTkgv+i7lIyUHjViBCZUS7D4GwznRc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664642452376508.0768541894297; Sat, 1 Oct 2022 09:40:52 -0700 (PDT) Received: from localhost ([::1]:53926 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefXn-0005tf-9L for importer@patchew.org; Sat, 01 Oct 2022 12:40:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33438) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefHW-0006kV-9a for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:05 -0400 Received: from mail-qk1-x72a.google.com ([2607:f8b0:4864:20::72a]:42614) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefHO-0006Gu-Dj for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:23:58 -0400 Received: by mail-qk1-x72a.google.com with SMTP id d15so4532656qka.9 for ; Sat, 01 Oct 2022 09:23:52 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.23.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:23:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=XPPHU0lTWthT7ltYYV7t26jbrDU+bNcf6qqSn2mwNC8=; b=kCk/cnCPZGTyn4lbeziQXU9ruNq56Sfirxfs9RebssrvtiIctRHf21YcKDxwAg/wUf HrGwpIWT7JnVohn/lroWJTkalKK51tzI35hi2wryYUaebH/7bt41XYAI1pySm6zLbRpA WBFX+RybOzHPb6D24CJUMOI8YenlOe7vbIY0/7go3bkv1CUkae0D4ZdDM1xnj8HsDnMG 9irFd3dHM8QGEYsMFxu53De9D5Pxpm/ifpJU9pq6IKRFe+Q5drQ5iFYUPU/lxCgG+Os0 GkkLm2ChrVi2JGmOG7h705xgSMYUIGKNiiZOou0hIJQNPyyzERSMT1svy9gyOGeH8vkl +U8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=XPPHU0lTWthT7ltYYV7t26jbrDU+bNcf6qqSn2mwNC8=; b=B2xyce8tP+XTz+Cxr3i/ZFMqg4OIUx6MlOL1G2QN8gmbBXe8SH5D1o+7EMDkZY2YYn T3M3tSET7kUTfxoKLsViRy3wK7Qh2KnoXohxV0jIs2oP5OSapFjUaUMYBeF243fS65VW Urjkwdiz/VuXKBFoLscVqEcAdKF0pS0uT8mr9T7k/Tw6WBK6nxljtdDAmHBEHK/TYNcc hLU9msSQm69eTNU7MH8q2OIHkz6BrMAAhAPXsTPj7YjCcbLEj0LFy3zFo5/jfN/LDR78 A7hsgFcMQWqBLawFmxnYrJA5+nt3W+PYhEtyUzFSdXhSRqRNZZRW6BVao55owHsLG3zL SDZg== X-Gm-Message-State: ACrzQf0qmj17q1tlKrZbB2VIbiyTrBLCqOJsauYX+W86NzBizDd2fWQv EaWXxxxlg/Uxhi0E6dKjvampTWol8IBDVw== X-Google-Smtp-Source: AMsMyM4wZFwiTQccpROvuGNG7dN/eM2OkrnJ1QbHXBIcJQtb06U/1sHc4mOJ2AV+CbXd0/b8MTr6zA== X-Received: by 2002:ae9:e206:0:b0:6cb:d54d:69ee with SMTP id c6-20020ae9e206000000b006cbd54d69eemr9816891qkc.466.1664641432065; Sat, 01 Oct 2022 09:23:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 12/42] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M Date: Sat, 1 Oct 2022 09:22:48 -0700 Message-Id: <20221001162318.153420-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72a; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664642454386100001 Content-Type: text/plain; charset="utf-8" The effect of TGE does not only apply to non-secure state, now that Secure EL2 exists. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 2875ea881c..1ea29bec58 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -157,8 +157,8 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx, case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: - /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ - if (!is_secure && (hcr_el2 & HCR_TGE)) { + /* TGE means that EL0/1 act as if SCTLR_EL1.M is zero */ + if (hcr_el2 & HCR_TGE) { return true; } break; --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664642349; cv=none; d=zohomail.com; s=zohoarc; b=CeXW/JB7a4Y2D1rRQiDPxoJJrg/8SlYJLpnZsGbEQHr7szPqvvDn9U6fw7/RjdtVdPedrIGV/mT3165mtJHIrzfnwrxtAt7k/fGXbuPBYxcPjRtBv2wCll7xVR592W8geWJJ7h7vDVs0HuVbkfCWdIJzcXODbtrXbvCKYqBgEqI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664642349; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7gsclz+yJ1LC9lf4uAjmiJKG45xyG8DkF/pgWvR4z/U=; b=Z6juZ9FbKpeFnXejmF+zmInevLnHbfzKUMpb2Ew/J2Mgb0MKZhEeK94I5h/S92GPe5dBeEqm0vGzzO+dd0tMkbGk0lj05Z/CCr9SkzhSLfFwGNJV9hCT2+p62MiGrgfBfMcwpS2nedUlMG53ciBs2py4Ttxare39jvSzlDZqV5U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664642349434455.16481198362226; Sat, 1 Oct 2022 09:39:09 -0700 (PDT) Received: from localhost ([::1]:57236 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefW8-0002H6-E1 for importer@patchew.org; Sat, 01 Oct 2022 12:39:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33434) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefHW-0006kT-8k for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:05 -0400 Received: from mail-qv1-xf32.google.com ([2607:f8b0:4864:20::f32]:46075) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefHQ-0006HO-EF for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:00 -0400 Received: by mail-qv1-xf32.google.com with SMTP id g9so834498qvo.12 for ; Sat, 01 Oct 2022 09:23:54 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.23.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:23:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=7gsclz+yJ1LC9lf4uAjmiJKG45xyG8DkF/pgWvR4z/U=; b=OhjW+ZSOGIbPYAfy2rXRKqigSG+IVjzfqEgCODIMYJ0nhqT5sFZ8iyUOz0nlvaj/s5 xhNYdAZSM5G1O9EtPPxT8xNS2M1uSvPDLJ2SN/KN0INYsWaUWgjzaFdsZlsbr3ddPCQS bfEiKpZSe0f6JMAuJlk4/wQRMv73NgjqUV1jE/+ri8TaCTl9mA20zd4IWaB5+xbgkdHu ICYmR5X3XV9lkAJ5i5aM0j61lyL/oeANjNb1/6WdVyaE+trBp+FYCMDleHYRH3l7aRqK C2jUgjb+/ZGS0vik+dYBtmdHyfiKd+zHHXQLwVvOIzCGCABGnFt64B8vWt1MECjSqmke k/cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=7gsclz+yJ1LC9lf4uAjmiJKG45xyG8DkF/pgWvR4z/U=; b=01e520FgOK5O8if597tllYyypB24DbEYwOFpdzYRzncUMhIW3VSZDL4wODqqCPAQnQ BVdGbyUdeHthuRtEmdVW1lyGBO+QEF5B6jfpoiX3nUapka7wgYnpPbiL8GDRJzZ6t4nf aKhTi5caKyRCWI2vwpTmAM+PDBewmKizbWPVMgOsa0WVBVsJsOErNN4/zoNgcm4Bi1Rf RsEJva15CmPL8hQCRBOlmpnFdKkf9JDhtpTXFeSdtGyaPOp7x/gwN9Ohuu4+1VvALkRW tw8Vwtm382MZIL7QHC7ocgBnHp/QY8t5kAotJyNXLu59BdlscZKRuhbj0LWR7mptAi3b OVGw== X-Gm-Message-State: ACrzQf32bL54cJO1XHP4CmfpsAIbzxnMMnIuHhC4+HHjUgaVSCBWjKv6 PYnKpJ/7byNjm450XchYThN9RpKm6BKUvg== X-Google-Smtp-Source: AMsMyM4isjJbcb6Qmlik/XkvwTHx/QFbIZZDYxohV6PH9JQBhYH66NhN76Iz/L3r77SmvrY4/HKiVQ== X-Received: by 2002:ad4:5c6c:0:b0:4b1:7030:b195 with SMTP id i12-20020ad45c6c000000b004b17030b195mr5809218qvh.107.1664641434351; Sat, 01 Oct 2022 09:23:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 13/42] target/arm: Introduce arm_hcr_el2_eff_secstate Date: Sat, 1 Oct 2022 09:22:49 -0700 Message-Id: <20221001162318.153420-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f32; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664642351529100001 Content-Type: text/plain; charset="utf-8" For page walking, we may require HCR for a security state that is not "current". Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 20 +++++++++++++------- target/arm/helper.c | 11 ++++++++--- 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6475dc0cfd..0f82f4aa1d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2406,15 +2406,15 @@ static inline bool arm_is_secure(CPUARMState *env) * Return true if the current security state has AArch64 EL2 or AArch32 Hy= p. * This corresponds to the pseudocode EL2Enabled() */ +static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secu= re) +{ + return arm_feature(env, ARM_FEATURE_EL2) + && (!secure || (env->cp15.scr_el3 & SCR_EEL2)); +} + static inline bool arm_is_el2_enabled(CPUARMState *env) { - if (arm_feature(env, ARM_FEATURE_EL2)) { - if (arm_is_secure_below_el3(env)) { - return (env->cp15.scr_el3 & SCR_EEL2) !=3D 0; - } - return true; - } - return false; + return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env)); } =20 #else @@ -2428,6 +2428,11 @@ static inline bool arm_is_secure(CPUARMState *env) return false; } =20 +static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secu= re) +{ + return false; +} + static inline bool arm_is_el2_enabled(CPUARMState *env) { return false; @@ -2440,6 +2445,7 @@ static inline bool arm_is_el2_enabled(CPUARMState *en= v) * "for all purposes other than a direct read or write access of HCR_EL2." * Not included here is HCR_RW. */ +uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure); uint64_t arm_hcr_el2_eff(CPUARMState *env); uint64_t arm_hcrx_el2_eff(CPUARMState *env); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 0fd0c73092..4eec22b1f8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5216,15 +5216,15 @@ static void hcr_writelow(CPUARMState *env, const AR= MCPRegInfo *ri, } =20 /* - * Return the effective value of HCR_EL2. + * Return the effective value of HCR_EL2, at the given security state. * Bits that are not included here: * RW (read from SCR_EL3.RW as needed) */ -uint64_t arm_hcr_el2_eff(CPUARMState *env) +uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure) { uint64_t ret =3D env->cp15.hcr_el2; =20 - if (!arm_is_el2_enabled(env)) { + if (!arm_is_el2_enabled_secstate(env, secure)) { /* * "This register has no effect if EL2 is not enabled in the * current Security state". This is ARMv8.4-SecEL2 speak for @@ -5283,6 +5283,11 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) return ret; } =20 +uint64_t arm_hcr_el2_eff(CPUARMState *env) +{ + return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env)); +} + /* * Corresponds to ARM pseudocode function ELIsInHost(). */ --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664642584; cv=none; d=zohomail.com; s=zohoarc; b=gUNzQ1pPxP52liubPvcUMUCkr/ELJ9QiLEpPC8TvQSf0mNOOe0FRJUEqC3qoW+Ws/FCN3RAIhZbMMfMbZ3FYebDc0E69N+POSzsWx0n+dqX+SuzUx+vwjRKPFcyiUYaucCOEuuV8mZ+41FzJyGvIfyQV+aqrn7rhI1QunQdUcpQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664642584; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4bFcMUoE4kIp+2MWdZM5AsV1Ns0C4SweuGTMktPkM3A=; b=jaU8+toDctaNI24Hqw7GGenOhIS6qyPd0+JMMKmr6V9QbmmKG1f9AMjotUjAFUhKjW0kr0Gin9tJw2A0Q9aSTXTeeTkxAgrruBJKId5F4vqVjMNzWAblQpbhfk9r188BVrUhicjS1PVm7IRmmVSh5bZW3MDOzv1S4uPt4FeaYG0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166464258416855.22821113610223; Sat, 1 Oct 2022 09:43:04 -0700 (PDT) Received: from localhost ([::1]:53328 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefZv-00039R-0T for importer@patchew.org; Sat, 01 Oct 2022 12:43:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33448) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefHY-0006ky-OE for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:06 -0400 Received: from mail-qv1-xf2a.google.com ([2607:f8b0:4864:20::f2a]:46856) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefHW-0006Hd-0k for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:03 -0400 Received: by mail-qv1-xf2a.google.com with SMTP id j8so4634171qvt.13 for ; Sat, 01 Oct 2022 09:23:57 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.23.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:23:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=4bFcMUoE4kIp+2MWdZM5AsV1Ns0C4SweuGTMktPkM3A=; b=RmJrPXJWq/ozpee8FKrA5+CKrZFEc6P5gjFoLee1ET3rtcfkjbr9IEDLwCMC5LWfVZ +vdiwm/iiN+ET2ste4EwEkUtCGFbWuOLC+VlVc+uwhxfUxgMmlYPAclypK+XRcnjIXpc I5f3l+j3FKHsKhgJvWkD6+eSllHvCIY7JI1J9mkm4xtvdrug595RGc7bzQqqP0AkAL7C ecxcKq1UtgBKPCCa7qnQl9D+4WCHorv/c9zaa71V/sNGixlxyyWZZccuWhvjJRoCZ/LM MiDnTtoC0rZR7fWlwqzxap1pwop+YLFYSV9Z86V/Lv6HxlDQqlKnsog2s/KOP1sJPC7T x2dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=4bFcMUoE4kIp+2MWdZM5AsV1Ns0C4SweuGTMktPkM3A=; b=h6EvYrt3GZzpQqT4nbAt0GzR6bQ4lmbvAiMMIxFVwVKzrtHaFUj/epo+K8+o854VyS c6wq0hlMW5TeeIDFs8/NY4oUKHp43Q8UlERl/cOHhhVsRHG79pxrAqfbrHrwRsW+sSq2 jwiMMXbYw8Icxg7hI/UGep1qRp8aAElV3nsS+KmKnWviMoOIZYwgnw1mSquyMO/8j5qt 6CRZ5EfIloQTFOUN0FvGnBPdYLDePIocsTgamM6rZlX0XrhabVN/iDOKwmyg+zrIJ+mw rnwBCDBk+Vm+4xUzImlfl1doW2OyU7l7AfYaJBjDqgKhGmJeIr7T8t9Zrl3r/H4UGU37 4GpQ== X-Gm-Message-State: ACrzQf3i3hoV9AYg8b9pGBQNf0VmVh0h7lj+FTX39Fd/ELOQqcFe3mON qA08GL6XjS3+0q4pYifvojVQJOUCriwDVA== X-Google-Smtp-Source: AMsMyM4qQeuFf+gd0mRI4T02kB23/EQH8cXtYJ5I0tyVCNkkIvrysgOHOW46TL6cB+J+953SzdHwwA== X-Received: by 2002:ad4:5966:0:b0:4ad:7832:a8ec with SMTP id eq6-20020ad45966000000b004ad7832a8ecmr11298393qvb.82.1664641437306; Sat, 01 Oct 2022 09:23:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 14/42] target/arm: Hoist read of *is_secure in S1_ptw_translate Date: Sat, 1 Oct 2022 09:22:50 -0700 Message-Id: <20221001162318.153420-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2a; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664642585102100001 Content-Type: text/plain; charset="utf-8" Rename the argument to is_secure_ptr, and introduce a local variable is_secure with the value. We only write back to the pointer toward the end of the function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 1ea29bec58..cb072792a2 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -207,24 +207,25 @@ static bool ptw_attrs_are_device(CPUARMState *env, AR= MCacheAttrs cacheattrs) =20 /* Translate a S1 pagetable walk through S2 if needed. */ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, - hwaddr addr, bool *is_secure, + hwaddr addr, bool *is_secure_ptr, ARMMMUFaultInfo *fi) { - ARMMMUIdx s2_mmu_idx =3D *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_S= tage2; + bool is_secure =3D *is_secure_ptr; + ARMMMUIdx s2_mmu_idx =3D is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_St= age2; =20 if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, s2_mmu_idx, *is_secure)) { + !regime_translation_disabled(env, s2_mmu_idx, is_secure)) { GetPhysAddrResult s2 =3D {}; int ret; =20 ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, - *is_secure, false, &s2, fi); + is_secure, false, &s2, fi); if (ret) { assert(fi->type !=3D ARMFault_None); fi->s2addr =3D addr; fi->stage2 =3D true; fi->s1ptw =3D true; - fi->s1ns =3D !*is_secure; + fi->s1ns =3D !is_secure; return ~0; } if ((arm_hcr_el2_eff(env) & HCR_PTW) && @@ -237,19 +238,20 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, fi->s2addr =3D addr; fi->stage2 =3D true; fi->s1ptw =3D true; - fi->s1ns =3D !*is_secure; + fi->s1ns =3D !is_secure; return ~0; } =20 if (arm_is_secure_below_el3(env)) { /* Check if page table walk is to secure or non-secure PA spac= e. */ - if (*is_secure) { - *is_secure =3D !(env->cp15.vstcr_el2 & VSTCR_SW); + if (is_secure) { + is_secure =3D !(env->cp15.vstcr_el2 & VSTCR_SW); } else { - *is_secure =3D !(env->cp15.vtcr_el2 & VTCR_NSW); + is_secure =3D !(env->cp15.vtcr_el2 & VTCR_NSW); } + *is_secure_ptr =3D is_secure; } else { - assert(!*is_secure); + assert(!is_secure); } =20 addr =3D s2.phys; --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664642569; cv=none; d=zohomail.com; s=zohoarc; b=WspMCRH8X6FuCVZlkTdUDrjMd0BCgXxnjF1HZ62j8ObYwqh1yFEy6kCgAjptdmy0gLwA7c4EwJElyIzA7NUjQNlbHcoLSmwakwA2HSnlBQY1Hf0bx6Lf+gxEZOSuLAFDrcAmfAa9L/EB7zWKYmmias8Feptk9P6X1Ye3tTvTjKY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664642569; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=P8opVlBK6qS9SIIhCXO8x07deEen8LaeMoy6ZbnmA70=; b=Uy3jm1gwY0TLOnZyUfFEPo2F7J1J5mJQkRCT34xiltioDJiozwtiAdOOhrTTh5Bq5vxTzJp/8euYCgO7MFv5XintjmANUL99tsmYrjTQ7aMKwRXVhJZg9hjBy/ibAXyxi2JE5/n7g6Kn5ydXaIILar7dkwb4iK4as5AHgbpn3P0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664642569077119.85649193111283; Sat, 1 Oct 2022 09:42:49 -0700 (PDT) Received: from localhost ([::1]:41282 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefZg-0002S7-15 for importer@patchew.org; Sat, 01 Oct 2022 12:42:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41554) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefHa-0006l4-3v for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:07 -0400 Received: from mail-qt1-x82a.google.com ([2607:f8b0:4864:20::82a]:45762) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefHW-0006Dr-1K for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:04 -0400 Received: by mail-qt1-x82a.google.com with SMTP id r20so4338428qtn.12 for ; Sat, 01 Oct 2022 09:24:00 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index cb072792a2..2f0eeee161 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2172,8 +2172,7 @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr) * s1 and s2 for the HCR_EL2.FWB =3D=3D 1 case, returning the * combined attributes in MAIR_EL1 format. */ -static uint8_t combined_attrs_fwb(CPUARMState *env, - ARMCacheAttrs s1, ARMCacheAttrs s2) +static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2) { switch (s2.attrs) { case 7: @@ -2246,7 +2245,7 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *= env, =20 /* Combine memory type and cacheability attributes */ if (arm_hcr_el2_eff(env) & HCR_FWB) { - ret.attrs =3D combined_attrs_fwb(env, s1, s2); + ret.attrs =3D combined_attrs_fwb(s1, s2); } else { ret.attrs =3D combined_attrs_nofwb(env, s1, s2); } --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664642458; cv=none; d=zohomail.com; s=zohoarc; b=UnUP/OCRg8OHUjHUbzugIKi1ftw2W7H0hMIeDT/PXWFsJfWkoNB2utcJ3BBsomPr188QhBKneLhDqSFtgkES4tPDGm594NYLqrY0WjBZTpzazR1A/57wO5p38EeUWycbFXqitc/1qEjGQx3gHIDOEVIzMhWG5tu9xuR6qj0HmAc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664642458; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CxZpo48Pit+l3tJZfLwPPiYxT3jz9P+qHlIFLFC1mV8=; b=mE6RHl4MHkOzPG8KiIIUiykd4gmCqeRHMrrJvEg4yzfnl6oV9sraH93LlMQmB9U57ZetC2wL47SjXfE8HByuP58ugYqgJaFZczgHzDSIngDlMtUiIaF/JlfboKSXdVMWIc6BtswgCID4Gg/iOKBB5cN/0w/xzrmq6EYfRLcYz1w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664642458545530.7311039092788; Sat, 1 Oct 2022 09:40:58 -0700 (PDT) Received: from localhost ([::1]:60916 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefXs-0006AB-Il for importer@patchew.org; Sat, 01 Oct 2022 12:40:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41560) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefHb-0006lJ-1V for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:07 -0400 Received: from mail-qt1-x831.google.com ([2607:f8b0:4864:20::831]:39907) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefHY-0006FR-Fz for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:06 -0400 Received: by mail-qt1-x831.google.com with SMTP id s18so4343014qtx.6 for ; Sat, 01 Oct 2022 09:24:02 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=CxZpo48Pit+l3tJZfLwPPiYxT3jz9P+qHlIFLFC1mV8=; b=oXEGdWoMRe4iYpWE5nrYbr9Ik915bZcmTV3psq9IFc24lLmWYsLo01Og3XRa+pis0C Kjll2Ej0WMH60e//n2LE8MalqLnm8GxSFLc2H2Twk3ZADMSVJt8JzOx1KbOKxBtvnPqA DWbfdZ3W0IPgHyERYdmJBxONyzB/9XU6CRg6m1DUuRzkV1pb3r3cYYJ1aFbPQtiSu6cF UE62myKPIF4eoVl3AnbAL4HkNd1begnzX3hrPxXXpJf0keqX1EtG0a764px/6tBFqO2l lGN0gEqtcldSHyOr0/Zo9Ub8Y4wC/Oe0seGDcGGeFidsbKkOT0vwUAq+7dn05htI66mv YaJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=CxZpo48Pit+l3tJZfLwPPiYxT3jz9P+qHlIFLFC1mV8=; b=TsxRpef8kkbv6ik+6u25wlxnM6+vCSWz/dqh1jg2bcsfL+ch95LPXYU/Bp1UIM+hQk d/BIl/RFWb+lonMakoZ6H1V4VV2+ErzGB509+3KeWcEb/flhJTCyAjq0DM170fj+Li9U afngHKFkwksSRtzo8PlZma82DSKohtAcb9IYm5YsmmicyZyoSOR3QBi25rEWkcHuibfc RloQ46E5fM/31ODQ/KpWgQEyy1u7JKyoAOTr3F4nWe8vnSD8NJhgaYKs26IluhAQvek7 o69w+SN/wTlpeWTzy9nC7gmpEbE5pTSMcpSL/2o6b3aaqJ8AOdnRwJ1Igd+yos33EZW4 fR9A== X-Gm-Message-State: ACrzQf3fokHxVCd3SdMWB7rajTN6z/Wo2k30PVgkeo4Z3OLS4c8xivAn oSyav4Sr+aVeY61dp7GjifrMoXbp5tBmoQ== X-Google-Smtp-Source: AMsMyM5wpI6H3pKCDzex3Ilvv+jODyl//eBroOZT2KrdPwV7hxxPw+BHwHP1sP9JAc89TCmYy+wqvw== X-Received: by 2002:a05:622a:1790:b0:35c:8450:d9e4 with SMTP id s16-20020a05622a179000b0035c8450d9e4mr10908000qtk.130.1664641442177; Sat, 01 Oct 2022 09:24:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 16/42] target/arm: Pass HCR to attribute subroutines. Date: Sat, 1 Oct 2022 09:22:52 -0700 Message-Id: <20221001162318.153420-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::831; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x831.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664642460343100001 Content-Type: text/plain; charset="utf-8" These subroutines did not need ENV for anything except retrieving the effective value of HCR anyway. We have computed the effective value of HCR in the callers, and this will be especially important for interpreting HCR in a non-current security state. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 2f0eeee161..a0dce9c313 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -186,7 +186,7 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; } =20 -static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattr= s) +static bool ptw_attrs_are_device(uint64_t hcr, ARMCacheAttrs cacheattrs) { /* * For an S1 page table walk, the stage 1 attributes are always @@ -198,7 +198,7 @@ static bool ptw_attrs_are_device(CPUARMState *env, ARMC= acheAttrs cacheattrs) * when cacheattrs.attrs bit [2] is 0. */ assert(cacheattrs.is_s2_format); - if (arm_hcr_el2_eff(env) & HCR_FWB) { + if (hcr & HCR_FWB) { return (cacheattrs.attrs & 0x4) =3D=3D 0; } else { return (cacheattrs.attrs & 0xc) =3D=3D 0; @@ -216,6 +216,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && !regime_translation_disabled(env, s2_mmu_idx, is_secure)) { GetPhysAddrResult s2 =3D {}; + uint64_t hcr; int ret; =20 ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, @@ -228,8 +229,9 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, fi->s1ns =3D !is_secure; return ~0; } - if ((arm_hcr_el2_eff(env) & HCR_PTW) && - ptw_attrs_are_device(env, s2.cacheattrs)) { + + hcr =3D arm_hcr_el2_eff(env); + if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) { /* * PTW set and S1 walk touched S2 Device memory: * generate Permission fault. @@ -2059,14 +2061,14 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, = uint32_t address, * ref: shared/translation/attrs/S2AttrDecode() * .../S2ConvertAttrsHints() */ -static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) +static uint8_t convert_stage2_attrs(uint64_t hcr, uint8_t s2attrs) { uint8_t hiattr =3D extract32(s2attrs, 2, 2); uint8_t loattr =3D extract32(s2attrs, 0, 2); uint8_t hihint =3D 0, lohint =3D 0; =20 if (hiattr !=3D 0) { /* normal memory */ - if (arm_hcr_el2_eff(env) & HCR_CD) { /* cache disabled */ + if (hcr & HCR_CD) { /* cache disabled */ hiattr =3D loattr =3D 1; /* non-cacheable */ } else { if (hiattr !=3D 1) { /* Write-through or write-back */ @@ -2112,12 +2114,12 @@ static uint8_t combine_cacheattr_nibble(uint8_t s1,= uint8_t s2) * s1 and s2 for the HCR_EL2.FWB =3D=3D 0 case, returning the * combined attributes in MAIR_EL1 format. */ -static uint8_t combined_attrs_nofwb(CPUARMState *env, +static uint8_t combined_attrs_nofwb(uint64_t hcr, ARMCacheAttrs s1, ARMCacheAttrs s2) { uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs; =20 - s2_mair_attrs =3D convert_stage2_attrs(env, s2.attrs); + s2_mair_attrs =3D convert_stage2_attrs(hcr, s2.attrs); =20 s1lo =3D extract32(s1.attrs, 0, 4); s2lo =3D extract32(s2_mair_attrs, 0, 4); @@ -2217,7 +2219,7 @@ static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, A= RMCacheAttrs s2) * @s1: Attributes from stage 1 walk * @s2: Attributes from stage 2 walk */ -static ARMCacheAttrs combine_cacheattrs(CPUARMState *env, +static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, ARMCacheAttrs s1, ARMCacheAttrs s2) { ARMCacheAttrs ret; @@ -2244,10 +2246,10 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState= *env, } =20 /* Combine memory type and cacheability attributes */ - if (arm_hcr_el2_eff(env) & HCR_FWB) { + if (hcr & HCR_FWB) { ret.attrs =3D combined_attrs_fwb(s1, s2); } else { - ret.attrs =3D combined_attrs_nofwb(env, s1, s2); + ret.attrs =3D combined_attrs_nofwb(hcr, s1, s2); } =20 /* @@ -2290,6 +2292,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, ARMCacheAttrs cacheattrs1; ARMMMUIdx s2_mmu_idx; bool is_el0; + uint64_t hcr; =20 ret =3D get_phys_addr_with_secure(env, address, access_type, s1_mmu_idx, is_secure, result,= fi); @@ -2338,7 +2341,8 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, } =20 /* Combine the S1 and S2 cache attributes. */ - if (arm_hcr_el2_eff(env) & HCR_DC) { + hcr =3D arm_hcr_el2_eff(env); + if (hcr & HCR_DC) { /* * HCR.DC forces the first stage attributes to * Normal Non-Shareable, @@ -2351,7 +2355,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, } cacheattrs1.shareability =3D 0; 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([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=LeO8wVc8x9qKMAPYpXMUEdsFvPVUI/smjTgJR5ckIew=; b=cBXj6+j56XUXm/Eq9UNrfPJ/f3BwV/G1hLpwcIJi3cmGGiyKeYE86AoWug+/XYxm6K eW2pwWcswEIFtfQzl9ZQSSrZkMla8IkQIbFkkloplC3rKRcBZSN7834pQ356HiTO3M/F GosCzdvOWPtXXR2Ha4veEKWOOQBSaEStMXVdckBSbEAc5aHGn4EVDUm55wvXvbcgiXeU GolRxoRSjcN6dlB/ApKp8QV7VFX5GfbuK1IalcxlfQaYVfeeuBylifeAfPbFn4IFadJ1 1r2FL28jmydKDLfOOq6SwaBM+ft6dgw7/DkyYdh4JFuXbvPreRkFE96MMnRlQoleeIdF MQfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=LeO8wVc8x9qKMAPYpXMUEdsFvPVUI/smjTgJR5ckIew=; b=8ONUa66nVLHEOzzaz4srbXxrDM2yMNBZ5NxMz21InLmFG2fMiXh4SzzsAiobkGztDP gzWqcnx1m7GX2hFro0iFFgRAK/bEhiOXvxx33ciw7An5qwCll7iZgruudcymizXiSEeB IM0liIT5SnfvE36f2jMdJV95OHPnUC3hIyNErfcBVB9uh2VrRVYacAxqGhM7ISztuVU8 1DG0MRdGnol/mOVh4nNl3nkcYh4IpT0cdQ3FWPcrMR7sY5qNbqIEjq3wC4Z36GEyyNU8 b/LsM6BFyiRyD5StdD/Q6PItyZ2REMwF0LSL0rhlJ/+WNS12RMT/onZLCoMUwRdpigRw EVDQ== X-Gm-Message-State: ACrzQf2bR5hMAOSC9SvdWcceTEMf7cW9nCYjBGrUIWY1s18pU8brDoa8 /h9gGlPPHYUACl9o9XShe8o51Hzkkswv9Q== X-Google-Smtp-Source: AMsMyM7AIs5S4FEhSvCCCNWmiWY3uESiBemXe4qpxyZJnxyvv/WZMBObXDXoLw8POhw8e3dj028Hyw== X-Received: by 2002:a05:620a:2406:b0:6cf:38fd:654b with SMTP id d6-20020a05620a240600b006cf38fd654bmr9842558qkn.417.1664641444770; Sat, 01 Oct 2022 09:24:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 17/42] target/arm: Fix ATS12NSO* from S PL1 Date: Sat, 1 Oct 2022 09:22:53 -0700 Message-Id: <20221001162318.153420-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72b; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664642978886100001 Content-Type: text/plain; charset="utf-8" Use arm_hcr_el2_eff_secstate instead of arm_hcr_el2_eff, so that we use is_secure instead of the current security state. These AT* operations have been broken since arm_hcr_el2_eff gained a check for "el2 enabled" for Secure EL2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a0dce9c313..7bf79779da 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -146,7 +146,7 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx, } } =20 - hcr_el2 =3D arm_hcr_el2_eff(env); + hcr_el2 =3D arm_hcr_el2_eff_secstate(env, is_secure); =20 switch (mmu_idx) { case ARMMMUIdx_Stage2: @@ -230,7 +230,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, return ~0; } =20 - hcr =3D arm_hcr_el2_eff(env); + hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) { /* * PTW set and S1 walk touched S2 Device memory: @@ -2341,7 +2341,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, } =20 /* Combine the S1 and S2 cache attributes. */ - hcr =3D arm_hcr_el2_eff(env); + hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); if (hcr & HCR_DC) { /* * HCR.DC forces the first stage attributes to @@ -2474,7 +2474,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, result->page_size =3D TARGET_PAGE_SIZE; =20 /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ - hcr =3D arm_hcr_el2_eff(env); + hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); result->cacheattrs.shareability =3D 0; result->cacheattrs.is_s2_format =3D false; if (hcr & HCR_DC) { --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664642589; cv=none; d=zohomail.com; s=zohoarc; b=lrvtgPbW4ebz0zc+Ry2NxSWqN1R6t4PddoyS0RxqT7UUpHKDKKGJMmNwGHlFOT42yeFo98T94tARYzBDOm77skXQG9JfpeFwaIQLQ6tu0gRIU8qyVlWie6uZFKEJjuQJGVKvFwQntdqCHI9JzRrYpsH2U0fpZK+dMfxAMfycQd4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664642589; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nVf0XoPBuFuQPXtT3jzdB8OzBoWMzBFYm3DKP93Thek=; b=C2i7HWYUwK0HBROjjMGR9HfHyX1Peaxag0rhGuB1050AS0L0M2d0UzNhOEi8TVZGp4sMtl2V4P7HNyZ+QGZAagW47GXffDX/QQkCCGgARBebU5cC5c8LVf/7gz8Wur48xwjMoODjldPZlW7Wm0XEmmliUkAKnHHD8/mmS5HrElQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664642589853697.7490908801292; Sat, 1 Oct 2022 09:43:09 -0700 (PDT) Received: from localhost ([::1]:46846 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefa0-0003Pe-S8 for importer@patchew.org; Sat, 01 Oct 2022 12:43:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41566) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefHe-0006mq-Ba for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:10 -0400 Received: from mail-qt1-x831.google.com ([2607:f8b0:4864:20::831]:40490) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefHb-0006DP-TS for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:09 -0400 Received: by mail-qt1-x831.google.com with SMTP id cj27so4336958qtb.7 for ; Sat, 01 Oct 2022 09:24:07 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=nVf0XoPBuFuQPXtT3jzdB8OzBoWMzBFYm3DKP93Thek=; b=Nm8jHM29wOTokPOMRAZcF4uyA0asZGULi+kSEv5C5K6cwB6ccKk4yZqLI6yQZ54TiF lHYKjycZQbUYAaXO4ouVRgYiNJFWUalmkok3fMpvMunrVI9lu+9Sy92dfWVkpxKs8NB3 koPa0dDJ1QjG2fyz4SpkXdX2lTZ2mp7O6h4q11XzKhDblKYlLXvD8F54y/idB4kU1Dyb Knaq5Rr8acvj4w6300Fax05kA6/VuQTkkb2KRSBLu0m9BxtsCeUcY38hhNc4ajoTRtGA ROh7b3ov8KKKjPRVginE0SIE3tG+OZ1BxK5CrURvh3w0w0apZ2+sRVJFCjdyRhryq2KW prnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=nVf0XoPBuFuQPXtT3jzdB8OzBoWMzBFYm3DKP93Thek=; b=UDA66ya/WN78ae5Rn6LuVmbVKHpc+rzH6+ec/A/cMHBPIL6NY8P+PMQET/lhG9DcMw qUL/LSo3T9ak0Mx0U80cbsnLbx0XKuH+R3OFN4tFC7pe+UZhFioe+UywqsvkU+NO0Z1p hz7PPeBAJHhhQmFH78whXqp/fMudjziAbDxiYKpMvUB7cwtCr6U6aAMfxdArNcpG8CRz 3YS6CeOC60GoV5M0uo34IoL1epCAFRXGWAaNjJtB7zqAGbGtl6Sj3819b3Tdospud3Yl G+uW9LeqNn7K6rCmHkuiNhpIVODEkSnS9eSrs/ixlaViakdEwUfKTGuCTMHWjGSPkuk9 brdw== X-Gm-Message-State: ACrzQf3wjUHzbqab5vYlt4EVpJy/q4yuH1r0MxoPsIfZDUGxS+/A9b6I OC/tZ+0irKFNze0gdE50U6GG+SLrO2XrWQ== X-Google-Smtp-Source: AMsMyM6QGSI9G/mQkt1LpRpuyOcBIL6yqIDBMzcvgiJrwqqDLZPhkMTr5HY56ZxBevacU/325XsZ4w== X-Received: by 2002:ac8:4e48:0:b0:35d:5831:af31 with SMTP id e8-20020ac84e48000000b0035d5831af31mr11204447qtw.188.1664641447117; Sat, 01 Oct 2022 09:24:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 18/42] target/arm: Split out get_phys_addr_disabled Date: Sat, 1 Oct 2022 09:22:54 -0700 Message-Id: <20221001162318.153420-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::831; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x831.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664642591117100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 138 +++++++++++++++++++++++++---------------------- 1 file changed, 74 insertions(+), 64 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7bf79779da..e494a9de67 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2272,6 +2272,78 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, return ret; } =20 +/* + * MMU disabled. S1 addresses within aa64 translation regimes are + * still checked for bounds -- see AArch64.S1DisabledOutput(). + */ +static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, bool is_secure, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) +{ + uint64_t hcr; + uint8_t memattr; + + if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2_S) { + int r_el =3D regime_el(env, mmu_idx); + if (arm_el_is_aa64(env, r_el)) { + int pamax =3D arm_pamax(env_archcpu(env)); + uint64_t tcr =3D env->cp15.tcr_el[r_el]; + int addrtop, tbi; + + tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); + if (access_type =3D=3D MMU_INST_FETCH) { + tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); + } + tbi =3D (tbi >> extract64(address, 55, 1)) & 1; + addrtop =3D (tbi ? 55 : 63); + + if (extract64(address, pamax, addrtop - pamax + 1) !=3D 0) { + fi->type =3D ARMFault_AddressSize; + fi->level =3D 0; + fi->stage2 =3D false; + return 1; + } + + /* + * When TBI is disabled, we've just validated that all of the + * bits above PAMax are zero, so logically we only need to + * clear the top byte for TBI. But it's clearer to follow + * the pseudocode set of addrdesc.paddress. + */ + address =3D extract64(address, 0, 52); + } + } + + result->phys =3D address; + result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->page_size =3D TARGET_PAGE_SIZE; + + /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ + hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); + result->cacheattrs.shareability =3D 0; + result->cacheattrs.is_s2_format =3D false; + if (hcr & HCR_DC) { + if (hcr & HCR_DCT) { + memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ + } else { + memattr =3D 0xff; /* Normal, WB, RWA */ + } + } else if (access_type =3D=3D MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr =3D 0xee; /* Normal, WT, RA, NT */ + } else { + memattr =3D 0x44; /* Normal, NC, No */ + } + result->cacheattrs.shareability =3D 2; /* outer sharable */ + } else { + memattr =3D 0x00; /* Device, nGnRnE */ + } + result->cacheattrs.attrs =3D memattr; + return 0; +} + bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, bool is_secure, GetPhysAddrResult *result, @@ -2432,71 +2504,9 @@ bool get_phys_addr_with_secure(CPUARMState *env, tar= get_ulong address, /* Definitely a real MMU, not an MPU */ =20 if (regime_translation_disabled(env, mmu_idx, is_secure)) { - uint64_t hcr; - uint8_t memattr; - - /* - * MMU disabled. S1 addresses within aa64 translation regimes are - * still checked for bounds -- see AArch64.TranslateAddressS1Off. - */ - if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2= _S) { - int r_el =3D regime_el(env, mmu_idx); - if (arm_el_is_aa64(env, r_el)) { - int pamax =3D arm_pamax(env_archcpu(env)); - uint64_t tcr =3D env->cp15.tcr_el[r_el]; - int addrtop, tbi; - - tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); - if (access_type =3D=3D MMU_INST_FETCH) { - tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); - } - tbi =3D (tbi >> extract64(address, 55, 1)) & 1; - addrtop =3D (tbi ? 55 : 63); - - if (extract64(address, pamax, addrtop - pamax + 1) !=3D 0)= { - fi->type =3D ARMFault_AddressSize; - fi->level =3D 0; - fi->stage2 =3D false; - return 1; - } - - /* - * When TBI is disabled, we've just validated that all of = the - * bits above PAMax are zero, so logically we only need to - * clear the top byte for TBI. But it's clearer to follow - * the pseudocode set of addrdesc.paddress. - */ - address =3D extract64(address, 0, 52); - } - } - result->phys =3D address; - result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - result->page_size =3D TARGET_PAGE_SIZE; - - /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ - hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); - result->cacheattrs.shareability =3D 0; - result->cacheattrs.is_s2_format =3D false; - if (hcr & HCR_DC) { - if (hcr & HCR_DCT) { - memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ - } else { - memattr =3D 0xff; /* Normal, WB, RWA */ - } - } else if (access_type =3D=3D MMU_INST_FETCH) { - if (regime_sctlr(env, mmu_idx) & SCTLR_I) { - memattr =3D 0xee; /* Normal, WT, RA, NT */ - } else { - memattr =3D 0x44; /* Normal, NC, No */ - } - result->cacheattrs.shareability =3D 2; /* outer sharable */ - } else { - memattr =3D 0x00; /* Device, nGnRnE */ - } - result->cacheattrs.attrs =3D memattr; - return 0; + return get_phys_addr_disabled(env, address, access_type, mmu_idx, + is_secure, result, fi); } - if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, is_secure, false, result, fi); --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664643197; cv=none; d=zohomail.com; s=zohoarc; b=FgOpBVCx3LSMK1KQvDQYH3OC8nLxMZ5PfVo/vwk8RnVzN+K2+UwfUiAZydtTQbvT6B7CW0dtER1dxT3QBBraHC2mUajBH2KxDHetE1Na7laRBQx2VNG/JY0Z0LwR2u6OkSzf1bwV8lmYK+4kQccPAGxjm0Nfj2y0mBr8+Vo7+B0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664643197; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=K3rpZd1EKThuVcaxZvC1gnAW/rSp7G0JgKV3rWVzF/U=; b=bFvmTMzHs9OWf638JZVhAlv1+psVRirY2hydLXsh89co07sCfB8q57soJn0E2oCFKBp4t5Kr4vIdBS1Azp7mCZJd6zjwSL3raBiAJjv8h3BZXHNktq5YOQmPTWWgV2WU1FYpSei1O54vffK5Iifilv/ODJzag9jINXPEOBUZ/rw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664643197910363.1153416305974; Sat, 1 Oct 2022 09:53:17 -0700 (PDT) Received: from localhost ([::1]:48676 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefjo-0007Vp-D9 for importer@patchew.org; Sat, 01 Oct 2022 12:53:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41568) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefHg-0006ox-9A for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:12 -0400 Received: from mail-qv1-xf2a.google.com ([2607:f8b0:4864:20::f2a]:46856) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefHe-0006Hd-4M for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:11 -0400 Received: by mail-qv1-xf2a.google.com with SMTP id j8so4634387qvt.13 for ; Sat, 01 Oct 2022 09:24:09 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=K3rpZd1EKThuVcaxZvC1gnAW/rSp7G0JgKV3rWVzF/U=; b=ax2/MuvRV0e/qM/5d/H45ZxqBfRqNzK1my09PMLQHUi1M0OFCKGMwUNiaDik9Bvv11 rB83RCT8CraxqZ2gTuqF2M1yDvAW+pmQHIsE+6GfaMExgA84HlozRGvCemJD6t+sdLfR zaRgk2X1aebi8PpSpTseudwwD/1T4CxG8bHoRPUXnuSmI3VZZhAtGVAuOPOmVRjN3+6v uvb7PWkzPotow0lwMWoFLN8wt1eGHw0rChZlHBm2PZbgGp4oUPr+t2c4hpt0+qcHxOos 5zb0PYpPkFQaH0Y6vzWhkizPvCW4ODziQy8QAgSmjPD+uIrp7xUtcNw0H2QTemLexYC8 MJAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=K3rpZd1EKThuVcaxZvC1gnAW/rSp7G0JgKV3rWVzF/U=; b=kO2jiMD3zPVjJNNTb/O7FhaBZYrvj6sweAdhUDEGQOhNSWVTT4Jl20k5rlBZVh2+TC 2DHEA7xZL7wFmVM4Z5arqRpnd01Ipwd4UJr8XWJijbiFChhIrXgjXGJCbJsLijVouepj RtP5EUnej6M+vid+akTLI9tDO5Nkh8bfvCT2BVzWq3/3gcwNNzLa48NhXhmS+JPLRzln /OfDG5QhSW8BVEhQQUOlPJODaP67qH6BNyBomB5MvoFfHQNfrm7T8bqlzPJn8B5fqS+V wAL+q7PMWLCJlwc2smvIQ20exeT7LTHVuKUcaFdMiT2T4LofIYUxXjQ/D0YWTGKcqahA qqAw== X-Gm-Message-State: ACrzQf0RVgf91egTSEUod4ZK5QDHMawcnXYk/oUsXsW/8FsmE+kyt62p TzXO48s8oTJaZab2upzr8x+2DxUCqaurTw== X-Google-Smtp-Source: AMsMyM6YdhbnX55x2XE1G9VaVBrsaOt2IRlKDWRASxj4KGXrvdTeojZbVty+VuYaKRTQEtX3rKT8Aw== X-Received: by 2002:a05:6214:2385:b0:474:78de:f8dd with SMTP id fw5-20020a056214238500b0047478def8ddmr11227933qvb.66.1664641449269; Sat, 01 Oct 2022 09:24:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 19/42] target/arm: Fix cacheattr in get_phys_addr_disabled Date: Sat, 1 Oct 2022 09:22:55 -0700 Message-Id: <20221001162318.153420-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2a; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664643199311100001 Content-Type: text/plain; charset="utf-8" Do not apply memattr or shareability for Stage2 translations. Make sure to apply HCR_{DC,DCT} only to Regime_EL10, per the pseudocode in AArch64.S1DisabledOutput. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v3: Do not use a switch or a goto. --- target/arm/ptw.c | 48 +++++++++++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 23 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e494a9de67..8d27a98a42 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2282,11 +2282,12 @@ static bool get_phys_addr_disabled(CPUARMState *env= , target_ulong address, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - uint64_t hcr; - uint8_t memattr; + uint8_t memattr =3D 0x00; /* Device nGnRnE */ + uint8_t shareability =3D 0; /* non-sharable */ =20 if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2_S) { int r_el =3D regime_el(env, mmu_idx); + if (arm_el_is_aa64(env, r_el)) { int pamax =3D arm_pamax(env_archcpu(env)); uint64_t tcr =3D env->cp15.tcr_el[r_el]; @@ -2314,32 +2315,33 @@ static bool get_phys_addr_disabled(CPUARMState *env= , target_ulong address, */ address =3D extract64(address, 0, 52); } + + /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ + if (r_el =3D=3D 1) { + uint64_t hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); + if (hcr & HCR_DC) { + if (hcr & HCR_DCT) { + memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ + } else { + memattr =3D 0xff; /* Normal, WB, RWA */ + } + } + } + if (memattr =3D=3D 0 && access_type =3D=3D MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr =3D 0xee; /* Normal, WT, RA, NT */ + } else { + memattr =3D 0x44; /* Normal, NC, No */ + } + shareability =3D 2; /* outer sharable */ + } + result->cacheattrs.is_s2_format =3D false; } =20 result->phys =3D address; result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; result->page_size =3D TARGET_PAGE_SIZE; - - /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ - hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); - result->cacheattrs.shareability =3D 0; - result->cacheattrs.is_s2_format =3D false; - if (hcr & HCR_DC) { - if (hcr & HCR_DCT) { - memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ - } else { - memattr =3D 0xff; /* Normal, WB, RWA */ - } - } else if (access_type =3D=3D MMU_INST_FETCH) { - if (regime_sctlr(env, mmu_idx) & SCTLR_I) { - memattr =3D 0xee; /* Normal, WT, RA, NT */ - } else { - memattr =3D 0x44; /* Normal, NC, No */ - } - result->cacheattrs.shareability =3D 2; /* outer sharable */ - } else { - memattr =3D 0x00; /* Device, nGnRnE */ - } + result->cacheattrs.shareability =3D shareability; result->cacheattrs.attrs =3D memattr; return 0; } --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664642972; cv=none; d=zohomail.com; s=zohoarc; b=Mq3+vWv/Co7LKEwD29JOv0aWKU0mdKFTXCVJFSBJxJPuW982liYFyXDcN0vVjt/TKi4g0t7H3WN1mf27BpdHRS77GZIZ20EwOMxEsJ2awlPFhuzPb9oURbEnR8GqRHs85agPLhoFeYmdcimHc0t8PDDrqX7TgvOwilc/ycEn840= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664642972; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UT7PUowAnf9kIJYhZKLeWwVw/owenw9n/bgkOzzGDTA=; b=UyrrKNqJ/HDyO+bCWspss0x+16w3z5T5JD37nTY/JU7gOMZWmNDq+x99CdHuv913tYUrXG9q2cFjQ/X93E9mZysIKH6mUNSrIFcLMdvaGVU33vfm/BH7BCnKUqTV04Jw2gcFEN/1adpADbxi1zOOqA8tfN/7CGm45HRuXDqDcwM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664642972965962.3039397571162; Sat, 1 Oct 2022 09:49:32 -0700 (PDT) Received: from localhost ([::1]:54858 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefgB-000122-SV for importer@patchew.org; Sat, 01 Oct 2022 12:49:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56076) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefHn-00078d-Cu for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:19 -0400 Received: from mail-qv1-xf2a.google.com ([2607:f8b0:4864:20::f2a]:34408) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefHi-0006KI-Ee for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:19 -0400 Received: by mail-qv1-xf2a.google.com with SMTP id i9so1134277qvu.1 for ; Sat, 01 Oct 2022 09:24:12 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=UT7PUowAnf9kIJYhZKLeWwVw/owenw9n/bgkOzzGDTA=; b=Nklxs0WOGJWlWSPNR5idPTXKHFjAL5m8TPVxF4Eyuk4BXfOGQpUWN75sH56leEc4Hw h+AHn+b7Rw3EzINSVjD2pJSWsTHPczLvn842Fyw+dI039Hwm8VUYAkWKFcthSBGAerTG 9AZO5lJMC3R5NEGh9dgyq0qtrkL8QVkfGq068geT+QJP/SP0hqJ+i2yrBB8g9hYTIIDZ Y8hXmR498INEFB/gA9As+a6y1/FQDA0RvadW9kvDZdcz4dMOBWDOi/Y/X68hYAyjy123 83XtKQ2J4JZ1gilWXJ8bbiBNFmrjc1FeC8H26ENe4k6gJL5JmErr8wm+P5Q28PtlSwRK 6UNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=UT7PUowAnf9kIJYhZKLeWwVw/owenw9n/bgkOzzGDTA=; b=tBKW6U7t0G0yfbh6yJyol8/mo8nCkfc+porOx2T9Rp5rpeZMj9qkOi1WBdUs0QqWMo pVXLajCUSPwRXYbSCNBn2cnj/bHfpIm8is5Few+yn5fR5NREIJMFsfDQ39cYtkhlv0wJ w+fgjawc7zLSEMyc8QETONSmN9A8lMx4mVbdx6s3BQUh2Ejj6kk7VJcbTSfmEI88LlKz 3FZRPXwJE8pzuIuNyd3Sl4NTvDCjlQoQub0fqtT5Kmb5MwZ1tS4e81hH678KSde9QCVQ qR08/z0MiMvFN2LR2KsifHIS5VIImMAJMPfwZU2eIEXu5lSvs4rtGGkyQI6skh7C8HZQ +YHw== X-Gm-Message-State: ACrzQf3D6QJu5wZNnGRohSdVVwQSnq+A0vLyrGUdg+bPH8ODmCnir9cx Gq6sC7wpZNHQXySEbzraJOEfsnTzRtu9TA== X-Google-Smtp-Source: AMsMyM66j0fMYuBSobolk0vYkJ0F/AS2BJ7dqsQ5czgvSbOxrxax0Pd0+TdIyvho2YMT1IclnPRSOg== X-Received: by 2002:a05:6214:1d21:b0:4ad:1361:befa with SMTP id f1-20020a0562141d2100b004ad1361befamr11050811qvd.111.1664641452096; Sat, 01 Oct 2022 09:24:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 20/42] target/arm: Use tlb_set_page_full Date: Sat, 1 Oct 2022 09:22:56 -0700 Message-Id: <20221001162318.153420-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2a; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664642974938100001 Content-Type: text/plain; charset="utf-8" Adjust GetPhysAddrResult to fill in CPUTLBEntryFull, so that it may be passed directly to tlb_set_page_full. The change is large, but mostly mechanical. The major non-mechanical change is page_size -> lg_page_size. Most of the time this is obvious, and is related to TARGET_PAGE_BITS. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 5 +- target/arm/helper.c | 12 +-- target/arm/m_helper.c | 20 ++--- target/arm/ptw.c | 181 ++++++++++++++++++++-------------------- target/arm/tlb_helper.c | 9 +- 5 files changed, 112 insertions(+), 115 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index b509d70851..fd17aee459 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1071,10 +1071,7 @@ typedef struct ARMCacheAttrs { =20 /* Fields that are valid upon success. */ typedef struct GetPhysAddrResult { - hwaddr phys; - target_ulong page_size; - int prot; - MemTxAttrs attrs; + CPUTLBEntryFull f; ARMCacheAttrs cacheattrs; } GetPhysAddrResult; =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 4eec22b1f8..6fe85c6642 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3320,8 +3320,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, /* Create a 64-bit PAR */ par64 =3D (1 << 11); /* LPAE bit always set */ if (!ret) { - par64 |=3D res.phys & ~0xfffULL; - if (!res.attrs.secure) { + par64 |=3D res.f.phys_addr & ~0xfffULL; + if (!res.f.attrs.secure) { par64 |=3D (1 << 9); /* NS */ } par64 |=3D (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */ @@ -3345,13 +3345,13 @@ static uint64_t do_ats_write(CPUARMState *env, uint= 64_t value, */ if (!ret) { /* We do not set any attribute bits in the PAR */ - if (res.page_size =3D=3D (1 << 24) + if (res.f.lg_page_size =3D=3D 24 && arm_feature(env, ARM_FEATURE_V7)) { - par64 =3D (res.phys & 0xff000000) | (1 << 1); + par64 =3D (res.f.phys_addr & 0xff000000) | (1 << 1); } else { - par64 =3D res.phys & 0xfffff000; + par64 =3D res.f.phys_addr & 0xfffff000; } - if (!res.attrs.secure) { + if (!res.f.attrs.secure) { par64 |=3D (1 << 9); /* NS */ } } else { diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 203ba411f6..355cd4d60a 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -223,8 +223,8 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr,= uint32_t value, } goto pend_fault; } - address_space_stl_le(arm_addressspace(cs, res.attrs), res.phys, value, - res.attrs, &txres); + address_space_stl_le(arm_addressspace(cs, res.f.attrs), res.f.phys_add= r, + value, res.f.attrs, &txres); if (txres !=3D MEMTX_OK) { /* BusFault trying to write the data */ if (mode =3D=3D STACK_LAZYFP) { @@ -298,8 +298,8 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest,= uint32_t addr, goto pend_fault; } =20 - value =3D address_space_ldl(arm_addressspace(cs, res.attrs), res.phys, - res.attrs, &txres); + value =3D address_space_ldl(arm_addressspace(cs, res.f.attrs), + res.f.phys_addr, res.f.attrs, &txres); if (txres !=3D MEMTX_OK) { /* BusFault trying to read the data */ qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n"); @@ -2022,8 +2022,8 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, bool secure, qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL= \n"); return false; } - *insn =3D address_space_lduw_le(arm_addressspace(cs, res.attrs), res.p= hys, - res.attrs, &txres); + *insn =3D address_space_lduw_le(arm_addressspace(cs, res.f.attrs), + res.f.phys_addr, res.f.attrs, &txres); if (txres !=3D MEMTX_OK) { env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_IBUSERR_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); @@ -2069,8 +2069,8 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMM= UIdx mmu_idx, } return false; } - value =3D address_space_ldl(arm_addressspace(cs, res.attrs), res.phys, - res.attrs, &txres); + value =3D address_space_ldl(arm_addressspace(cs, res.f.attrs), + res.f.phys_addr, res.f.attrs, &txres); if (txres !=3D MEMTX_OK) { /* BusFault trying to read the data */ qemu_log_mask(CPU_LOG_INT, @@ -2817,8 +2817,8 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t ad= dr, uint32_t op) } else { mrvalid =3D true; } - r =3D res.prot & PAGE_READ; - rw =3D res.prot & PAGE_WRITE; + r =3D res.f.prot & PAGE_READ; + rw =3D res.f.prot & PAGE_WRITE; } else { r =3D false; rw =3D false; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8d27a98a42..1bc194ffa1 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -256,7 +256,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, assert(!is_secure); } =20 - addr =3D s2.phys; + addr =3D s2.f.phys_addr; } return addr; } @@ -476,7 +476,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, /* 1Mb section. */ phys_addr =3D (desc & 0xfff00000) | (address & 0x000fffff); ap =3D (desc >> 10) & 3; - result->page_size =3D 1024 * 1024; + result->f.lg_page_size =3D 20; /* 1MB */ } else { /* Lookup l2 entry. */ if (type =3D=3D 1) { @@ -497,12 +497,12 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32= _t address, case 1: /* 64k page. */ phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); ap =3D (desc >> (4 + ((address >> 13) & 6))) & 3; - result->page_size =3D 0x10000; + result->f.lg_page_size =3D 16; break; case 2: /* 4k page. */ phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); ap =3D (desc >> (4 + ((address >> 9) & 6))) & 3; - result->page_size =3D 0x1000; + result->f.lg_page_size =3D 12; break; case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ if (type =3D=3D 1) { @@ -510,7 +510,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, if (arm_feature(env, ARM_FEATURE_XSCALE) || arm_feature(env, ARM_FEATURE_V6)) { phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); - result->page_size =3D 0x1000; + result->f.lg_page_size =3D 12; } else { /* * UNPREDICTABLE in ARMv5; we choose to take a @@ -521,7 +521,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, } } else { phys_addr =3D (desc & 0xfffffc00) | (address & 0x3ff); - result->page_size =3D 0x400; + result->f.lg_page_size =3D 10; } ap =3D (desc >> 4) & 3; break; @@ -530,14 +530,14 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32= _t address, g_assert_not_reached(); } } - result->prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); - result->prot |=3D result->prot ? PAGE_EXEC : 0; - if (!(result->prot & (1 << access_type))) { + result->f.prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + result->f.prot |=3D result->f.prot ? PAGE_EXEC : 0; + if (!(result->f.prot & (1 << access_type))) { /* Access permission fault. */ fi->type =3D ARMFault_Permission; goto do_fault; } - result->phys =3D phys_addr; + result->f.phys_addr =3D phys_addr; return false; do_fault: fi->domain =3D domain; @@ -607,11 +607,11 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, phys_addr =3D (desc & 0xff000000) | (address & 0x00ffffff); phys_addr |=3D (uint64_t)extract32(desc, 20, 4) << 32; phys_addr |=3D (uint64_t)extract32(desc, 5, 4) << 36; - result->page_size =3D 0x1000000; + result->f.lg_page_size =3D 24; /* 16MB */ } else { /* Section. */ phys_addr =3D (desc & 0xfff00000) | (address & 0x000fffff); - result->page_size =3D 0x100000; + result->f.lg_page_size =3D 20; /* 1MB */ } ap =3D ((desc >> 10) & 3) | ((desc >> 13) & 4); xn =3D desc & (1 << 4); @@ -636,12 +636,12 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, case 1: /* 64k page. */ phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); xn =3D desc & (1 << 15); - result->page_size =3D 0x10000; + result->f.lg_page_size =3D 16; break; case 2: case 3: /* 4k page. */ phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); xn =3D desc & 1; - result->page_size =3D 0x1000; + result->f.lg_page_size =3D 12; break; default: /* Never happens, but compiler isn't smart enough to tell. */ @@ -649,7 +649,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, } } if (domain_prot =3D=3D 3) { - result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->f.prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; } else { if (pxn && !regime_is_user(env, mmu_idx)) { xn =3D 1; @@ -667,14 +667,14 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, fi->type =3D ARMFault_AccessFlag; goto do_fault; } - result->prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); + result->f.prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); } else { - result->prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + result->f.prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot= ); } - if (result->prot && !xn) { - result->prot |=3D PAGE_EXEC; + if (result->f.prot && !xn) { + result->f.prot |=3D PAGE_EXEC; } - if (!(result->prot & (1 << access_type))) { + if (!(result->f.prot & (1 << access_type))) { /* Access permission fault. */ fi->type =3D ARMFault_Permission; goto do_fault; @@ -685,9 +685,9 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, * the CPU doesn't support TZ or this is a non-secure translation * regime, because the attribute will already be non-secure. */ - result->attrs.secure =3D false; + result->f.attrs.secure =3D false; } - result->phys =3D phys_addr; + result->f.phys_addr =3D phys_addr; return false; do_fault: fi->domain =3D domain; @@ -1298,16 +1298,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { ns =3D mmu_idx =3D=3D ARMMMUIdx_Stage2; xn =3D extract32(attrs, 11, 2); - result->prot =3D get_S2prot(env, ap, xn, s1_is_el0); + result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); } else { ns =3D extract32(attrs, 3, 1); xn =3D extract32(attrs, 12, 1); pxn =3D extract32(attrs, 11, 1); - result->prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn= ); + result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, p= xn); } =20 fault_type =3D ARMFault_Permission; - if (!(result->prot & (1 << access_type))) { + if (!(result->f.prot & (1 << access_type))) { goto do_fault; } =20 @@ -1317,11 +1317,11 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, * the CPU doesn't support TZ or this is a non-secure translation * regime, because the attribute will already be non-secure. */ - result->attrs.secure =3D false; + result->f.attrs.secure =3D false; } /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB.= */ if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { - arm_tlb_bti_gp(&result->attrs) =3D true; + arm_tlb_bti_gp(&result->f.attrs) =3D true; } =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { @@ -1347,8 +1347,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, result->cacheattrs.shareability =3D extract32(attrs, 6, 2); } =20 - result->phys =3D descaddr; - result->page_size =3D page_size; + result->f.phys_addr =3D descaddr; + result->f.lg_page_size =3D ctz64(page_size); return false; =20 do_fault: @@ -1373,12 +1373,12 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, =20 if (regime_translation_disabled(env, mmu_idx, is_secure)) { /* MPU disabled. */ - result->phys =3D address; - result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->f.phys_addr =3D address; + result->f.prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return false; } =20 - result->phys =3D address; + result->f.phys_addr =3D address; for (n =3D 7; n >=3D 0; n--) { base =3D env->cp15.c6_region[n]; if ((base & 1) =3D=3D 0) { @@ -1414,16 +1414,16 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, fi->level =3D 1; return true; } - result->prot =3D PAGE_READ | PAGE_WRITE; + result->f.prot =3D PAGE_READ | PAGE_WRITE; break; case 2: - result->prot =3D PAGE_READ; + result->f.prot =3D PAGE_READ; if (!is_user) { - result->prot |=3D PAGE_WRITE; + result->f.prot |=3D PAGE_WRITE; } break; case 3: - result->prot =3D PAGE_READ | PAGE_WRITE; + result->f.prot =3D PAGE_READ | PAGE_WRITE; break; case 5: if (is_user) { @@ -1431,10 +1431,10 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, fi->level =3D 1; return true; } - result->prot =3D PAGE_READ; + result->f.prot =3D PAGE_READ; break; case 6: - result->prot =3D PAGE_READ; + result->f.prot =3D PAGE_READ; break; default: /* Bad permission. */ @@ -1442,12 +1442,12 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, fi->level =3D 1; return true; } - result->prot |=3D PAGE_EXEC; + result->f.prot |=3D PAGE_EXEC; return false; } =20 static void get_phys_addr_pmsav7_default(CPUARMState *env, ARMMMUIdx mmu_i= dx, - int32_t address, int *prot) + int32_t address, uint8_t *prot) { if (!arm_feature(env, ARM_FEATURE_M)) { *prot =3D PAGE_READ | PAGE_WRITE; @@ -1531,9 +1531,9 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, int n; bool is_user =3D regime_is_user(env, mmu_idx); =20 - result->phys =3D address; - result->page_size =3D TARGET_PAGE_SIZE; - result->prot =3D 0; + result->f.phys_addr =3D address; + result->f.lg_page_size =3D TARGET_PAGE_BITS; + result->f.prot =3D 0; =20 if (regime_translation_disabled(env, mmu_idx, secure) || m_is_ppb_region(env, address)) { @@ -1545,7 +1545,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, * which always does a direct read using address_space_ldl(), rath= er * than going via this function, so we don't need to check that he= re. */ - get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot); + get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.pro= t); } else { /* MPU enabled */ for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { /* region search */ @@ -1587,7 +1587,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, if (ranges_overlap(base, rmask, address & TARGET_PAGE_MASK, TARGET_PAGE_SIZE)) { - result->page_size =3D 1; + result->f.lg_page_size =3D 0; } continue; } @@ -1625,7 +1625,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, continue; } if (rsize < TARGET_PAGE_BITS) { - result->page_size =3D 1 << rsize; + result->f.lg_page_size =3D rsize; } break; } @@ -1636,7 +1636,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, fi->type =3D ARMFault_Background; return true; } - get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->p= rot); + get_phys_addr_pmsav7_default(env, mmu_idx, address, + &result->f.prot); } else { /* a MPU hit! */ uint32_t ap =3D extract32(env->pmsav7.dracr[n], 8, 3); uint32_t xn =3D extract32(env->pmsav7.dracr[n], 12, 1); @@ -1653,16 +1654,16 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, case 5: break; /* no access */ case 3: - result->prot |=3D PAGE_WRITE; + result->f.prot |=3D PAGE_WRITE; /* fall through */ case 2: case 6: - result->prot |=3D PAGE_READ | PAGE_EXEC; + result->f.prot |=3D PAGE_READ | PAGE_EXEC; break; case 7: /* for v7M, same as 6; for R profile a reserved value = */ if (arm_feature(env, ARM_FEATURE_M)) { - result->prot |=3D PAGE_READ | PAGE_EXEC; + result->f.prot |=3D PAGE_READ | PAGE_EXEC; break; } /* fall through */ @@ -1678,16 +1679,16 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, case 1: case 2: case 3: - result->prot |=3D PAGE_WRITE; + result->f.prot |=3D PAGE_WRITE; /* fall through */ case 5: case 6: - result->prot |=3D PAGE_READ | PAGE_EXEC; + result->f.prot |=3D PAGE_READ | PAGE_EXEC; break; case 7: /* for v7M, same as 6; for R profile a reserved value = */ if (arm_feature(env, ARM_FEATURE_M)) { - result->prot |=3D PAGE_READ | PAGE_EXEC; + result->f.prot |=3D PAGE_READ | PAGE_EXEC; break; } /* fall through */ @@ -1700,14 +1701,14 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, =20 /* execute never */ if (xn) { - result->prot &=3D ~PAGE_EXEC; + result->f.prot &=3D ~PAGE_EXEC; } } } =20 fi->type =3D ARMFault_Permission; fi->level =3D 1; - return !(result->prot & (1 << access_type)); + return !(result->f.prot & (1 << access_type)); } =20 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, @@ -1733,9 +1734,9 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, uint32_t addr_page_base =3D address & TARGET_PAGE_MASK; uint32_t addr_page_limit =3D addr_page_base + (TARGET_PAGE_SIZE - 1); =20 - result->page_size =3D TARGET_PAGE_SIZE; - result->phys =3D address; - result->prot =3D 0; + result->f.lg_page_size =3D TARGET_PAGE_BITS; + result->f.phys_addr =3D address; + result->f.prot =3D 0; if (mregion) { *mregion =3D -1; } @@ -1785,13 +1786,13 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, ranges_overlap(base, limit - base + 1, addr_page_base, TARGET_PAGE_SIZE)) { - result->page_size =3D 1; + result->f.lg_page_size =3D 0; } continue; } =20 if (base > addr_page_base || limit < addr_page_limit) { - result->page_size =3D 1; + result->f.lg_page_size =3D 0; } =20 if (matchregion !=3D -1) { @@ -1817,7 +1818,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, =20 if (matchregion =3D=3D -1) { /* hit using the background region */ - get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot); + get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.pro= t); } else { uint32_t ap =3D extract32(env->pmsav8.rbar[secure][matchregion], 1= , 2); uint32_t xn =3D extract32(env->pmsav8.rbar[secure][matchregion], 0= , 1); @@ -1832,9 +1833,9 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, xn =3D 1; } =20 - result->prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); - if (result->prot && !xn && !(pxn && !is_user)) { - result->prot |=3D PAGE_EXEC; + result->f.prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); + if (result->f.prot && !xn && !(pxn && !is_user)) { + result->f.prot |=3D PAGE_EXEC; } /* * We don't need to look the attribute up in the MAIR0/MAIR1 @@ -1847,7 +1848,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, =20 fi->type =3D ARMFault_Permission; fi->level =3D 1; - return !(result->prot & (1 << access_type)); + return !(result->f.prot & (1 << access_type)); } =20 static bool v8m_is_sau_exempt(CPUARMState *env, @@ -2011,9 +2012,9 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, } else { fi->type =3D ARMFault_QEMU_SFault; } - result->page_size =3D sattrs.subpage ? 1 : TARGET_PAGE_SIZ= E; - result->phys =3D address; - result->prot =3D 0; + result->f.lg_page_size =3D sattrs.subpage ? 0 : TARGET_PAG= E_BITS; + result->f.phys_addr =3D address; + result->f.prot =3D 0; return true; } } else { @@ -2023,7 +2024,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, * might downgrade a secure access to nonsecure. */ if (sattrs.ns) { - result->attrs.secure =3D false; + result->f.attrs.secure =3D false; } else if (!secure) { /* * NS access to S memory must fault. @@ -2036,9 +2037,9 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). */ fi->type =3D ARMFault_QEMU_SFault; - result->page_size =3D sattrs.subpage ? 1 : TARGET_PAGE_SIZ= E; - result->phys =3D address; - result->prot =3D 0; + result->f.lg_page_size =3D sattrs.subpage ? 0 : TARGET_PAG= E_BITS; + result->f.phys_addr =3D address; + result->f.prot =3D 0; return true; } } @@ -2047,7 +2048,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, ret =3D pmsav8_mpu_lookup(env, address, access_type, mmu_idx, secure, result, fi, NULL); if (sattrs.subpage) { - result->page_size =3D 1; + result->f.lg_page_size =3D 0; } return ret; } @@ -2338,9 +2339,9 @@ static bool get_phys_addr_disabled(CPUARMState *env, = target_ulong address, result->cacheattrs.is_s2_format =3D false; } =20 - result->phys =3D address; - result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - result->page_size =3D TARGET_PAGE_SIZE; + result->f.phys_addr =3D address; + result->f.prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->f.lg_page_size =3D TARGET_PAGE_BITS; result->cacheattrs.shareability =3D shareability; result->cacheattrs.attrs =3D memattr; return 0; @@ -2377,8 +2378,8 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, return ret; } =20 - ipa =3D result->phys; - ipa_secure =3D result->attrs.secure; + ipa =3D result->f.phys_addr; + ipa_secure =3D result->f.attrs.secure; if (is_secure) { /* Select TCR based on the NS bit from the S1 walk. */ s2walk_secure =3D !(ipa_secure @@ -2398,7 +2399,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, * Save the stage1 results so that we may merge * prot and cacheattrs later. */ - s1_prot =3D result->prot; + s1_prot =3D result->f.prot; cacheattrs1 =3D result->cacheattrs; memset(result, 0, sizeof(*result)); =20 @@ -2407,7 +2408,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ - result->prot &=3D s1_prot; + result->f.prot &=3D s1_prot; =20 /* If S2 fails, return early. */ if (ret) { @@ -2435,10 +2436,10 @@ bool get_phys_addr_with_secure(CPUARMState *env, ta= rget_ulong address, /* Check if IPA translates to secure or non-secure PA space. */ if (is_secure) { if (ipa_secure) { - result->attrs.secure =3D + result->f.attrs.secure =3D !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)); } else { - result->attrs.secure =3D + result->f.attrs.secure =3D !((env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)) || (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))); } @@ -2457,8 +2458,8 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, * cannot upgrade an non-secure translation regime's attributes * to secure. */ - result->attrs.secure =3D is_secure; - result->attrs.user =3D regime_is_user(env, mmu_idx); + result->f.attrs.secure =3D is_secure; + result->f.attrs.user =3D regime_is_user(env, mmu_idx); =20 /* * Fast Context Switch Extension. This doesn't exist at all in v8. @@ -2475,7 +2476,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, =20 if (arm_feature(env, ARM_FEATURE_PMSA)) { bool ret; - result->page_size =3D TARGET_PAGE_SIZE; + result->f.lg_page_size =3D TARGET_PAGE_BITS; =20 if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ @@ -2496,9 +2497,9 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, (access_type =3D=3D MMU_DATA_STORE ? "writing" : "ex= ecute"), (uint32_t)address, mmu_idx, ret ? "Miss" : "Hit", - result->prot & PAGE_READ ? 'r' : '-', - result->prot & PAGE_WRITE ? 'w' : '-', - result->prot & PAGE_EXEC ? 'x' : '-'); + result->f.prot & PAGE_READ ? 'r' : '-', + result->f.prot & PAGE_WRITE ? 'w' : '-', + result->f.prot & PAGE_EXEC ? 'x' : '-'); =20 return ret; } @@ -2573,10 +2574,10 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *= cs, vaddr addr, bool ret; =20 ret =3D get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi); - *attrs =3D res.attrs; + *attrs =3D res.f.attrs; =20 if (ret) { return -1; } - return res.phys; + return res.f.phys_addr; } diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index ad225b1cb2..49601394ec 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -227,17 +227,16 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, * target page size are handled specially, so for those we * pass in the exact addresses. */ - if (res.page_size >=3D TARGET_PAGE_SIZE) { - res.phys &=3D TARGET_PAGE_MASK; + if (res.f.lg_page_size >=3D TARGET_PAGE_BITS) { + res.f.phys_addr &=3D TARGET_PAGE_MASK; address &=3D TARGET_PAGE_MASK; } /* Notice and record tagged memory. */ if (cpu_isar_feature(aa64_mte, cpu) && res.cacheattrs.attrs =3D=3D= 0xf0) { - arm_tlb_mte_tagged(&res.attrs) =3D true; + arm_tlb_mte_tagged(&res.f.attrs) =3D true; } =20 - tlb_set_page_with_attrs(cs, address, res.phys, res.attrs, - res.prot, mmu_idx, res.page_size); + tlb_set_page_full(cs, mmu_idx, address, &res.f); return true; } else if (probe) { return false; --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664643419; cv=none; d=zohomail.com; s=zohoarc; b=ZxD42r0ghdm6mGOFQ0Hkrs6bMb/vqRcAW7Q3aqPIaBVrmVirFSG/g9XYWVgeMBX6yRgKC2ovmx0GvYcebcWxs+40rwB/FObjSEQX1p3vFXUrNu8w28sPcLGBuwPTgMxCrD2SZYgpod6OcfK6bdOvtsL/6N26Kw34UgBDsgQSkMk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664643419; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ue9Nl0D44aZHstGkTsjwRG+rtSs9n3MbvqWOGp6wdbM=; b=K9+53d6qkfphWtP31GIFxk0ycIPbY7PQI26QICMjsDpf1sOkjGfYOZ6eS4zbv3xuTgyz1W5CaR9Z//2mjKA6sHX1QHWK9XuTJhACQhihILsWfoZiRREoww0LyuHxfczSApO7Ap6vH7sV3vexfN5xDnP0Bgxk5g/H8NDyABoAcNM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664643419567342.82893212016165; Sat, 1 Oct 2022 09:56:59 -0700 (PDT) Received: from localhost ([::1]:49728 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefnO-0004V0-L1 for importer@patchew.org; Sat, 01 Oct 2022 12:56:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56072) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefHl-0006y7-GI for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:17 -0400 Received: from mail-qk1-x729.google.com ([2607:f8b0:4864:20::729]:34404) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefHj-0006F8-1h for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:16 -0400 Received: by mail-qk1-x729.google.com with SMTP id g2so4549116qkk.1 for ; Sat, 01 Oct 2022 09:24:14 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=Ue9Nl0D44aZHstGkTsjwRG+rtSs9n3MbvqWOGp6wdbM=; b=V4GNfkahZI+n5FLCJ4JJehf9MHqoVFM1H9B45TSFxJpg3iKrJbqbHDfB82xbHbMGum EMF1JAFBNg0cg887Scb5FhQNohpUyXzBSzFRJG33GoYOqOlTCZLVjp0Y9lmFqiaur03C fqOCJiKMB0U9N8hBS74hz87DBz789ujSSr3NFSoPQXmh/00DBt2PY8+RuAqm8FMy8D+a ft6JTaFlAdwaeScjjeR01Rxq7uQDOaSJuXltWP9Bh5IjqpXaTcD6PdJ4kUKMokgMg38U Faiq0u+O6maan2RGqn5rAfvgeeztPTouWsg1QX6aPE2Si+q7KuMXM9zJvtvQWDetUKA0 c6MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=Ue9Nl0D44aZHstGkTsjwRG+rtSs9n3MbvqWOGp6wdbM=; b=zD9SluN28mm6OASuFQ4bcZYsoUB4WVFPughf3lvJWJkfDAVbdy+RuwM0yPAUIkz7A/ hROsifP1y8LN1D+rZ4P3zl9q52NcruuptSRIEIKNbdlkHCBZNQvM9XozY+ubT+OBhsC8 PHjkbLdcH/oHG7NNDnA4qV91BcIADsd4h55jrOFNAQvygWuEMXfKA0pTMXlbFnLzQYb5 d22c83TVfTZmQkBloNy5bi968y/kglj1VvvoAIrsLZXgdcTb/fo6YlmqmgoI0cgfh1tq xWFi5EHchGBZxxv6TrtBg1ACVTHBbhfr7SqdnRHEsyexRjiEWAuU9nv0PIAsst2P3LiI 4Xgg== X-Gm-Message-State: ACrzQf0Xkocp50WCvtQ9o3ofOicadAGfvkcAt+HdvbS+vXF/uQXUnMeC CO7KyooHJbrf8/oe5I6h/l582piZCXrcjg== X-Google-Smtp-Source: AMsMyM7DLin52W4mHlBDXtEXGoUHprLie5YzmQHXsukNB+899No0wb63LaT9HzOn4v1/p+1NyfxD3w== X-Received: by 2002:a37:c443:0:b0:6ce:191a:bb60 with SMTP id h3-20020a37c443000000b006ce191abb60mr9578844qkm.53.1664641454395; Sat, 01 Oct 2022 09:24:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 21/42] target/arm: Enable TARGET_PAGE_ENTRY_EXTRA Date: Sat, 1 Oct 2022 09:22:57 -0700 Message-Id: <20221001162318.153420-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::729; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x729.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664643420409100001 Content-Type: text/plain; charset="utf-8" Copy attrs and sharability, into the TLB. This will eventually be used by S1_ptw_translate to report stage1 translation failures, and by do_ats_write to fill in PAR_EL1. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu-param.h | 8 ++++++++ target/arm/tlb_helper.c | 3 +++ 2 files changed, 11 insertions(+) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 08681828ac..118ca0e5c0 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -30,6 +30,14 @@ */ # define TARGET_PAGE_BITS_VARY # define TARGET_PAGE_BITS_MIN 10 + +/* + * Cache the attrs and sharability fields from the page table entry. + */ +# define TARGET_PAGE_ENTRY_EXTRA \ + uint8_t pte_attrs; \ + uint8_t shareability; + #endif =20 #define NB_MMU_MODES 8 diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 49601394ec..353edbeb1d 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -236,6 +236,9 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, arm_tlb_mte_tagged(&res.f.attrs) =3D true; } =20 + res.f.pte_attrs =3D res.cacheattrs.attrs; + res.f.shareability =3D res.cacheattrs.shareability; + tlb_set_page_full(cs, mmu_idx, address, &res.f); return true; } else if (probe) { --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664643559; cv=none; d=zohomail.com; s=zohoarc; b=Db4q58LR9SlffX7ruOJB7d/4xcaqUzs5vEsVM5MTk/5Tp1CimtdaJXTuo+fyefpXZvtF0EnrvTpqp0Tdr6DIefwMGG67aMezpIB5lh9HEGv6wQaYxrehYG7Sj5Fh5ms9hjLPfMvBCapo6NhFLb13QSxRlm4KSJa0eyabqkWxNP4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664643559; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+/MYc5jaf3Cn9sR9s34xhVh/NsLcIfsDyp8ApkijnX0=; b=MEuUsOzGaz8yLHZ00PmAg6ch8zg/bgqqN2UW+tKm3LZErJjBjDL2UhafRWcCw/0Aym9rjMHjEdu1fD494ic5xZPlkBT6EJBfHKfPyTiwWVwvYg5r6OVw9PkxINIX3gXcsY5xcdPaEPYFKfoYecYd/2eG873CmZcS7W3Wj+0EUMQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664643559366148.82905343658956; Sat, 1 Oct 2022 09:59:19 -0700 (PDT) Received: from localhost ([::1]:53150 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefpe-0000lT-9w for importer@patchew.org; Sat, 01 Oct 2022 12:59:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56078) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefHo-0007Aa-7t for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:20 -0400 Received: from mail-qv1-xf2b.google.com ([2607:f8b0:4864:20::f2b]:39765) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefHm-0006Ky-40 for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:19 -0400 Received: by mail-qv1-xf2b.google.com with SMTP id z18so4439615qvn.6 for ; Sat, 01 Oct 2022 09:24:17 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=+/MYc5jaf3Cn9sR9s34xhVh/NsLcIfsDyp8ApkijnX0=; b=Tm5usSr5fFSdGe44W283+sl7FvcrJUixQ+xZ0ckFjGtYXT87ZhnVnyTiqMhtLui4or jJYyJYU1cofxeIEvntcoJqLprCn+E3+1J9S4VrdMPBohnLFtchx+OxSOq4k8+vjPZEBv /Y4U32Pe9llzWSyjovpdwX+Bm59mZ6F12EG5pqGyrkw1A+HZjuqxL2AXo0Ti4+acdJPy h4VjrNCmc0wYGrb6XyO1cB3ccfscz78Pk+iqbMZTg/HK8+54m04PFPnxyxVzbPPZ2i0q /zG9hpXcNu3sPaGY4HJ35f8gwpymbjKZsxpf/9YwJLsek7MnYNUnEOHq0hssYEkeDXO0 oQsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=+/MYc5jaf3Cn9sR9s34xhVh/NsLcIfsDyp8ApkijnX0=; b=jhgXvCWgvcUZ3Kl4VvuEov1quqMq7RmqPNVzZivOojL+NiorcArS+EGkyiQRrSnJro nGBbuPZ1FWs/ktfOlNSrpmcAO0UOyTUvA6oqB+OqSbywism8jSpgs3WB1YLAjIQdNcQF dpSa1F2fmSEhmDTux9mimS03S/a+E9x2k330Y4FOQpmz45W+HUVhnly8dHtNk7sq8Rj4 hGY2iDcd2cpfA99/9LqGiwPzMpjDHXuEf/gf1QHJv4LvPHs0YqTeA+J6F94n5dIO+QAL BgGawhQgX3oiGxlE6Zl0jjZQ/4lV1yy/TvlNOxW9xeSGflQWbARQpPo4RIhbRuyjQFIW hNZQ== X-Gm-Message-State: ACrzQf23tsEkg4APHktheaTruLPwh2X1bU5hB/4iSfLbznjO4qrJpaoj WCipFsPs+F2OoDwdGTCEGR7NdTgBGWtaCw== X-Google-Smtp-Source: AMsMyM5INScgMLoU9wOQjVVIwz7EzcC2F4+d4PJYJvhpT9Lsv5IJ4lFYyP8SjaYyFKb01hgTlpM0bw== X-Received: by 2002:a05:6214:2121:b0:4af:9418:ac4b with SMTP id r1-20020a056214212100b004af9418ac4bmr11472124qvc.30.1664641457051; Sat, 01 Oct 2022 09:24:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 22/42] target/arm: Use probe_access_full for MTE Date: Sat, 1 Oct 2022 09:22:58 -0700 Message-Id: <20221001162318.153420-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2b; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664643560797100001 Content-Type: text/plain; charset="utf-8" The CPUTLBEntryFull structure now stores the original pte attributes, as well as the physical address. Therefore, we no longer need a separate bit in MemTxAttrs, nor do we need to walk the tree of memory regions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 1 - target/arm/sve_ldst_internal.h | 1 + target/arm/mte_helper.c | 61 +++++++++------------------------- target/arm/sve_helper.c | 54 ++++++++++-------------------- target/arm/tlb_helper.c | 4 --- 5 files changed, 35 insertions(+), 86 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0f82f4aa1d..2694a93894 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3394,7 +3394,6 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxA= ttrs *x) * generic target bits directly. */ #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) -#define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) =20 /* * AArch64 usage of the PAGE_TARGET_* bits for linux-user. diff --git a/target/arm/sve_ldst_internal.h b/target/arm/sve_ldst_internal.h index b5c473fc48..4f159ec4ad 100644 --- a/target/arm/sve_ldst_internal.h +++ b/target/arm/sve_ldst_internal.h @@ -134,6 +134,7 @@ typedef struct { void *host; int flags; MemTxAttrs attrs; + bool tagged; } SVEHostPage; =20 bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env, diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index fdd23ab3f8..a81c4a3318 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -105,10 +105,9 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, i= nt ptr_mmu_idx, TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); return tags + index; #else - uintptr_t index; CPUTLBEntryFull *full; + MemTxAttrs attrs; int in_page, flags; - ram_addr_t ptr_ra; hwaddr ptr_paddr, tag_paddr, xlat; MemoryRegion *mr; ARMASIdx tag_asi; @@ -124,30 +123,12 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, = int ptr_mmu_idx, * valid. Indicate to probe_access_flags no-fault, then assert that * we received a valid page. */ - flags =3D probe_access_flags(env, ptr, ptr_access, ptr_mmu_idx, - ra =3D=3D 0, &host, ra); + flags =3D probe_access_full(env, ptr, ptr_access, ptr_mmu_idx, + ra =3D=3D 0, &host, &full, ra); assert(!(flags & TLB_INVALID_MASK)); =20 - /* - * Find the CPUTLBEntryFull for ptr. This *must* be present in the TLB - * because we just found the mapping. - * TODO: Perhaps there should be a cputlb helper that returns a - * matching tlb entry + iotlb entry. - */ - index =3D tlb_index(env, ptr_mmu_idx, ptr); -# ifdef CONFIG_DEBUG_TCG - { - CPUTLBEntry *entry =3D tlb_entry(env, ptr_mmu_idx, ptr); - target_ulong comparator =3D (ptr_access =3D=3D MMU_DATA_LOAD - ? entry->addr_read - : tlb_addr_write(entry)); - g_assert(tlb_hit(comparator, ptr)); - } -# endif - full =3D &env_tlb(env)->d[ptr_mmu_idx].fulltlb[index]; - /* If the virtual page MemAttr !=3D Tagged, access unchecked. */ - if (!arm_tlb_mte_tagged(&full->attrs)) { + if (full->pte_attrs !=3D 0xf0) { return NULL; } =20 @@ -162,6 +143,13 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, i= nt ptr_mmu_idx, return NULL; } =20 + /* + * Remember these values across the second lookup below, + * which may invalidate this pointer via tlb resize. + */ + ptr_paddr =3D full->phys_addr; + attrs =3D full->attrs; + /* * The Normal memory access can extend to the next page. E.g. a single * 8-byte access to the last byte of a page will check only the last @@ -170,9 +158,8 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, */ in_page =3D -(ptr | TARGET_PAGE_MASK); if (unlikely(ptr_size > in_page)) { - void *ignore; - flags |=3D probe_access_flags(env, ptr + in_page, ptr_access, - ptr_mmu_idx, ra =3D=3D 0, &ignore, ra); + flags |=3D probe_access_full(env, ptr + in_page, ptr_access, + ptr_mmu_idx, ra =3D=3D 0, &host, &full,= ra); assert(!(flags & TLB_INVALID_MASK)); } =20 @@ -180,33 +167,17 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, = int ptr_mmu_idx, if (unlikely(flags & TLB_WATCHPOINT)) { int wp =3D ptr_access =3D=3D MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_= WRITE; assert(ra !=3D 0); - cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, - full->attrs, wp, ra); + cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, attrs, wp, ra); } =20 - /* - * Find the physical address within the normal mem space. - * The memory region lookup must succeed because TLB_MMIO was - * not set in the cputlb lookup above. - */ - mr =3D memory_region_from_host(host, &ptr_ra); - tcg_debug_assert(mr !=3D NULL); - tcg_debug_assert(memory_region_is_ram(mr)); - ptr_paddr =3D ptr_ra; - do { - ptr_paddr +=3D mr->addr; - mr =3D mr->container; - } while (mr); - /* Convert to the physical address in tag space. */ tag_paddr =3D ptr_paddr >> (LOG2_TAG_GRANULE + 1); =20 /* Look up the address in tag space. */ - tag_asi =3D full->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; + tag_asi =3D attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; tag_as =3D cpu_get_address_space(env_cpu(env), tag_asi); mr =3D address_space_translate(tag_as, tag_paddr, &xlat, NULL, - tag_access =3D=3D MMU_DATA_STORE, - full->attrs); + tag_access =3D=3D MMU_DATA_STORE, attrs); =20 /* * Note that @mr will never be NULL. If there is nothing in the addre= ss diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 9cae8fd352..3d0d2987cd 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -5351,8 +5351,19 @@ bool sve_probe_page(SVEHostPage *info, bool nofault,= CPUARMState *env, */ addr =3D useronly_clean_ptr(addr); =20 +#ifdef CONFIG_USER_ONLY flags =3D probe_access_flags(env, addr, access_type, mmu_idx, nofault, &info->host, retaddr); + memset(&info->attrs, 0, sizeof(info->attrs)); + /* Require both ANON and MTE; see allocation_tag_mem(). */ + info->tagged =3D (flags & PAGE_ANON) && (flags & PAGE_MTE); +#else + CPUTLBEntryFull *full; + flags =3D probe_access_full(env, addr, access_type, mmu_idx, nofault, + &info->host, &full, retaddr); + info->attrs =3D full->attrs; + info->tagged =3D full->pte_attrs =3D=3D 0xf0; +#endif info->flags =3D flags; =20 if (flags & TLB_INVALID_MASK) { @@ -5362,33 +5373,6 @@ bool sve_probe_page(SVEHostPage *info, bool nofault,= CPUARMState *env, =20 /* Ensure that info->host[] is relative to addr, not addr + mem_off. */ info->host -=3D mem_off; - -#ifdef CONFIG_USER_ONLY - memset(&info->attrs, 0, sizeof(info->attrs)); - /* Require both MAP_ANON and PROT_MTE -- see allocation_tag_mem. */ - arm_tlb_mte_tagged(&info->attrs) =3D - (flags & PAGE_ANON) && (flags & PAGE_MTE); -#else - /* - * Find the iotlbentry for addr and return the transaction attributes. - * This *must* be present in the TLB because we just found the mapping. - */ - { - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - -# ifdef CONFIG_DEBUG_TCG - CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong comparator =3D (access_type =3D=3D MMU_DATA_LOAD - ? entry->addr_read - : tlb_addr_write(entry)); - g_assert(tlb_hit(comparator, addr)); -# endif - - CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; - info->attrs =3D full->attrs; - } -#endif - return true; } =20 @@ -5617,7 +5601,7 @@ void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUAR= MState *env, intptr_t mem_off, reg_off, reg_last; =20 /* Process the page only if MemAttr =3D=3D Tagged. */ - if (arm_tlb_mte_tagged(&info->page[0].attrs)) { + if (info->page[0].tagged) { mem_off =3D info->mem_off_first[0]; reg_off =3D info->reg_off_first[0]; reg_last =3D info->reg_off_split; @@ -5638,7 +5622,7 @@ void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUAR= MState *env, } =20 mem_off =3D info->mem_off_first[1]; - if (mem_off >=3D 0 && arm_tlb_mte_tagged(&info->page[1].attrs)) { + if (mem_off >=3D 0 && info->page[1].tagged) { reg_off =3D info->reg_off_first[1]; reg_last =3D info->reg_off_last[1]; =20 @@ -6017,7 +6001,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const = target_ulong addr, * Disable MTE checking if the Tagged bit is not set. Since TBI must * be set within MTEDESC for MTE, !mtedesc =3D> !mte_active. */ - if (!arm_tlb_mte_tagged(&info.page[0].attrs)) { + if (!info.page[0].tagged) { mtedesc =3D 0; } =20 @@ -6568,7 +6552,7 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *= vg, void *vm, cpu_check_watchpoint(env_cpu(env), addr, msize, info.attrs, BP_MEM_READ, reta= ddr); } - if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { + if (mtedesc && info.tagged) { mte_check(env, mtedesc, addr, retaddr); } if (unlikely(info.flags & TLB_MMIO)) { @@ -6585,7 +6569,7 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *= vg, void *vm, msize, info.attrs, BP_MEM_READ, retaddr); } - if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { + if (mtedesc && info.tagged) { mte_check(env, mtedesc, addr, retaddr); } tlb_fn(env, &scratch, reg_off, addr, retaddr); @@ -6786,9 +6770,7 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t= *vg, void *vm, (env_cpu(env), addr, msize) & BP_MEM_READ)) { goto fault; } - if (mtedesc && - arm_tlb_mte_tagged(&info.attrs) && - !mte_probe(env, mtedesc, addr)) { + if (mtedesc && info.tagged && !mte_probe(env, mtedesc, add= r)) { goto fault; } =20 @@ -6974,7 +6956,7 @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *= vg, void *vm, info.attrs, BP_MEM_WRITE, retaddr= ); } =20 - if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { + if (mtedesc && info.tagged) { mte_check(env, mtedesc, addr, retaddr); } } diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 353edbeb1d..3462a6ea14 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -231,10 +231,6 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, res.f.phys_addr &=3D TARGET_PAGE_MASK; address &=3D TARGET_PAGE_MASK; } - /* Notice and record tagged memory. */ - if (cpu_isar_feature(aa64_mte, cpu) && res.cacheattrs.attrs =3D=3D= 0xf0) { - arm_tlb_mte_tagged(&res.f.attrs) =3D true; - } =20 res.f.pte_attrs =3D res.cacheattrs.attrs; res.f.shareability =3D res.cacheattrs.shareability; --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664643194; cv=none; d=zohomail.com; s=zohoarc; b=NUAjIV5cGoxjJYaYK88yevCtwY3ZnrzYqu0Pc2ZSwxls4sbn2vUuiVF6qklstep98T15QRioL7pwbk3MG2R/nuaOXQZLSSHtBTK/maCVX4Yr6wCo0NPxxprCOARQt5YYpTJzEfwzV7Pg1QjbaS+Nm78FXq0FXT0y9o5Qam3iEYA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664643194; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=H5wRwyD67tK/HHDlYGbPLh0Azkr3is2XWTQhRNefVK0=; b=Z40VqsLedAEFkQVLllOnqUFtu5GPhtaSoOCtsl37aujDLoryWIooUrhpDENzTtTXY1LDBnPKdOoKRUwdkd3+eEyouBQ0hwr6ZORBQy8mHNI/J8Y5kTnQOhq1Ppd8WLp70KaDIEaMDJvFVtRhr4wCobXIe55QGGvLehvODyxrIMU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664643194810804.6813244937181; Sat, 1 Oct 2022 09:53:14 -0700 (PDT) Received: from localhost ([::1]:48674 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefjl-0007NE-MF for importer@patchew.org; Sat, 01 Oct 2022 12:53:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56084) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefHp-0007HB-Kf for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:21 -0400 Received: from mail-qk1-x72a.google.com ([2607:f8b0:4864:20::72a]:42614) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefHn-0006Gu-MF for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:21 -0400 Received: by mail-qk1-x72a.google.com with SMTP id d15so4533049qka.9 for ; Sat, 01 Oct 2022 09:24:19 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=H5wRwyD67tK/HHDlYGbPLh0Azkr3is2XWTQhRNefVK0=; b=FqPMFrjXrK5LaLhkzo4xfkgIlt2Py9uJxb+7qq+6t7Bp3DXC6Myk8wVKbUWd053XiU iaLvwc0HEjspgy433K98Tv7lnISFlD5way/hj0Y13Mq/gCcEZUlafQIWVQrquGk0w5jf 27rdJGf/bVK4AWun+GMjPVc+rF1zswg0UHRYQ0DNXrlWXKH05gfULRx6ojE/gCENPw9x 34XSQs0mLIw4DetdE38ijPye6NvKgsD6K/aycj+fmwvhWThrXDoXjWfni5CvIEJuPIHj indQiJL9nEABANnCbUNyhPWTyX16jHAwW2QPxn6CHQdbvDPQEDgMDHDy7LMjxPYC4aha kSPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=H5wRwyD67tK/HHDlYGbPLh0Azkr3is2XWTQhRNefVK0=; b=O9CwfEm8EYFuRY/HH3mTkHKGxCOx32b6djiouxywFr20/OwyerJwyWH6UJ55tHSQRO eDxuSkGEhPUpbWPDzGk4NJ7/pPBbJSh5xenoLG+rI4nYb54MEobojEfyLVNXjCR1usOV Z5km2y6DUZf60mVEQokti5Om3I91pRYiOoXxV1KfhFH7BQ/D88hqX1k4f7peaaGc7oAg I58jt4mvcmECpPLtjwrIfmLsw6ixaDbs/yjvYqE9XRCmNNIU4p7BgoiAgHUd6FtpHtZX G0KLeHav92Ig/HFFqyKTgwKZdssbD7UPec0gZ6Srm9n9JzcZdNEBJE9Roh0mb+SiDNg8 IvJQ== X-Gm-Message-State: ACrzQf2XU5tBOD0MOKoPQ6Za9NQnNTFCw/ALBGEZth8iTHDcmpy9skbn M+WgwolrVQxDtdnvBaBjNuzjI69w/7R9SQ== X-Google-Smtp-Source: AMsMyM6QRqH5Gbbzu044bSywk45d6mnLeV2yWvYkQoa8DT9BuUMlcJCdxElvPOtJeQgSqdLb9mKnWg== X-Received: by 2002:a05:620a:318a:b0:6ce:732a:f92 with SMTP id bi10-20020a05620a318a00b006ce732a0f92mr9662205qkb.347.1664641458978; Sat, 01 Oct 2022 09:24:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 23/42] target/arm: Use probe_access_full for BTI Date: Sat, 1 Oct 2022 09:22:59 -0700 Message-Id: <20221001162318.153420-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72a; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664643195358100001 Content-Type: text/plain; charset="utf-8" Add a field to TARGET_PAGE_ENTRY_EXTRA to hold the guarded bit. In is_guarded_page, use probe_access_full instead of just guessing that the tlb entry is still present. Also handles the FIXME about executing from device memory. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu-param.h | 8 ++++---- target/arm/cpu.h | 13 ------------- target/arm/internals.h | 1 + target/arm/ptw.c | 7 ++++--- target/arm/translate-a64.c | 22 ++++++++-------------- 5 files changed, 17 insertions(+), 34 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 118ca0e5c0..689a9645dc 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -32,12 +32,12 @@ # define TARGET_PAGE_BITS_MIN 10 =20 /* - * Cache the attrs and sharability fields from the page table entry. + * Cache the attrs, sharability, and gp fields from the page table entry. */ # define TARGET_PAGE_ENTRY_EXTRA \ - uint8_t pte_attrs; \ - uint8_t shareability; - + uint8_t pte_attrs; \ + uint8_t shareability; \ + bool guarded; #endif =20 #define NB_MMU_MODES 8 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2694a93894..c8cad2ef7c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3382,19 +3382,6 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *e= nv, unsigned regno) /* Shared between translate-sve.c and sve_helper.c. */ extern const uint64_t pred_esz_masks[5]; =20 -/* Helper for the macros below, validating the argument type. */ -static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) -{ - return x; -} - -/* - * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. - * Using these should be a bit more self-documenting than using the - * generic target bits directly. - */ -#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) - /* * AArch64 usage of the PAGE_TARGET_* bits for linux-user. * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect diff --git a/target/arm/internals.h b/target/arm/internals.h index fd17aee459..a50189e2e4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1067,6 +1067,7 @@ typedef struct ARMCacheAttrs { unsigned int attrs:8; unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PT= Es */ bool is_s2_format:1; + bool guarded:1; /* guarded bit of the v8-64 PTE */ } ARMCacheAttrs; =20 /* Fields that are valid upon success. */ diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 1bc194ffa1..ccfef2caca 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1319,9 +1319,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, uin= t64_t address, */ result->f.attrs.secure =3D false; } - /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB.= */ - if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { - arm_tlb_bti_gp(&result->f.attrs) =3D true; + + /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. = */ + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { + result->f.guarded =3D guarded; } =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5b67375f4e..22802d1d2f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14601,22 +14601,16 @@ static bool is_guarded_page(CPUARMState *env, Dis= asContext *s) #ifdef CONFIG_USER_ONLY return page_get_flags(addr) & PAGE_BTI; #else + CPUTLBEntryFull *full; + void *host; int mmu_idx =3D arm_to_core_mmu_idx(s->mmu_idx); - unsigned int index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); + int flags; =20 - /* - * We test this immediately after reading an insn, which means - * that any normal page must be in the TLB. The only exception - * would be for executing from flash or device memory, which - * does not retain the TLB entry. - * - * FIXME: Assume false for those, for now. We could use - * arm_cpu_get_phys_page_attrs_debug to re-read the page - * table entry even for that case. - */ - return (tlb_hit(entry->addr_code, addr) && - arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].fulltlb[index].attrs)= ); + flags =3D probe_access_full(env, addr, MMU_INST_FETCH, mmu_idx, + false, &host, &full, 0); + assert(!(flags & TLB_INVALID_MASK)); + + return full->guarded; #endif } =20 --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664643822; cv=none; d=zohomail.com; s=zohoarc; b=lqlaFq3AV8rkzMCuNtqKemhEf2ceEZv+B/Tm77r9MXQ/vZPtggzleiriFGAxnX8gNY6MPAe0WVjAUpEB60A5PcH22wHSsDUnkcb60rB1aZWAQK0honto1PZsRuxi7KamsE8si4ovmiXTU89/Qw2SO1B6UOu8MYQAfNWBewXucgQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664643822; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PIHa4426Hp/agSFdW8nii/mkTFfd47hTZ6myTQDFrL4=; b=UhQ8A6GJdP9qRH4ucY/u8CqOggNMPm5JzwP8Rcyv1rARvOOei6CfWcJl94H9Cxkp/9qjMOxEPXH6O2B2plNmTlVJlqoCEbvyzVbi7jCnaq8tigs3+wnD/+HHF5dU8ceWIWvdEGWwKEPLn91soT8V+RFuhJtBhdpoNYDysrWowmE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664643822739561.2827054014548; Sat, 1 Oct 2022 10:03:42 -0700 (PDT) Received: from localhost ([::1]:47182 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeftt-0007DZ-R7 for importer@patchew.org; Sat, 01 Oct 2022 13:03:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56092) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefHr-0007P3-MT for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:23 -0400 Received: from mail-qt1-x82d.google.com ([2607:f8b0:4864:20::82d]:44966) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefHq-0006Mx-3l for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:23 -0400 Received: by mail-qt1-x82d.google.com with SMTP id f26so4334767qto.11 for ; Sat, 01 Oct 2022 09:24:21 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=PIHa4426Hp/agSFdW8nii/mkTFfd47hTZ6myTQDFrL4=; b=BQ7pt44C1sVEbwBqxlFsjZdpe2Neex0+bbLXjMcr78tItPI/uo1wnUIdxv0VqOFfye HIS+1jyJmDW6v9mVlQ95iErD2fCfXRfRc+RNd5+hEqSV2TKkqmaJ/fK5GM/zkKbGvwUP EL/C+vrLGAi/bFKgiNgyKwPbx+3JUB845M9P/FQkLIimJOSD5+Wd27745dsseOyAyM8C S0GAQuIfIRpJ15+cBSTtF60hqcoXa6b6s0JlQz9uD1DhroqBYo1+WbvoCeFk3TMNkngy XZdCkMM3oA9aIinE0UaWznGCKxFl1mFBAw4Lv1+X1TafwrrIOcNRDCZjVdv79iOcjC4L zf9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=PIHa4426Hp/agSFdW8nii/mkTFfd47hTZ6myTQDFrL4=; b=QOD+7wlpaYksVd62lOvpkjZ/9njn38ggYHEgCpXK1RFrNI8XVl8TSZEn37LsfqX0yK StyYwXwBQRjM+3mJALSGddmIZQzXZO7+Zi5FNx+qCYrwHHNL9htuGDLLo6c1A4AUiyXf gPHLtc/a35m6z724coM5nFvQMLLc/ytz7o29mnB9ZJZkWOJ6eoewCDJalVHCf3TCGc8Z Hta5TFQnP1VZbPEmBBND6Qz4gee63BweBSY67LiAzkntlde57gQYvhifGstJ/sp6eFIY 94deLN5PIkg/u7T1eK/6FNahUUOPoQtZSEPvNnlnSwwhpmckA2X/8mRc58Mn7D8QME76 416g== X-Gm-Message-State: ACrzQf0Mb83Lh1o5pNiOMSaoILAL9VzKGZ3vRvjx1pLCv486M4c/0dOP C69ExZHe/BIk4iAA25RmrGzGdUSFWseseA== X-Google-Smtp-Source: AMsMyM7SCRv81kk3FHTtCjbA4C030PXq/TBDbWOz8GsCK8n1BQs6a7Pa1k9cDB0dPrvek08jkFVVWg== X-Received: by 2002:ac8:7f4d:0:b0:35c:b953:185a with SMTP id g13-20020ac87f4d000000b0035cb953185amr11071651qtk.382.1664641461036; Sat, 01 Oct 2022 09:24:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 24/42] target/arm: Add ARMMMUIdx_Phys_{S,NS} Date: Sat, 1 Oct 2022 09:23:00 -0700 Message-Id: <20221001162318.153420-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82d; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664643824224100001 Content-Type: text/plain; charset="utf-8" Not yet used, but add mmu indexes for 1-1 mapping to physical addresses. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 7 ++++++- target/arm/ptw.c | 19 +++++++++++++++++-- 3 files changed, 24 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 689a9645dc..98bd9e435e 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -40,6 +40,6 @@ bool guarded; #endif =20 -#define NB_MMU_MODES 8 +#define NB_MMU_MODES 10 =20 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c8cad2ef7c..0effa85c56 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2899,8 +2899,9 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_syn= c); * EL2 EL2&0 +PAN * EL2 (aka NS PL2) * EL3 (aka S PL1) + * Physical (NS & S) * - * for a total of 8 different mmu_idx. + * for a total of 10 different mmu_idx. * * R profile CPUs have an MPU, but can use the same set of MMU indexes * as A profile. They only need to distinguish EL0 and EL1 (and @@ -2965,6 +2966,10 @@ typedef enum ARMMMUIdx { ARMMMUIdx_E2 =3D 6 | ARM_MMU_IDX_A, ARMMMUIdx_E3 =3D 7 | ARM_MMU_IDX_A, =20 + /* TLBs with 1-1 mapping to the physical address spaces. */ + ARMMMUIdx_Phys_NS =3D 8 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_S =3D 9 | ARM_MMU_IDX_A, + /* * These are not allocated TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. diff --git a/target/arm/ptw.c b/target/arm/ptw.c index ccfef2caca..05dcacf45b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -179,6 +179,11 @@ static bool regime_translation_disabled(CPUARMState *e= nv, ARMMMUIdx mmu_idx, case ARMMMUIdx_E3: break; =20 + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_S: + /* No translation for physical address spaces. */ + return true; + default: g_assert_not_reached(); } @@ -2286,10 +2291,17 @@ static bool get_phys_addr_disabled(CPUARMState *env= , target_ulong address, { uint8_t memattr =3D 0x00; /* Device nGnRnE */ uint8_t shareability =3D 0; /* non-sharable */ + int r_el; =20 - if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2_S) { - int r_el =3D regime_el(env, mmu_idx); + switch (mmu_idx) { + case ARMMMUIdx_Stage2: + case ARMMMUIdx_Stage2_S: + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_S: + break; =20 + default: + r_el =3D regime_el(env, mmu_idx); if (arm_el_is_aa64(env, r_el)) { int pamax =3D arm_pamax(env_archcpu(env)); uint64_t tcr =3D env->cp15.tcr_el[r_el]; @@ -2338,6 +2350,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, = target_ulong address, shareability =3D 2; /* outer sharable */ } result->cacheattrs.is_s2_format =3D false; + break; } =20 result->f.phys_addr =3D address; @@ -2543,6 +2556,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, is_secure =3D arm_is_secure_below_el3(env); break; case ARMMMUIdx_Stage2: + case ARMMMUIdx_Phys_NS: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: @@ -2551,6 +2565,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, break; case ARMMMUIdx_E3: case ARMMMUIdx_Stage2_S: + case ARMMMUIdx_Phys_S: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664642947; cv=none; d=zohomail.com; s=zohoarc; b=DLIT5KClCJwiNerdRZSRcQ0+qduF1dTFhVAtmG/b5nt6Jf02ftgGcmmyNFD8LmVgM0axeXpMOG3zm55eaWMpxIoINg3tIsIzrbEjiE5xYJrJjz3z5F6umMhUONqj4LdTdZsZUJxcHaOBxhtTMYGeseUlY1LR1rpXuh1nbVnAzjk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664642947; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8Pt4idMHV+SQTFhlrqrA/oWq+H95plUs6Sfrolgz6Ls=; b=RA4eaJlfRXAPVXZa3DjiXy5wbr8+JICW7ZIYCxtmlaZaeQD2+eB0DUwa3zxdeBupo59gwvbM2o5GCbFmty5UJdRbCTuEiMkYxqal8Q4o6I+MunfdIAngPV3eLkofGjv8yLAb2z6NQ/xzdVl/qzXnD8Sh3YSMX0XP4uTmBV77xd4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664642946998897.1992389871101; Sat, 1 Oct 2022 09:49:06 -0700 (PDT) Received: from localhost ([::1]:33300 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeffl-0000mL-To for importer@patchew.org; Sat, 01 Oct 2022 12:49:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38792) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefHu-0007aJ-Re for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:26 -0400 Received: from mail-qt1-x82b.google.com ([2607:f8b0:4864:20::82b]:35429) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefHs-0006Nb-An for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:26 -0400 Received: by mail-qt1-x82b.google.com with SMTP id g23so4351486qtu.2 for ; Sat, 01 Oct 2022 09:24:23 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=8Pt4idMHV+SQTFhlrqrA/oWq+H95plUs6Sfrolgz6Ls=; b=Gk6STV9oxtGDPdNkdmTUoLnQN729OGcFCRF8Y+zE+KE/EuzwuCC3VXb5suiSvR6Y2H 7W0VWxIiwGrn8FtJ6Cico47Vc9C8aZ+TWcsok7PRWS8QjgihieWYm2942aZNlHsG1QcU BzJEpDpBZdsduQ3EDvzRS6tvWSAUov1yJ/sILQNwmSt56NOcGF1frqfLcK3UCLo6jfmh YDciXu1d7mrBoYKB7Q1CU1uAej0R+k+3eLdqHyRlM5WOo4ms2r/flAU/lq3pRT1nuXPc 1tf0vBVb4/9vAwOCL/W8zs1ZquCckfGH8dxvFz48Vkooicul5U9lVUkbsGfAyl2/gJiB UOnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=8Pt4idMHV+SQTFhlrqrA/oWq+H95plUs6Sfrolgz6Ls=; b=YuqWEMXkCnopcHXZp9FlnI/fz4zReI0F+WRFkUgj42ExYW3+6mMF7UWlkfT656sm6Z WZf6Tm6SaGAbWWEb0itnjurRA4Fq5fFZvp3O4X1aWBOrmBbWMg5cLo9znBnxEIACWHV+ 8iCWhmY1Ux4hkEqxVI42hv5Zbfo8YfYLT68yZA/Oz40LUl8fngzJwqnTRaUS+TjhTKar 4jsyAqQWvBiMRr6f/lIiZFmKa27iZM8aLlKGPI/KhwDviDAvWZcRFGJGl62LAhd/iuVF 88yl7IFh0APx77zHHkfCcQUnXkBc/fukRIBCFgzYlu3G3p7iFC7M5PAQGMp5Mt3Qlmc4 VCmw== X-Gm-Message-State: ACrzQf0KJIFVgA8gD00ypfc9AFCZqQ6TFnXc6j1h8xcb4BHKJPavcomF 7zGX3Z/UI/COvceBGrHoArPRmUm8HpbcLg== X-Google-Smtp-Source: AMsMyM45j2AvS3Znok2HSa5sdP2OBUrDfdQjdKAlFBQzh6cxpYQA97RukiZRAm9cW9C0S+07Z/iyVA== X-Received: by 2002:ac8:5e14:0:b0:35c:bab9:173e with SMTP id h20-20020ac85e14000000b0035cbab9173emr11194971qtx.222.1664641463304; Sat, 01 Oct 2022 09:24:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 25/42] target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx Date: Sat, 1 Oct 2022 09:23:01 -0700 Message-Id: <20221001162318.153420-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82b; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664642948767100001 Content-Type: text/plain; charset="utf-8" We had been marking this ARM_MMU_IDX_NOTLB, move it to a real tlb. Flush the tlb when invalidating stage 1+2 translations. Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 23 +++++++++++++---------- target/arm/helper.c | 4 +++- 3 files changed, 17 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 98bd9e435e..283618f601 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -40,6 +40,6 @@ bool guarded; #endif =20 -#define NB_MMU_MODES 10 +#define NB_MMU_MODES 12 =20 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0effa85c56..732c0c00ac 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2900,8 +2900,9 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_syn= c); * EL2 (aka NS PL2) * EL3 (aka S PL1) * Physical (NS & S) + * Stage2 (NS & S) * - * for a total of 10 different mmu_idx. + * for a total of 12 different mmu_idx. * * R profile CPUs have an MPU, but can use the same set of MMU indexes * as A profile. They only need to distinguish EL0 and EL1 (and @@ -2970,6 +2971,15 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Phys_NS =3D 8 | ARM_MMU_IDX_A, ARMMMUIdx_Phys_S =3D 9 | ARM_MMU_IDX_A, =20 + /* + * Used for second stage of an S12 page table walk, or for descriptor + * loads during first stage of an S1 page table walk. Note that both + * are in use simultaneously for SecureEL2: the security state for + * the S2 ptw is selected by the NS bit from the S1 ptw. + */ + ARMMMUIdx_Stage2 =3D 10 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2_S =3D 11 | ARM_MMU_IDX_A, + /* * These are not allocated TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. @@ -2977,15 +2987,6 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1_PAN =3D 2 | ARM_MMU_IDX_NOTLB, - /* - * Not allocated a TLB: used only for second stage of an S12 page - * table walk, or for descriptor loads during first stage of an S1 - * page table walk. Note that if we ever want to have a TLB for this - * then various TLB flush insns which currently are no-ops or flush - * only stage 1 MMU indexes will need to change to flush stage 2. - */ - ARMMMUIdx_Stage2 =3D 3 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage2_S =3D 4 | ARM_MMU_IDX_NOTLB, =20 /* * M-profile. @@ -3016,6 +3017,8 @@ typedef enum ARMMMUIdxBit { TO_CORE_BIT(E20_2), TO_CORE_BIT(E20_2_PAN), TO_CORE_BIT(E3), + TO_CORE_BIT(Stage2), + TO_CORE_BIT(Stage2_S), =20 TO_CORE_BIT(MUser), TO_CORE_BIT(MPriv), diff --git a/target/arm/helper.c b/target/arm/helper.c index 6fe85c6642..19a03eb200 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4319,7 +4319,9 @@ static int alle1_tlbmask(CPUARMState *env) */ return (ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_1_PAN | - ARMMMUIdxBit_E10_0); + ARMMMUIdxBit_E10_0 | + ARMMMUIdxBit_Stage2 | + ARMMMUIdxBit_Stage2_S); } =20 static int e2_tlbmask(CPUARMState *env) --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664643420; cv=none; d=zohomail.com; s=zohoarc; b=YhqDek/UYC7xzLMjN/2ELoVpfnKDQOveqGrcfMJYKogsPxH3PlIIUC8hb7OwGOlsCnXuiGtnsVWrkuA9/z0IQ8NcVbMAKaUTTNsI1I6WaJZFMalOieHp3sCXUWf2AgxpqVSDDez0PefNLKb4Bd9pVj3UvdDI8Om/nkZrRkK25j4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664643420; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eb41dB13E+ZPEBfGGmg85O0xNXDKjVd8ViYdMqOjaTw=; b=Ppp+tzAcuSG/0/81VcCLT64vB7HVCgxfZjSG3/kmv0TtnHnuB9aGriBuerr7fB4Ap5E1KIp4/pJBE2aUC/sI+JWUXNoZFpRhyTO6FyZx5ZvpW2UxIn5DQNfcJrBjdhnQbvHGQc6ZdqSCggXBNR0MLCKMLUScCJxX4WUBS53J5LA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664643420576565.5323748319806; Sat, 1 Oct 2022 09:57:00 -0700 (PDT) Received: from localhost ([::1]:49724 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefnN-0004RK-W3 for importer@patchew.org; Sat, 01 Oct 2022 12:56:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38796) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefHx-0007hQ-FR for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:29 -0400 Received: from mail-qk1-x735.google.com ([2607:f8b0:4864:20::735]:33419) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefHu-0006Nw-H7 for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:29 -0400 Received: by mail-qk1-x735.google.com with SMTP id h28so4557221qka.0 for ; Sat, 01 Oct 2022 09:24:26 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=eb41dB13E+ZPEBfGGmg85O0xNXDKjVd8ViYdMqOjaTw=; b=MU/Pd6j+kwoJLl5nRsXf4241GuKrM6hjR/EcDoIErl1BD2IbhR6QT0DPMvisqZDlwy Nwa82qmAg5wRI6+sp7hkJRTIQVbXU7xFJhIIBYXNJZJ9GRkJ3RWNMFtID77HpWxxUdiG m8sjy+IwmZvTopuKr5ilXoOiZ6OUUz3ykabQYTJa3QnpYBxS5es5fuGtI8ZLuxsdcdq+ RoHJ/JKRQEohR0YnXTZTlAS1KzrfwjWycmc+BDK7emhz+Oyz5p7QEtsY1Dy3764LVsAB /MRAgi7Y2kkocKxMt1oNDadHZ9+68RztxajR6rIblvgcLBDv+1N3lTfI6nm1JmJirSRv JtGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=eb41dB13E+ZPEBfGGmg85O0xNXDKjVd8ViYdMqOjaTw=; b=ay/ErlpVJuTy40MUloOu/IvGx8T3QVY8FdqQPGQxyIA64Yz/YYZbLn59YtDiffb7fp ffjK3jqotNxG1trQQPQGlUKpEwOiSEmwqTV6bOL84BNnHS9sI0MMdT8D+p4YFdmEADhO 1bBQS7Cx+gvWZ24tI1UKgKKMXX3PCWpfls8Bb8IhFsF3cib+hAQDpBfQcPGzw9cLttUj r/rG1rHYdrneskbWtSaA24S9tpBr4I4bkITLHqKijtqwCg2KubtSjD+0AXh4JhkMKWsN sklR47+yNbL1Gfk+xDLUCucWa+i5iEoHNBgb7RzeH0fG7F0vKivOsnTYKvc9xNabI4AZ a6aQ== X-Gm-Message-State: ACrzQf0JcYn0mz297gzP6Mtgai9hicSch34bREl1fLaATpD/5YbiPC9g m0oJ8vEOdpmA0nHgxARJ8ogoaVJeGm8wjQ== X-Google-Smtp-Source: AMsMyM5Sml+60mVsCoY8NStV8qg1pUKy/yJQSD8yAojyEMJrWEJwAZ9DDwKffvnHHfB9Yl18vnMt7A== X-Received: by 2002:a05:620a:29c5:b0:6ce:b8f3:fd5b with SMTP id s5-20020a05620a29c500b006ceb8f3fd5bmr9911997qkp.107.1664641465532; Sat, 01 Oct 2022 09:24:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 26/42] target/arm: Plumb debug into S1_ptw_translate Date: Sat, 1 Oct 2022 09:23:02 -0700 Message-Id: <20221001162318.153420-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::735; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x735.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664643422247100003 Content-Type: text/plain; charset="utf-8" Before using softmmu page tables for the ptw, plumb down a debug parameter so that we can query page table entries from gdbstub without modifying cpu state. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 66 +++++++++++++++++++++++++++++------------------- 1 file changed, 40 insertions(+), 26 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 05dcacf45b..45adb9d5a9 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -16,7 +16,7 @@ =20 static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, - bool is_secure, bool s1_is_el0, + bool is_secure, bool s1_is_el0, bool debug, GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) __attribute__((nonnull)); =20 @@ -212,7 +212,7 @@ static bool ptw_attrs_are_device(uint64_t hcr, ARMCache= Attrs cacheattrs) =20 /* Translate a S1 pagetable walk through S2 if needed. */ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, - hwaddr addr, bool *is_secure_ptr, + hwaddr addr, bool *is_secure_ptr, bool debu= g, ARMMMUFaultInfo *fi) { bool is_secure =3D *is_secure_ptr; @@ -225,7 +225,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, int ret; =20 ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, - is_secure, false, &s2, fi); + is_secure, false, debug, &s2, fi); if (ret) { assert(fi->type !=3D ARMFault_None); fi->s2addr =3D addr; @@ -268,7 +268,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, =20 /* All loads done in the course of a page table walk go through here. */ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) + ARMMMUIdx mmu_idx, bool debug, ARMMMUFaultInfo= *fi) { CPUState *cs =3D env_cpu(env); MemTxAttrs attrs =3D {}; @@ -276,7 +276,7 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr ad= dr, bool is_secure, AddressSpace *as; uint32_t data; =20 - addr =3D S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); + addr =3D S1_ptw_translate(env, mmu_idx, addr, &is_secure, debug, fi); attrs.secure =3D is_secure; as =3D arm_addressspace(cs, attrs); if (fi->s1ptw) { @@ -296,7 +296,7 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr ad= dr, bool is_secure, } =20 static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) + ARMMMUIdx mmu_idx, bool debug, ARMMMUFaultInfo= *fi) { CPUState *cs =3D env_cpu(env); MemTxAttrs attrs =3D {}; @@ -304,7 +304,7 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr ad= dr, bool is_secure, AddressSpace *as; uint64_t data; =20 - addr =3D S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); + addr =3D S1_ptw_translate(env, mmu_idx, addr, &is_secure, debug, fi); attrs.secure =3D is_secure; as =3D arm_addressspace(cs, attrs); if (fi->s1ptw) { @@ -433,8 +433,8 @@ static int simple_ap_to_rw_prot(CPUARMState *env, ARMMM= UIdx mmu_idx, int ap) =20 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool is_secure, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) + bool is_secure, bool debug, + GetPhysAddrResult *result, ARMMMUFaultInfo *f= i) { int level =3D 1; uint32_t table; @@ -453,7 +453,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, fi->type =3D ARMFault_Translation; goto do_fault; } - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); + desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, debug, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -491,7 +491,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, /* Fine pagetable. */ table =3D (desc & 0xfffff000) | ((address >> 8) & 0xffc); } - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); + desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, debug, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -552,8 +552,8 @@ do_fault: =20 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool is_secure, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) + bool is_secure, bool debug, + GetPhysAddrResult *result, ARMMMUFaultInfo *f= i) { ARMCPU *cpu =3D env_archcpu(env); int level =3D 1; @@ -576,7 +576,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, fi->type =3D ARMFault_Translation; goto do_fault; } - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); + desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, debug, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -629,7 +629,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, ns =3D extract32(desc, 3, 1); /* Lookup l2 entry. */ table =3D (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); + desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, debug, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -984,7 +984,7 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa6= 4, int level, */ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, - bool is_secure, bool s1_is_el0, + bool is_secure, bool s1_is_el0, bool debug, GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) { ARMCPU *cpu =3D env_archcpu(env); @@ -1210,7 +1210,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, descaddr |=3D (address >> (stride * (4 - level))) & indexmask; descaddr &=3D ~7ULL; nstable =3D extract32(tableattrs, 4, 1); - descriptor =3D arm_ldq_ptw(env, descaddr, !nstable, mmu_idx, fi); + descriptor =3D arm_ldq_ptw(env, descaddr, !nstable, mmu_idx, debug= , fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -2361,10 +2361,13 @@ static bool get_phys_addr_disabled(CPUARMState *env= , target_ulong address, return 0; } =20 -bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, - MMUAccessType access_type, ARMMMUIdx mmu_id= x, - bool is_secure, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) +static bool get_phys_addr_with_secure_debug(CPUARMState *env, + target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, + bool is_secure, bool debug, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) { ARMMMUIdx s1_mmu_idx =3D stage_1_mmu_idx(mmu_idx); =20 @@ -2418,7 +2421,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, memset(result, 0, sizeof(*result)); =20 ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, - s2walk_secure, is_el0, result, fi); + s2walk_secure, is_el0, debug, result,= fi); fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ @@ -2526,16 +2529,25 @@ bool get_phys_addr_with_secure(CPUARMState *env, ta= rget_ulong address, } if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, - is_secure, false, result, fi); + is_secure, false, debug, result, fi); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, - is_secure, result, fi); + is_secure, debug, result, fi); } else { return get_phys_addr_v5(env, address, access_type, mmu_idx, - is_secure, result, fi); + is_secure, debug, result, fi); } } =20 +bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_id= x, + bool is_secure, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) +{ + return get_phys_addr_with_secure_debug(env, address, access_type, mmu_= idx, + is_secure, false, result, fi); +} + bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) @@ -2587,9 +2599,11 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *c= s, vaddr addr, GetPhysAddrResult res =3D {}; ARMMMUFaultInfo fi =3D {}; ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); + bool is_secure =3D arm_is_secure(env); bool ret; =20 - ret =3D get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi); + ret =3D get_phys_addr_with_secure_debug(env, addr, MMU_DATA_LOAD, mmu_= idx, + is_secure, true, &res, &fi); *attrs =3D res.f.attrs; =20 if (ret) { --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664644012; cv=none; d=zohomail.com; s=zohoarc; b=LRIKarSCarNNJDe74e4jcnCvi5ZxVbR8lUztFd1Iiri/gpcL6F2B8acQjeBZNhQfWaSIJzurgRndIpdaiM3mk56HZrICgVZVSyjT3DedOJyEJ+bSYdXXDrAu1ZJd0WjJGCcfKMDQfGN5hugYchRn74+dw8ZYCdLzAB/pa2FoxK4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=8i+GnsYsjdhfrh1IH3Iu5+k/jBY4+XRApAtU5rIcPD0=; b=DzP5sOaGpW29SJyHVNND0VX+xMw1YTyIP8IA9qrSmxSz5MA6tZ2bSbt2FuJRkfDxYA JY86KstCIpnUsAg2rR+JAFM43zsnGSqKzoEG2A3cv/hUXg+MjtmLcLWZ+NIvwWTm7svB dOgwzY8v6YjjKbSjU9Fs0yyJhOrhZNIApgNbPdI5GUtbQJopiNcqFMyE0sgx22Y1Farc 0fhGYALuZoxkYloRThwEsyZk+OAmxDnub0zgtPg4z8fFj0MuSDA6l7nMSIl2HaGctmkS 1W+GiJi2SmNkoEYXj0ioI9AEXJZiEyK89SkhPgKwf3E3YWQlyOJT/R1aQ88Zy/Yrw0ox 5sHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=8i+GnsYsjdhfrh1IH3Iu5+k/jBY4+XRApAtU5rIcPD0=; b=W92CLTj66QiwbUsz+maxOKaL4Pnr+Eerj0A2uXSH0DuaZaczGN0IzeeKvW+z1cAkLO w0zA+NA24ZzDXKCoDBSMe09ijHmNcDJrVTIoSq/Hwnb5bT5nKqRoyEcWVES7hA0Loi4X VBrUdUFyW6OvcHdg1BalAGl9vIkFrnTs674Ro55TOt4CcJZYnOdV9vB0xyMUDCUU3yHP 7jYWld19rSK0dBrY7ZqqfGx8WqaGzVfuK/sVfDlh/7QPEvqSgWcBsBH6pTUFRYx4BBOw LNxe7uxSqmW0ISZOEMrSnWQIP/2N5jHJS0OiA5EEsLERhx77Y14IR36sOePjUbfnM/65 p9pQ== X-Gm-Message-State: ACrzQf1AH+wLI7ISsRJbeFLv8ii6hBfAvB7HjrGVLDwd/swdryy+UfJN +9Kx64uc97aBNHDH/WKVkjFDKyrrOgJNhQ== X-Google-Smtp-Source: AMsMyM6iNZPS8iJzGS8Cn1fT0WGVZoVsVTAH1CaXnfdlUyJh1L+8LEHCMh7XBsHDvXOwMQCTmXmqxg== X-Received: by 2002:a05:620a:280d:b0:6cf:ab57:a130 with SMTP id f13-20020a05620a280d00b006cfab57a130mr9829664qkp.749.1664641468099; Sat, 01 Oct 2022 09:24:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 27/42] target/arm: Use softmmu tlbs for page table walking Date: Sat, 1 Oct 2022 09:23:03 -0700 Message-Id: <20221001162318.153420-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72a; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664644013216100001 Content-Type: text/plain; charset="utf-8" So far, limit the change to S1_ptw_translate, arm_ldl_ptw, and arm_ldq_ptw. Use probe_access_full to find the host address, and if so use a host load. If the probe fails, we've got our fault info already. On the off chance that page tables are not in RAM, continue to use the address_space_ld* functions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 5 + target/arm/ptw.c | 207 ++++++++++++++++++++++++++-------------- target/arm/tlb_helper.c | 17 +++- 3 files changed, 155 insertions(+), 74 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 732c0c00ac..7108568685 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -225,6 +225,8 @@ typedef struct CPUARMTBFlags { target_ulong flags2; } CPUARMTBFlags; =20 +typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; + typedef struct CPUArchState { /* Regs for current mode. */ uint32_t regs[16]; @@ -715,6 +717,9 @@ typedef struct CPUArchState { struct CPUBreakpoint *cpu_breakpoint[16]; struct CPUWatchpoint *cpu_watchpoint[16]; =20 + /* Optional fault info across tlb lookup. */ + ARMMMUFaultInfo *tlb_fi; + /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 45adb9d5a9..ba496c3421 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/range.h" +#include "exec/exec-all.h" #include "cpu.h" #include "internals.h" #include "idau.h" @@ -191,7 +192,7 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; } =20 -static bool ptw_attrs_are_device(uint64_t hcr, ARMCacheAttrs cacheattrs) +static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) { /* * For an S1 page table walk, the stage 1 attributes are always @@ -202,41 +203,72 @@ static bool ptw_attrs_are_device(uint64_t hcr, ARMCac= heAttrs cacheattrs) * With HCR_EL2.FWB =3D=3D 1 this is when descriptor bit [4] is 0, ie * when cacheattrs.attrs bit [2] is 0. */ - assert(cacheattrs.is_s2_format); if (hcr & HCR_FWB) { - return (cacheattrs.attrs & 0x4) =3D=3D 0; + return (attrs & 0x4) =3D=3D 0; } else { - return (cacheattrs.attrs & 0xc) =3D=3D 0; + return (attrs & 0xc) =3D=3D 0; } } =20 /* Translate a S1 pagetable walk through S2 if needed. */ -static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, - hwaddr addr, bool *is_secure_ptr, bool debu= g, - ARMMMUFaultInfo *fi) +static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr a= ddr, + bool *is_secure_ptr, void **hphys, hwaddr *gp= hys, + bool debug, ARMMMUFaultInfo *fi) { bool is_secure =3D *is_secure_ptr; ARMMMUIdx s2_mmu_idx =3D is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_St= age2; + bool s2_phys =3D false; + uint8_t pte_attrs; + bool pte_secure; =20 - if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, s2_mmu_idx, is_secure)) { - GetPhysAddrResult s2 =3D {}; - uint64_t hcr; - int ret; + if (!arm_mmu_idx_is_stage1_of_2(mmu_idx) + || regime_translation_disabled(env, s2_mmu_idx, is_secure)) { + s2_mmu_idx =3D is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; + s2_phys =3D true; + } =20 - ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, - is_secure, false, debug, &s2, fi); - if (ret) { - assert(fi->type !=3D ARMFault_None); - fi->s2addr =3D addr; - fi->stage2 =3D true; - fi->s1ptw =3D true; - fi->s1ns =3D !is_secure; - return ~0; + if (unlikely(debug)) { + /* + * From gdbstub, do not use softmmu so that we don't modify the + * state of the cpu at all, including softmmu tlb contents. + */ + if (s2_phys) { + *gphys =3D addr; + pte_attrs =3D 0; + pte_secure =3D is_secure; + } else { + GetPhysAddrResult s2 =3D { }; + if (!get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, + is_secure, false, debug, &s2, fi)) { + goto fail; + } + *gphys =3D s2.f.phys_addr; + pte_attrs =3D s2.cacheattrs.attrs; + pte_secure =3D s2.f.attrs.secure; } + *hphys =3D NULL; + } else { + CPUTLBEntryFull *full; + int flags; =20 - hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); - if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) { + env->tlb_fi =3D fi; + flags =3D probe_access_full(env, addr, MMU_DATA_LOAD, + arm_to_core_mmu_idx(s2_mmu_idx), + true, hphys, &full, 0); + env->tlb_fi =3D NULL; + + if (unlikely(flags & TLB_INVALID_MASK)) { + goto fail; + } + *gphys =3D full->phys_addr; + pte_attrs =3D full->pte_attrs; + pte_secure =3D full->attrs.secure; + } + + if (!s2_phys) { + uint64_t hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); + + if ((hcr & HCR_PTW) && S2_attrs_are_device(hcr, pte_attrs)) { /* * PTW set and S1 walk touched S2 Device memory: * generate Permission fault. @@ -246,24 +278,25 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, fi->stage2 =3D true; fi->s1ptw =3D true; fi->s1ns =3D !is_secure; - return ~0; + return false; } - - if (arm_is_secure_below_el3(env)) { - /* Check if page table walk is to secure or non-secure PA spac= e. */ - if (is_secure) { - is_secure =3D !(env->cp15.vstcr_el2 & VSTCR_SW); - } else { - is_secure =3D !(env->cp15.vtcr_el2 & VTCR_NSW); - } - *is_secure_ptr =3D is_secure; - } else { - assert(!is_secure); - } - - addr =3D s2.f.phys_addr; } - return addr; + + if (is_secure) { + /* Check if page table walk is to secure or non-secure PA space. */ + *is_secure_ptr =3D !(pte_secure + ? env->cp15.vstcr_el2 & VSTCR_SW + : env->cp15.vtcr_el2 & VTCR_NSW); + } + return true; + + fail: + assert(fi->type !=3D ARMFault_None); + fi->s2addr =3D addr; + fi->stage2 =3D true; + fi->s1ptw =3D true; + fi->s1ns =3D !is_secure; + return false; } =20 /* All loads done in the course of a page table walk go through here. */ @@ -271,56 +304,88 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr = addr, bool is_secure, ARMMMUIdx mmu_idx, bool debug, ARMMMUFaultInfo= *fi) { CPUState *cs =3D env_cpu(env); - MemTxAttrs attrs =3D {}; - MemTxResult result =3D MEMTX_OK; - AddressSpace *as; + void *hphys; + hwaddr gphys; uint32_t data; + bool be; =20 - addr =3D S1_ptw_translate(env, mmu_idx, addr, &is_secure, debug, fi); - attrs.secure =3D is_secure; - as =3D arm_addressspace(cs, attrs); - if (fi->s1ptw) { + if (!S1_ptw_translate(env, mmu_idx, addr, &is_secure, + &hphys, &gphys, debug, fi)) { + /* Failure. */ + assert(fi->s1ptw); return 0; } - if (regime_translation_big_endian(env, mmu_idx)) { - data =3D address_space_ldl_be(as, addr, attrs, &result); + + be =3D regime_translation_big_endian(env, mmu_idx); + if (likely(hphys)) { + /* Page tables are in RAM, and we have the host address. */ + if (be) { + data =3D ldl_be_p(hphys); + } else { + data =3D ldl_le_p(hphys); + } } else { - data =3D address_space_ldl_le(as, addr, attrs, &result); + /* Page tables are in MMIO. */ + MemTxAttrs attrs =3D { .secure =3D is_secure }; + AddressSpace *as =3D arm_addressspace(cs, attrs); + MemTxResult result =3D MEMTX_OK; + + if (be) { + data =3D address_space_ldl_be(as, gphys, attrs, &result); + } else { + data =3D address_space_ldl_le(as, gphys, attrs, &result); + } + if (unlikely(result !=3D MEMTX_OK)) { + fi->type =3D ARMFault_SyncExternalOnWalk; + fi->ea =3D arm_extabort_type(result); + return 0; + } } - if (result =3D=3D MEMTX_OK) { - return data; - } - fi->type =3D ARMFault_SyncExternalOnWalk; - fi->ea =3D arm_extabort_type(result); - return 0; + return data; } =20 static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, ARMMMUIdx mmu_idx, bool debug, ARMMMUFaultInfo= *fi) { CPUState *cs =3D env_cpu(env); - MemTxAttrs attrs =3D {}; - MemTxResult result =3D MEMTX_OK; - AddressSpace *as; + void *hphys; + hwaddr gphys; uint64_t data; + bool be; =20 - addr =3D S1_ptw_translate(env, mmu_idx, addr, &is_secure, debug, fi); - attrs.secure =3D is_secure; - as =3D arm_addressspace(cs, attrs); - if (fi->s1ptw) { + if (!S1_ptw_translate(env, mmu_idx, addr, &is_secure, + &hphys, &gphys, debug, fi)) { + /* Failure. */ + assert(fi->s1ptw); return 0; } - if (regime_translation_big_endian(env, mmu_idx)) { - data =3D address_space_ldq_be(as, addr, attrs, &result); + + be =3D regime_translation_big_endian(env, mmu_idx); + if (likely(hphys)) { + /* Page tables are in RAM, and we have the host address. */ + if (be) { + data =3D ldq_be_p(hphys); + } else { + data =3D ldq_le_p(hphys); + } } else { - data =3D address_space_ldq_le(as, addr, attrs, &result); + /* Page tables are in MMIO. */ + MemTxAttrs attrs =3D { .secure =3D is_secure }; + AddressSpace *as =3D arm_addressspace(cs, attrs); + MemTxResult result =3D MEMTX_OK; + + if (be) { + data =3D address_space_ldq_be(as, gphys, attrs, &result); + } else { + data =3D address_space_ldq_le(as, gphys, attrs, &result); + } + if (unlikely(result !=3D MEMTX_OK)) { + fi->type =3D ARMFault_SyncExternalOnWalk; + fi->ea =3D arm_extabort_type(result); + return 0; + } } - if (result =3D=3D MEMTX_OK) { - return data; - } - fi->type =3D ARMFault_SyncExternalOnWalk; - fi->ea =3D arm_extabort_type(result); - return 0; + return data; } =20 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 3462a6ea14..69b0dc69df 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -208,10 +208,21 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr) { ARMCPU *cpu =3D ARM_CPU(cs); - ARMMMUFaultInfo fi =3D {}; GetPhysAddrResult res =3D {}; + ARMMMUFaultInfo local_fi, *fi; int ret; =20 + /* + * Allow S1_ptw_translate to see any fault generated here. + * Since this may recurse, read and clear. + */ + fi =3D cpu->env.tlb_fi; + if (fi) { + cpu->env.tlb_fi =3D NULL; + } else { + fi =3D memset(&local_fi, 0, sizeof(local_fi)); + } + /* * Walk the page table and (if the mapping exists) add the page * to the TLB. On success, return true. Otherwise, if probing, @@ -220,7 +231,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, */ ret =3D get_phys_addr(&cpu->env, address, access_type, core_to_arm_mmu_idx(&cpu->env, mmu_idx), - &res, &fi); + &res, fi); if (likely(!ret)) { /* * Map a single [sub]page. Regions smaller than our declared @@ -242,7 +253,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, } else { /* now we have a real cpu fault */ cpu_restore_state(cs, retaddr, true); - arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); + arm_deliver_fault(cpu, address, access_type, mmu_idx, fi); } } #else --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664643251; cv=none; d=zohomail.com; s=zohoarc; b=XGp1Pu5SPIFU7gtxjTTylryVYNLTuPvvVE0t0EhIPlv07U9dNh0b3ssX5wtKGmBlPgUvmM6Mp8J6nqWizLlPUPQeG60C5JyurBqVWcG7lwWX6PmSX4caMDvcdDHU47On33GS2Ezb35PQDzXacsvlvgcrXrnsTO1NvI7ooPsKGLM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664643251; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jzDPmkcbyBXmgF7/UF+Ax8S2mqEsTchVghdM8qEDw1g=; b=CewGjWk2SreAAQ/bN9aYB5WQvk8Kk0SeX00lNNEbVkWJVx4TiH0e1mSyizXDzrYKqjO1UUf+waNJl2BSKkvryKYlHp7so2obYfzs+QC+dYULkocYlhqDA79NhATLOiamowC/0Lcz4DdG1bqwMLEP4+S39oTFMsrYvGOBtwaJN30= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16646432512371005.2667954678623; Sat, 1 Oct 2022 09:54:11 -0700 (PDT) Received: from localhost ([::1]:48816 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefkg-0000na-7Z for importer@patchew.org; Sat, 01 Oct 2022 12:54:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38802) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefI1-0007sS-0P for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:33 -0400 Received: from mail-qk1-x734.google.com ([2607:f8b0:4864:20::734]:38557) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefHy-0006Gl-Qb for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:32 -0400 Received: by mail-qk1-x734.google.com with SMTP id 3so4548441qka.5 for ; Sat, 01 Oct 2022 09:24:30 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::734; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x734.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664643251595100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 196 +++++++++++++++++++++++++---------------------- 1 file changed, 106 insertions(+), 90 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index ba496c3421..3f5733a237 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -21,6 +21,15 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_= t address, GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) __attribute__((nonnull)); =20 +static bool get_phys_addr_with_secure_debug(CPUARMState *env, + target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, + bool is_secure, bool debug, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) + __attribute__((nonnull)); + /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. = */ static const uint8_t pamax_map[] =3D { [0] =3D 32, @@ -2426,6 +2435,98 @@ static bool get_phys_addr_disabled(CPUARMState *env,= target_ulong address, return 0; } =20 +static bool get_phys_addr_twostage(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx s1_mmu_idx, + bool is_secure, bool debug, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) +{ + hwaddr ipa; + int s1_prot; + int ret; + bool ipa_secure, s2walk_secure; + ARMCacheAttrs cacheattrs1; + ARMMMUIdx s2_mmu_idx; + bool is_el0; + uint64_t hcr; + + ret =3D get_phys_addr_with_secure_debug(env, address, access_type, + s1_mmu_idx, is_secure, debug, + result, fi); + + /* If S1 fails or S2 is disabled, return early. */ + if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secur= e)) { + return ret; + } + + ipa =3D result->f.phys_addr; + ipa_secure =3D result->f.attrs.secure; + if (is_secure) { + /* Select TCR based on the NS bit from the S1 walk. */ + s2walk_secure =3D !(ipa_secure + ? env->cp15.vstcr_el2 & VSTCR_SW + : env->cp15.vtcr_el2 & VTCR_NSW); + } else { + assert(!ipa_secure); + s2walk_secure =3D false; + } + + s2_mmu_idx =3D (s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2); + is_el0 =3D s1_mmu_idx =3D=3D ARMMMUIdx_Stage1_E0; + + /* + * S1 is done, now do S2 translation. + * Save the stage1 results so that we may merge prot and cacheattrs la= ter. + */ + s1_prot =3D result->f.prot; + cacheattrs1 =3D result->cacheattrs; + memset(result, 0, sizeof(*result)); + + ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, + s2walk_secure, is_el0, debug, result, fi); + fi->s2addr =3D ipa; + + /* Combine the S1 and S2 perms. */ + result->f.prot &=3D s1_prot; + + /* If S2 fails, return early. */ + if (ret) { + return ret; + } + + /* Combine the S1 and S2 cache attributes. */ + hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); + if (hcr & HCR_DC) { + /* + * HCR.DC forces the first stage attributes to + * Normal Non-Shareable, + * Inner Write-Back Read-Allocate Write-Allocate, + * Outer Write-Back Read-Allocate Write-Allocate. + * Do not overwrite Tagged within attrs. + */ + if (cacheattrs1.attrs !=3D 0xf0) { + cacheattrs1.attrs =3D 0xff; + } + cacheattrs1.shareability =3D 0; + } + result->cacheattrs =3D combine_cacheattrs(hcr, cacheattrs1, + result->cacheattrs); + + /* Check if IPA translates to secure or non-secure PA space. */ + if (is_secure) { + if (ipa_secure) { + result->f.attrs.secure =3D + !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)); + } else { + result->f.attrs.secure =3D + !((env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)) + || (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))); + } + } + return 0; +} + static bool get_phys_addr_with_secure_debug(CPUARMState *env, target_ulong address, MMUAccessType access_type, @@ -2442,97 +2543,12 @@ static bool get_phys_addr_with_secure_debug(CPUARMS= tate *env, * translations if mmu_idx is a two-stage regime. */ if (arm_feature(env, ARM_FEATURE_EL2)) { - hwaddr ipa; - int s1_prot; - int ret; - bool ipa_secure, s2walk_secure; - ARMCacheAttrs cacheattrs1; - ARMMMUIdx s2_mmu_idx; - bool is_el0; - uint64_t hcr; - - ret =3D get_phys_addr_with_secure(env, address, access_type, - s1_mmu_idx, is_secure, result,= fi); - - /* If S1 fails or S2 is disabled, return early. */ - if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, - is_secure)) { - return ret; - } - - ipa =3D result->f.phys_addr; - ipa_secure =3D result->f.attrs.secure; - if (is_secure) { - /* Select TCR based on the NS bit from the S1 walk. */ - s2walk_secure =3D !(ipa_secure - ? env->cp15.vstcr_el2 & VSTCR_SW - : env->cp15.vtcr_el2 & VTCR_NSW); - } else { - assert(!ipa_secure); - s2walk_secure =3D false; - } - - s2_mmu_idx =3D (s2walk_secure - ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2); - is_el0 =3D mmu_idx =3D=3D ARMMMUIdx_E10_0; - - /* - * S1 is done, now do S2 translation. - * Save the stage1 results so that we may merge - * prot and cacheattrs later. - */ - s1_prot =3D result->f.prot; - cacheattrs1 =3D result->cacheattrs; - memset(result, 0, sizeof(*result)); - - ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, - s2walk_secure, is_el0, debug, result,= fi); - fi->s2addr =3D ipa; - - /* Combine the S1 and S2 perms. */ - result->f.prot &=3D s1_prot; - - /* If S2 fails, return early. */ - if (ret) { - return ret; - } - - /* Combine the S1 and S2 cache attributes. */ - hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); - if (hcr & HCR_DC) { - /* - * HCR.DC forces the first stage attributes to - * Normal Non-Shareable, - * Inner Write-Back Read-Allocate Write-Allocate, - * Outer Write-Back Read-Allocate Write-Allocate. - * Do not overwrite Tagged within attrs. - */ - if (cacheattrs1.attrs !=3D 0xf0) { - cacheattrs1.attrs =3D 0xff; - } - cacheattrs1.shareability =3D 0; - } - result->cacheattrs =3D combine_cacheattrs(hcr, cacheattrs1, - result->cacheattrs); - - /* Check if IPA translates to secure or non-secure PA space. */ - if (is_secure) { - if (ipa_secure) { - result->f.attrs.secure =3D - !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)); - } else { - result->f.attrs.secure =3D - !((env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)) - || (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))); - } - } - return 0; - } else { - /* - * For non-EL2 CPUs a stage1+stage2 translation is just stage = 1. - */ - mmu_idx =3D stage_1_mmu_idx(mmu_idx); + return get_phys_addr_twostage(env, address, access_type, + s1_mmu_idx, is_secure, debug, + result, fi); } + /* For non-EL2 CPUs a stage1+stage2 translation is just stage 1. */ + mmu_idx =3D s1_mmu_idx; } =20 /* --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664642483; cv=none; d=zohomail.com; s=zohoarc; b=W0eCGXvG3VFxPrHbnoGyTyOqz4y0+VdX9Hldn2XAAc1ccCRLjO/8hDWyqdILygb0O1gSvucZ7kH7+DlZpbXlBiWH0EsP6KUK+UsJ61biVfrJGNLMImaKy9FYK3MwYKNSW4Tf2m5dIgrsacRNohsxp2nrEmFFgTiUkcq8OdLttos= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664642483; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1wNWHezVm2UV71ghHCMk5XJVYInqSqpNnuv7vR6v7WU=; b=ZTEfgHqVUlpan6pHHM+ADludFhNYpNu0u/FBAaEmKgqZZOKIQpAPwahvV+sNRn9VdsetRj+DjflPnRs5Xa3uTN4u77JB1HZvReWmAy0wqFwO8JCu59+InAyfNOtkj5vs9akdfIgOtmizPO8ud6oIdwPDnBkif1AMm+GBHyjhnHM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664642483532170.96040791150017; Sat, 1 Oct 2022 09:41:23 -0700 (PDT) Received: from localhost ([::1]:51686 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefYH-0007fb-IF for importer@patchew.org; Sat, 01 Oct 2022 12:41:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38808) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefI3-0007y6-76 for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:35 -0400 Received: from mail-qt1-x82b.google.com ([2607:f8b0:4864:20::82b]:35429) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefI1-0006Nb-GF for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:34 -0400 Received: by mail-qt1-x82b.google.com with SMTP id g23so4351608qtu.2 for ; Sat, 01 Oct 2022 09:24:33 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=1wNWHezVm2UV71ghHCMk5XJVYInqSqpNnuv7vR6v7WU=; b=uta0XtAq0zkGKDu1c8hXsyDPsYAVjvfwUFxTlVAbeYrrGuciXQxZBWDudQidrIOY8u dVq9oEyZaBn8TJ/rEzaVbMjB+LBstcPRC9TWdLCCKdxJ34bhzDJsZHwxyGS9djzqSk9p /QL8aUdQqIm2S25JCv2yI57K82sqYDmyc6SY79UXucx7wUwTjDXu9YkxEHWDXAMXsloK oE+jaT9tgbJTspU7ZslVg7kzYAuy1PQMy06Fn4MJrZBD5CEnmfvFX9nVjwrkDK+uVNOm gymT77MgonR9yAMCSUA4OHT7LMi9hb970673mONltVyy21rcGW1qsPt+M7pFuUFADpUp Fnng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=1wNWHezVm2UV71ghHCMk5XJVYInqSqpNnuv7vR6v7WU=; b=NbSFe6Tbe31XM9JKx6tQn4TVxDzupgsENVhUaavN6vfK02mVWhdmozUjWhtqoO3DTn xHzgWiYsnzrDjxMn8T/HL9m2QcGajP0SMdPTDPkaS6Ng0RSww0ByPhI9RQXITMD/SF24 Nhma9lRnopSSh5pEfYUzZXg1c3rZSaWk0GdHTJWTisO0ksA1/JEC9m0cHKbxRHxs0IgW q0USp38m6vZ0vSGhwwTtSqihjVOzkaqI766N58ftq2k5c4SNAPtYE9REASD4xjQMgXRg nqCXE/Q7DTtfQjD6A2p8vEoLuGp5M/obH4BwoblHB0IfNtQspoXw87XEtyE6JJ7FyjET FiBg== X-Gm-Message-State: ACrzQf3udccrh9y7XZWPtABqtSmiIH4rHQ/AWaixSDfLxJTOFkyTt8jd gggoqP4J/lucRLqZvPKJnW0WFurfHUk6hg== X-Google-Smtp-Source: AMsMyM6R9vw8DNySmHtI+whI6lCpvQhR0hEpR3RQbXBzeYlTWbFnybiAME62VZAgvK96fPcTcG7rOw== X-Received: by 2002:ac8:5c0b:0:b0:35c:e066:998d with SMTP id i11-20020ac85c0b000000b0035ce066998dmr10906978qti.336.1664641472882; Sat, 01 Oct 2022 09:24:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 29/42] target/arm: Use bool consistently for get_phys_addr subroutines Date: Sat, 1 Oct 2022 09:23:05 -0700 Message-Id: <20221001162318.153420-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82b; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664642484516100001 Content-Type: text/plain; charset="utf-8" The return type of the functions is already bool, but in a few instances we used an integer type with the return statement. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 3f5733a237..445382ab03 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2432,7 +2432,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, = target_ulong address, result->f.lg_page_size =3D TARGET_PAGE_BITS; result->cacheattrs.shareability =3D shareability; result->cacheattrs.attrs =3D memattr; - return 0; + return false; } =20 static bool get_phys_addr_twostage(CPUARMState *env, target_ulong address, @@ -2444,8 +2444,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = target_ulong address, { hwaddr ipa; int s1_prot; - int ret; - bool ipa_secure, s2walk_secure; + bool ret, ipa_secure, s2walk_secure; ARMCacheAttrs cacheattrs1; ARMMMUIdx s2_mmu_idx; bool is_el0; @@ -2524,7 +2523,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = target_ulong address, || (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))); } } - return 0; + return false; } =20 static bool get_phys_addr_with_secure_debug(CPUARMState *env, --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664643569; cv=none; d=zohomail.com; s=zohoarc; b=F9kevxUU3zYSc5cI/MsO35xGNNRBxOoAaweDvdr8NLigdBWnLSq/vHHmN584urmfQvTT8BOz17BLDtOB7Gr6/dIuPzgYRRsmG97+sxj4qCBdLfLKOOZ9zUyqAbv8I7hPqc2ffaYGXp8tWQITvoDfwSK2/qxs7bloNTmuFZ9u9nk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664643569; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WH93/bK7v3kp/pKnTict/jbomZX/0gxJBlUtQBFUx68=; b=DQUNR5OIQPOUilzlDcyUpVTE4QA/u4jdafz0GAop0zBvft75n1tHdzvg1jTfW/yDQAxwjYeRwhy9bih7dfYRd9s3IIywVa4Yi2W59MWd/ZwjNWjoyZ/iL1sZVum0vIJp3Svc9HGVtNiXX6/9BfNNkTCIaDJK5r4aTqvAZxE+IpI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664643569945595.5387357837457; Sat, 1 Oct 2022 09:59:29 -0700 (PDT) Received: from localhost ([::1]:36806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefpn-0001DH-RK for importer@patchew.org; Sat, 01 Oct 2022 12:59:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50672) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefI8-0008Go-AQ for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:40 -0400 Received: from mail-qk1-x736.google.com ([2607:f8b0:4864:20::736]:46857) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefI6-0006PQ-5a for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:40 -0400 Received: by mail-qk1-x736.google.com with SMTP id d17so4524602qko.13 for ; Sat, 01 Oct 2022 09:24:37 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=WH93/bK7v3kp/pKnTict/jbomZX/0gxJBlUtQBFUx68=; b=fw16RTiYbXvGuI1+bAZl3XOPQOivuJ28ewOkNsEcxowpjr6zUucmOMbX5wqofcsbcd r4hNNckolDWXfHN5WauEJJmdSaCfaS2qZIGg7eUKnrQgyo28LkBif+OQyDkMmJJdvTl2 pDKH0/90Kbq1he4i6nvvhkAvp4PJMz9EHs5ns1X+5HO6uh1v5gRfsmZwi5ixNXLg0hXI +nk4OsU2YiR17yWaBzswPaqU25ypMvH1vXdAP5tuKvz/KJ/5SqT7ST0FAWPFZl0gJ6aR EjM5B59bnFZvWOGK7z7o7C3jBwVda2zWsQqb+yi5H5ZsDqk9Myt8dOGK3Piw9O0Sckcx PLTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=WH93/bK7v3kp/pKnTict/jbomZX/0gxJBlUtQBFUx68=; b=WRYn7R66yGn6ofnmZ4CMyM3eNDSd/x7wOYS+QA4QGQMg0HZqyuZ8zUdtlt+dGWa0bG lXC89mesEs+S0TlTMyx7wKZcXERsrJbRBEx5mz+lYRfrwVpEeoPXn8aiYfi/x7rz+o2x wky43hP7guqE1aiwQZCER6gohxMo2XtIcZHdMKGxWkjYSetBjuo83fImVNDhPCLJBWEF m3Wita0AsEn7GspDMe/a0SYV95qqzcuTgdF3IMx590IlACJOmWQBSGs3tLaF0rlnC9wK CxlIZy5XSrpDeVKJ3aw9p5NQg+BogT3r39QFc2clJq4pHUJr3pstFsC5Uv+iHfebMMT4 up3g== X-Gm-Message-State: ACrzQf1QM2E6K8IcNdc9WD+BhGaZVlAHzsKMGAaK2KKljbbhN7lTKArA EePQxWcZE6z4dgY6f2QLcZINyQVHR8oy8w== X-Google-Smtp-Source: AMsMyM60wIuvcByFIvwoQYiW4d3+dWA7C1FURoet2/qcj+HQfYyZiYj4WBvGTArmCtjQiM4L7aF7Ug== X-Received: by 2002:a05:620a:448e:b0:6ce:8dd2:bc46 with SMTP id x14-20020a05620a448e00b006ce8dd2bc46mr9748377qkp.705.1664641477034; Sat, 01 Oct 2022 09:24:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 30/42] target/arm: Add ptw_idx argument to S1_ptw_translate Date: Sat, 1 Oct 2022 09:23:06 -0700 Message-Id: <20221001162318.153420-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::736; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x736.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664643571000100001 Content-Type: text/plain; charset="utf-8" Hoist the computation of the mmu_idx for the ptw up to get_phys_addr_with_secure_debug and get_phys_addr_twostage. This removes the duplicate check for stage2 disabled from the middle of the walk, performing it only once. Pass ptw_idx through get_phys_addr_{v5,v6,lpae} and arm_{ldl,ldq}_ptw. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 104 ++++++++++++++++++++++++++++++++--------------- 1 file changed, 71 insertions(+), 33 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 445382ab03..7a77bea2c7 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -17,7 +17,8 @@ =20 static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, - bool is_secure, bool s1_is_el0, bool debug, + ARMMMUIdx ptw_idx, bool is_secure, + bool s1_is_el0, bool debug, GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) __attribute__((nonnull)); =20 @@ -220,21 +221,16 @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t= attrs) } =20 /* Translate a S1 pagetable walk through S2 if needed. */ -static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr a= ddr, +static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, + ARMMMUIdx s2_mmu_idx, hwaddr addr, bool *is_secure_ptr, void **hphys, hwaddr *gp= hys, bool debug, ARMMMUFaultInfo *fi) { bool is_secure =3D *is_secure_ptr; - ARMMMUIdx s2_mmu_idx =3D is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_St= age2; - bool s2_phys =3D false; uint8_t pte_attrs; - bool pte_secure; + bool s2_phys, pte_secure; =20 - if (!arm_mmu_idx_is_stage1_of_2(mmu_idx) - || regime_translation_disabled(env, s2_mmu_idx, is_secure)) { - s2_mmu_idx =3D is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; - s2_phys =3D true; - } + s2_phys =3D s2_mmu_idx =3D=3D ARMMMUIdx_Phys_S || s2_mmu_idx =3D=3D AR= MMMUIdx_Phys_NS; =20 if (unlikely(debug)) { /* @@ -247,8 +243,12 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUI= dx mmu_idx, hwaddr addr, pte_secure =3D is_secure; } else { GetPhysAddrResult s2 =3D { }; + ARMMMUIdx phys_idx =3D (is_secure ? ARMMMUIdx_Phys_S + : ARMMMUIdx_Phys_NS); + if (!get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, - is_secure, false, debug, &s2, fi)) { + phys_idx, is_secure, false, debug, + &s2, fi)) { goto fail; } *gphys =3D s2.f.phys_addr; @@ -310,7 +310,8 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUId= x mmu_idx, hwaddr addr, =20 /* All loads done in the course of a page table walk go through here. */ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, bool debug, ARMMMUFaultInfo= *fi) + ARMMMUIdx mmu_idx, ARMMMUIdx ptw_idx, + bool debug, ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); void *hphys; @@ -318,7 +319,7 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr ad= dr, bool is_secure, uint32_t data; bool be; =20 - if (!S1_ptw_translate(env, mmu_idx, addr, &is_secure, + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, &is_secure, &hphys, &gphys, debug, fi)) { /* Failure. */ assert(fi->s1ptw); @@ -354,7 +355,8 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr ad= dr, bool is_secure, } =20 static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, bool debug, ARMMMUFaultInfo= *fi) + ARMMMUIdx mmu_idx, ARMMMUIdx ptw_idx, + bool debug, ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); void *hphys; @@ -362,7 +364,7 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr ad= dr, bool is_secure, uint64_t data; bool be; =20 - if (!S1_ptw_translate(env, mmu_idx, addr, &is_secure, + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, &is_secure, &hphys, &gphys, debug, fi)) { /* Failure. */ assert(fi->s1ptw); @@ -507,7 +509,7 @@ static int simple_ap_to_rw_prot(CPUARMState *env, ARMMM= UIdx mmu_idx, int ap) =20 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool is_secure, bool debug, + ARMMMUIdx ptw_idx, bool is_secure, bool debug, GetPhysAddrResult *result, ARMMMUFaultInfo *f= i) { int level =3D 1; @@ -527,7 +529,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, fi->type =3D ARMFault_Translation; goto do_fault; } - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, debug, fi); + desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, debug, f= i); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -565,7 +567,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, /* Fine pagetable. */ table =3D (desc & 0xfffff000) | ((address >> 8) & 0xffc); } - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, debug, fi); + desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, debu= g, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -626,7 +628,7 @@ do_fault: =20 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool is_secure, bool debug, + ARMMMUIdx ptw_idx, bool is_secure, bool debug, GetPhysAddrResult *result, ARMMMUFaultInfo *f= i) { ARMCPU *cpu =3D env_archcpu(env); @@ -650,7 +652,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, fi->type =3D ARMFault_Translation; goto do_fault; } - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, debug, fi); + desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, debug, f= i); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -703,7 +705,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, ns =3D extract32(desc, 3, 1); /* Lookup l2 entry. */ table =3D (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, debug, fi); + desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, debu= g, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -1058,7 +1060,8 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_a= a64, int level, */ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, - bool is_secure, bool s1_is_el0, bool debug, + ARMMMUIdx ptw_idx, bool is_secure, + bool s1_is_el0, bool debug, GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) { ARMCPU *cpu =3D env_archcpu(env); @@ -1284,7 +1287,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, descaddr |=3D (address >> (stride * (4 - level))) & indexmask; descaddr &=3D ~7ULL; nstable =3D extract32(tableattrs, 4, 1); - descriptor =3D arm_ldq_ptw(env, descaddr, !nstable, mmu_idx, debug= , fi); + descriptor =3D arm_ldq_ptw(env, descaddr, !nstable, mmu_idx, + ptw_idx, debug, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -2446,7 +2450,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = target_ulong address, int s1_prot; bool ret, ipa_secure, s2walk_secure; ARMCacheAttrs cacheattrs1; - ARMMMUIdx s2_mmu_idx; + ARMMMUIdx s2_mmu_idx, s2_ptw_idx; bool is_el0; uint64_t hcr; =20 @@ -2471,7 +2475,13 @@ static bool get_phys_addr_twostage(CPUARMState *env,= target_ulong address, s2walk_secure =3D false; } =20 - s2_mmu_idx =3D (s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2); + if (s2walk_secure) { + s2_mmu_idx =3D ARMMMUIdx_Stage2_S; + s2_ptw_idx =3D ARMMMUIdx_Phys_S; + } else { + s2_mmu_idx =3D ARMMMUIdx_Stage2; + s2_ptw_idx =3D ARMMMUIdx_Phys_NS; + } is_el0 =3D s1_mmu_idx =3D=3D ARMMMUIdx_Stage1_E0; =20 /* @@ -2482,7 +2492,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = target_ulong address, cacheattrs1 =3D result->cacheattrs; memset(result, 0, sizeof(*result)); =20 - ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, + ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, s2_ptw_i= dx, s2walk_secure, is_el0, debug, result, fi); fi->s2addr =3D ipa; =20 @@ -2534,9 +2544,32 @@ static bool get_phys_addr_with_secure_debug(CPUARMSt= ate *env, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - ARMMMUIdx s1_mmu_idx =3D stage_1_mmu_idx(mmu_idx); + ARMMMUIdx s1_mmu_idx, ptw_idx; =20 - if (mmu_idx !=3D s1_mmu_idx) { + switch (mmu_idx) { + case ARMMMUIdx_Phys_S: + case ARMMMUIdx_Phys_NS: + do_disabled: + /* Checking Phys early avoids special casing later vs regime_el. */ + return get_phys_addr_disabled(env, address, access_type, mmu_idx, + is_secure, result, fi); + + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: + /* First stage lookup uses second stage for ptw. */ + ptw_idx =3D is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; + break; + + case ARMMMUIdx_E10_0: + s1_mmu_idx =3D ARMMMUIdx_Stage1_E0; + goto do_twostage; + case ARMMMUIdx_E10_1: + s1_mmu_idx =3D ARMMMUIdx_Stage1_E1; + goto do_twostage; + case ARMMMUIdx_E10_1_PAN: + s1_mmu_idx =3D ARMMMUIdx_Stage1_E1_PAN; + do_twostage: /* * Call ourselves recursively to do the stage 1 and then stage 2 * translations if mmu_idx is a two-stage regime. @@ -2548,6 +2581,12 @@ static bool get_phys_addr_with_secure_debug(CPUARMSt= ate *env, } /* For non-EL2 CPUs a stage1+stage2 translation is just stage 1. */ mmu_idx =3D s1_mmu_idx; + /* fall through */ + + default: + /* Single stage and second stage uses physical for ptw. */ + ptw_idx =3D is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; + break; } =20 /* @@ -2604,18 +2643,17 @@ static bool get_phys_addr_with_secure_debug(CPUARMS= tate *env, /* Definitely a real MMU, not an MPU */ =20 if (regime_translation_disabled(env, mmu_idx, is_secure)) { - return get_phys_addr_disabled(env, address, access_type, mmu_idx, - is_secure, result, fi); + goto do_disabled; } if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, - is_secure, false, debug, result, fi); + ptw_idx, is_secure, false, debug, result= , fi); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, - is_secure, debug, result, fi); + ptw_idx, is_secure, debug, result, fi); } else { return get_phys_addr_v5(env, address, access_type, mmu_idx, - is_secure, debug, result, fi); + ptw_idx, is_secure, debug, result, fi); } } =20 --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664644112; cv=none; d=zohomail.com; s=zohoarc; b=PaVRlZtSEn+GIZTNPf4ZoItK6jRKTNCZVFP7Gd8iss84hye8MKHhXxzRTKoNTat+DrYRqto8lHxxryGODNzziyw2E7+jSYXB8FmO1jl95ygShL5Rw/xK7pJzbLjMcuYGTlodup85CjqBt5Td1FhvkaM7/EdnB2AmhyAYiWpCSQE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664644112; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hVHPTtrjmM6MNnCdxtnW1ZJbSHSO1tW4oindFVrgmZU=; b=Or6aKYeCB75A7Jjr6jeQCcTh5Lq/fuqZFdMqpT2dwunRNHL7BpVwI4x46ynNhVNozMVeWj6WVVLIEd3jgrIsTVulsgd5O+okHs1sBeHQuNP+Mi6oSxUBtP2OahhR3Om6jXpmxIlAKazoPz6btTMvtfxvGM6BBA2iOab940R7rQw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664644112507865.1336226349727; Sat, 1 Oct 2022 10:08:32 -0700 (PDT) Received: from localhost ([::1]:45190 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefyZ-0006Xh-Gp for importer@patchew.org; Sat, 01 Oct 2022 13:08:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50676) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefI9-0008LK-Ip for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:41 -0400 Received: from mail-qv1-xf34.google.com ([2607:f8b0:4864:20::f34]:39770) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefI7-0006DC-Jr for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:41 -0400 Received: by mail-qv1-xf34.google.com with SMTP id z18so4439939qvn.6 for ; Sat, 01 Oct 2022 09:24:39 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=hVHPTtrjmM6MNnCdxtnW1ZJbSHSO1tW4oindFVrgmZU=; b=onJGwdnkg+b6fFSsOItnuuTHvQR8qpV76LpSBLr6ZnsZPNKs3LZSvijmu13cwzl1Rl JoQmy41pCEMDX76xZzwQQS6kZDeYnneVcQ3ffY4IiZ+rfhm+JpwfboDVHGgbitusCBzP IdipD78AWWDPruAyfAkNBJGC+Q43wnUWuqY2tjv5aSpWRATj1XEded6smZX03zriRd1E PMMS75V6c1nVdUoGg6rb/EtnhM7GNdGrHVq8anUCIX69jaF3m/1HjsIweBhkRHDlv+6o zQ9rpFrcp3oKGQLnk45aT6VUtne6OWV/e4yKRgMSIZPntoghTHtS60qqlGYTotgZq2v+ +CmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=hVHPTtrjmM6MNnCdxtnW1ZJbSHSO1tW4oindFVrgmZU=; b=dlws0aShGvPnllYhPRKJoncAwVFHrH7j019GtOpBTplNT7Y1iYfXXnr1N9HmpG3/Ei uSYlCLjpi9bZyFrTKYjFmYcr+631hNVqPWOKjPGAKxOTCTg2uZHGyBPdLko8VfTaG9NP WhrJONA+Jsmm+VMZb6u2Rq3d4NhDOAl6BJHHtOMHpTIVJHnBvhea60HFyc6h4lrTpAUz mVgDby0jh8egoQzmBz34eMD5Mq04inYwRRgAGX9bdtmaf3bxPvXt2OnccQIA+YOe15ij l4TrfYiCxgcl6R7I1Gy4OwU48ySUepX9S11OTsu4/iH9PaiUK8boymJTV2H9lqNMpYf+ D/eA== X-Gm-Message-State: ACrzQf1Xmk/H63FO0Zrjzboa+VWNoir8gc4y8aREYFqIdV5jH8WQx2x6 3hWLvvMr7FhWWTJl9vc3EYld5HVDEHGhbQ== X-Google-Smtp-Source: AMsMyM5D1HAJ0HuHxckJc+bCh+9tAuDGffKcuejDIRFP7d0BkNWioX3q4D4kP3CKnTXldB/O9a9E+A== X-Received: by 2002:a05:6214:19c2:b0:4b1:7a38:49c1 with SMTP id j2-20020a05621419c200b004b17a3849c1mr3267819qvc.1.1664641479007; Sat, 01 Oct 2022 09:24:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 31/42] target/arm: Add isar predicates for FEAT_HAFDBS Date: Sat, 1 Oct 2022 09:23:07 -0700 Message-Id: <20221001162318.153420-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f34; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664644113696100001 Content-Type: text/plain; charset="utf-8" The MMFR1 field may indicate support for hardware update of access flag alone, or access flag and dirty bit. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7108568685..e499a84850 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4100,6 +4100,16 @@ static inline bool isar_feature_aa64_lva(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) !=3D 0; } =20 +static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) !=3D 0; +} + +static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >=3D 2; +} + static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) !=3D 0; --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664644229; cv=none; d=zohomail.com; s=zohoarc; b=LHItzouNxVm9j3pi7LBYhBcKZHoZaLc+FcsBVamw78yARGIaxsVVFESWB5jvIdVjA00kxhCdmVhuvCgMvLRrwXHkE/+MlmNTyy0sUmbmIDGLTldgTnF09LOgSv8XwjSKS9y5UhIrdw6cIPquvZQ3Rjgzv1+fT5TE6uOKwNOXbt4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664644229; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jXnTwa6UKQ364zxEijW2Djrh5kilE9wYQnYihj42TBk=; b=CqWTEI2P/OAkROCW90wJH+LlbC9uj06vYnwukgDT6o6DN93p3iWWcTXKstve24g8uMPZ+vZaPEpvdrFPGDqZhG4a5WyfugdJkCFeCWinmUPV56XPnCz9eLTRCrrkfL6eL4XpqIrOlqKXFZWK96kCxX9qwMUB2DMw2s+5uLtV67I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664644229887352.9324576303263; Sat, 1 Oct 2022 10:10:29 -0700 (PDT) Received: from localhost ([::1]:45294 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeg0R-0000q1-U8 for importer@patchew.org; Sat, 01 Oct 2022 13:10:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50680) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefIB-0008SK-PV for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:43 -0400 Received: from mail-qv1-xf34.google.com ([2607:f8b0:4864:20::f34]:40818) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefIA-0006Pz-AA for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:43 -0400 Received: by mail-qv1-xf34.google.com with SMTP id h10so2940438qvq.7 for ; Sat, 01 Oct 2022 09:24:41 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f34; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664644230424100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 2 ++ target/arm/helper.c | 8 +++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index a50189e2e4..e95b6b1b8f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1014,6 +1014,8 @@ typedef struct ARMVAParameters { bool using64k : 1; bool tsz_oob : 1; /* tsz has been clamped to legal range */ bool ds : 1; + bool ha : 1; + bool hd : 1; } ARMVAParameters; =20 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, diff --git a/target/arm/helper.c b/target/arm/helper.c index 19a03eb200..70ae3816b9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10280,7 +10280,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, ARMMMUIdx mmu_idx, bool data) { uint64_t tcr =3D regime_tcr(env, mmu_idx); - bool epd, hpd, using16k, using64k, tsz_oob, ds; + bool epd, hpd, using16k, using64k, tsz_oob, ds, ha, hd; int select, tsz, tbi, max_tsz, min_tsz, ps, sh; ARMCPU *cpu =3D env_archcpu(env); =20 @@ -10298,6 +10298,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, epd =3D false; sh =3D extract32(tcr, 12, 2); ps =3D extract32(tcr, 16, 3); + ha =3D extract32(tcr, 21, 1) && cpu_isar_feature(aa64_hafs, cpu); + hd =3D extract32(tcr, 22, 1) && cpu_isar_feature(aa64_hdbs, cpu); ds =3D extract64(tcr, 32, 1); } else { /* @@ -10322,6 +10324,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, hpd =3D extract64(tcr, 42, 1); } ps =3D extract64(tcr, 32, 3); + ha =3D extract64(tcr, 39, 1) && cpu_isar_feature(aa64_hafs, cpu); + hd =3D extract64(tcr, 40, 1) && cpu_isar_feature(aa64_hdbs, cpu); ds =3D extract64(tcr, 59, 1); } =20 @@ -10393,6 +10397,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, .using64k =3D using64k, .tsz_oob =3D tsz_oob, .ds =3D ds, + .ha =3D ha, + .hd =3D ha & hd, }; } =20 --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664643784; cv=none; d=zohomail.com; s=zohoarc; b=ZWmR0S5OsjfnDq33juiLnNd8byvKjVeI7+cHEvAYMqPuA0VDRICqcaNdLVzp8wlzTjNzSk2D81xZ7KSi8b0jl0FqVXaINthkIuEfDWvhFjggghHnGhT8eh6F/kBzE2RNkYlPVXA6LXVtQHpIox6ha/GJkV2e22wctnQALFzRdps= ARC-Message-Signature: i=1; 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([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=ddXuP4NAsi4/7/1r07P/ZZueGAkWOaBdn4p1jeEw/4M=; b=Iskyk8clX7kpEPtUqf4aj+vKy9wJKkfAN6ZRv0iUiXXjsuEldPAQdprxbgWjugIV2g R+cK1utM2cmCOSclNn6//OV8PffFTNsGtuuMIUlD+g/U2m0CkvMrYoxs3fMTWiJeElZ9 5BNdW69hV7l6e5+ITU5wA+yJ0h9qxbeWPyw/UFLlh82+/cEGnqbm1Vs48xFgnn6IE9CH z6br7LRvYTCT48u4VDgBf/+6Cw7mRly0snlNEZIncCEfYhgbZJ0alLZpp3/W/8EFrfvA 5/v3Tvr9bhNBYV5Laxse7MrCJz1hywwHMjCoh455ihTuXNWBuHeibzPjlgEzilGCtz/3 Jj9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=ddXuP4NAsi4/7/1r07P/ZZueGAkWOaBdn4p1jeEw/4M=; b=kmYHqgXBn+q8Zei23d5feOnTFMpGZZpTGDi77eoDHvHZYZxwNUjucZNIoPKFSesU/B jy0hjqEm2y0guOODLM0bKEH3ff9XIuNPRzOiArUt1cVNvO8DzNM9RkVCry49niGufC4h S5NvmC7+hoszUwpVeK2MuoNlWGcXsjMezWFedenQfC4RQasHaitLgyH6RxzfMBN9+SQY J8sfok2DQjjmZx50u66j5lnwcSALUyJeH4MTFvjf91jrtV1ebvWUu3Ngtr2GaB9RbI9F 1BsFyAixT5Rj+HwL9/3mPliWbjZkox1q2RnOqNI2euxevQ45Z/Lt+h+2W7qBK2uk2kd0 JmcQ== X-Gm-Message-State: ACrzQf1zNnuNgqWls6rDSErb5ayB4bOnVAlnxdjL+Tb947BNy2MWPfUn tuqJ5As21gdd7TmgvyxdqkMHBkAI0CD6Xw== X-Google-Smtp-Source: AMsMyM60GKAzyruNLP7odTqJhlNztDF1pkUggajoOJEy+d65aizXMsjqfWhrKlR9cDCNNO/fVc24wA== X-Received: by 2002:ac8:57cc:0:b0:35c:b5d1:9024 with SMTP id w12-20020ac857cc000000b0035cb5d19024mr11071935qta.214.1664641483531; Sat, 01 Oct 2022 09:24:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 33/42] target/arm: Split out S1TranslateResult type Date: Sat, 1 Oct 2022 09:23:09 -0700 Message-Id: <20221001162318.153420-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::832; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x832.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664643785971100001 Content-Type: text/plain; charset="utf-8" Consolidate the results of S1_ptw_translate in one struct. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 70 +++++++++++++++++++++++++----------------------- 1 file changed, 36 insertions(+), 34 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7a77bea2c7..99ad894180 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -220,13 +220,18 @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t= attrs) } } =20 +typedef struct { + bool is_secure; + void *hphys; + hwaddr gphys; +} S1TranslateResult; + /* Translate a S1 pagetable walk through S2 if needed. */ static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, ARMMMUIdx s2_mmu_idx, hwaddr addr, - bool *is_secure_ptr, void **hphys, hwaddr *gp= hys, - bool debug, ARMMMUFaultInfo *fi) + bool is_secure, bool debug, + S1TranslateResult *res, ARMMMUFaultInfo *fi) { - bool is_secure =3D *is_secure_ptr; uint8_t pte_attrs; bool s2_phys, pte_secure; =20 @@ -238,7 +243,7 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUId= x mmu_idx, * state of the cpu at all, including softmmu tlb contents. */ if (s2_phys) { - *gphys =3D addr; + res->gphys =3D addr; pte_attrs =3D 0; pte_secure =3D is_secure; } else { @@ -251,11 +256,11 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, &s2, fi)) { goto fail; } - *gphys =3D s2.f.phys_addr; + res->gphys =3D s2.f.phys_addr; pte_attrs =3D s2.cacheattrs.attrs; pte_secure =3D s2.f.attrs.secure; } - *hphys =3D NULL; + res->hphys =3D NULL; } else { CPUTLBEntryFull *full; int flags; @@ -263,13 +268,13 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, env->tlb_fi =3D fi; flags =3D probe_access_full(env, addr, MMU_DATA_LOAD, arm_to_core_mmu_idx(s2_mmu_idx), - true, hphys, &full, 0); + true, &res->hphys, &full, 0); env->tlb_fi =3D NULL; =20 if (unlikely(flags & TLB_INVALID_MASK)) { goto fail; } - *gphys =3D full->phys_addr; + res->gphys =3D full->phys_addr; pte_attrs =3D full->pte_attrs; pte_secure =3D full->attrs.secure; } @@ -291,12 +296,11 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, } } =20 - if (is_secure) { - /* Check if page table walk is to secure or non-secure PA space. */ - *is_secure_ptr =3D !(pte_secure - ? env->cp15.vstcr_el2 & VSTCR_SW - : env->cp15.vtcr_el2 & VTCR_NSW); - } + /* Check if page table walk is to secure or non-secure PA space. */ + res->is_secure =3D (is_secure && + !(pte_secure + ? env->cp15.vstcr_el2 & VSTCR_SW + : env->cp15.vtcr_el2 & VTCR_NSW)); return true; =20 fail: @@ -314,36 +318,35 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr = addr, bool is_secure, bool debug, ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); - void *hphys; - hwaddr gphys; + S1TranslateResult s1; uint32_t data; bool be; =20 - if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, &is_secure, - &hphys, &gphys, debug, fi)) { + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, + debug, &s1, fi)) { /* Failure. */ assert(fi->s1ptw); return 0; } =20 be =3D regime_translation_big_endian(env, mmu_idx); - if (likely(hphys)) { + if (likely(s1.hphys)) { /* Page tables are in RAM, and we have the host address. */ if (be) { - data =3D ldl_be_p(hphys); + data =3D ldl_be_p(s1.hphys); } else { - data =3D ldl_le_p(hphys); + data =3D ldl_le_p(s1.hphys); } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs =3D { .secure =3D is_secure }; + MemTxAttrs attrs =3D { .secure =3D s1.is_secure }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 if (be) { - data =3D address_space_ldl_be(as, gphys, attrs, &result); + data =3D address_space_ldl_be(as, s1.gphys, attrs, &result); } else { - data =3D address_space_ldl_le(as, gphys, attrs, &result); + data =3D address_space_ldl_le(as, s1.gphys, attrs, &result); } if (unlikely(result !=3D MEMTX_OK)) { fi->type =3D ARMFault_SyncExternalOnWalk; @@ -359,36 +362,35 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr = addr, bool is_secure, bool debug, ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); - void *hphys; - hwaddr gphys; + S1TranslateResult s1; uint64_t data; bool be; =20 - if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, &is_secure, - &hphys, &gphys, debug, fi)) { + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, + debug, &s1, fi)) { /* Failure. */ assert(fi->s1ptw); return 0; } =20 be =3D regime_translation_big_endian(env, mmu_idx); - if (likely(hphys)) { + if (likely(s1.hphys)) { /* Page tables are in RAM, and we have the host address. */ if (be) { - data =3D ldq_be_p(hphys); + data =3D ldq_be_p(s1.hphys); } else { - data =3D ldq_le_p(hphys); + data =3D ldq_le_p(s1.hphys); } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs =3D { .secure =3D is_secure }; + MemTxAttrs attrs =3D { .secure =3D s1.is_secure }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 if (be) { - data =3D address_space_ldq_be(as, gphys, attrs, &result); + data =3D address_space_ldq_be(as, s1.gphys, attrs, &result); } else { - data =3D address_space_ldq_le(as, gphys, attrs, &result); + data =3D address_space_ldq_le(as, s1.gphys, attrs, &result); } if (unlikely(result !=3D MEMTX_OK)) { fi->type =3D ARMFault_SyncExternalOnWalk; --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=n1zqtffVj+e5QIYH+tiRjV15qJp6GZoBT6L+6JANVjQ=; b=img0YxndVMlnokJrp2TD2W0moTjnkTziKwcI9ri2GGyVoCVFocuLT1FGvnWzL7gbHT YH2YIK4Ohtb4xCNVUNJyBsUkGmkpEzD5xUJFdyn9rDBldFTiwc2Tt/uAx0lcJWmrcE+o EKxwHn+vQUlVIB4vDJe16AdzwjtejLM92piX6JNU12dzbBbe1tzGG4BSoDaieBOoYsWF 67bv3iNoun+AwL9GcWEZoGda52lxs9Z5qMgC0D/WAX5o0KxiL01r7mW0YuR+R9eLpEAu h7cUn9rEH8u+2YdvEmI6WNDVL1KJvFZn6vnqk03/E1IwJrtZYQRodIUxl8+a0GTKKinr mduA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=n1zqtffVj+e5QIYH+tiRjV15qJp6GZoBT6L+6JANVjQ=; b=vluzG0CAqw0At+11ON8K6Lpk/Q6+a3ALBdlJWJqsu4WPtpya8A9haT2txDVp/CxixE nmS6oq9lN6EWnqqRXlkVqxmQI5zKQRdn7Ubqq6s9nilblj/ui+BbP7BtIpnFBp2Iw1UE JZZ6uX5IVtRya6MW6QxdkQ3PcnUUSIOjjlB144IQNXXNVv+XtTpR+BBVl5nTNjlZlaga cat0y0WyXZY9tBBkj6jbX4WhSyIXxANjcBcaZ9XY7mANJcQnMpLNE5xSw1m4qCJxtoXN ujW8JEl/u2T/sQ7//wINLC6FlA8ioHRxbHAJ7/zrE5C6ZRCl4f+KfsyeyuRq5Tu2IdY4 CT6g== X-Gm-Message-State: ACrzQf3Zt9K2WqXJGAORDRRPS0gz2pa+x/b/ukZhZN5Vhd1Rs4yQ+RSV lbPVmuTYXZcri9n+5dtAQBErMDNg8XJ+zA== X-Google-Smtp-Source: AMsMyM5/547YBgBC/PeS6lEbsG0U2Sb8Bnz4MUDCSe1o1GkKscBZI5fGCB+EkVUCHqjH/WMQqr/cQQ== X-Received: by 2002:a05:620a:25c8:b0:6ae:2408:6e9a with SMTP id y8-20020a05620a25c800b006ae24086e9amr9874309qko.222.1664641485728; Sat, 01 Oct 2022 09:24:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 34/42] target/arm: Move be test for regime into S1TranslateResult Date: Sat, 1 Oct 2022 09:23:10 -0700 Message-Id: <20221001162318.153420-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72c; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664643516590100001 Content-Type: text/plain; charset="utf-8" Hoist this test out of arm_ld[lq]_ptw into S1_ptw_translate. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 99ad894180..d356b0b22d 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -222,6 +222,7 @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t a= ttrs) =20 typedef struct { bool is_secure; + bool be; void *hphys; hwaddr gphys; } S1TranslateResult; @@ -301,6 +302,7 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUId= x mmu_idx, !(pte_secure ? env->cp15.vstcr_el2 & VSTCR_SW : env->cp15.vtcr_el2 & VTCR_NSW)); + res->be =3D regime_translation_big_endian(env, mmu_idx); return true; =20 fail: @@ -320,7 +322,6 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr ad= dr, bool is_secure, CPUState *cs =3D env_cpu(env); S1TranslateResult s1; uint32_t data; - bool be; =20 if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, debug, &s1, fi)) { @@ -329,10 +330,9 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr a= ddr, bool is_secure, return 0; } =20 - be =3D regime_translation_big_endian(env, mmu_idx); if (likely(s1.hphys)) { /* Page tables are in RAM, and we have the host address. */ - if (be) { + if (s1.be) { data =3D ldl_be_p(s1.hphys); } else { data =3D ldl_le_p(s1.hphys); @@ -343,7 +343,7 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr ad= dr, bool is_secure, AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 - if (be) { + if (s1.be) { data =3D address_space_ldl_be(as, s1.gphys, attrs, &result); } else { data =3D address_space_ldl_le(as, s1.gphys, attrs, &result); @@ -364,7 +364,6 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr ad= dr, bool is_secure, CPUState *cs =3D env_cpu(env); S1TranslateResult s1; uint64_t data; - bool be; =20 if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, debug, &s1, fi)) { @@ -373,10 +372,9 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr a= ddr, bool is_secure, return 0; } =20 - be =3D regime_translation_big_endian(env, mmu_idx); if (likely(s1.hphys)) { /* Page tables are in RAM, and we have the host address. */ - if (be) { + if (s1.be) { data =3D ldq_be_p(s1.hphys); } else { data =3D ldq_le_p(s1.hphys); @@ -387,7 +385,7 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr ad= dr, bool is_secure, AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 - if (be) { + if (s1.be) { data =3D address_space_ldq_be(as, s1.gphys, attrs, &result); } else { data =3D address_space_ldq_le(as, s1.gphys, attrs, &result); --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664644370; cv=none; d=zohomail.com; s=zohoarc; b=B0uE7Q0X2iHOsDRyWNbZ2l/8zd6j5VAIXtSBCPndVcdDfq7re8spEAddSawtP1ZjzX2bHvLN1DhIIbKD47tjtllqF3BB4wZfYsRblepXAxKEenBknCsMEoRaXp3oCj/NbRvUA6YZw40Oa5QCWB+3g5lMnvTsEYSqz+0q8SLubOg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664644370; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bV7kcmVq1B6RlQRM4hyx85LaGxM1dlmN2rlKELHByAI=; b=aaG2DKjOeh66yDiDqCvXbU2dGkqlT29am8q+u8WKWApKwja9mwV4JlD7wnyycJWnhPIvoTMNqv7ECx2pus82de6JSvYvNtYcHGtgybDdwHAq8j1bYvGBVk0IRHJUrPD20YLi4fI+P+iLQZqk/MbtnFMH7BlPXO7Ev7TtjRCgkKU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166464437080069.1765372367372; Sat, 1 Oct 2022 10:12:50 -0700 (PDT) Received: from localhost ([::1]:48160 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeg2j-0003EU-Gg for importer@patchew.org; Sat, 01 Oct 2022 13:12:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49114) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefIK-0000SM-4B for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:52 -0400 Received: from mail-qk1-x733.google.com ([2607:f8b0:4864:20::733]:35596) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefIH-0006Rg-3N for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:51 -0400 Received: by mail-qk1-x733.google.com with SMTP id u28so4542726qku.2 for ; Sat, 01 Oct 2022 09:24:48 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=bV7kcmVq1B6RlQRM4hyx85LaGxM1dlmN2rlKELHByAI=; b=wNO+RKhEOiier9Ja8cN2CqUhcHLfuUmXbtsHeOoaC7hIZcU61jqUaKlpbz5KZzdkkW XuT+oDXE6rBgd2fibngxBl1DDv4HOUack5fSmkOC06ltguzlb4syG8i8M5juC8EjUOZt q+oLySy+JElX3fSZgp0ih8SuX5Ax+B5TlseVVg35shiBV9jm28VrHnDCNUWCtbi4dFBz 3f3xbnsiNCQX/hyv2n2N1KYCycLQg3QS7+RY/fn5+rzPdVevz4pZ2WehH0zxi+pHP8m+ oluNMHQACcFJGWrHKOLr14qdhY9FSIH89ZC6XgqnvGJcfb5bXR21sdG24W37MOT3beTC XsLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=bV7kcmVq1B6RlQRM4hyx85LaGxM1dlmN2rlKELHByAI=; b=O3ZOOVQxIf1eQ+t0LyNqcDyPy+SPXPJ4TtIEy3p8WsWXjWcNt97YtG9hwf9E9B2n0w GDW0Lpg3BtY/EH1PSWPUg+TVt1FPgnd/bxbDc7EurrlPC03N7f2XpEMsOFb15r2/9mgY ZvMLmWG+HzjAc4OaerXQMv39SnWiwz08K6vc5eo4+YSr+vdeU2/fRz0us9TB6T6aTt8j g1V9vW0otpNUX+fvjq1d8CRjgLEgwUt3yo1ErADy/NVQnrPOULLcIXYCPoHG64DMI5Vh /9GOz3/BopxxaZNAmw7Wa12mount6e3JUy1+pW4jZDNoRtCojhZqErkTWJxhPKM8G56o jEbQ== X-Gm-Message-State: ACrzQf147lK0P6c0jhhBybKKHlqPufiOdy7lzV3RFCBZki/NAYLjwfNd +mJ9mmEO6pQIJTEXRGOoBuJB2RZAKjPiYw== X-Google-Smtp-Source: AMsMyM47qSh9JpKoVjg08QhcHnxSB9z0yTu8ipE7g7IClX7Z+YA61tPYEeDlheDt2F1p+tDnyTYg6g== X-Received: by 2002:a05:620a:2793:b0:6cb:c11a:130f with SMTP id g19-20020a05620a279300b006cbc11a130fmr9564402qkp.549.1664641487894; Sat, 01 Oct 2022 09:24:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 35/42] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw Date: Sat, 1 Oct 2022 09:23:11 -0700 Message-Id: <20221001162318.153420-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::733; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x733.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664644371197100001 Content-Type: text/plain; charset="utf-8" Separate S1 translation from the actual lookup. Will enable lpae hardware updates. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 92 +++++++++++++++++++++++++----------------------- 1 file changed, 48 insertions(+), 44 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index d356b0b22d..84b55b640b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -315,38 +315,29 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, } =20 /* All loads done in the course of a page table walk go through here. */ -static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUIdx ptw_idx, - bool debug, ARMMMUFaultInfo *fi) +static uint32_t arm_ldl_ptw(CPUARMState *env, const S1TranslateResult *s1, + ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); - S1TranslateResult s1; uint32_t data; =20 - if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, - debug, &s1, fi)) { - /* Failure. */ - assert(fi->s1ptw); - return 0; - } - - if (likely(s1.hphys)) { + if (likely(s1->hphys)) { /* Page tables are in RAM, and we have the host address. */ - if (s1.be) { - data =3D ldl_be_p(s1.hphys); + if (s1->be) { + data =3D ldl_be_p(s1->hphys); } else { - data =3D ldl_le_p(s1.hphys); + data =3D ldl_le_p(s1->hphys); } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs =3D { .secure =3D s1.is_secure }; + MemTxAttrs attrs =3D { .secure =3D s1->is_secure }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 - if (s1.be) { - data =3D address_space_ldl_be(as, s1.gphys, attrs, &result); + if (s1->be) { + data =3D address_space_ldl_be(as, s1->gphys, attrs, &result); } else { - data =3D address_space_ldl_le(as, s1.gphys, attrs, &result); + data =3D address_space_ldl_le(as, s1->gphys, attrs, &result); } if (unlikely(result !=3D MEMTX_OK)) { fi->type =3D ARMFault_SyncExternalOnWalk; @@ -357,38 +348,29 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr = addr, bool is_secure, return data; } =20 -static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUIdx ptw_idx, - bool debug, ARMMMUFaultInfo *fi) +static uint64_t arm_ldq_ptw(CPUARMState *env, const S1TranslateResult *s1, + ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); - S1TranslateResult s1; uint64_t data; =20 - if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, - debug, &s1, fi)) { - /* Failure. */ - assert(fi->s1ptw); - return 0; - } - - if (likely(s1.hphys)) { + if (likely(s1->hphys)) { /* Page tables are in RAM, and we have the host address. */ - if (s1.be) { - data =3D ldq_be_p(s1.hphys); + if (s1->be) { + data =3D ldq_be_p(s1->hphys); } else { - data =3D ldq_le_p(s1.hphys); + data =3D ldq_le_p(s1->hphys); } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs =3D { .secure =3D s1.is_secure }; + MemTxAttrs attrs =3D { .secure =3D s1->is_secure }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 - if (s1.be) { - data =3D address_space_ldq_be(as, s1.gphys, attrs, &result); + if (s1->be) { + data =3D address_space_ldq_be(as, s1->gphys, attrs, &result); } else { - data =3D address_space_ldq_le(as, s1.gphys, attrs, &result); + data =3D address_space_ldq_le(as, s1->gphys, attrs, &result); } if (unlikely(result !=3D MEMTX_OK)) { fi->type =3D ARMFault_SyncExternalOnWalk; @@ -520,6 +502,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, int domain =3D 0; int domain_prot; hwaddr phys_addr; + S1TranslateResult s1; uint32_t dacr; =20 /* Pagetable walk. */ @@ -529,7 +512,11 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_= t address, fi->type =3D ARMFault_Translation; goto do_fault; } - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, debug, f= i); + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, table, + is_secure, debug, &s1, fi)) { + goto do_fault; + } + desc =3D arm_ldl_ptw(env, &s1, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -567,7 +554,11 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_= t address, /* Fine pagetable. */ table =3D (desc & 0xfffff000) | ((address >> 8) & 0xffc); } - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, debu= g, fi); + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, table, + is_secure, debug, &s1, fi)) { + goto do_fault; + } + desc =3D arm_ldl_ptw(env, &s1, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -643,6 +634,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, int domain_prot; hwaddr phys_addr; uint32_t dacr; + S1TranslateResult s1; bool ns; =20 /* Pagetable walk. */ @@ -652,7 +644,11 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_= t address, fi->type =3D ARMFault_Translation; goto do_fault; } - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, debug, f= i); + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, table, + is_secure, debug, &s1, fi)) { + goto do_fault; + } + desc =3D arm_ldl_ptw(env, &s1, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -705,7 +701,11 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_= t address, ns =3D extract32(desc, 3, 1); /* Lookup l2 entry. */ table =3D (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, debu= g, fi); + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, table, + is_secure, debug, &s1, fi)) { + goto do_fault; + } + desc =3D arm_ldl_ptw(env, &s1, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -1281,14 +1281,18 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, */ tableattrs =3D is_secure ? 0 : (1 << 4); for (;;) { + S1TranslateResult s1; uint64_t descriptor; bool nstable; =20 descaddr |=3D (address >> (stride * (4 - level))) & indexmask; descaddr &=3D ~7ULL; nstable =3D extract32(tableattrs, 4, 1); - descriptor =3D arm_ldq_ptw(env, descaddr, !nstable, mmu_idx, - ptw_idx, debug, fi); + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, descaddr, + !nstable, debug, &s1, fi)) { + goto do_fault; + } + descriptor =3D arm_ldq_ptw(env, &s1, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=uo3G0jvzPeglF/SX1GKlp5DbZMlHCpPo+axikVVXW7s=; b=qoFTjBbC9GjlmIYa974l+7+tbswJ7QCI5slHd3RCcNI7XtqZzXonvsiDtIFiR5Pl+b ktaAm5xnum9PaFWw5mu9U0zV7bKzTuOdS2LfnQxtbGh/Sl7GnWc6JBzYlvO9uipOCPds Hu3O515zeWsKfEn2Yijgv+omBzElzolnrg8GwkvjU+HpxWOxV3vl13riuSS1lHK705aB R16cc0eR4XIGToBLXWBvztmM2tisC7skPU23iuFwyWRrSEEj6DDZ2Ic1c+m55SB4sLbw Z3VH1i9ppf33Ym7j27TgSl0Ws2vTGLyapCnzBDa65t67gL85hBSnfeBCLKZIUl6wvors ukxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=uo3G0jvzPeglF/SX1GKlp5DbZMlHCpPo+axikVVXW7s=; b=4/n8gKK8WxgKGWcLbE+XSZnOkpG6Gd74nT24adYahqB5fj0VZyY2QuEyaxaqny22TG 6+ToaSJwylAdY8YUhR38TyLanVHB7an7xkQ/VP4pdA8bOidWWKBDiFraNtmzZeuFZsL7 v4PDrxpp163V9XFLr2c53l2gOvY9/fjHQmHX5o32gkbZAI7YjMMiC+FoMFbYIr5iqdFU 6xUtU8Ws2svL712jfuDA3XPyAEfXN9knV1g2s423uS+T7QvZRsRouDTDgaRz2W2Bj080 siPCwr/ibKH/tTHcYrpDaFmfZXSeIqMz45oevlEs5fRIyekUiu9Pxzq1ScS/CdBOp3ss fBYA== X-Gm-Message-State: ACrzQf3XCjdK0b+hcMw8mo4Kc1P/VjKgdbWpoH/6iF8DMDjtG6K5Jc8E 3jvc0BOHcreneOOW3UlJ5JljvTmXVuNNyA== X-Google-Smtp-Source: AMsMyM5sjiMwyk60zWGkxtMzIkfuDgQORpe84I4oKeuRBe5Uf+6/OTAaEpIevXqAdl2yAz7LKQl9Fg== X-Received: by 2002:a05:620a:271b:b0:6cd:fd1f:7472 with SMTP id b27-20020a05620a271b00b006cdfd1f7472mr9654125qkp.142.1664641490011; Sat, 01 Oct 2022 09:24:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 36/42] target/arm: Add ARMFault_UnsuppAtomicUpdate Date: Sat, 1 Oct 2022 09:23:12 -0700 Message-Id: <20221001162318.153420-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::736; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x736.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664642794061100001 Content-Type: text/plain; charset="utf-8" This fault type is to be used with FEAT_HAFDBS when the guest enables hw updates, but places the tables in memory where atomic updates are unsupported. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index e95b6b1b8f..4a2b1ec31c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -338,6 +338,7 @@ typedef enum ARMFaultType { ARMFault_AsyncExternal, ARMFault_Debug, ARMFault_TLBConflict, + ARMFault_UnsuppAtomicUpdate, ARMFault_Lockdown, ARMFault_Exclusive, ARMFault_ICacheMaint, @@ -524,6 +525,9 @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *= fi) case ARMFault_TLBConflict: fsc =3D 0x30; break; + case ARMFault_UnsuppAtomicUpdate: + fsc =3D 0x31; + break; case ARMFault_Lockdown: fsc =3D 0x34; break; --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664643753; cv=none; d=zohomail.com; s=zohoarc; b=S4TOwvWJCjZUvzud7d2aU/XmFi3sdVMWPGXzR+dAUZE4CpJaRsMipFAuDHN4bvYrkDoPJC9Cj0XuRX30BlZv3zVp5DDltlaSG77dXAzXf0dRFNjA3e5TOyLimhs0u8IAr/olfKllPmnd1IsxiDa+D25YgokctbKFQSrPz3IA2lA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664643753; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=d9kz4Yl5xD4sEfVOwu1Hh/lMUPctSMFvhkB/+NtfgYo=; b=nUa/mVmcl7KNQGGkNbAf9C6WvMAdfxgfxnQ6uMvXmHzHLxGUVKXt/l3lrX4Mpa3ivMxASQjer4NTurzjUemAkJfuulVF2OvUcBIYYEwhNys9Kt/qfOMqP1oxxP1YgeOl/oKf9PBSZJZXLFVMHCIyYDCmt4BFIzRTx8ZpvQG1id0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664643753807104.63790822802605; Sat, 1 Oct 2022 10:02:33 -0700 (PDT) Received: from localhost ([::1]:57900 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oefsm-0004DU-HW for importer@patchew.org; Sat, 01 Oct 2022 13:02:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49120) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefIN-0000cW-G4 for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:55 -0400 Received: from mail-qv1-xf2a.google.com ([2607:f8b0:4864:20::f2a]:34408) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefIL-0006KI-FE for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:55 -0400 Received: by mail-qv1-xf2a.google.com with SMTP id i9so1134912qvu.1 for ; Sat, 01 Oct 2022 09:24:53 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=d9kz4Yl5xD4sEfVOwu1Hh/lMUPctSMFvhkB/+NtfgYo=; b=jem+VTRIbnclC7w2eIRNj9BnyCG5P7TvpvULDvgUhoT/S6WgMInQiSEppQf82Ja0kb I09NrhRXI+2gtWSghexSSXgkkzGfIguwzbbX/mquFCwhP1p7V1p+IfwMgE/8m0DjZOuT n2U3BQX8MTAPV/gHnw0MShWWDtPxQAMlx0fUPY6kppRSiSLIXJdnjhLfaNm5oi9tG2eM lL9C1XeK/IUk79rfNcRmmO3LabJfDKcYE5xfenSMv4kz1lYeFh6vzRIQZWGVogCIlpSQ FC3dH0neWNqjQXAegRU9kwUoXQygW1nu1pNnz6l+drrDR0qGRwuu5LdG0l4AWPhuCEuX /klw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=d9kz4Yl5xD4sEfVOwu1Hh/lMUPctSMFvhkB/+NtfgYo=; b=4AdXdyhxRbIQVPINboLIwjUyEH/LnD6HFhzbSAMCcvirtJ7Rhim2MfQ7oEkc+xMrtd LitfWL24O050+WH5UUbxe1a/clDDS/z0Ha2nO0Vr+Z42VmRAxLR/TgEJq8u3QzrYTOJE XZDafFJiPwow+8tLHgmM4VBf+PUADUfXseHPkieayhg0vAWFB5j5cDn/l0/AFPDWqzKh ayD0P4i6pd3lhSmNGK3YaEB8nhApupc3g5fEUaAcIzU7yEkrRE9pn+K/pEaCRGY+CQRq 4jJROnsvh1w32EDl8csWwZob5aorYYIDgiAt7z2bPqCDdY5+EgFYABbbkp98W0X1TQeI 4DuA== X-Gm-Message-State: ACrzQf04z/5aNeYWK+SYm/EJ98Zky5Lhfj50i7Gh9jE7aSYHrmrsSQNg IkieroHojQ3tZZ4u1s1efLk9ExKc9BcX+g== X-Google-Smtp-Source: AMsMyM602xhqu7Ru1kSL/BJI0JLsfA5SCMtp9ggW2aLbER0dhxdQ7awvK5C4SulfxPAa4oSq/mvDaQ== X-Received: by 2002:a05:6214:ac1:b0:4af:9cdb:e4f with SMTP id g1-20020a0562140ac100b004af9cdb0e4fmr11176041qvi.40.1664641492713; Sat, 01 Oct 2022 09:24:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 37/42] target/arm: Remove loop from get_phys_addr_lpae Date: Sat, 1 Oct 2022 09:23:13 -0700 Message-Id: <20221001162318.153420-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2a; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664643755824100001 Content-Type: text/plain; charset="utf-8" The unconditional loop was used both to iterate over levels and to control parsing of attributes. Use an explicit goto in both cases. While this appears less clean for iterating over levels, we will need to jump back into the middle of this loop for atomic updates, which is even uglier. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 176 +++++++++++++++++++++++------------------------ 1 file changed, 88 insertions(+), 88 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 84b55b640b..e6b385a8b1 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1082,6 +1082,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); bool guarded =3D false; + S1TranslateResult s1; + uint64_t descriptor; + bool nstable; =20 /* TODO: This code does not support shareability levels. */ if (aarch64) { @@ -1280,96 +1283,93 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, * bits at each step. */ tableattrs =3D is_secure ? 0 : (1 << 4); - for (;;) { - S1TranslateResult s1; - uint64_t descriptor; - bool nstable; =20 - descaddr |=3D (address >> (stride * (4 - level))) & indexmask; - descaddr &=3D ~7ULL; - nstable =3D extract32(tableattrs, 4, 1); - if (!S1_ptw_translate(env, mmu_idx, ptw_idx, descaddr, - !nstable, debug, &s1, fi)) { - goto do_fault; - } - descriptor =3D arm_ldq_ptw(env, &s1, fi); - if (fi->type !=3D ARMFault_None) { - goto do_fault; - } - - if (!(descriptor & 1) || - (!(descriptor & 2) && (level =3D=3D 3))) { - /* Invalid, or the Reserved level 3 encoding */ - goto do_fault; - } - - descaddr =3D descriptor & descaddrmask; - - /* - * For FEAT_LPA and PS=3D6, bits [51:48] of descaddr are in [15:12] - * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of - * descaddr are in [9:8]. Otherwise, if descaddr is out of range, - * raise AddressSizeFault. - */ - if (outputsize > 48) { - if (param.ds) { - descaddr |=3D extract64(descriptor, 8, 2) << 50; - } else { - descaddr |=3D extract64(descriptor, 12, 4) << 48; - } - } else if (descaddr >> outputsize) { - fault_type =3D ARMFault_AddressSize; - goto do_fault; - } - - if ((descriptor & 2) && (level < 3)) { - /* - * Table entry. The top five bits are attributes which may - * propagate down through lower levels of the table (and - * which are all arranged so that 0 means "no effect", so - * we can gather them up by ORing in the bits at each level). - */ - tableattrs |=3D extract64(descriptor, 59, 5); - level++; - indexmask =3D indexmask_grainsize; - continue; - } - /* - * Block entry at level 1 or 2, or page entry at level 3. - * These are basically the same thing, although the number - * of bits we pull in from the vaddr varies. Note that although - * descaddrmask masks enough of the low bits of the descriptor - * to give a correct page or table address, the address field - * in a block descriptor is smaller; so we need to explicitly - * clear the lower bits here before ORing in the low vaddr bits. - */ - page_size =3D (1ULL << ((stride * (4 - level)) + 3)); - descaddr &=3D ~(hwaddr)(page_size - 1); - descaddr |=3D (address & (page_size - 1)); - /* Extract attributes from the descriptor */ - attrs =3D extract64(descriptor, 2, 10) - | (extract64(descriptor, 52, 12) << 10); - - if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_St= age2_S) { - /* Stage 2 table descriptors do not include any attribute fiel= ds */ - break; - } - /* Merge in attributes from table descriptors */ - attrs |=3D nstable << 3; /* NS */ - guarded =3D extract64(descriptor, 50, 1); /* GP */ - if (param.hpd) { - /* HPD disables all the table attributes except NSTable. */ - break; - } - attrs |=3D extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ - /* - * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] =3D= =3D 1 - * means "force PL1 access only", which means forcing AP[1] to 0. - */ - attrs &=3D ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] =3D> = AP[1] */ - attrs |=3D extract32(tableattrs, 3, 1) << 5; /* APT[1] =3D> A= P[2] */ - break; + next_level: + descaddr |=3D (address >> (stride * (4 - level))) & indexmask; + descaddr &=3D ~7ULL; + nstable =3D extract32(tableattrs, 4, 1); + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, descaddr, + !nstable, debug, &s1, fi)) { + goto do_fault; } + descriptor =3D arm_ldq_ptw(env, &s1, fi); + if (fi->type !=3D ARMFault_None) { + goto do_fault; + } + + if (!(descriptor & 1) || (!(descriptor & 2) && (level =3D=3D 3))) { + /* Invalid, or the Reserved level 3 encoding */ + goto do_fault; + } + + descaddr =3D descriptor & descaddrmask; + + /* + * For FEAT_LPA and PS=3D6, bits [51:48] of descaddr are in [15:12] + * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of + * descaddr are in [9:8]. Otherwise, if descaddr is out of range, + * raise AddressSizeFault. + */ + if (outputsize > 48) { + if (param.ds) { + descaddr |=3D extract64(descriptor, 8, 2) << 50; + } else { + descaddr |=3D extract64(descriptor, 12, 4) << 48; + } + } else if (descaddr >> outputsize) { + fault_type =3D ARMFault_AddressSize; + goto do_fault; + } + + if ((descriptor & 2) && (level < 3)) { + /* + * Table entry. The top five bits are attributes which may + * propagate down through lower levels of the table (and + * which are all arranged so that 0 means "no effect", so + * we can gather them up by ORing in the bits at each level). + */ + tableattrs |=3D extract64(descriptor, 59, 5); + level++; + indexmask =3D indexmask_grainsize; + goto next_level; + } + + /* + * Block entry at level 1 or 2, or page entry at level 3. + * These are basically the same thing, although the number + * of bits we pull in from the vaddr varies. Note that although + * descaddrmask masks enough of the low bits of the descriptor + * to give a correct page or table address, the address field + * in a block descriptor is smaller; so we need to explicitly + * clear the lower bits here before ORing in the low vaddr bits. + */ + page_size =3D (1ULL << ((stride * (4 - level)) + 3)); + descaddr &=3D ~(page_size - 1); + descaddr |=3D (address & (page_size - 1)); + /* Extract attributes from the descriptor */ + attrs =3D extract64(descriptor, 2, 10) + | (extract64(descriptor, 52, 12) << 10); + + if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { + /* Stage 2 table descriptors do not include any attribute fields */ + goto skip_attrs; + } + /* Merge in attributes from table descriptors */ + attrs |=3D nstable << 3; /* NS */ + guarded =3D extract64(descriptor, 50, 1); /* GP */ + if (param.hpd) { + /* HPD disables all the table attributes except NSTable. */ + goto skip_attrs; + } + attrs |=3D extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ + /* + * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] =3D=3D 1 + * means "force PL1 access only", which means forcing AP[1] to 0. + */ + attrs &=3D ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] =3D> AP[1= ] */ + attrs |=3D extract32(tableattrs, 3, 1) << 5; /* APT[1] =3D> AP[2]= */ + skip_attrs: + /* * Here descaddr is the final physical address, and attributes * are all in attrs. --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664644599; cv=none; d=zohomail.com; s=zohoarc; b=b52zRae8wiIQe+P95XkIgIu2H4Iy9AmFkwZMHh1/1GBP3oA9/iodvZUH8zV8SKr9SjZqxFcccu7UZZw04OInrKz1n4YG9WEi6On2cgAJq/zFPb2XIiNNb62y/T5vP4STPUjaKyYOIZ7CM5Q90AOLAxMP53v7kICb6QyteCYzdIQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664644599; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oFbrxWVVhP20S+fjmMivVlKkgtDc/8Dpni4vZ5iFbtA=; b=dO45ItpDjqzYx+055F/tHdwkzieJq6SrRgg0urZfEORZC2ArK9S6yhkccLIBoT5buI9J75BsQh1sB5MnIVXdGHGGvJqp1ZZreBE2UngmzNJZASeBnQ+rcoGFPmE3ePX8qtiCijMu8WazyTNrTdToOfEWiuL6KTl42LwBMwEiMsg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664644599805161.71296512461367; Sat, 1 Oct 2022 10:16:39 -0700 (PDT) Received: from localhost ([::1]:38104 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeg6O-0004wr-QQ for importer@patchew.org; Sat, 01 Oct 2022 13:16:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53280) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefIQ-0000kp-28 for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:58 -0400 Received: from mail-qt1-x82b.google.com ([2607:f8b0:4864:20::82b]:35429) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefIN-0006Nb-9o for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:24:57 -0400 Received: by mail-qt1-x82b.google.com with SMTP id g23so4351921qtu.2 for ; Sat, 01 Oct 2022 09:24:54 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=oFbrxWVVhP20S+fjmMivVlKkgtDc/8Dpni4vZ5iFbtA=; b=vU6wYrs17obk+VOuEmRB21oaSwR9txXT/QMl6b74uvukqjgfMUbO6G1TTiOBx0DskI vv4C9+MClcLhODLJvWo4zKm+/QYFkix2zlKvndv9gfX8kDDm3vZZOYISfCbf3MUrZb/B 6vcrjf2QezPOBafCTssBp8OI0+ePYO7QYp6N2ojcEJrVXBzgBgrhoaFKJOvTJn0D4ghM idiwF2jTnEnpMEA0YIgwCtTPGsgcgIaX+Mr84qzLBNguHveXuTOU9G75Fr0TZ7BGL5Zj ez/sMI/9uSFzcgvXHnZahBcYwVDptqvb9lAoXHXT8+TD/F/jMEROex5Sbov3ajTaZmlA S/8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=oFbrxWVVhP20S+fjmMivVlKkgtDc/8Dpni4vZ5iFbtA=; b=V6HmMsFFObJhnRK7c/b6NsIAoA1YuaFOr7vsvAm9xXk8/ph3Ky47IL/v9MUsfVASEC BEI8ZV7sUeX2gK517PPcXtwXy/R/xpRicKde/LkG1q6GJ/5OZ7crsEmL5fwPoW0q0IpY RT2Ttp9n33FvUSQwXGPMGEXmL/XQFROIoctc7ufH8x+/WRsHhlOEfj4dh/WgIdpFge+O dzZNITdLJhly4QtE4JbyTjvp2mv51gj6Ft+DTv5kUcSGOChmDcEzO2cFTnXAlIp2XsLS VSiyiFsRKG4WQFBn83L65s+OWWVPv8SoAB+Fwmtv20GGfiMbHOwG2NgcgfC1Gts+7b/w 447w== X-Gm-Message-State: ACrzQf05eUpOt7/jSkAu2sfjK7Pa441pecgRHn5Zxj+NLUrDScga4PUB /lkCHaAuuvGUsxK5AaDNS3OjxEw6eLzjcw== X-Google-Smtp-Source: AMsMyM7mNP5uLqVjvorujFAGivQtVwSRXiI2BjXz4kHa+cvqx1huaQMJ5iVlY/QJxDqCdS+tPytP2A== X-Received: by 2002:ac8:4e48:0:b0:35d:5831:af31 with SMTP id e8-20020ac84e48000000b0035d5831af31mr11206288qtw.188.1664641494564; Sat, 01 Oct 2022 09:24:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 38/42] target/arm: Fix fault reporting in get_phys_addr_lpae Date: Sat, 1 Oct 2022 09:23:14 -0700 Message-Id: <20221001162318.153420-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82b; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664644600910100001 Content-Type: text/plain; charset="utf-8" Always overriding fi->type was incorrect, as we would not properly propagate the fault type from S1_ptw_translate, or arm_ldq_ptw. Simplify things by providing a new label for a translation fault. For other faults, store into fi directly. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e6b385a8b1..01a27b30fb 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1065,8 +1065,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) { ARMCPU *cpu =3D env_archcpu(env); - /* Read an LPAE long-descriptor translation table. */ - ARMFaultType fault_type =3D ARMFault_Translation; uint32_t level; ARMVAParameters param; uint64_t ttbr; @@ -1104,8 +1102,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, * so our choice is to always raise the fault. */ if (param.tsz_oob) { - fault_type =3D ARMFault_Translation; - goto do_fault; + goto do_translation_fault; } =20 addrsize =3D 64 - 8 * param.tbi; @@ -1142,8 +1139,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, addrsize - inputsize); if (-top_bits !=3D param.select) { /* The gap between the two regions is a Translation fault */ - fault_type =3D ARMFault_Translation; - goto do_fault; + goto do_translation_fault; } } =20 @@ -1175,7 +1171,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, * Translation table walk disabled =3D> Translation fault on TLB m= iss * Note: This is always 0 on 64-bit EL2 and EL3. */ - goto do_fault; + goto do_translation_fault; } =20 if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2_S) { @@ -1206,8 +1202,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, if (param.ds && stride =3D=3D 9 && sl2) { if (sl0 !=3D 0) { level =3D 0; - fault_type =3D ARMFault_Translation; - goto do_fault; + goto do_translation_fault; } startlevel =3D -1; } else if (!aarch64 || stride =3D=3D 9) { @@ -1226,8 +1221,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, ok =3D check_s2_mmu_setup(cpu, aarch64, startlevel, inputsize, stride, outputsize); if (!ok) { - fault_type =3D ARMFault_Translation; - goto do_fault; + goto do_translation_fault; } level =3D startlevel; } @@ -1249,7 +1243,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, descaddr |=3D extract64(ttbr, 2, 4) << 48; } else if (descaddr >> outputsize) { level =3D 0; - fault_type =3D ARMFault_AddressSize; + fi->type =3D ARMFault_AddressSize; goto do_fault; } =20 @@ -1299,7 +1293,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, =20 if (!(descriptor & 1) || (!(descriptor & 2) && (level =3D=3D 3))) { /* Invalid, or the Reserved level 3 encoding */ - goto do_fault; + goto do_translation_fault; } =20 descaddr =3D descriptor & descaddrmask; @@ -1317,7 +1311,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, descaddr |=3D extract64(descriptor, 12, 4) << 48; } } else if (descaddr >> outputsize) { - fault_type =3D ARMFault_AddressSize; + fi->type =3D ARMFault_AddressSize; goto do_fault; } =20 @@ -1374,9 +1368,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, * Here descaddr is the final physical address, and attributes * are all in attrs. */ - fault_type =3D ARMFault_AccessFlag; if ((attrs & (1 << 8)) =3D=3D 0) { /* Access flag */ + fi->type =3D ARMFault_AccessFlag; goto do_fault; } =20 @@ -1393,8 +1387,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, p= xn); } =20 - fault_type =3D ARMFault_Permission; if (!(result->f.prot & (1 << access_type))) { + fi->type =3D ARMFault_Permission; goto do_fault; } =20 @@ -1439,8 +1433,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, result->f.lg_page_size =3D ctz64(page_size); return false; =20 -do_fault: - fi->type =3D fault_type; + do_translation_fault: + fi->type =3D ARMFault_Translation; + do_fault: fi->level =3D level; /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ fi->stage2 =3D fi->s1ptw || (mmu_idx =3D=3D ARMMMUIdx_Stage2 || --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=D/bcq+Rmc5kTJJoslvPDGiIa/oqbD812IdeJZK1JGaY=; b=hxCcT0K6+ZzCqFH5oQoUbsABqZ8bSoWdTWeORD+slU7Jvei/qRyHxbMK92KRrW2lVE EDjQP4ApwtkYIQcYY3+INFU93R1uhGEQTNL7WB1BIO8MrIufksZm/ReFFPHsw5XczItu Y2DFSNYVf3cL9REV/Ollr87AadMJ5DUkyzucuT+6H0CyAC6jZB7Hj0CsTptKSO5YCkVn UyPLcJjEv88/JdCP/7vXSsvtx0MeTdfuqqbrvm782K6K22F3jVpNBOQh/C/E3jNud55H cqnqU5tuNfKSLVtuz+Hzwnfca8u2I7hqxm7zv0cBc9vzTi30irzJVfoZk1qWscxGm+q/ rULQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=D/bcq+Rmc5kTJJoslvPDGiIa/oqbD812IdeJZK1JGaY=; b=Qg4YzDKns/VVwXTulfLOusLOcDPQW03q9If4uAKSK6I6/9lQOK7FSFbyO4cn3a1dAe nnFA4jQfhlWzrOQejOq6/3BzoUgGCTeQWKPuo6ayh9AD0DwYhjgNRtrylod00a9+Q0vK e5gfSdnc5DTgfPq5tHQgvR+JpI5xfat1IW17nkTiKot0JcJg1X49njmLBCqJkxMVT2UW PxbliW0uvoMP2DZ185mf1BdvEOVbZVhn5IW3KRo5FIBGytD7uHHzjgYXvgFdMyYGLrSo deeGrAgQPfgTz5U5I3j0S5RvqoUwNg7u4YGiJVVwiuD3Bo0kB0G4CcfGBpQm1xamoduv Mo1A== X-Gm-Message-State: ACrzQf0z6wz7Q0mLbsrhpPe/qmxpmoDkRWDfAzgBo0Ya+JGd6QO4GJt1 N/0SWrtQgKUiEzWkN8o0wuba7HKknUbsaQ== X-Google-Smtp-Source: AMsMyM6+ZkdPFelLhLUvDt+a1W94xA6vC7yxhl7XuHJk+XGh599RmMXPABwqYhAasl+2sG9T7aplUQ== X-Received: by 2002:a37:a83:0:b0:6cf:8255:8676 with SMTP id 125-20020a370a83000000b006cf82558676mr9568666qkk.628.1664641496986; Sat, 01 Oct 2022 09:24:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 39/42] target/arm: Don't shift attrs in get_phys_addr_lpae Date: Sat, 1 Oct 2022 09:23:15 -0700 Message-Id: <20221001162318.153420-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::734; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x734.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664643872416100001 Content-Type: text/plain; charset="utf-8" Leave the upper and lower attributes in the place they originate from in the descriptor. Shifting them around is confusing, since one cannot read the bit numbers out of the manual. Also, new attributes have been added which would alter the shifts. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 01a27b30fb..c68fd73617 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1071,7 +1071,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, hwaddr descaddr, indexmask, indexmask_grainsize; uint32_t tableattrs; target_ulong page_size; - uint32_t attrs; + uint64_t attrs; int32_t stride; int addrsize, inputsize, outputsize; uint64_t tcr =3D regime_tcr(env, mmu_idx); @@ -1341,49 +1341,48 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, descaddr &=3D ~(page_size - 1); descaddr |=3D (address & (page_size - 1)); /* Extract attributes from the descriptor */ - attrs =3D extract64(descriptor, 2, 10) - | (extract64(descriptor, 52, 12) << 10); + attrs =3D descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(52, 1= 2)); =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { /* Stage 2 table descriptors do not include any attribute fields */ goto skip_attrs; } /* Merge in attributes from table descriptors */ - attrs |=3D nstable << 3; /* NS */ + attrs |=3D nstable << 5; /* NS */ guarded =3D extract64(descriptor, 50, 1); /* GP */ if (param.hpd) { /* HPD disables all the table attributes except NSTable. */ goto skip_attrs; } - attrs |=3D extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ + attrs |=3D extract64(tableattrs, 0, 2) << 53; /* XN, PXN */ /* * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] =3D=3D 1 * means "force PL1 access only", which means forcing AP[1] to 0. */ - attrs &=3D ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] =3D> AP[1= ] */ - attrs |=3D extract32(tableattrs, 3, 1) << 5; /* APT[1] =3D> AP[2]= */ + attrs &=3D ~(extract64(tableattrs, 2, 1) << 6); /* !APT[0] =3D> AP[1= ] */ + attrs |=3D extract32(tableattrs, 3, 1) << 7; /* APT[1] =3D> AP[2]= */ skip_attrs: =20 /* * Here descaddr is the final physical address, and attributes * are all in attrs. */ - if ((attrs & (1 << 8)) =3D=3D 0) { + if ((attrs & (1 << 10)) =3D=3D 0) { /* Access flag */ fi->type =3D ARMFault_AccessFlag; goto do_fault; } =20 - ap =3D extract32(attrs, 4, 2); + ap =3D extract32(attrs, 6, 2); =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { ns =3D mmu_idx =3D=3D ARMMMUIdx_Stage2; - xn =3D extract32(attrs, 11, 2); + xn =3D extract64(attrs, 54, 2); result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); } else { - ns =3D extract32(attrs, 3, 1); - xn =3D extract32(attrs, 12, 1); - pxn =3D extract32(attrs, 11, 1); + ns =3D extract32(attrs, 5, 1); + xn =3D extract64(attrs, 54, 1); + pxn =3D extract64(attrs, 53, 1); result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, p= xn); } =20 @@ -1408,10 +1407,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { result->cacheattrs.is_s2_format =3D true; - result->cacheattrs.attrs =3D extract32(attrs, 0, 4); + result->cacheattrs.attrs =3D extract32(attrs, 2, 4); } else { /* Index into MAIR registers for cache attributes */ - uint8_t attrindx =3D extract32(attrs, 0, 3); + uint8_t attrindx =3D extract32(attrs, 2, 3); uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; assert(attrindx <=3D 7); result->cacheattrs.is_s2_format =3D false; @@ -1426,7 +1425,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, if (param.ds) { result->cacheattrs.shareability =3D param.sh; } else { - result->cacheattrs.shareability =3D extract32(attrs, 6, 2); + result->cacheattrs.shareability =3D extract32(attrs, 8, 2); } =20 result->f.phys_addr =3D descaddr; --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664644758; cv=none; d=zohomail.com; s=zohoarc; b=TxJ+kG0xStCmxSz8MpkvgRTI3BRTsKzd5ZDjshxljbuINB6ruSngT1l+9O2gUMJJjHuBJ8OS2Mi6LoYWLWn3Cxwkcps2BjwRe7flum1rN8QbrjxmPMvHuIENTZCfMCamJB05ZtznX7b+bMXAnDB5rIlXRyJv6Y9df0ypXVfGVRg= ARC-Message-Signature: i=1; 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([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id i19-20020a05620a249300b006b5e296452csm6403305qkn.54.2022.10.01.09.28.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:28:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=c3faqUVexkW9Ve/ySw7NotLcZ32qWMzAZ3wh+jbFG0Y=; b=S461/8spdNdshMllW4X9a3n2XFBsfMMa86ssRTXrrRk/x2VKBlvmFHkA+qgk5hzsVj LfPP5Nr4ncNHEdMiLcyDLDjFiCw3fOSSIzG1PLlQEIp6jmvuXbZIJO8YKoPNdnhRlK3e XXziGJNfa/vLt1MEf0I7fSfTqDZfIdxd7nPtBHxKTImUfm7GDvHyqkp3pEWEn16JygsN yBDHgcVsySynVmTOpypqo6PSU2ol/0o88rmZm3wyh5MwC3XQZgn9jABKUo6QVYv6X8A/ V9bKNPD6s8KI/c3q1awNgfdvR7gA+s0xxhMklyNmNguX8inZluGG59XM/lQBRbMWjipY qVRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=c3faqUVexkW9Ve/ySw7NotLcZ32qWMzAZ3wh+jbFG0Y=; b=PIpvFcJ3R8p5KUrY9/IaM2ts/ejVqVtNP76MBnYAKT6s6h6pRYytHVceC8Lz9VyLL+ vqOKAjYOI0GnFHqu9+2QdopoWeTfKsXC+v/GYwl/9KXrK3LYWPn/V2WccYeWMGMi+0Xa ob7i2uJrfF2VZ7znw0w8hySnE5UILYAIz0yzGnFWHiW39Dxd3MIX2Y1lcPH0Ra+TIE8Y TDkgrTKycu1RVDUgENVI6j/V0MA8mci0KKIfVlRUW3MBFhOVWQs/MnP99YYan9lvzkCC 6j00jA9m7tEvXntSubITMK08eZj0E7Xkp9L9XeQ2YR6+COleugimT2CGEcYYBkOcCBUk h32A== X-Gm-Message-State: ACrzQf2/nDjtP5wa8SUjrtPehTtdIQoInbvednDhxdxJ1cxrmI/Yx2dl NOMGvpIqTysTQOG3x0PHgP5xEA7WyOin9A== X-Google-Smtp-Source: AMsMyM4v1FDZRHiNn2L89BWxBYfNoyJLrlfRoUr5tZbDh09kQKWxxfiPsSTClnkhY2065NBRApG51A== X-Received: by 2002:a05:620a:1727:b0:6ce:9b88:92aa with SMTP id az39-20020a05620a172700b006ce9b8892aamr9698822qkb.160.1664641682742; Sat, 01 Oct 2022 09:28:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 40/42] target/arm: Consider GP an attribute in get_phys_addr_lpae Date: Sat, 1 Oct 2022 09:23:16 -0700 Message-Id: <20221001162318.153420-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72b; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664644760014100001 Content-Type: text/plain; charset="utf-8" Both GP and DBM are in the upper attribute block. Extend the computation of attrs to include them, then simplify the setting of guarded. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index c68fd73617..45734b0d28 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1079,7 +1079,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, uint32_t el =3D regime_el(env, mmu_idx); uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); - bool guarded =3D false; S1TranslateResult s1; uint64_t descriptor; bool nstable; @@ -1341,7 +1340,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, descaddr &=3D ~(page_size - 1); descaddr |=3D (address & (page_size - 1)); /* Extract attributes from the descriptor */ - attrs =3D descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(52, 1= 2)); + attrs =3D descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50, 1= 4)); =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { /* Stage 2 table descriptors do not include any attribute fields */ @@ -1349,7 +1348,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, } /* Merge in attributes from table descriptors */ attrs |=3D nstable << 5; /* NS */ - guarded =3D extract64(descriptor, 50, 1); /* GP */ if (param.hpd) { /* HPD disables all the table attributes except NSTable. */ goto skip_attrs; @@ -1402,7 +1400,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, =20 /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. = */ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { - result->f.guarded =3D guarded; + result->f.guarded =3D extract64(attrs, 50, 1); /* GP */ } =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664644872; cv=none; d=zohomail.com; s=zohoarc; b=AG7Iu1QWiGKeEwcruMm5qfP2Gl7eXY7LxDb5TaauMJwHzr4alpRcxoqYolx2OLYNY9fAgiZxXwmikbopYs4Y0GNdVhStmhRA5gmQBZ/bRznT0QG2yFzeYpJJciQWt5P/pTlUyrAT+Y/dYjr4Ze7+oa4l9VGaLl9RG0ZgB+pIVVU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664644872; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8bt/ljGVvBvksdluIpA9+aSBfVlrp86kwVwyB2a9tgo=; b=cxShvdPdFx0n49h8csOAvOe7CBVJUcTl0fyYPcbLvBHXZQAY4CYZno+D+bHk7mnTcI3cWwd7+9NDnJ29IM+Iv7u8aV6GauGArn7WJqoMS5Jf04+JuJL1/NYoHFSAz9kQHDoTBxqK+SwX30qhUDAxrc2xhXnzjItpn1Fbd4WVgHo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664644872243989.0729206815356; Sat, 1 Oct 2022 10:21:12 -0700 (PDT) Received: from localhost ([::1]:51192 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oegAp-0000E2-9L for importer@patchew.org; Sat, 01 Oct 2022 13:21:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58878) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oefLU-0008Bd-Cw for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:28:08 -0400 Received: from mail-qv1-xf33.google.com ([2607:f8b0:4864:20::f33]:39785) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oefLS-000744-55 for qemu-devel@nongnu.org; Sat, 01 Oct 2022 12:28:07 -0400 Received: by mail-qv1-xf33.google.com with SMTP id z18so4443139qvn.6 for ; Sat, 01 Oct 2022 09:28:05 -0700 (PDT) Received: from stoup.. ([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id i19-20020a05620a249300b006b5e296452csm6403305qkn.54.2022.10.01.09.28.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:28:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=8bt/ljGVvBvksdluIpA9+aSBfVlrp86kwVwyB2a9tgo=; b=aAcIh1HDg7NEWV8Vhtaua50eUioEWuQjJeEg+9Luqcn3NG96AqjVe4v7YmdkUkyk9j /VR9NoI1GWb+4j+5oCUpKV4vEc+Iw0o+Rj27K4iCVnnvVxZCs44E1FXEsUQFORMboGRD yvzq60/1UGqxX7PzYrUr0Fe5p74QvxLEwwjKhmkETpVdBRvouoWiBA566tXpgK/ZorLN R+kWEEvH1InzUWrSUgg9Zcr3LMx1Xzmp8gZDP4fyv/JmTwliYZmlegGySTOs4mGE2a+3 /eICWoQdqvVw7ZwZ0sLBKpMyph72rg7Q7LMVlw5Q2gggTenEkfadCO5fkdovNqU/8+Ju 4R5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=8bt/ljGVvBvksdluIpA9+aSBfVlrp86kwVwyB2a9tgo=; b=uuaKrYxdDdfs4ICKx4rWGiqU3dVUu3/HODJ+E0+VHfBzibfvwDgWarkIZBuYsaK9t5 7NeoVyB6QuuThG33gicxwI3EAU+JDoeub/k0LFu0UXv+PejAydfFVNtMqNlIOj5MO2rg hTvCXuRfP3EqEcOOoZWzQir2+aUfU8SmLsTOvdv271ibSRo3G7Ky/vIvHjqy0kTKKvq0 eJFRvwwk/u/8hb4sqr/SdJ/kcpx5WdmDXWynhasOU0IAULMJRfQw+GkWkZhoPGATO4J6 P6h50VHbMAQdHdAT0a6yHILyx6SGmBClwDPfcDKpgGCM1qbGqnjGqmHw1jBvkacknw/P JnYA== X-Gm-Message-State: ACrzQf2IxAvXWxTt7lL8Euv3vEd0qg/s7qST8EIgSCEaJphafvcmdorZ Rv1Flu2aMCExw6xsWcPdUaz6SpEBiRAuKA== X-Google-Smtp-Source: AMsMyM4kWgc+t2D+z/3FNSDHyFzl4EHVXhxSfR+iPF1w5BNwsIsb/aDI7d/hLsH9e17IeMvguV/CUA== X-Received: by 2002:a05:6214:5295:b0:4ac:ae7d:6a46 with SMTP id kj21-20020a056214529500b004acae7d6a46mr11402457qvb.131.1664641684920; Sat, 01 Oct 2022 09:28:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 41/42] target/arm: Implement FEAT_HAFDBS Date: Sat, 1 Oct 2022 09:23:17 -0700 Message-Id: <20221001162318.153420-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f33; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664644874279100001 Content-Type: text/plain; charset="utf-8" Perform the atomic update for hardware management of the access flag and the dirty bit. A limitation of the implementation so far is that the page table itself must already be writable, i.e. the dirty bit for the stage2 page table must already be set, i.e. we cannot set both dirty bits at the same time. This is allowed because it is CONSTRAINED UNPREDICTABLE whether any atomic update happens at all. The implementation is allowed to simply fall back on software update at any time. Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/ptw.c | 119 ++++++++++++++++++++++++++++++++-- 3 files changed, 115 insertions(+), 6 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index be7bbffe59..c3582d075e 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -31,6 +31,7 @@ the following architecture extensions: - FEAT_FRINTTS (Floating-point to integer instructions) - FEAT_FlagM (Flag manipulation instructions v2) - FEAT_FlagM2 (Enhancements to flag manipulation instructions) +- FEAT_HAFDBS (Hardware management of the access flag and dirty bit state) - FEAT_HCX (Support for the HCRX_EL2 register) - FEAT_HPDS (Hierarchical permission disables) - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e6314e86d2..b064dc7964 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1116,6 +1116,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D t; =20 t =3D cpu->isar.id_aa64mmfr1; + t =3D FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 45734b0d28..14ab56d1b5 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -223,6 +223,7 @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t a= ttrs) typedef struct { bool is_secure; bool be; + bool rw; void *hphys; hwaddr gphys; } S1TranslateResult; @@ -261,7 +262,8 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUId= x mmu_idx, pte_attrs =3D s2.cacheattrs.attrs; pte_secure =3D s2.f.attrs.secure; } - res->hphys =3D NULL; + res->hphys =3D NULL; /* force slow path */ + res->rw =3D false; /* debug never modifies */ } else { CPUTLBEntryFull *full; int flags; @@ -276,6 +278,7 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUId= x mmu_idx, goto fail; } res->gphys =3D full->phys_addr; + res->rw =3D full->prot & PAGE_WRITE; pte_attrs =3D full->pte_attrs; pte_secure =3D full->attrs.secure; } @@ -381,6 +384,56 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, const S1= TranslateResult *s1, return data; } =20 +static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, + uint64_t new_val, const S1TranslateResult *s1, + ARMMMUFaultInfo *fi) +{ + uint64_t cur_val; + + if (unlikely(!s1->hphys)) { + fi->type =3D ARMFault_UnsuppAtomicUpdate; + fi->s1ptw =3D true; + return 0; + } + +#ifndef CONFIG_ATOMIC64 + /* + * We can't support the atomic operation on the host. We should be + * running in round-robin mode though, which means that we would only + * race with dma i/o. + */ + qemu_mutex_lock_iothread(); + if (s1->be) { + cur_val =3D ldq_be_p(s1->hphys); + if (cur_val =3D=3D old_val) { + stq_be_p(s1->hphys, new_val); + } + } else { + cur_val =3D ldq_le_p(s1->hphys); + if (cur_val =3D=3D old_val) { + stq_le_p(s1->hphys, new_val); + } + } + qemu_mutex_unlock_iothread(); +#else + if (s1->be) { + old_val =3D cpu_to_be64(old_val); + new_val =3D cpu_to_be64(new_val); + cur_val =3D qatomic_cmpxchg__nocheck((uint64_t *)s1->hphys, + old_val, new_val); + cur_val =3D be64_to_cpu(cur_val); + } else { + old_val =3D cpu_to_le64(old_val); + new_val =3D cpu_to_le64(new_val); + cur_val =3D qatomic_cmpxchg__nocheck((uint64_t *)s1->hphys, + old_val, new_val); + cur_val =3D le64_to_cpu(cur_val); + } +#endif + + return cur_val; +} + static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, uint32_t *table, uint32_t address) { @@ -1290,6 +1343,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, goto do_fault; } =20 + restart_atomic_update: if (!(descriptor & 1) || (!(descriptor & 2) && (level =3D=3D 3))) { /* Invalid, or the Reserved level 3 encoding */ goto do_translation_fault; @@ -1365,10 +1419,28 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, * Here descaddr is the final physical address, and attributes * are all in attrs. */ - if ((attrs & (1 << 10)) =3D=3D 0) { + if ((attrs & (1 << 10)) =3D=3D 0 && !debug) { /* Access flag */ - fi->type =3D ARMFault_AccessFlag; - goto do_fault; + uint64_t new_des, old_des; + + /* + * If HA is disabled, or if the pte is not writable, + * pass on the access fault to software. + */ + if (!param.ha || !s1.rw) { + fi->type =3D ARMFault_AccessFlag; + goto do_fault; + } + + old_des =3D descriptor; + new_des =3D descriptor | (1 << 10); /* AF */ + descriptor =3D arm_casq_ptw(env, old_des, new_des, &s1, fi); + if (fi->type !=3D ARMFault_None) { + goto do_fault; + } + if (old_des !=3D descriptor) { + goto restart_atomic_update; + } } =20 ap =3D extract32(attrs, 6, 2); @@ -1385,8 +1457,43 @@ static bool get_phys_addr_lpae(CPUARMState *env, uin= t64_t address, } =20 if (!(result->f.prot & (1 << access_type))) { - fi->type =3D ARMFault_Permission; - goto do_fault; + uint64_t new_des, old_des; + + /* Writes may set dirty if DBM attribute is set. */ + if (!param.hd + || access_type !=3D MMU_DATA_STORE + || !extract64(attrs, 51, 1) /* DBM */ + || !s1.rw) { + fi->type =3D ARMFault_Permission; + goto do_fault; + } + + old_des =3D descriptor; + if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_St= age2_S) { + new_des =3D descriptor | (1ull << 7); /* S2AP[1] */ + } else { + new_des =3D descriptor & ~(1ull << 7); /* AP[2] */ + } + + /* + * If the descriptor didn't change, then attributes weren't the + * reason for the permission fault, so deliver it. + */ + if (old_des =3D=3D new_des) { + fi->type =3D ARMFault_Permission; + goto do_fault; + } + + descriptor =3D arm_casq_ptw(env, old_des, new_des, &s1, fi); + if (fi->type !=3D ARMFault_None) { + goto do_fault; + } + if (old_des !=3D descriptor) { + goto restart_atomic_update; + } + + /* Success: the page is now writable. */ + result->f.prot |=3D 1 << MMU_DATA_STORE; } =20 if (ns) { --=20 2.34.1 From nobody Tue May 7 12:34:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664644058; cv=none; d=zohomail.com; s=zohoarc; b=FljSfJikFIfpUY8tdIf9XCFAqBkBsxw2iqClpqMLluj/1If2s7zC1uCMS3fEdb6oVdaLQ7qAxvylMh2g78INnkMce9okX0SKWvSKJr8rrqlx7S/3o3PMA+0LFKSMq8v1JWxDPft2bEj/gjTS+6UiQKjogB7POIVswMKbl8Otdz4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664644058; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id i19-20020a05620a249300b006b5e296452csm6403305qkn.54.2022.10.01.09.28.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:28:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=iKmDVfGqOt9FVdwkjo2E3YIFL8ZFEk46sXJgTciBX1Q=; b=WeqX6DrD6GjetwekiLJvwL2oQP0X/CVIfAeIX/AnA4utc/2GL/R0RCSwNliLrrcvhv hCByEvsiGkFAHaNu5IDG1nfB5l55FH9AMan7bhHkh6Mg88lTvao2C2fHq9ONAgQ7wKRr VleA79+9N+DWDXtLAV1GkpwKFPmGbiWKVbyLQpSh/y0eLG5DiRu36JRvDcbmvqXOFR3i NXYfiekrT/0zYEvpVvMTIuD+t457LHe/qtLzDakmBlJToC6DjHHnGG1vwAnRh2/R8ksH eRXY1uHO/kPIt+OAaOAgfMQNWg+EbT+QwfR5kdCT46DSU6mmiirSf9JvwYnyhO0bDwwS vFoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=iKmDVfGqOt9FVdwkjo2E3YIFL8ZFEk46sXJgTciBX1Q=; b=ve2g1JxUe2/UPwKTKp91Y4bCk+M3vN5wrZ14tfNJUwu+SXSTcegQ2w4txr++Uev6Ji dl9qu2MoxVaGO7rf6OfMFuKnju70z5FwJCLBU/runkjlTQYyjGqu9H4d552b7aXo/9F+ EsYHwbVCO5UGq/RQpYWkSSfU/6YmYXvszQvsTGvU4fjywhoyPeSppgp3gMhVy7Vi762R M+04tDTI3Va6jgRFbzyGKZ8L6ACRGbYUv8Z37JIQUM7a/9gPF59zmzWQspbpAlI5qncU A6DGlUHRMLc5xxci+GLvOhQcf2aWb4/I2Wkg23rCJ65u4HuZVkdJShVAfcC0ww3ECoQe vcrA== X-Gm-Message-State: ACrzQf3vGf7hzAgt9IlFjFgKpoYveVg/5xz0LbM+xs1HuSSIrG/m3J5Q wQ1LazF/CRTPbmFVxqN17IqWLbzEl253Og== X-Google-Smtp-Source: AMsMyM7u4ymHwfOHhyhZQdJKNntM4ObsrFfNAktErztb3ICTxYWT/zMabg6McHFPvAaphxUfHibhew== X-Received: by 2002:ac8:5909:0:b0:35b:ce5c:ed73 with SMTP id 9-20020ac85909000000b0035bce5ced73mr10918232qty.635.1664641687726; Sat, 01 Oct 2022 09:28:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Marc Zyngier Subject: [PATCH v3 42/42] target/arm: Use the max page size in a 2-stage ptw Date: Sat, 1 Oct 2022 09:23:18 -0700 Message-Id: <20221001162318.153420-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82a; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664644059411100001 Content-Type: text/plain; charset="utf-8" We had only been reporting the stage2 page size. This causes problems if stage1 is using a larger page size (16k, 2M, etc), but stage2 is using a smaller page size, because cputlb does not set large_page_{addr,mask} properly. Fix by using the max of the two page sizes. Reported-by: Marc Zyngier Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 14ab56d1b5..985a5703c3 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2550,7 +2550,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = target_ulong address, ARMMMUFaultInfo *fi) { hwaddr ipa; - int s1_prot; + int s1_prot, s1_lgpgsz; bool ret, ipa_secure, s2walk_secure; ARMCacheAttrs cacheattrs1; ARMMMUIdx s2_mmu_idx, s2_ptw_idx; @@ -2592,6 +2592,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = target_ulong address, * Save the stage1 results so that we may merge prot and cacheattrs la= ter. */ s1_prot =3D result->f.prot; + s1_lgpgsz =3D result->f.lg_page_size; cacheattrs1 =3D result->cacheattrs; memset(result, 0, sizeof(*result)); =20 @@ -2607,6 +2608,14 @@ static bool get_phys_addr_twostage(CPUARMState *env,= target_ulong address, return ret; } =20 + /* + * Use the maximum of the S1 & S2 page size, so that invalidation + * of pages > TARGET_PAGE_SIZE works correctly. + */ + if (result->f.lg_page_size < s1_lgpgsz) { + result->f.lg_page_size =3D s1_lgpgsz; + } + /* Combine the S1 and S2 cache attributes. */ hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); if (hcr & HCR_DC) { --=20 2.34.1