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([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id o15-20020a05620a22cf00b006bb78d095c5sm3196055qki.79.2022.09.30.15.03.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 15:03:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=XYRaFM7NBrkMyyb5R6XrzLrGa558v90pQOaMAn7lGPk=; b=rI6yTkKjofz8jEr9XLfNhWVOBExlrXv/bvy9Ps5Oq3kW3b4e7ChbvYn8HZAmrLE6Ox f1Hqyc9CXBY/ETROk3RBeASrGPIxzzgB1ASOouXy+gJQKnqWUpfXQQLo3hvajTRX84qQ 5inH7n1LO54jzEJUSvPdC0nFe+zITo9p2z/545v1ft66A3+4jxUMH8TMQGTwlpgsoKmc Aphvnp/z96pTDX9tQsOkmsFIw+5lGcODobV846xYqShWSZ7uRI7FVeTd2DVMCvEqUbWs jAwLIBcIA40Iw3gEvjDAVYMf897Gjcw+jNGEvKJtgvLLKjWtEES22mPPrEHKr5UlX+zm QgNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=XYRaFM7NBrkMyyb5R6XrzLrGa558v90pQOaMAn7lGPk=; b=lINdkI/GKv4EGeViwl3aA+TMtEXaM5D53VHD3BND63h7d6+b3oWoyg94JwAUMFIx1f +bbokk6GbwUlVwiBIq9v0HaIP/oGkPHiJi38LUqRAUg/FS9dEfznH5DlwOKV2g0bmylP 8ifM3xPvzw3PMaCV7WdEvYabIBTaWCsrzyrpqnOmWqlSVeu3q6n0W2DBmis09xsTDh7z OtiIkoDxGoesknvenGUxaDTl/h5OSyurunnhNQ+kYsvZMLvd2A61PazFkDXpW+oa6oe4 cThNysRLef2g0WWYDlJ7MMVoGQ3JuzmGO8JBTrlL/9nDEuyzwR6rj9WYWkJiGSsB6Ieu 8OHw== X-Gm-Message-State: ACrzQf1acf+CJMidZYn8iFP4MSSsAHYFAZYxezx8cApiHW9s+hSEDehg ARFy0QsBDLy/vVyOKBmP851QIebDY/JI5g== X-Google-Smtp-Source: AMsMyM54ZInEKTg3jJAygSqf3yAoEI7JHvmcQwAbe3bchghiku3HWD3iBIs2ROufoaYzRVBYogS4BQ== X-Received: by 2002:a05:6214:21a5:b0:4af:b677:7429 with SMTP id t5-20020a05621421a500b004afb6777429mr5700033qvc.60.1664575410834; Fri, 30 Sep 2022 15:03:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 8/9] target/arm: Introduce gen_pc_plus_diff for aarch32 Date: Fri, 30 Sep 2022 15:03:11 -0700 Message-Id: <20220930220312.135327-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930220312.135327-1-richard.henderson@linaro.org> References: <20220930220312.135327-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f30; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664575847014100001 In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/translate.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index fd35db8c8c..050da9e740 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -276,11 +276,16 @@ static target_long jmp_diff(DisasContext *s, target_l= ong diff) return diff + (s->thumb ? 4 : 8); } =20 +static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, target_long di= ff) +{ + tcg_gen_movi_i32(var, s->pc_curr + diff); +} + /* Set a variable to the value of a CPU register. */ void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) { if (reg =3D=3D 15) { - tcg_gen_movi_i32(var, read_pc(s)); + gen_pc_plus_diff(s, var, jmp_diff(s, 0)); } else { tcg_gen_mov_i32(var, cpu_R[reg]); } @@ -296,7 +301,8 @@ TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int = ofs) TCGv_i32 tmp =3D tcg_temp_new_i32(); =20 if (reg =3D=3D 15) { - tcg_gen_movi_i32(tmp, (read_pc(s) & ~3) + ofs); + /* This difference computes a page offset so ok for TARGET_TB_PCRE= L. */ + gen_pc_plus_diff(s, tmp, (read_pc(s) & ~3) - s->pc_curr + ofs); } else { tcg_gen_addi_i32(tmp, cpu_R[reg], ofs); } @@ -1159,7 +1165,7 @@ void unallocated_encoding(DisasContext *s) /* Force a TB lookup after an instruction that changes the CPU state. */ void gen_lookup_tb(DisasContext *s) { - tcg_gen_movi_i32(cpu_R[15], s->base.pc_next); + gen_pc_plus_diff(s, cpu_R[15], curr_insn_len(s)); s->base.is_jmp =3D DISAS_EXIT; } =20 @@ -6483,7 +6489,7 @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a) return false; } tmp =3D load_reg(s, a->rm); - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | s->thumb); gen_bx(s, tmp); return true; } @@ -8351,7 +8357,7 @@ static bool trans_B_cond_thumb(DisasContext *s, arg_c= i *a) =20 static bool trans_BL(DisasContext *s, arg_i *a) { - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | s->thumb); gen_jmp(s, jmp_diff(s, a->imm)); return true; } @@ -8370,7 +8376,7 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) if (s->thumb && (a->imm & 2)) { return false; } - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | s->thumb); store_cpu_field_constant(!s->thumb, thumb); /* This difference computes a page offset so ok for TARGET_TB_PCREL. */ gen_jmp(s, (read_pc(s) & ~3) - s->pc_curr + a->imm); @@ -8380,7 +8386,7 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) static bool trans_BL_BLX_prefix(DisasContext *s, arg_BL_BLX_prefix *a) { assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); - tcg_gen_movi_i32(cpu_R[14], read_pc(s) + (a->imm << 12)); + gen_pc_plus_diff(s, cpu_R[14], jmp_diff(s, a->imm << 12)); return true; } =20 @@ -8390,7 +8396,7 @@ static bool trans_BL_suffix(DisasContext *s, arg_BL_s= uffix *a) =20 assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); tcg_gen_addi_i32(tmp, cpu_R[14], (a->imm << 1) | 1); - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | 1); gen_bx(s, tmp); return true; } @@ -8406,7 +8412,7 @@ static bool trans_BLX_suffix(DisasContext *s, arg_BLX= _suffix *a) tmp =3D tcg_temp_new_i32(); tcg_gen_addi_i32(tmp, cpu_R[14], a->imm << 1); tcg_gen_andi_i32(tmp, tmp, 0xfffffffc); - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | 1); gen_bx(s, tmp); return true; } @@ -8729,10 +8735,11 @@ static bool op_tbranch(DisasContext *s, arg_tbranch= *a, bool half) tcg_gen_add_i32(addr, addr, tmp); =20 gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), half ? MO_UW : MO_UB); - tcg_temp_free_i32(addr); =20 tcg_gen_add_i32(tmp, tmp, tmp); - tcg_gen_addi_i32(tmp, tmp, read_pc(s)); + gen_pc_plus_diff(s, addr, jmp_diff(s, 0)); + tcg_gen_add_i32(tmp, tmp, addr); + tcg_temp_free_i32(addr); store_reg(s, 15, tmp); return true; } --=20 2.34.1