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([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id l18-20020a05620a28d200b006ce813bb306sm3696370qkp.125.2022.09.30.14.26.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 14:26:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=dAY3x/lc+/32wE3SHUuBvqOuB1dTrfgmxaF5UaNYDSM=; b=LyAx713FsGqZPlEYHubbGANF2BxE+FvOtJ1XXhRaHhGnAXLsNgW12IrrABW/ahc3jF l3GCjkHc9CnzwwS1bZQaFc+8f7JDTclY6q2xx5xh6FPo2T+rolWaC4fn/Rc2skzIiAWg WpxFQ+r4qZ92/4EFzr6hO74RcTJ1u0TT01CxeftYwUtfSY3OfdJPbiA5quMm+fq8TQpb djqRz0GVAH5F+tbFKKUTMxBZLW7E5L0d4+LHoCjqpVFRddIZa5Xs2Sv4BG5HoEYUQNup m2WRQakiwBPRhUurhSZxtwrkUs1K4DNCr+zTULKVkGCJyvOrNfT9r40qlURi4ziaewFx OyOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=dAY3x/lc+/32wE3SHUuBvqOuB1dTrfgmxaF5UaNYDSM=; b=awrky+rvJMrvPyk0i8n9yZM5eXJzh1QUbuYL7R5yRtP/ZxWw7fDyMj4GWnpM+YVH+Q /4VhCJlvHFpBu5hng+2e2SYRzCWuMu4JxgxFIPje0xYNhS/VAcIUBGUmJztn0sXzVRWl BiJ/6kbhn5kkAHc9Wg9LioL8VywCS1saEpSrqfMugOBLhqlYlsU35RLbFteIlDJRkR56 YLRGgv863n0YeVwPDgxBTwraucuwgKXDDmUNJb9u33VLfxtfEAcwnUE0RtB7uNBsTVix 2goQR4lf/YhTYEQJE527DkSNX6smhIFnl/XGidFi8QwMJA0/AG6c3D69HptRKi5xVbMy eRoQ== X-Gm-Message-State: ACrzQf2wWD56CkZXGhO+EXvFGBizcnLQVHO8whgku6JQemqVGvgEfgn8 4XAiLAtD+JrsvyogeIfkhwYEOpM09bfAYA== X-Google-Smtp-Source: AMsMyM4v07izf/ZTJKRya1f18YBIFiJNcTClkLbkNjBTXNc9ku9EBNIccNU5ZKlcBqLFCKpNPTthOA== X-Received: by 2002:a05:620a:99b:b0:6ce:4c0a:3ab2 with SMTP id x27-20020a05620a099b00b006ce4c0a3ab2mr7509188qkx.250.1664573205199; Fri, 30 Sep 2022 14:26:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linux.org, alex.bennee@linux.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 08/18] accel/tcg: Introduce tlb_set_page_full Date: Fri, 30 Sep 2022 14:26:12 -0700 Message-Id: <20220930212622.108363-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930212622.108363-1-richard.henderson@linaro.org> References: <20220930212622.108363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::736; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x736.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664573823969100001 Now that we have collected all of the page data into CPUTLBEntryFull, provide an interface to record that all in one go, instead of using 4 arguments. This interface allows CPUTLBEntryFull to be extended without having to change the number of arguments. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 14 +++++++++++ include/exec/exec-all.h | 22 ++++++++++++++++++ accel/tcg/cputlb.c | 51 ++++++++++++++++++++++++++--------------- 3 files changed, 69 insertions(+), 18 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index f70f54d850..5e12cc1854 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -148,7 +148,21 @@ typedef struct CPUTLBEntryFull { * + the offset within the target MemoryRegion (otherwise) */ hwaddr xlat_section; + + /* + * @phys_addr contains the physical address in the address space + * given by cpu_asidx_from_attrs(cpu, @attrs). + */ + hwaddr phys_addr; + + /* @attrs contains the memory transaction attributes for the page. */ MemTxAttrs attrs; + + /* @prot contains the complete protections for the page. */ + uint8_t prot; + + /* @lg_page_size contains the log2 of the page size. */ + uint8_t lg_page_size; } CPUTLBEntryFull; =20 /* diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index d255d69bc1..b1b920a713 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -257,6 +257,28 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUStat= e *cpu, uint16_t idxmap, unsigned bits); =20 +/** + * tlb_set_page_full: + * @cpu: CPU context + * @mmu_idx: mmu index of the tlb to modify + * @vaddr: virtual address of the entry to add + * @full: the details of the tlb entry + * + * Add an entry to @cpu tlb index @mmu_idx. All of the fields of + * @full must be filled, except for xlat_section, and constitute + * the complete description of the translated page. + * + * This is generally called by the target tlb_fill function after + * having performed a successful page table walk to find the physical + * address and attributes for the translation. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only + * used by tlb_flush_page. + */ +void tlb_set_page_full(CPUState *cpu, int mmu_idx, target_ulong vaddr, + CPUTLBEntryFull *full); + /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e3ee4260bd..361078471b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1095,16 +1095,16 @@ static void tlb_add_large_page(CPUArchState *env, i= nt mmu_idx, env_tlb(env)->d[mmu_idx].large_page_mask =3D lp_mask; } =20 -/* Add a new TLB entry. At most one entry for a given virtual address +/* + * Add a new TLB entry. At most one entry for a given virtual address * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the * supplied size is only used by tlb_flush_page. * * Called from TCG-generated code, which is under an RCU read-side * critical section. */ -void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, - hwaddr paddr, MemTxAttrs attrs, int prot, - int mmu_idx, target_ulong size) +void tlb_set_page_full(CPUState *cpu, int mmu_idx, + target_ulong vaddr, CPUTLBEntryFull *full) { CPUArchState *env =3D cpu->env_ptr; CPUTLB *tlb =3D env_tlb(env); @@ -1117,35 +1117,36 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_= ulong vaddr, CPUTLBEntry *te, tn; hwaddr iotlb, xlat, sz, paddr_page; target_ulong vaddr_page; - int asidx =3D cpu_asidx_from_attrs(cpu, attrs); - int wp_flags; + int asidx, wp_flags, prot; bool is_ram, is_romd; =20 assert_cpu_is_self(cpu); =20 - if (size <=3D TARGET_PAGE_SIZE) { + if (full->lg_page_size <=3D TARGET_PAGE_BITS) { sz =3D TARGET_PAGE_SIZE; } else { - tlb_add_large_page(env, mmu_idx, vaddr, size); - sz =3D size; + sz =3D (hwaddr)1 << full->lg_page_size; + tlb_add_large_page(env, mmu_idx, vaddr, sz); } vaddr_page =3D vaddr & TARGET_PAGE_MASK; - paddr_page =3D paddr & TARGET_PAGE_MASK; + paddr_page =3D full->phys_addr & TARGET_PAGE_MASK; =20 + prot =3D full->prot; + asidx =3D cpu_asidx_from_attrs(cpu, full->attrs); section =3D address_space_translate_for_iotlb(cpu, asidx, paddr_page, - &xlat, &sz, attrs, &prot); + &xlat, &sz, full->attrs, &= prot); assert(sz >=3D TARGET_PAGE_SIZE); =20 tlb_debug("vaddr=3D" TARGET_FMT_lx " paddr=3D0x" TARGET_FMT_plx " prot=3D%x idx=3D%d\n", - vaddr, paddr, prot, mmu_idx); + vaddr, full->phys_addr, prot, mmu_idx); =20 address =3D vaddr_page; - if (size < TARGET_PAGE_SIZE) { + if (full->lg_page_size < TARGET_PAGE_BITS) { /* Repeat the MMU check and TLB fill on every access. */ address |=3D TLB_INVALID_MASK; } - if (attrs.byte_swap) { + if (full->attrs.byte_swap) { address |=3D TLB_BSWAP; } =20 @@ -1236,8 +1237,10 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_u= long vaddr, * subtract here is that of the page base, and not the same as the * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). */ + desc->fulltlb[index] =3D *full; desc->fulltlb[index].xlat_section =3D iotlb - vaddr_page; - desc->fulltlb[index].attrs =3D attrs; + desc->fulltlb[index].phys_addr =3D paddr_page; + desc->fulltlb[index].prot =3D prot; =20 /* Now calculate the new entry */ tn.addend =3D addend - vaddr_page; @@ -1272,9 +1275,21 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_u= long vaddr, qemu_spin_unlock(&tlb->c.lock); } =20 -/* Add a new TLB entry, but without specifying the memory - * transaction attributes to be used. - */ +void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, + hwaddr paddr, MemTxAttrs attrs, int prot, + int mmu_idx, target_ulong size) +{ + CPUTLBEntryFull full =3D { + .phys_addr =3D paddr, + .attrs =3D attrs, + .prot =3D prot, + .lg_page_size =3D ctz64(size) + }; + + assert(is_power_of_2(size)); + tlb_set_page_full(cpu, mmu_idx, vaddr, &full); +} + void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size) --=20 2.34.1