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([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id l18-20020a05620a28d200b006ce813bb306sm3696370qkp.125.2022.09.30.14.26.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 14:26:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=nRMEXB7YPadVE5hdI4341oxvhxYYKiN9qf3uVsx6pus=; b=JI7MqMZIN4sqpu5KArzh/h/nKvYtzU4gCCdDHY3hgdiSXdekWjRwf59i55SdGIYBUV Nrq51aK2sP/+DrvjDmrU7c0oBjPrbD8HdN1yy9uD5YNyqTJ1QMBWepJ2DUNR855cvlLP 47a/6PehqXa/QAlIhwxyZJMpIitPFOq6YvAimRBntwOfrUDEc2FVvxCyJvwDLQq676D7 nQ9EUwTvDWE8b7J187Di7sVvs05RuaKmWIp8FnqO8KbGbhqC+bqRb3YWZ2Ro68cpyAC6 OGR9igfkjkG2dpzaRrGGxtlDDVu6UHCug7nVDuvGPf0NS2U9LikYUx3lCxz/3AtOd30Y ZNkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=nRMEXB7YPadVE5hdI4341oxvhxYYKiN9qf3uVsx6pus=; b=MbycM26EzjXNZje7aPrXN9cfYwzSMclmGNcoFILhgzWP/EkMrWhmCWA0icYIwnOpka +g8Rz/XJeGc8t37wQKPhU2cvcfwolYw6Ws+ER4QyhFbRlLkx7KwDXRu6n7im5cT7bYsm TXQs6VpgPtf0USvF9EuGISFRQVUSnPSghuy7LHoPfxTncA3Ltua74P3Bu3O1Vj9dwSLN TtZGUTh0Jd1EnWdlAj75nMqW9ffx/OXIfduBJbCskOEvTozxWWhRoGvpylTMA5Ful30n ztOP2U1kms4W27xU5zNnHZBBn8F0kyRzkmKmnKsDB1tBlDZ7WFUNpjQ4nPmv7Riyc1lW 9HXg== X-Gm-Message-State: ACrzQf0pYMnvSa35cZ+siAPKlFwZwC33kupv/7NwPAM9DY97RaJuWasJ Xtx1gRi2dqoQP6joFZkWyCOEgZSYe74YEQ== X-Google-Smtp-Source: AMsMyM5ecYLIhHYSqy2Rhi09D2X70FHUyXLO23Dsa+vDjVYjf2ysvdBLEO3HlNY7tbuQYCHnE6iXAg== X-Received: by 2002:a05:620a:2456:b0:6ce:3cfe:dd62 with SMTP id h22-20020a05620a245600b006ce3cfedd62mr7429925qkn.380.1664573189433; Fri, 30 Sep 2022 14:26:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linux.org, alex.bennee@linux.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v6 01/18] cpu: cache CPUClass in CPUState for hot code paths Date: Fri, 30 Sep 2022 14:26:05 -0700 Message-Id: <20220930212622.108363-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930212622.108363-1-richard.henderson@linaro.org> References: <20220930212622.108363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::733; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x733.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664573523948100001 From: Alex Benn=C3=A9e The class cast checkers are quite expensive and always on (unlike the dynamic case who's checks are gated by CONFIG_QOM_CAST_DEBUG). To avoid the overhead of repeatedly checking something which should never change we cache the CPUClass reference for use in the hot code paths. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-Id: <20220811151413.3350684-3-alex.bennee@linaro.org> Signed-off-by: C=C3=A9dric Le Goater Message-Id: <20220923084803.498337-3-clg@kaod.org> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 9 +++++++++ cpu.c | 9 ++++----- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 500503da13..1a7e1a9380 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -51,6 +51,13 @@ typedef int (*WriteCoreDumpFunction)(const void *buf, si= ze_t size, */ #define CPU(obj) ((CPUState *)(obj)) =20 +/* + * The class checkers bring in CPU_GET_CLASS() which is potentially + * expensive given the eventual call to + * object_class_dynamic_cast_assert(). Because of this the CPUState + * has a cached value for the class in cs->cc which is set up in + * cpu_exec_realizefn() for use in hot code paths. + */ typedef struct CPUClass CPUClass; DECLARE_CLASS_CHECKERS(CPUClass, CPU, TYPE_CPU) @@ -317,6 +324,8 @@ struct qemu_work_item; struct CPUState { /*< private >*/ DeviceState parent_obj; + /* cache to avoid expensive CPU_GET_CLASS */ + CPUClass *cc; /*< public >*/ =20 int nr_cores; diff --git a/cpu.c b/cpu.c index 584ac78baf..14365e36f3 100644 --- a/cpu.c +++ b/cpu.c @@ -131,9 +131,8 @@ const VMStateDescription vmstate_cpu_common =3D { =20 void cpu_exec_realizefn(CPUState *cpu, Error **errp) { -#ifndef CONFIG_USER_ONLY - CPUClass *cc =3D CPU_GET_CLASS(cpu); -#endif + /* cache the cpu class for the hotpath */ + cpu->cc =3D CPU_GET_CLASS(cpu); =20 cpu_list_add(cpu); if (!accel_cpu_realizefn(cpu, errp)) { @@ -151,8 +150,8 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); } - if (cc->sysemu_ops->legacy_vmsd !=3D NULL) { - vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd= , cpu); + if (cpu->cc->sysemu_ops->legacy_vmsd !=3D NULL) { + vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy= _vmsd, cpu); } #endif /* CONFIG_USER_ONLY */ } --=20 2.34.1