From nobody Sat Apr 27 07:51:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664573522; cv=none; d=zohomail.com; s=zohoarc; b=lyWSki/rViuFOGZODsPyJhttC++Y4U1rOfOi8i1UTXwtSKJ6EgJoqAxfV9UHKaNx2duDgFx9lkXvkBcgHX5VudebOCNACN4zxJZdRcxbifGkQ5eYDIMwGDTviBdLwlqiM6NgJZdRI+OBBTWW4jizA4nkOKCSJpHu/HTs28yCXEI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664573522; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nRMEXB7YPadVE5hdI4341oxvhxYYKiN9qf3uVsx6pus=; b=Hxio43DPIbw9fpZiIklqYX7obp4Vsxzlh1tJcMsNxU9kSXn5Bu7NcNl8AnjXMLLgtDYoWCH7720jLXlHyW2US037Mauj6dAkC6KSnBXGPi9u1RRU4C9ALesNV6rS/TzDc4CW9FIf/1fAhAnDr9w/HQUvxwL4V0Mg/lyd3nV+L3k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664573522771565.5916023003693; Fri, 30 Sep 2022 14:32:02 -0700 (PDT) Received: from localhost ([::1]:53774 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeNc0-0005YG-IX for importer@patchew.org; Fri, 30 Sep 2022 17:32:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49936) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeNWi-0005tB-7P for qemu-devel@nongnu.org; Fri, 30 Sep 2022 17:26:32 -0400 Received: from mail-qk1-x733.google.com ([2607:f8b0:4864:20::733]:37843) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeNWg-0005N5-Fs for qemu-devel@nongnu.org; Fri, 30 Sep 2022 17:26:31 -0400 Received: by mail-qk1-x733.google.com with SMTP id s9so3616839qkg.4 for ; Fri, 30 Sep 2022 14:26:30 -0700 (PDT) Received: from stoup.. ([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id l18-20020a05620a28d200b006ce813bb306sm3696370qkp.125.2022.09.30.14.26.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 14:26:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=nRMEXB7YPadVE5hdI4341oxvhxYYKiN9qf3uVsx6pus=; b=JI7MqMZIN4sqpu5KArzh/h/nKvYtzU4gCCdDHY3hgdiSXdekWjRwf59i55SdGIYBUV Nrq51aK2sP/+DrvjDmrU7c0oBjPrbD8HdN1yy9uD5YNyqTJ1QMBWepJ2DUNR855cvlLP 47a/6PehqXa/QAlIhwxyZJMpIitPFOq6YvAimRBntwOfrUDEc2FVvxCyJvwDLQq676D7 nQ9EUwTvDWE8b7J187Di7sVvs05RuaKmWIp8FnqO8KbGbhqC+bqRb3YWZ2Ro68cpyAC6 OGR9igfkjkG2dpzaRrGGxtlDDVu6UHCug7nVDuvGPf0NS2U9LikYUx3lCxz/3AtOd30Y ZNkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=nRMEXB7YPadVE5hdI4341oxvhxYYKiN9qf3uVsx6pus=; b=MbycM26EzjXNZje7aPrXN9cfYwzSMclmGNcoFILhgzWP/EkMrWhmCWA0icYIwnOpka +g8Rz/XJeGc8t37wQKPhU2cvcfwolYw6Ws+ER4QyhFbRlLkx7KwDXRu6n7im5cT7bYsm TXQs6VpgPtf0USvF9EuGISFRQVUSnPSghuy7LHoPfxTncA3Ltua74P3Bu3O1Vj9dwSLN TtZGUTh0Jd1EnWdlAj75nMqW9ffx/OXIfduBJbCskOEvTozxWWhRoGvpylTMA5Ful30n ztOP2U1kms4W27xU5zNnHZBBn8F0kyRzkmKmnKsDB1tBlDZ7WFUNpjQ4nPmv7Riyc1lW 9HXg== X-Gm-Message-State: ACrzQf0pYMnvSa35cZ+siAPKlFwZwC33kupv/7NwPAM9DY97RaJuWasJ Xtx1gRi2dqoQP6joFZkWyCOEgZSYe74YEQ== X-Google-Smtp-Source: AMsMyM5ecYLIhHYSqy2Rhi09D2X70FHUyXLO23Dsa+vDjVYjf2ysvdBLEO3HlNY7tbuQYCHnE6iXAg== X-Received: by 2002:a05:620a:2456:b0:6ce:3cfe:dd62 with SMTP id h22-20020a05620a245600b006ce3cfedd62mr7429925qkn.380.1664573189433; Fri, 30 Sep 2022 14:26:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linux.org, alex.bennee@linux.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v6 01/18] cpu: cache CPUClass in CPUState for hot code paths Date: Fri, 30 Sep 2022 14:26:05 -0700 Message-Id: <20220930212622.108363-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930212622.108363-1-richard.henderson@linaro.org> References: <20220930212622.108363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::733; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x733.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664573523948100001 From: Alex Benn=C3=A9e The class cast checkers are quite expensive and always on (unlike the dynamic case who's checks are gated by CONFIG_QOM_CAST_DEBUG). To avoid the overhead of repeatedly checking something which should never change we cache the CPUClass reference for use in the hot code paths. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-Id: <20220811151413.3350684-3-alex.bennee@linaro.org> Signed-off-by: C=C3=A9dric Le Goater Message-Id: <20220923084803.498337-3-clg@kaod.org> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 9 +++++++++ cpu.c | 9 ++++----- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 500503da13..1a7e1a9380 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -51,6 +51,13 @@ typedef int (*WriteCoreDumpFunction)(const void *buf, si= ze_t size, */ #define CPU(obj) ((CPUState *)(obj)) =20 +/* + * The class checkers bring in CPU_GET_CLASS() which is potentially + * expensive given the eventual call to + * object_class_dynamic_cast_assert(). Because of this the CPUState + * has a cached value for the class in cs->cc which is set up in + * cpu_exec_realizefn() for use in hot code paths. + */ typedef struct CPUClass CPUClass; DECLARE_CLASS_CHECKERS(CPUClass, CPU, TYPE_CPU) @@ -317,6 +324,8 @@ struct qemu_work_item; struct CPUState { /*< private >*/ DeviceState parent_obj; + /* cache to avoid expensive CPU_GET_CLASS */ + CPUClass *cc; /*< public >*/ =20 int nr_cores; diff --git a/cpu.c b/cpu.c index 584ac78baf..14365e36f3 100644 --- a/cpu.c +++ b/cpu.c @@ -131,9 +131,8 @@ const VMStateDescription vmstate_cpu_common =3D { =20 void cpu_exec_realizefn(CPUState *cpu, Error **errp) { -#ifndef CONFIG_USER_ONLY - CPUClass *cc =3D CPU_GET_CLASS(cpu); -#endif + /* cache the cpu class for the hotpath */ + cpu->cc =3D CPU_GET_CLASS(cpu); =20 cpu_list_add(cpu); if (!accel_cpu_realizefn(cpu, errp)) { @@ -151,8 +150,8 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); } - if (cc->sysemu_ops->legacy_vmsd !=3D NULL) { - vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd= , cpu); + if (cpu->cc->sysemu_ops->legacy_vmsd !=3D NULL) { + vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy= _vmsd, cpu); } #endif /* CONFIG_USER_ONLY */ } --=20 2.34.1 From nobody Sat Apr 27 07:51:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664573761; cv=none; d=zohomail.com; s=zohoarc; b=oDqUbHVsxRfJBRwrDxO88pZBqQyH4B+kYZClt8iwH7nADpOfFSvim2HWx0sDTa9poW2h26qEmCF5+OtM4fiOAzybJS+2yo63FCXI2oOHqYZJ3WwktYpZ2VPphIYSOU9SHTu56bBDHMJ2zdROyDBJPRzOqzQ7nXbqPQeRoJs1FrA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664573761; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FcUiK2Okdru3cG4LiS1rgcAo1RAHSsbMmma9k9kUJWI=; b=ZOsqhPDgGQ6vDMqsZAZ7/i1I7tikUl6UyJ8ZPG9OEngjuiQgH3YiI0dyJVm6XIFyB8+tBblLigLrlfOZWWkDLdBG8RfEkA30YHEBbIOCsS8YwQdCDhmGigeOez86AQBczwZGgj4ghdZRsjF/DvY0CYvVMbbqTBxmFDUEUCgYWIY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664573761768696.545054156555; Fri, 30 Sep 2022 14:36:01 -0700 (PDT) Received: from localhost ([::1]:42940 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeNfs-0001UB-2t for importer@patchew.org; Fri, 30 Sep 2022 17:36:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49938) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeNWk-0005um-2Q for qemu-devel@nongnu.org; Fri, 30 Sep 2022 17:26:34 -0400 Received: from mail-qk1-x72f.google.com ([2607:f8b0:4864:20::72f]:34742) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeNWi-0005NJ-E8 for qemu-devel@nongnu.org; Fri, 30 Sep 2022 17:26:33 -0400 Received: by mail-qk1-x72f.google.com with SMTP id g2so3622883qkk.1 for ; Fri, 30 Sep 2022 14:26:32 -0700 (PDT) Received: from stoup.. ([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id l18-20020a05620a28d200b006ce813bb306sm3696370qkp.125.2022.09.30.14.26.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 14:26:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=FcUiK2Okdru3cG4LiS1rgcAo1RAHSsbMmma9k9kUJWI=; b=M/vYG3g7pBcDMupCoDn3WfBcgdaFwjO23mq2B70iQzSKpCv0IeE5jHTfJI5fVLT1E0 PgI0Orj1mKrCAH1NhBZPBW0BmMzJfAHWDfn0wFqIo6Ir9Yo4g0Yrx42qUAZrdPduAs0C nKeiu1JeKKr45k60si+HolYZeGPtoQrAbX/+JpWaek7G3OXyfxX+O229yJTxJR1Ui/w9 O83M8VhOH0+s2BdPv3M+sWErbyOsRVMa66z9pmmi9Kx0K1N/gRSMfJm9IvSlTJ+YwnhI 5EZaYaQ/X4skWGpAq9Bxu585DCazSoAp/hPu0V8M1EraIqP4aKAXPHsiN7QqXwLQACwo /8Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=FcUiK2Okdru3cG4LiS1rgcAo1RAHSsbMmma9k9kUJWI=; b=7fv7tJPAx5GaSGWf4zh1/KLBsO0xgk/6G0dwpO8zgm20ka2t8GI4IVbqOqCj8MUi1K hUr+zMSbKMuuDD2u8U/Lz8+VzslCYJlK7aJjIcC8c9t3KC9aT22jdxdW+JXG+KJ4PFsw 430S3zzFL/8B+Txmp8jdEH8PYDqVoYWiU/jf5Et8HyiG/ixnOcoxHJIiMv17x5rJucQh HCkvtqFynre+pSydtQIDNcsDEvoAcRiAT5RI+P5IdAt36jZKwLDCtxR48aQJXNBY6YIT rz0tEu32aZ6K+P+jIlaRYYqENS1vmze+GFxaPWZmF8GCxgpIHOTxuDKye3FhNfKUHy0r fvyA== X-Gm-Message-State: ACrzQf3+tA4DyKHm3WNw4w5+1UyZtnbMGf1iZudrOk9U7DvkhcFRB/j6 /BqMfrN0aeusEAJQUWjVsdiE1Fs9Xx/9sA== X-Google-Smtp-Source: AMsMyM6loljQRd6cl4HV3UCyakLRfBTm65jW08ySn2YeIn5/YxSqYO2KALAAdswRzWp37hnb6tdkEg== X-Received: by 2002:a05:620a:29c9:b0:6ce:a961:af73 with SMTP id s9-20020a05620a29c900b006cea961af73mr7625044qkp.226.1664573191390; Fri, 30 Sep 2022 14:26:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linux.org, alex.bennee@linux.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v6 02/18] hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs Date: Fri, 30 Sep 2022 14:26:06 -0700 Message-Id: <20220930212622.108363-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930212622.108363-1-richard.henderson@linaro.org> References: <20220930212622.108363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72f; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664573763657100001 From: Alex Benn=C3=A9e This is a heavily used function so lets avoid the cost of CPU_GET_CLASS. On the romulus-bmc run it has a modest effect: Before: 36.812 s =C2=B1 0.506 s After: 35.912 s =C2=B1 0.168 s Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-Id: <20220811151413.3350684-4-alex.bennee@linaro.org> Signed-off-by: C=C3=A9dric Le Goater Message-Id: <20220923084803.498337-4-clg@kaod.org> Signed-off-by: Richard Henderson --- hw/core/cpu-sysemu.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index 00253f8929..5eaf2e79e6 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -69,11 +69,10 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr add= r) =20 int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); int ret =3D 0; =20 - if (cc->sysemu_ops->asidx_from_attrs) { - ret =3D cc->sysemu_ops->asidx_from_attrs(cpu, attrs); + if (cpu->cc->sysemu_ops->asidx_from_attrs) { + ret =3D cpu->cc->sysemu_ops->asidx_from_attrs(cpu, attrs); assert(ret < cpu->num_ases && ret >=3D 0); } return ret; --=20 2.34.1 From nobody Sat Apr 27 07:51:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664573380; cv=none; d=zohomail.com; s=zohoarc; b=KVQAhhy7vBKWIHUmF6UYoSSpCNR0s6Z3JdWfZ6nk+iV4inYQAkYzQX6y2OQ6idltvpG06wRODXJr6nb/2dNlH5ksT+Et9XKkD+xrP6DX9tSHGcMPosOM3v5vZiBHtmHZKwg/fLLTjfTJ6oQ0y7AqpNrtCX24piUEevuaF3kC5Ec= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664573380; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=q0eg+3QiI3aRqtvdrrAtNwv7hcqy9NWtzJtlLArJ6SQ=; b=Eb4448FoINqCX/5+vQexrDEnefJsUDBv4iTvR0HAze0Dlk80F6X3WPS/9CL3KSmLY+wjAtQkndKZUQ1mvo3Q5cElzi0pzjlyyTQ7SwsNaG1HVR0DJuPFjDZ8ugy2e+u0Dp3julLaGyP2Pxio+pbiyw701qmdG4+eJ4qq6HrUNrw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664573380193206.15214926438182; Fri, 30 Sep 2022 14:29:40 -0700 (PDT) Received: from localhost ([::1]:49510 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeNZj-0001wc-6L for importer@patchew.org; Fri, 30 Sep 2022 17:29:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48190) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeNWm-0005yi-C5 for qemu-devel@nongnu.org; Fri, 30 Sep 2022 17:26:36 -0400 Received: from mail-qv1-xf29.google.com ([2607:f8b0:4864:20::f29]:44935) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeNWk-0005NZ-Qs for qemu-devel@nongnu.org; Fri, 30 Sep 2022 17:26:36 -0400 Received: by mail-qv1-xf29.google.com with SMTP id u9so2598983qvo.11 for ; Fri, 30 Sep 2022 14:26:34 -0700 (PDT) Received: from stoup.. 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bh=q0eg+3QiI3aRqtvdrrAtNwv7hcqy9NWtzJtlLArJ6SQ=; b=tE/5qLP+TaZHAD9l24kbOspIuWOTLHnfSf8mqRv9Gy2mWKkyjOSu/YKwdeWlk2XeLv uM8B0f+g6sr0WakHkjDI9Y1drLBwoTW+qKfEmjCsdKBun/wODwcTBgc2k7p9u+cEhf66 Cepd4rJ407wLtVFvQslNzBV4Oebn7TzOBpbkAYeFYKXTmv3/L6iDfbZuTrzqHFF4jB/l Hm6q3lgZ0m41y6hXhwBqg/yTJzDZDdsSsqJvL37xhzjaJ1HD8SZNpzy6/zR+8zo+EDrl AVNmQ1GPXqT49Cs6cPxQ6yXrzVKbTmCNR1gGpj8tfvrZWJxrM6agAW7KPAfEASMvX6gN 2Ycw== X-Gm-Message-State: ACrzQf3PFquL3wFavAKiqYC9tPcUjTypBcpixsbOh3s3e5SWsCyVq5AV uzJ9XY9S997lO6FILfmNj65wbs1JnFv9qQ== X-Google-Smtp-Source: AMsMyM7XSoqFmK9UJM0uXCTAudcTr0B6NSC9pzgTvdueUdsjuoQu1fQg9OgoZLWI/rZDttc0pCMN9Q== X-Received: by 2002:a0c:f550:0:b0:4b1:7af4:eece with SMTP id p16-20020a0cf550000000b004b17af4eecemr65594qvm.110.1664573193789; Fri, 30 Sep 2022 14:26:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linux.org, alex.bennee@linux.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v6 03/18] cputlb: used cached CPUClass in our hot-paths Date: Fri, 30 Sep 2022 14:26:07 -0700 Message-Id: <20220930212622.108363-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930212622.108363-1-richard.henderson@linaro.org> References: <20220930212622.108363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f29; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664573382142100001 From: Alex Benn=C3=A9e Before: 35.912 s =C2=B1 0.168 s After: 35.565 s =C2=B1 0.087 s Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-Id: <20220811151413.3350684-5-alex.bennee@linaro.org> Signed-off-by: C=C3=A9dric Le Goater Message-Id: <20220923084803.498337-5-clg@kaod.org> Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 8fad2d9b83..193bfc1cfc 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1291,15 +1291,14 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, static void tlb_fill(CPUState *cpu, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t ret= addr) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); bool ok; =20 /* * This is not a probe, so only valid return is success; failure * should result in exception + longjmp to the cpu loop. */ - ok =3D cc->tcg_ops->tlb_fill(cpu, addr, size, - access_type, mmu_idx, false, retaddr); + ok =3D cpu->cc->tcg_ops->tlb_fill(cpu, addr, size, + access_type, mmu_idx, false, retaddr); assert(ok); } =20 @@ -1307,9 +1306,8 @@ static inline void cpu_unaligned_access(CPUState *cpu= , vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, mmu_idx, reta= ddr); + cpu->cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, + mmu_idx, retaddr); } =20 static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, @@ -1539,10 +1537,9 @@ static int probe_access_internal(CPUArchState *env, = target_ulong addr, if (!tlb_hit_page(tlb_addr, page_addr)) { if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) { CPUState *cs =3D env_cpu(env); - CPUClass *cc =3D CPU_GET_CLASS(cs); =20 - if (!cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_type, - mmu_idx, nonfault, retaddr)) { + if (!cs->cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_ty= pe, + mmu_idx, nonfault, retaddr)) { /* Non-faulting page table read failed. */ *phost =3D NULL; return TLB_INVALID_MASK; --=20 2.34.1 From nobody Sat Apr 27 07:51:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664573589; cv=none; d=zohomail.com; s=zohoarc; b=n2ovf/Jki+Xed8bQ3KlXqvPwGV1xD8JTt7E6f8iOxVOYu0Se0JbQLqe2Onxvv9Eqbem8VDfXuCQWFOvB0xRud/iTY7v2/OnzJeSrBxsXFC6+qkXhjpEInGkI70KG13tR28LeZmP/zI2mBdSLSM6waOyeoFWwWia6sSdu/e1r/bc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Rename the 'addr' member to 'xlat_section' to more clearly indicate its purpose. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 22 ++++---- accel/tcg/cputlb.c | 102 +++++++++++++++++++------------------ target/arm/mte_helper.c | 14 ++--- target/arm/sve_helper.c | 4 +- target/arm/translate-a64.c | 2 +- 5 files changed, 73 insertions(+), 71 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index ba3cd32a1e..f70f54d850 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -108,6 +108,7 @@ typedef uint64_t target_ulong; # endif # endif =20 +/* Minimalized TLB entry for use by TCG fast path. */ typedef struct CPUTLBEntry { /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not @@ -131,14 +132,14 @@ typedef struct CPUTLBEntry { =20 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) !=3D (1 << CPU_TLB_ENTRY_BITS)); =20 -/* The IOTLB is not accessed directly inline by generated TCG code, - * so the CPUIOTLBEntry layout is not as critical as that of the - * CPUTLBEntry. (This is also why we don't want to combine the two - * structs into one.) +/* + * The full TLB entry, which is not accessed by generated TCG code, + * so the layout is not as critical as that of CPUTLBEntry. This is + * also why we don't want to combine the two structs. */ -typedef struct CPUIOTLBEntry { +typedef struct CPUTLBEntryFull { /* - * @addr contains: + * @xlat_section contains: * - in the lower TARGET_PAGE_BITS, a physical section number * - with the lower TARGET_PAGE_BITS masked off, an offset which * must be added to the virtual address to obtain: @@ -146,9 +147,9 @@ typedef struct CPUIOTLBEntry { * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) * + the offset within the target MemoryRegion (otherwise) */ - hwaddr addr; + hwaddr xlat_section; MemTxAttrs attrs; -} CPUIOTLBEntry; +} CPUTLBEntryFull; =20 /* * Data elements that are per MMU mode, minus the bits accessed by @@ -172,9 +173,8 @@ typedef struct CPUTLBDesc { size_t vindex; /* The tlb victim table, in two parts. */ CPUTLBEntry vtable[CPU_VTLB_SIZE]; - CPUIOTLBEntry viotlb[CPU_VTLB_SIZE]; - /* The iotlb. */ - CPUIOTLBEntry *iotlb; + CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE]; + CPUTLBEntryFull *fulltlb; } CPUTLBDesc; =20 /* diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 193bfc1cfc..aa22f578cb 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -200,13 +200,13 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, C= PUTLBDescFast *fast, } =20 g_free(fast->table); - g_free(desc->iotlb); + g_free(desc->fulltlb); =20 tlb_window_reset(desc, now, 0); /* desc->n_used_entries is cleared by the caller */ fast->mask =3D (new_size - 1) << CPU_TLB_ENTRY_BITS; fast->table =3D g_try_new(CPUTLBEntry, new_size); - desc->iotlb =3D g_try_new(CPUIOTLBEntry, new_size); + desc->fulltlb =3D g_try_new(CPUTLBEntryFull, new_size); =20 /* * If the allocations fail, try smaller sizes. We just freed some @@ -215,7 +215,7 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPU= TLBDescFast *fast, * allocations to fail though, so we progressively reduce the allocati= on * size, aborting if we cannot even allocate the smallest TLB we suppo= rt. */ - while (fast->table =3D=3D NULL || desc->iotlb =3D=3D NULL) { + while (fast->table =3D=3D NULL || desc->fulltlb =3D=3D NULL) { if (new_size =3D=3D (1 << CPU_TLB_DYN_MIN_BITS)) { error_report("%s: %s", __func__, strerror(errno)); abort(); @@ -224,9 +224,9 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPU= TLBDescFast *fast, fast->mask =3D (new_size - 1) << CPU_TLB_ENTRY_BITS; =20 g_free(fast->table); - g_free(desc->iotlb); + g_free(desc->fulltlb); fast->table =3D g_try_new(CPUTLBEntry, new_size); - desc->iotlb =3D g_try_new(CPUIOTLBEntry, new_size); + desc->fulltlb =3D g_try_new(CPUTLBEntryFull, new_size); } } =20 @@ -258,7 +258,7 @@ static void tlb_mmu_init(CPUTLBDesc *desc, CPUTLBDescFa= st *fast, int64_t now) desc->n_used_entries =3D 0; fast->mask =3D (n_entries - 1) << CPU_TLB_ENTRY_BITS; fast->table =3D g_new(CPUTLBEntry, n_entries); - desc->iotlb =3D g_new(CPUIOTLBEntry, n_entries); + desc->fulltlb =3D g_new(CPUTLBEntryFull, n_entries); tlb_mmu_flush_locked(desc, fast); } =20 @@ -299,7 +299,7 @@ void tlb_destroy(CPUState *cpu) CPUTLBDescFast *fast =3D &env_tlb(env)->f[i]; =20 g_free(fast->table); - g_free(desc->iotlb); + g_free(desc->fulltlb); } } =20 @@ -1219,7 +1219,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, =20 /* Evict the old entry into the victim tlb. */ copy_tlb_helper_locked(tv, te); - desc->viotlb[vidx] =3D desc->iotlb[index]; + desc->vfulltlb[vidx] =3D desc->fulltlb[index]; tlb_n_used_entries_dec(env, mmu_idx); } =20 @@ -1236,8 +1236,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, * subtract here is that of the page base, and not the same as the * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). */ - desc->iotlb[index].addr =3D iotlb - vaddr_page; - desc->iotlb[index].attrs =3D attrs; + desc->fulltlb[index].xlat_section =3D iotlb - vaddr_page; + desc->fulltlb[index].attrs =3D attrs; =20 /* Now calculate the new entry */ tn.addend =3D addend - vaddr_page; @@ -1327,7 +1327,7 @@ static inline void cpu_transaction_failed(CPUState *c= pu, hwaddr physaddr, } } =20 -static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, +static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full, int mmu_idx, target_ulong addr, uintptr_t retaddr, MMUAccessType access_type, MemOp op) { @@ -1339,9 +1339,9 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBE= ntry *iotlbentry, bool locked =3D false; MemTxResult r; =20 - section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); + section =3D iotlb_to_section(cpu, full->xlat_section, full->attrs); mr =3D section->mr; - mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; + mr_offset =3D (full->xlat_section & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc =3D retaddr; if (!cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); @@ -1351,14 +1351,14 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTL= BEntry *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_read(mr, mr_offset, &val, op, iotlbentry-= >attrs); + r =3D memory_region_dispatch_read(mr, mr_offset, &val, op, full->attrs= ); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - section->offset_within_region; =20 cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), access= _type, - mmu_idx, iotlbentry->attrs, r, retaddr); + mmu_idx, full->attrs, r, retaddr); } if (locked) { qemu_mutex_unlock_iothread(); @@ -1368,8 +1368,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBE= ntry *iotlbentry, } =20 /* - * Save a potentially trashed IOTLB entry for later lookup by plugin. - * This is read by tlb_plugin_lookup if the iotlb entry doesn't match + * Save a potentially trashed CPUTLBEntryFull for later lookup by plugin. + * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match * because of the side effect of io_writex changing memory layout. */ static void save_iotlb_data(CPUState *cs, hwaddr addr, @@ -1383,7 +1383,7 @@ static void save_iotlb_data(CPUState *cs, hwaddr addr, #endif } =20 -static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, +static void io_writex(CPUArchState *env, CPUTLBEntryFull *full, int mmu_idx, uint64_t val, target_ulong addr, uintptr_t retaddr, MemOp op) { @@ -1394,9 +1394,9 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntr= y *iotlbentry, bool locked =3D false; MemTxResult r; =20 - section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); + section =3D iotlb_to_section(cpu, full->xlat_section, full->attrs); mr =3D section->mr; - mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; + mr_offset =3D (full->xlat_section & TARGET_PAGE_MASK) + addr; if (!cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); } @@ -1406,20 +1406,20 @@ static void io_writex(CPUArchState *env, CPUIOTLBEn= try *iotlbentry, * The memory_region_dispatch may trigger a flush/resize * so for plugins we save the iotlb_data just in case. */ - save_iotlb_data(cpu, iotlbentry->addr, section, mr_offset); + save_iotlb_data(cpu, full->xlat_section, section, mr_offset); =20 if (!qemu_mutex_iothread_locked()) { qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_write(mr, mr_offset, val, op, iotlbentry-= >attrs); + r =3D memory_region_dispatch_write(mr, mr_offset, val, op, full->attrs= ); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - section->offset_within_region; =20 cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), - MMU_DATA_STORE, mmu_idx, iotlbentry->attrs,= r, + MMU_DATA_STORE, mmu_idx, full->attrs, r, retaddr); } if (locked) { @@ -1466,9 +1466,10 @@ static bool victim_tlb_hit(CPUArchState *env, size_t= mmu_idx, size_t index, copy_tlb_helper_locked(vtlb, &tmptlb); qemu_spin_unlock(&env_tlb(env)->c.lock); =20 - CPUIOTLBEntry tmpio, *io =3D &env_tlb(env)->d[mmu_idx].iotlb[i= ndex]; - CPUIOTLBEntry *vio =3D &env_tlb(env)->d[mmu_idx].viotlb[vidx]; - tmpio =3D *io; *io =3D *vio; *vio =3D tmpio; + CPUTLBEntryFull *f1 =3D &env_tlb(env)->d[mmu_idx].fulltlb[inde= x]; + CPUTLBEntryFull *f2 =3D &env_tlb(env)->d[mmu_idx].vfulltlb[vid= x]; + CPUTLBEntryFull tmpf; + tmpf =3D *f1; *f1 =3D *f2; *f2 =3D tmpf; return true; } } @@ -1481,9 +1482,9 @@ static bool victim_tlb_hit(CPUArchState *env, size_t = mmu_idx, size_t index, (ADDR) & TARGET_PAGE_MASK) =20 static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size, - CPUIOTLBEntry *iotlbentry, uintptr_t retaddr) + CPUTLBEntryFull *full, uintptr_t retaddr) { - ram_addr_t ram_addr =3D mem_vaddr + iotlbentry->addr; + ram_addr_t ram_addr =3D mem_vaddr + full->xlat_section; =20 trace_memory_notdirty_write_access(mem_vaddr, ram_addr, size); =20 @@ -1575,9 +1576,9 @@ int probe_access_flags(CPUArchState *env, target_ulon= g addr, /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUIOTLBEntry *iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[inde= x]; + CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; =20 - notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr); + notdirty_write(env_cpu(env), addr, 1, full, retaddr); flags &=3D ~TLB_NOTDIRTY; } =20 @@ -1602,19 +1603,19 @@ void *probe_access(CPUArchState *env, target_ulong = addr, int size, =20 if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) { uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUIOTLBEntry *iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[inde= x]; + CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; =20 /* Handle watchpoints. */ if (flags & TLB_WATCHPOINT) { int wp_access =3D (access_type =3D=3D MMU_DATA_STORE ? BP_MEM_WRITE : BP_MEM_READ); cpu_check_watchpoint(env_cpu(env), addr, size, - iotlbentry->attrs, wp_access, retaddr); + full->attrs, wp_access, retaddr); } =20 /* Handle clean RAM pages. */ if (flags & TLB_NOTDIRTY) { - notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr); + notdirty_write(env_cpu(env), addr, 1, full, retaddr); } } =20 @@ -1671,7 +1672,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState = *env, target_ulong addr, * should have just filled the TLB. The one corner case is io_writex * which can cause TLB flushes and potential resizing of the TLBs * losing the information we need. In those cases we need to recover - * data from a copy of the iotlbentry. As long as this always occurs + * data from a copy of the CPUTLBEntryFull. As long as this always occurs * from the same thread (which a mem callback will be) this is safe. */ =20 @@ -1686,11 +1687,12 @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong = addr, int mmu_idx, if (likely(tlb_hit(tlb_addr, addr))) { /* We must have an iotlb entry for MMIO */ if (tlb_addr & TLB_MMIO) { - CPUIOTLBEntry *iotlbentry; - iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[index]; + CPUTLBEntryFull *full; + full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; data->is_io =3D true; - data->v.io.section =3D iotlb_to_section(cpu, iotlbentry->addr,= iotlbentry->attrs); - data->v.io.offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + = addr; + data->v.io.section =3D + iotlb_to_section(cpu, full->xlat_section, full->attrs); + data->v.io.offset =3D (full->xlat_section & TARGET_PAGE_MASK) = + addr; } else { data->is_io =3D false; data->v.ram.hostaddr =3D (void *)((uintptr_t)addr + tlbe->adde= nd); @@ -1798,7 +1800,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, =20 if (unlikely(tlb_addr & TLB_NOTDIRTY)) { notdirty_write(env_cpu(env), addr, size, - &env_tlb(env)->d[mmu_idx].iotlb[index], retaddr); + &env_tlb(env)->d[mmu_idx].fulltlb[index], retaddr); } =20 return hostaddr; @@ -1906,7 +1908,7 @@ load_helper(CPUArchState *env, target_ulong addr, Mem= OpIdx oi, =20 /* Handle anything that isn't just a straight memory access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - CPUIOTLBEntry *iotlbentry; + CPUTLBEntryFull *full; bool need_swap; =20 /* For anything that is unaligned, recurse through full_load. */ @@ -1914,20 +1916,20 @@ load_helper(CPUArchState *env, target_ulong addr, M= emOpIdx oi, goto do_unaligned_access; } =20 - iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[index]; + full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; =20 /* Handle watchpoints. */ if (unlikely(tlb_addr & TLB_WATCHPOINT)) { /* On watchpoint hit, this will longjmp out. */ cpu_check_watchpoint(env_cpu(env), addr, size, - iotlbentry->attrs, BP_MEM_READ, retaddr); + full->attrs, BP_MEM_READ, retaddr); } =20 need_swap =3D size > 1 && (tlb_addr & TLB_BSWAP); =20 /* Handle I/O access. */ if (likely(tlb_addr & TLB_MMIO)) { - return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, + return io_readx(env, full, mmu_idx, addr, retaddr, access_type, op ^ (need_swap * MO_BSWAP)); } =20 @@ -2242,12 +2244,12 @@ store_helper_unaligned(CPUArchState *env, target_ul= ong addr, uint64_t val, */ if (unlikely(tlb_addr & TLB_WATCHPOINT)) { cpu_check_watchpoint(env_cpu(env), addr, size - size2, - env_tlb(env)->d[mmu_idx].iotlb[index].attrs, + env_tlb(env)->d[mmu_idx].fulltlb[index].attrs, BP_MEM_WRITE, retaddr); } if (unlikely(tlb_addr2 & TLB_WATCHPOINT)) { cpu_check_watchpoint(env_cpu(env), page2, size2, - env_tlb(env)->d[mmu_idx].iotlb[index2].attrs, + env_tlb(env)->d[mmu_idx].fulltlb[index2].attr= s, BP_MEM_WRITE, retaddr); } =20 @@ -2311,7 +2313,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, =20 /* Handle anything that isn't just a straight memory access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - CPUIOTLBEntry *iotlbentry; + CPUTLBEntryFull *full; bool need_swap; =20 /* For anything that is unaligned, recurse through byte stores. */ @@ -2319,20 +2321,20 @@ store_helper(CPUArchState *env, target_ulong addr, = uint64_t val, goto do_unaligned_access; } =20 - iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[index]; + full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; =20 /* Handle watchpoints. */ if (unlikely(tlb_addr & TLB_WATCHPOINT)) { /* On watchpoint hit, this will longjmp out. */ cpu_check_watchpoint(env_cpu(env), addr, size, - iotlbentry->attrs, BP_MEM_WRITE, retaddr); + full->attrs, BP_MEM_WRITE, retaddr); } =20 need_swap =3D size > 1 && (tlb_addr & TLB_BSWAP); =20 /* Handle I/O access. */ if (tlb_addr & TLB_MMIO) { - io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, + io_writex(env, full, mmu_idx, val, addr, retaddr, op ^ (need_swap * MO_BSWAP)); return; } @@ -2344,7 +2346,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, =20 /* Handle clean RAM pages. */ if (tlb_addr & TLB_NOTDIRTY) { - notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr); + notdirty_write(env_cpu(env), addr, size, full, retaddr); } =20 haddr =3D (void *)((uintptr_t)addr + entry->addend); diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index d11a8c70d0..fdd23ab3f8 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -106,7 +106,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, return tags + index; #else uintptr_t index; - CPUIOTLBEntry *iotlbentry; + CPUTLBEntryFull *full; int in_page, flags; ram_addr_t ptr_ra; hwaddr ptr_paddr, tag_paddr, xlat; @@ -129,7 +129,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, assert(!(flags & TLB_INVALID_MASK)); =20 /* - * Find the iotlbentry for ptr. This *must* be present in the TLB + * Find the CPUTLBEntryFull for ptr. This *must* be present in the TLB * because we just found the mapping. * TODO: Perhaps there should be a cputlb helper that returns a * matching tlb entry + iotlb entry. @@ -144,10 +144,10 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, = int ptr_mmu_idx, g_assert(tlb_hit(comparator, ptr)); } # endif - iotlbentry =3D &env_tlb(env)->d[ptr_mmu_idx].iotlb[index]; + full =3D &env_tlb(env)->d[ptr_mmu_idx].fulltlb[index]; =20 /* If the virtual page MemAttr !=3D Tagged, access unchecked. */ - if (!arm_tlb_mte_tagged(&iotlbentry->attrs)) { + if (!arm_tlb_mte_tagged(&full->attrs)) { return NULL; } =20 @@ -181,7 +181,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, int wp =3D ptr_access =3D=3D MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_= WRITE; assert(ra !=3D 0); cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, - iotlbentry->attrs, wp, ra); + full->attrs, wp, ra); } =20 /* @@ -202,11 +202,11 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, = int ptr_mmu_idx, tag_paddr =3D ptr_paddr >> (LOG2_TAG_GRANULE + 1); =20 /* Look up the address in tag space. */ - tag_asi =3D iotlbentry->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; + tag_asi =3D full->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; tag_as =3D cpu_get_address_space(env_cpu(env), tag_asi); mr =3D address_space_translate(tag_as, tag_paddr, &xlat, NULL, tag_access =3D=3D MMU_DATA_STORE, - iotlbentry->attrs); + full->attrs); =20 /* * Note that @mr will never be NULL. If there is nothing in the addre= ss diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index d6f7ef94fe..9cae8fd352 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -5384,8 +5384,8 @@ bool sve_probe_page(SVEHostPage *info, bool nofault, = CPUARMState *env, g_assert(tlb_hit(comparator, addr)); # endif =20 - CPUIOTLBEntry *iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[inde= x]; - info->attrs =3D iotlbentry->attrs; + CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + info->attrs =3D full->attrs; } #endif =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9bed336b47..78b2d91ed4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14624,7 +14624,7 @@ static bool is_guarded_page(CPUARMState *env, Disas= Context *s) * table entry even for that case. */ return (tlb_hit(entry->addr_code, addr) && - arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].iotlb[index].attrs)); + arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].fulltlb[index].attrs)= ); #endif } =20 --=20 2.34.1 From nobody Sat Apr 27 07:51:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664573316; cv=none; d=zohomail.com; s=zohoarc; b=RTRl6USxvHdMthT6SaCJu997vBTq2+54XcjgoX0uKMy/UXq/y+ZkvoCL/Yh2vP2lJ8YgF5u9nll8o99eNcUvZRxPxxOau88qF4YDv0B5nF0BD2pOHb1845vhLyYDp1A+k1StQZKk2ZAJwZB/WJBZpshrHhcIps8HONjxku5pGM4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664573316; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=z6NCzPC6tE1OG0rvY3WzwqtBapUdS48hi6o10eMrDQY=; b=SrNMlMa5RIWRe4kRYO4QSrvh5wEv49cjbikylQbV2U5enNO2DKJeX7aDloTs7XA2z2eJUjaA1PkPxnpNq9Fy2KbmyQnhT6HfRVJztSy0LhEbaXogVIJCrodXQNpkOWr0kp0lQqxlIMynDctiGuxGzvQFQFZ3+M6O1KCHpishQE4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664573316955571.5585860086281; Fri, 30 Sep 2022 14:28:36 -0700 (PDT) Received: from localhost ([::1]:49370 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeNYh-0000UY-Kq for importer@patchew.org; Fri, 30 Sep 2022 17:28:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48196) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeNWs-0006Be-Tp for qemu-devel@nongnu.org; Fri, 30 Sep 2022 17:26:42 -0400 Received: from mail-qv1-xf2f.google.com ([2607:f8b0:4864:20::f2f]:40879) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeNWq-0005O0-9v for qemu-devel@nongnu.org; Fri, 30 Sep 2022 17:26:42 -0400 Received: by mail-qv1-xf2f.google.com with SMTP id h10so1877248qvq.7 for ; Fri, 30 Sep 2022 14:26:38 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 1 - accel/tcg/cputlb.c | 7 +++---- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 1a7e1a9380..009dc0d336 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -225,7 +225,6 @@ struct CPUWatchpoint { * the memory regions get moved around by io_writex. */ typedef struct SavedIOTLB { - hwaddr addr; MemoryRegionSection *section; hwaddr mr_offset; } SavedIOTLB; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index aa22f578cb..d06ff44ce9 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1372,12 +1372,11 @@ static uint64_t io_readx(CPUArchState *env, CPUTLBE= ntryFull *full, * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match * because of the side effect of io_writex changing memory layout. */ -static void save_iotlb_data(CPUState *cs, hwaddr addr, - MemoryRegionSection *section, hwaddr mr_offset) +static void save_iotlb_data(CPUState *cs, MemoryRegionSection *section, + hwaddr mr_offset) { #ifdef CONFIG_PLUGIN SavedIOTLB *saved =3D &cs->saved_iotlb; - saved->addr =3D addr; saved->section =3D section; saved->mr_offset =3D mr_offset; #endif @@ -1406,7 +1405,7 @@ static void io_writex(CPUArchState *env, CPUTLBEntryF= ull *full, * The memory_region_dispatch may trigger a flush/resize * so for plugins we save the iotlb_data just in case. */ - save_iotlb_data(cpu, full->xlat_section, section, mr_offset); + save_iotlb_data(cpu, section, mr_offset); =20 if (!qemu_mutex_iothread_locked()) { qemu_mutex_lock_iothread(); --=20 2.34.1 From nobody Sat Apr 27 07:51:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664573342; cv=none; d=zohomail.com; s=zohoarc; b=nDBXxme+rXM9RuRT63f7XY2zSVmzNUzy4wemgX+LD1kOkTIcmcREXJY5nSlZRsg6/NkIc08qFU6yeMsdb2yY4WeiTXOhMacOCJIlseNqLyLh40cCgeEiH95pfc7Ld+HfFs0D+z+xt7Cno9+2WH0SzR0UO4hG+eNLS1bBnMskrbg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664573342; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=St5dCg8yC5zIkIV0jUFWp9UWjpefIW881mvaUfGPCfo=; b=FWa/R3pSoWr42YNYGaaKtuLCTLPSTjyGC7NUDV2smTu6N/kgjsg3oW9aBseKq1DoELXSSQn5Xwed25WbxoWyUpptVMb8Ifmi/1xFWqQCrdchVZZk5/r1O4/LtdtT11I6/YdrTM/Stfyv8Nchd4nVpq/Gc1kRdtyFeXA5jPDiLM0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664573342257932.2898635359985; Fri, 30 Sep 2022 14:29:02 -0700 (PDT) Received: from localhost ([::1]:47392 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeNZ6-0000qK-9p for importer@patchew.org; Fri, 30 Sep 2022 17:29:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48200) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeNWu-0006FY-AL for qemu-devel@nongnu.org; Fri, 30 Sep 2022 17:26:44 -0400 Received: from mail-qv1-xf2c.google.com ([2607:f8b0:4864:20::f2c]:39858) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeNWr-0005OH-Ry for qemu-devel@nongnu.org; Fri, 30 Sep 2022 17:26:44 -0400 Received: by mail-qv1-xf2c.google.com with SMTP id z18so3378178qvn.6 for ; Fri, 30 Sep 2022 14:26:41 -0700 (PDT) Received: from stoup.. ([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id l18-20020a05620a28d200b006ce813bb306sm3696370qkp.125.2022.09.30.14.26.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 14:26:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=St5dCg8yC5zIkIV0jUFWp9UWjpefIW881mvaUfGPCfo=; b=wyyQ/kPFXbgigJ4kzZxQj6DW70lHpPFMo3lKF7N1JKIgS+LyX5asEN6RWCydAVU9J0 DkM8g3zkSKNPz1jBgBZXl+yTtQJ1TvQSvoeOCOy0hwUyvRIJ8wieS5PH2UloFlXuF3h1 hHPjW9kFWNXiOejIySNfhU24MZ2bnaEzzZ6oXFmlIC5EZmge+FHr1Pl1RT05vlH0Vkge X5v8OdncOATH1w+6av83QvslLJ/+l9HkuYv0RetkoqsCQzOC/ysg8yEFG5CjOFwBfA9+ +laKO/jaURcaHVf/ZLVuyo+30D1q72b5EJpF9MRiFtt3xMpYJL9uuYyfa3ZIEMvqazQk /ynQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=St5dCg8yC5zIkIV0jUFWp9UWjpefIW881mvaUfGPCfo=; b=sEpW5aBhtH+S/8pRedGdXr1uN1yvbxCzirYKs6zwEAxZFWZW5wsAPPTNrlg//NYmee rczzELk02X0IF2XaycWsSLLHlr71ZGf5roCpAaX3Bc/HMhxVeUxZuPjFPf6M3rzq9tjc acXxOM5mU6sVWN4hw6mCzeE/Ufjyh7e0TF0KhPfBixf6xUPv1GsZQZGvBpww2xpqC906 p/perb7NieC9gil71JTZp8bJ/lA2+ZVxUSKRbQn0iEyKuh4nWcrq3nobGyM4Ke9csU1P v8dilFciiokRp+W/RlMAy3GYCW1cHpBPs7QKQOM/wfmDk0GtbqTa+bUalZF6s1c/gmRi 4JEA== X-Gm-Message-State: ACrzQf1Lad9gWv6RsXEq3YJ7xnWQdePKgdN1U5shuhHLsyStjz2t4fGa UarpYx4saaFYv7JEPutjfgsA10kseBDFpw== X-Google-Smtp-Source: AMsMyM6FsBRHrfETcLXaL3mawrA8irQ2f1b0z7fJ9v2dBKaP6vFqPV5jwkEWzHB2CGIIhPye+hqWFA== X-Received: by 2002:a05:6214:5096:b0:4af:aef9:f78c with SMTP id kk22-20020a056214509600b004afaef9f78cmr7994664qvb.63.1664573200394; Fri, 30 Sep 2022 14:26:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linux.org, alex.bennee@linux.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Hildenbrand , Peter Maydell Subject: [PATCH v6 06/18] accel/tcg: Suppress auto-invalidate in probe_access_internal Date: Fri, 30 Sep 2022 14:26:10 -0700 Message-Id: <20220930212622.108363-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930212622.108363-1-richard.henderson@linaro.org> References: <20220930212622.108363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2c; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664573344051100003 When PAGE_WRITE_INV is set when calling tlb_set_page, we immediately set TLB_INVALID_MASK in order to force tlb_fill to be called on the next lookup. Here in probe_access_internal, we have just called tlb_fill and eliminated true misses, thus the lookup must be valid. This allows us to remove a warning comment from s390x. There doesn't seem to be a reason to change the code though. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 10 +++++++++- target/s390x/tcg/mem_helper.c | 4 ---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d06ff44ce9..264f84a248 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1533,6 +1533,7 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, } tlb_addr =3D tlb_read_ofs(entry, elt_ofs); =20 + flags =3D TLB_FLAGS_MASK; page_addr =3D addr & TARGET_PAGE_MASK; if (!tlb_hit_page(tlb_addr, page_addr)) { if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) { @@ -1547,10 +1548,17 @@ static int probe_access_internal(CPUArchState *env,= target_ulong addr, =20 /* TLB resize via tlb_fill may have moved the entry. */ entry =3D tlb_entry(env, mmu_idx, addr); + + /* + * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately, + * to force the next access through tlb_fill. We've just + * called tlb_fill, so we know that this entry *is* valid. + */ + flags &=3D ~TLB_INVALID_MASK; } tlb_addr =3D tlb_read_ofs(entry, elt_ofs); } - flags =3D tlb_addr & TLB_FLAGS_MASK; + flags &=3D tlb_addr; =20 /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) { diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index fc52aa128b..3758b9e688 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -148,10 +148,6 @@ static int s390_probe_access(CPUArchState *env, target= _ulong addr, int size, #else int flags; =20 - /* - * For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr= =3D=3DNULL - * to detect if there was an exception during tlb_fill(). - */ env->tlb_fill_exc =3D 0; flags =3D probe_access_flags(env, addr, access_type, mmu_idx, nonfault= , phost, ra); --=20 2.34.1 From nobody Sat Apr 27 07:51:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664573561; cv=none; d=zohomail.com; s=zohoarc; b=ctgzFE8d7tmJuFoS0TfchRHE3Uvob+PkoYN0jqeTh/fD2btJELinwRTitquRwTI/r2mvlHC1r1qMX8afg/JgqoMY/fTw9MSB6CZbFu/BeuGh1ysFv5KscpEsdoFH+3utk0lhtPJ/Asr0A2V/nqKytadOpjZ8pD6ObtUw0BcP790= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664573561; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=m+Sqb4KGdCuWUPK1XHg8WBMkrVNPK8kei5cVHcxSXxQ=; b=Dme9tyEQXFNw2WberqDWXU9f3nvZ+qk2YFq1c1U4hh1/6OrbwHkAwntygPSEkNazkSv6EFCu5T6H8H0Aond0OGfS7GwMLG6NXDEceD/2N/XbxyVHzQHTcwjF6O7bmgNqLqhlf8iGGrHp5kN7lPpMsBp0h1EseWX1Gx4/AQoIbOQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664573561316182.8653119372093; Fri, 30 Sep 2022 14:32:41 -0700 (PDT) Received: from localhost ([::1]:36196 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeNce-00062J-8m for importer@patchew.org; Fri, 30 Sep 2022 17:32:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60692) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeNWv-0006Kp-Rm for qemu-devel@nongnu.org; Fri, 30 Sep 2022 17:26:45 -0400 Received: from mail-qv1-xf29.google.com ([2607:f8b0:4864:20::f29]:43612) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeNWt-0005OW-Tc for qemu-devel@nongnu.org; Fri, 30 Sep 2022 17:26:45 -0400 Received: by mail-qv1-xf29.google.com with SMTP id s13so3581678qvq.10 for ; Fri, 30 Sep 2022 14:26:43 -0700 (PDT) Received: from stoup.. ([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id l18-20020a05620a28d200b006ce813bb306sm3696370qkp.125.2022.09.30.14.26.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 14:26:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=m+Sqb4KGdCuWUPK1XHg8WBMkrVNPK8kei5cVHcxSXxQ=; b=OjU3Mkc1aoJs1Qej/N02NP/lVewAvuvszEgv6hpmljQxGASeyiXe5QC9gAhD14AYFh jH1rrys9wG/lX06f8nzT5gARmg5IMSPoIX84Y+sJ+OS0vNOVDut0gzxelm8E0UA59FR2 /veV6neiXr0+mTum9hD2r6QXaKHXofcktMudjMGSMpskmeE9eq/Wzt9jANzJN6gapT/N YQ5ppWWB0x1HbddyjxlhDZ/0kmwvXJCi+/q4FUbSKyCKAJxMq0IYY99cTewgy5Img3+M XKKxcYV42cWyXLuZjby0wAzChF3KpvV7D4dHjPYg2HP5NC6VDg+rUiCTiK2nuzFRZ0Ej HrSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=m+Sqb4KGdCuWUPK1XHg8WBMkrVNPK8kei5cVHcxSXxQ=; b=LSd+2xiz8qLKofBYe3ri/aYPrW1E/yveuos2WVX3EvTfsjfnInSZ/tgRDS1q12FS2u 2NhoqxXXB5YhJdudC9dWlIV3x5ahuvLuASWXnIZ396RmxiAwCmbYZqXRGDn9156Hgq5j 5ML9iH2Nv9yw0g6V3dhHYNq+nE3Zqc5wmQFTwRm1ZGeUda/FvKkN5HHyQVSHIJ9EuxCz FvP9nT0e7BuxSV6feA4OelyyRqojlaiN7RSJ2Z2CZKcLntfsgodkIgW+TYTTKjoYgzjN cUZ4V66bsx5eB3msI/Tybk3JU7puaI5kUF4XwDLvwyQepXXxXJBEiwLV7vgzl8Ec8jXr DEJw== X-Gm-Message-State: ACrzQf2mS8UeaKaHB2IefcpToT7BdaIK0B2Xd8dzEifzE18noNvjfjfk q8oODi3KhxCvxC28dsDK6NyjKDjXC7Hq1w== X-Google-Smtp-Source: AMsMyM5qEI9c/PGRslrDgB8thZYv0Wb9l62Vroc4ofNH3agQmLYicsMv8RgD8Itbp0wUq3r04DB8Tg== X-Received: by 2002:a05:6214:3011:b0:4ad:82d6:d579 with SMTP id ke17-20020a056214301100b004ad82d6d579mr8670464qvb.37.1664573203068; Fri, 30 Sep 2022 14:26:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linux.org, alex.bennee@linux.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 07/18] accel/tcg: Introduce probe_access_full Date: Fri, 30 Sep 2022 14:26:11 -0700 Message-Id: <20220930212622.108363-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930212622.108363-1-richard.henderson@linaro.org> References: <20220930212622.108363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f29; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664573562033100001 Add an interface to return the CPUTLBEntryFull struct that goes with the lookup. The result is not intended to be valid across multiple lookups, so the user must use the results immediately. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 15 +++++++++++++ accel/tcg/cputlb.c | 47 +++++++++++++++++++++++++---------------- 2 files changed, 44 insertions(+), 18 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index bcad607c4e..d255d69bc1 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -434,6 +434,21 @@ int probe_access_flags(CPUArchState *env, target_ulong= addr, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr); =20 +#ifndef CONFIG_USER_ONLY +/** + * probe_access_full: + * Like probe_access_flags, except also return into @pfull. + * + * The CPUTLBEntryFull structure returned via @pfull is transient + * and must be consumed or copied immediately, before any further + * access or changes to TLB @mmu_idx. + */ +int probe_access_full(CPUArchState *env, target_ulong addr, + MMUAccessType access_type, int mmu_idx, + bool nonfault, void **phost, + CPUTLBEntryFull **pfull, uintptr_t retaddr); +#endif + #define CODE_GEN_ALIGN 16 /* must be >=3D of the size of a icach= e line */ =20 /* Estimated block size for TB allocation. */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 264f84a248..e3ee4260bd 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1510,7 +1510,8 @@ static void notdirty_write(CPUState *cpu, vaddr mem_v= addr, unsigned size, static int probe_access_internal(CPUArchState *env, target_ulong addr, int fault_size, MMUAccessType access_type, int mmu_idx, bool nonfault, - void **phost, uintptr_t retaddr) + void **phost, CPUTLBEntryFull **pfull, + uintptr_t retaddr) { uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); @@ -1543,10 +1544,12 @@ static int probe_access_internal(CPUArchState *env,= target_ulong addr, mmu_idx, nonfault, retaddr)) { /* Non-faulting page table read failed. */ *phost =3D NULL; + *pfull =3D NULL; return TLB_INVALID_MASK; } =20 /* TLB resize via tlb_fill may have moved the entry. */ + index =3D tlb_index(env, mmu_idx, addr); entry =3D tlb_entry(env, mmu_idx, addr); =20 /* @@ -1560,6 +1563,8 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, } flags &=3D tlb_addr; =20 + *pfull =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) { *phost =3D NULL; @@ -1571,37 +1576,44 @@ static int probe_access_internal(CPUArchState *env,= target_ulong addr, return flags; } =20 -int probe_access_flags(CPUArchState *env, target_ulong addr, - MMUAccessType access_type, int mmu_idx, - bool nonfault, void **phost, uintptr_t retaddr) +int probe_access_full(CPUArchState *env, target_ulong addr, + MMUAccessType access_type, int mmu_idx, + bool nonfault, void **phost, CPUTLBEntryFull **pfull, + uintptr_t retaddr) { - int flags; - - flags =3D probe_access_internal(env, addr, 0, access_type, mmu_idx, - nonfault, phost, retaddr); + int flags =3D probe_access_internal(env, addr, 0, access_type, mmu_idx, + nonfault, phost, pfull, retaddr); =20 /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; - - notdirty_write(env_cpu(env), addr, 1, full, retaddr); + notdirty_write(env_cpu(env), addr, 1, *pfull, retaddr); flags &=3D ~TLB_NOTDIRTY; } =20 return flags; } =20 +int probe_access_flags(CPUArchState *env, target_ulong addr, + MMUAccessType access_type, int mmu_idx, + bool nonfault, void **phost, uintptr_t retaddr) +{ + CPUTLBEntryFull *full; + + return probe_access_full(env, addr, access_type, mmu_idx, + nonfault, phost, &full, retaddr); +} + void *probe_access(CPUArchState *env, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retad= dr) { + CPUTLBEntryFull *full; void *host; int flags; =20 g_assert(-(addr | TARGET_PAGE_MASK) >=3D size); =20 flags =3D probe_access_internal(env, addr, size, access_type, mmu_idx, - false, &host, retaddr); + false, &host, &full, retaddr); =20 /* Per the interface, size =3D=3D 0 merely faults the access. */ if (size =3D=3D 0) { @@ -1609,9 +1621,6 @@ void *probe_access(CPUArchState *env, target_ulong ad= dr, int size, } =20 if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) { - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; - /* Handle watchpoints. */ if (flags & TLB_WATCHPOINT) { int wp_access =3D (access_type =3D=3D MMU_DATA_STORE @@ -1632,11 +1641,12 @@ void *probe_access(CPUArchState *env, target_ulong = addr, int size, void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, MMUAccessType access_type, int mmu_idx) { + CPUTLBEntryFull *full; void *host; int flags; =20 flags =3D probe_access_internal(env, addr, 0, access_type, - mmu_idx, true, &host, 0); + mmu_idx, true, &host, &full, 0); =20 /* No combination of flags are expected by the caller. */ return flags ? NULL : host; @@ -1655,10 +1665,11 @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr = addr, tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong ad= dr, void **hostp) { + CPUTLBEntryFull *full; void *p; =20 (void)probe_access_internal(env, addr, 1, MMU_INST_FETCH, - cpu_mmu_index(env, true), false, &p, 0); + cpu_mmu_index(env, true), false, &p, &full= , 0); if (p =3D=3D NULL) { return -1; } --=20 2.34.1 From nobody Sat Apr 27 07:51:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664573822; cv=none; d=zohomail.com; s=zohoarc; b=TXMEgpIfb9dEu5lIbjlSV+wfWtiH4rFbBHApD12KsgQKcnvhGusRbscrYeFdReXf3rZsJTORXbeelHo7a6FNx35sQhdX/ZnHpjVNQ7ogTPo3keZM/oxqXgxl0Qd2YIlAwtb3FMjJja5q5/wrL4ix9WX1HXwNACaiU9SeJAkEng8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664573822; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dAY3x/lc+/32wE3SHUuBvqOuB1dTrfgmxaF5UaNYDSM=; b=nTlp7TCzpFF0L6FTO+qWdlDgk3bJ1dgR58XT6+3Z3ONnwg7FMhu80SEdI7yWGNMAwVidWqzn7w0WVwNYE4Lb6SFK1J21XmvLtelFt5W36i3inVNNq/NPwLO4iMSWyyzsvV39DZL6AV35KDAiRDd0JWi/MBYV4HhfQDhUYNXhipY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664573822470414.7284937298897; Fri, 30 Sep 2022 14:37:02 -0700 (PDT) Received: from localhost ([::1]:36238 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeNgr-00039A-8C for importer@patchew.org; Fri, 30 Sep 2022 17:37:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60696) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeNWy-0006T4-0u for qemu-devel@nongnu.org; Fri, 30 Sep 2022 17:26:48 -0400 Received: from mail-qk1-x736.google.com ([2607:f8b0:4864:20::736]:45784) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeNWw-0005Op-59 for qemu-devel@nongnu.org; Fri, 30 Sep 2022 17:26:47 -0400 Received: by mail-qk1-x736.google.com with SMTP id i17so3605056qkk.12 for ; Fri, 30 Sep 2022 14:26:45 -0700 (PDT) Received: from stoup.. ([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id l18-20020a05620a28d200b006ce813bb306sm3696370qkp.125.2022.09.30.14.26.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 14:26:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=dAY3x/lc+/32wE3SHUuBvqOuB1dTrfgmxaF5UaNYDSM=; b=LyAx713FsGqZPlEYHubbGANF2BxE+FvOtJ1XXhRaHhGnAXLsNgW12IrrABW/ahc3jF l3GCjkHc9CnzwwS1bZQaFc+8f7JDTclY6q2xx5xh6FPo2T+rolWaC4fn/Rc2skzIiAWg WpxFQ+r4qZ92/4EFzr6hO74RcTJ1u0TT01CxeftYwUtfSY3OfdJPbiA5quMm+fq8TQpb djqRz0GVAH5F+tbFKKUTMxBZLW7E5L0d4+LHoCjqpVFRddIZa5Xs2Sv4BG5HoEYUQNup m2WRQakiwBPRhUurhSZxtwrkUs1K4DNCr+zTULKVkGCJyvOrNfT9r40qlURi4ziaewFx OyOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=dAY3x/lc+/32wE3SHUuBvqOuB1dTrfgmxaF5UaNYDSM=; b=awrky+rvJMrvPyk0i8n9yZM5eXJzh1QUbuYL7R5yRtP/ZxWw7fDyMj4GWnpM+YVH+Q /4VhCJlvHFpBu5hng+2e2SYRzCWuMu4JxgxFIPje0xYNhS/VAcIUBGUmJztn0sXzVRWl BiJ/6kbhn5kkAHc9Wg9LioL8VywCS1saEpSrqfMugOBLhqlYlsU35RLbFteIlDJRkR56 YLRGgv863n0YeVwPDgxBTwraucuwgKXDDmUNJb9u33VLfxtfEAcwnUE0RtB7uNBsTVix 2goQR4lf/YhTYEQJE527DkSNX6smhIFnl/XGidFi8QwMJA0/AG6c3D69HptRKi5xVbMy eRoQ== X-Gm-Message-State: ACrzQf2wWD56CkZXGhO+EXvFGBizcnLQVHO8whgku6JQemqVGvgEfgn8 4XAiLAtD+JrsvyogeIfkhwYEOpM09bfAYA== X-Google-Smtp-Source: AMsMyM4v07izf/ZTJKRya1f18YBIFiJNcTClkLbkNjBTXNc9ku9EBNIccNU5ZKlcBqLFCKpNPTthOA== X-Received: by 2002:a05:620a:99b:b0:6ce:4c0a:3ab2 with SMTP id x27-20020a05620a099b00b006ce4c0a3ab2mr7509188qkx.250.1664573205199; Fri, 30 Sep 2022 14:26:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linux.org, alex.bennee@linux.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 08/18] accel/tcg: Introduce tlb_set_page_full Date: Fri, 30 Sep 2022 14:26:12 -0700 Message-Id: <20220930212622.108363-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930212622.108363-1-richard.henderson@linaro.org> References: <20220930212622.108363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::736; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x736.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664573823969100001 Now that we have collected all of the page data into CPUTLBEntryFull, provide an interface to record that all in one go, instead of using 4 arguments. This interface allows CPUTLBEntryFull to be extended without having to change the number of arguments. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 14 +++++++++++ include/exec/exec-all.h | 22 ++++++++++++++++++ accel/tcg/cputlb.c | 51 ++++++++++++++++++++++++++--------------- 3 files changed, 69 insertions(+), 18 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index f70f54d850..5e12cc1854 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -148,7 +148,21 @@ typedef struct CPUTLBEntryFull { * + the offset within the target MemoryRegion (otherwise) */ hwaddr xlat_section; + + /* + * @phys_addr contains the physical address in the address space + * given by cpu_asidx_from_attrs(cpu, @attrs). + */ + hwaddr phys_addr; + + /* @attrs contains the memory transaction attributes for the page. */ MemTxAttrs attrs; + + /* @prot contains the complete protections for the page. */ + uint8_t prot; + + /* @lg_page_size contains the log2 of the page size. */ + uint8_t lg_page_size; } CPUTLBEntryFull; =20 /* diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index d255d69bc1..b1b920a713 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -257,6 +257,28 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUStat= e *cpu, uint16_t idxmap, unsigned bits); =20 +/** + * tlb_set_page_full: + * @cpu: CPU context + * @mmu_idx: mmu index of the tlb to modify + * @vaddr: virtual address of the entry to add + * @full: the details of the tlb entry + * + * Add an entry to @cpu tlb index @mmu_idx. All of the fields of + * @full must be filled, except for xlat_section, and constitute + * the complete description of the translated page. + * + * This is generally called by the target tlb_fill function after + * having performed a successful page table walk to find the physical + * address and attributes for the translation. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only + * used by tlb_flush_page. + */ +void tlb_set_page_full(CPUState *cpu, int mmu_idx, target_ulong vaddr, + CPUTLBEntryFull *full); + /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e3ee4260bd..361078471b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1095,16 +1095,16 @@ static void tlb_add_large_page(CPUArchState *env, i= nt mmu_idx, env_tlb(env)->d[mmu_idx].large_page_mask =3D lp_mask; } =20 -/* Add a new TLB entry. At most one entry for a given virtual address +/* + * Add a new TLB entry. At most one entry for a given virtual address * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the * supplied size is only used by tlb_flush_page. * * Called from TCG-generated code, which is under an RCU read-side * critical section. */ -void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, - hwaddr paddr, MemTxAttrs attrs, int prot, - int mmu_idx, target_ulong size) +void tlb_set_page_full(CPUState *cpu, int mmu_idx, + target_ulong vaddr, CPUTLBEntryFull *full) { CPUArchState *env =3D cpu->env_ptr; CPUTLB *tlb =3D env_tlb(env); @@ -1117,35 +1117,36 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_= ulong vaddr, CPUTLBEntry *te, tn; hwaddr iotlb, xlat, sz, paddr_page; target_ulong vaddr_page; - int asidx =3D cpu_asidx_from_attrs(cpu, attrs); - int wp_flags; + int asidx, wp_flags, prot; bool is_ram, is_romd; =20 assert_cpu_is_self(cpu); =20 - if (size <=3D TARGET_PAGE_SIZE) { + if (full->lg_page_size <=3D TARGET_PAGE_BITS) { sz =3D TARGET_PAGE_SIZE; } else { - tlb_add_large_page(env, mmu_idx, vaddr, size); - sz =3D size; + sz =3D (hwaddr)1 << full->lg_page_size; + tlb_add_large_page(env, mmu_idx, vaddr, sz); } vaddr_page =3D vaddr & TARGET_PAGE_MASK; - paddr_page =3D paddr & TARGET_PAGE_MASK; + paddr_page =3D full->phys_addr & TARGET_PAGE_MASK; =20 + prot =3D full->prot; + asidx =3D cpu_asidx_from_attrs(cpu, full->attrs); section =3D address_space_translate_for_iotlb(cpu, asidx, paddr_page, - &xlat, &sz, attrs, &prot); + &xlat, &sz, full->attrs, &= prot); assert(sz >=3D TARGET_PAGE_SIZE); =20 tlb_debug("vaddr=3D" TARGET_FMT_lx " paddr=3D0x" TARGET_FMT_plx " prot=3D%x idx=3D%d\n", - vaddr, paddr, prot, mmu_idx); + vaddr, full->phys_addr, prot, mmu_idx); =20 address =3D vaddr_page; - if (size < TARGET_PAGE_SIZE) { + if (full->lg_page_size < TARGET_PAGE_BITS) { /* Repeat the MMU check and TLB fill on every access. */ address |=3D TLB_INVALID_MASK; } - if (attrs.byte_swap) { + if (full->attrs.byte_swap) { address |=3D TLB_BSWAP; } =20 @@ -1236,8 +1237,10 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_u= long vaddr, * subtract here is that of the page base, and not the same as the * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). */ + desc->fulltlb[index] =3D *full; desc->fulltlb[index].xlat_section =3D iotlb - vaddr_page; - desc->fulltlb[index].attrs =3D attrs; + desc->fulltlb[index].phys_addr =3D paddr_page; + desc->fulltlb[index].prot =3D prot; =20 /* Now calculate the new entry */ tn.addend =3D addend - vaddr_page; @@ -1272,9 +1275,21 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_u= long vaddr, qemu_spin_unlock(&tlb->c.lock); } =20 -/* Add a new TLB entry, but without specifying the memory - * transaction attributes to be used. - */ +void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, + hwaddr paddr, MemTxAttrs attrs, int prot, + int mmu_idx, target_ulong size) +{ + CPUTLBEntryFull full =3D { + .phys_addr =3D paddr, + .attrs =3D attrs, + .prot =3D prot, + .lg_page_size =3D ctz64(size) + }; + + assert(is_power_of_2(size)); + tlb_set_page_full(cpu, mmu_idx, vaddr, &full); +} + void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size) --=20 2.34.1 From nobody Sat Apr 27 07:51:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id l18-20020a05620a28d200b006ce813bb306sm3696370qkp.125.2022.09.30.14.26.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 14:26:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=pPZ5BGim//7jDbDR7RtfT/BbVdLxSz70QtZLu4dhW0s=; b=prbHZS2FnkFrvu/FG/97FvMy2MOeK9IFnU5C4synr+hbKxZApVc4z8OncYHCIdBwfU /JMqWmAAVvbw+qHT8XFXXvl7SMmBPl7RI+O586GtjYiRBI08FUy63djdzqANeS1ObTyf 8yYzE1s3MmlUvuya13D/7umNshpNAgvJ2r7NtiIUXe4Wu9Isz5iPu3Z8z8Tcw/+K7smv 8XtbkO8e/Gqra/OTHthUfQxr4UkScKIOmh0+onGSbqFb+TtTkE0i6/EIvuUFThxCewfR +J2LxsFsWGyutOLuBBxiXkxZfGrpjbOBjDd7AAvGZ5BBEEDv3/R1Q6EsJfbnAnk9yYCT klnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=pPZ5BGim//7jDbDR7RtfT/BbVdLxSz70QtZLu4dhW0s=; b=lBYeX9ho1fyA5qf/IcKrM4dg5+K9sN39kQAULxzITWM5766/aq6EK59sD0TNnhTWe6 78k/eiY+RNgMQyoTOl5uUPZ48+jOcC5weu0TPFqLqzge/4NBUtgFYCsYUaiLBlqSSmZP XGD6Pz31ILk4VYoMowGAEdXDBAKG7GRSMLPqpX7w+QIG74hsY0ueWpYmYHmFUsZHkJ1G vaF5nCaX7Fr3FoBY7sqvj7jQ6zuY8om5MMH0E/3oGifNvkRw/BzGE/ILrF1DzaFDZHNg SyFtFwh7kJjbbe/jGdnnhwAEq9uy8lyQ+A4GHG4/FYcYHzGUnlDF0EHq/NcqyEQeb01H KG7w== X-Gm-Message-State: ACrzQf2FGKfKtMdTMvZlvP9Ueq2VoOAkvJ6JfIjP1uPxc8zq3WZVFxdi LvFsop5KHZMYHiq14y+YQqLG+EGprnBRgw== X-Google-Smtp-Source: AMsMyM7KIR9bWx8lrKZBnDOBPS+GUpG6dzGcUGRj354+gqoFQBeBi9UfwGGGqi9iqM+BLfdYZFEnAw== X-Received: by 2002:a05:620a:2605:b0:6ce:1509:e9f7 with SMTP id z5-20020a05620a260500b006ce1509e9f7mr7628039qko.379.1664573207329; Fri, 30 Sep 2022 14:26:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linux.org, alex.bennee@linux.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 09/18] include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA Date: Fri, 30 Sep 2022 14:26:13 -0700 Message-Id: <20220930212622.108363-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930212622.108363-1-richard.henderson@linaro.org> References: <20220930212622.108363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::731; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x731.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664573952907100001 Allow the target to cache items from the guest page tables. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 5e12cc1854..67239b4e5e 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -163,6 +163,15 @@ typedef struct CPUTLBEntryFull { =20 /* @lg_page_size contains the log2 of the page size. */ uint8_t lg_page_size; + + /* + * Allow target-specific additions to this structure. + * This may be used to cache items from the guest cpu + * page tables for later use by the implementation. + */ +#ifdef TARGET_PAGE_ENTRY_EXTRA + TARGET_PAGE_ENTRY_EXTRA +#endif } CPUTLBEntryFull; =20 /* --=20 2.34.1 From nobody Sat Apr 27 07:51:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664574142; cv=none; d=zohomail.com; s=zohoarc; b=QYW+WWUfyfAYTs9sBQxDNz9k2D9ywKL4OHMryibB1J9OoFE/tm2/pm6j8vL8QHcSXFryeF3zhxI4eh14xh66mBctDSLzeZVF7wsQ8kmXu8uOZE3GpHRK+uamh4dPoLK9W8miC2btAxt2SfNUVetY11umXB+rrcMpg9qY0bzVr88= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664574142; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iNSv5kupswjOCEJBCw0DforCHK3ePnESyn5fLqIud2Q=; b=j7fFx+T2U7yxqR7FIK37+MDL0RCx8ELIXmBOM+BrPPU2rs4awiqDZBj9mQFEa+/V+WXuNvYxL4pAuDpj7tcMGzElSYs1cFdKlUlFQzOXArEqX7iYYlZ+RDtZrRW67gt5WFoPv4wo5u7ms4K2ML2kzJH436rCT8k2asZHRsX8oqs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664574142086563.7448024730195; Fri, 30 Sep 2022 14:42:22 -0700 (PDT) Received: from localhost ([::1]:55910 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeNm0-00021T-Pk for importer@patchew.org; Fri, 30 Sep 2022 17:42:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeNX2-0006g1-CC for qemu-devel@nongnu.org; Fri, 30 Sep 2022 17:26:52 -0400 Received: from mail-qv1-xf2e.google.com ([2607:f8b0:4864:20::f2e]:45748) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeNX0-0005PU-IP for qemu-devel@nongnu.org; Fri, 30 Sep 2022 17:26:52 -0400 Received: by mail-qv1-xf2e.google.com with SMTP id m18so3574515qvo.12 for ; Fri, 30 Sep 2022 14:26:50 -0700 (PDT) Received: from stoup.. ([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id l18-20020a05620a28d200b006ce813bb306sm3696370qkp.125.2022.09.30.14.26.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 14:26:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=iNSv5kupswjOCEJBCw0DforCHK3ePnESyn5fLqIud2Q=; b=bwNX081EWvP9oo86UkS1k5quV2yfv94BkZQUi5ShkR1a+ury9qyxl09uXMcRtzXsyf +8VkEItMoRQzMfG9mlcTp+DGwdqejSW5iGEzjkOskIPAzx78C+goY8+OPZHLRkWq0COK tOsTlTbFwCfh9Lm/C7JRBPWpVA5eQH25w7eCvQJo0K//isswBAMcmbpJz7A/MgMnWBjU wsK12xb+9dCGpLmVuMm/f+bLF2UonGDoOyfAt9azEDSaHtVEj0Sxb2zrbB4sa3BQTziu dW9FghyV6IZ5aA3KweUPUBlDG9cH71XZyzKtjaiquSrao5Db2jPGbBCg1FjG+QoFrJSK YNBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=iNSv5kupswjOCEJBCw0DforCHK3ePnESyn5fLqIud2Q=; b=gyTbVX3sXIZOYIPE7TRBKsmEaAg8IMK7oTLOVhQoyK6D5Pr7L/EY1MlVf3xr0zKAiS KYG0frkQ43peBeJeyzDkQLBKGwFWJknALjwA+0fi17kG358BuyFlmGVeMQYfS0lIK32e QHqGH7ug9lTjymiqH2r6w2HMrpigUnmO/GXCuKSTTBvkwSXHvATOfIPBr5KqpZ5yySQA fa3pONUZZpZEpSN9Gc3uSPM2XSPa+hcF5ibYFI3ljsa3YonmAXT0XIex/WxOwxD2qXcm xmIN6ui+oe+x9eVPgrFWidfggouJXG7lWS7avB7nPEanQz0MSBAFTiTGTc4FFnKAqRvP ML7g== X-Gm-Message-State: ACrzQf1VwunGGdkzGMQ57aUkDIh4vdVGnw5nM6prnwER96gVTU861x5s umaX+Za+PPiqvhUR68nQcRQyF0r7F6+HDQ== X-Google-Smtp-Source: AMsMyM6/pu1Oa/gYdwYyPZjLyCB1Zy4nIaMWDLTzaz0Eqdk2Lr348Gbw71IofxBEmDkBFxTsJ0l8Xg== X-Received: by 2002:a0c:9cc2:0:b0:4ac:d5ec:cd5a with SMTP id j2-20020a0c9cc2000000b004acd5eccd5amr8638024qvf.131.1664573209582; Fri, 30 Sep 2022 14:26:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linux.org, alex.bennee@linux.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v6 10/18] accel/tcg: Remove PageDesc code_bitmap Date: Fri, 30 Sep 2022 14:26:14 -0700 Message-Id: <20220930212622.108363-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930212622.108363-1-richard.henderson@linaro.org> References: <20220930212622.108363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2e; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664574143330100001 This bitmap is created and discarded immediately. We gain nothing by its existence. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-Id: <20220822232338.1727934-2-richard.henderson@linaro.org> --- accel/tcg/translate-all.c | 78 ++------------------------------------- 1 file changed, 4 insertions(+), 74 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index d71d04d338..59432dc558 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -102,21 +102,14 @@ #define assert_memory_lock() tcg_debug_assert(have_mmap_lock()) #endif =20 -#define SMC_BITMAP_USE_THRESHOLD 10 - typedef struct PageDesc { /* list of TBs intersecting this ram page */ uintptr_t first_tb; -#ifdef CONFIG_SOFTMMU - /* in order to optimize self modifying code, we count the number - of lookups we do to a given page to use a bitmap */ - unsigned long *code_bitmap; - unsigned int code_write_count; -#else +#ifdef CONFIG_USER_ONLY unsigned long flags; void *target_data; #endif -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_SOFTMMU QemuSpin lock; #endif } PageDesc; @@ -907,17 +900,6 @@ void tb_htable_init(void) qht_init(&tb_ctx.htable, tb_cmp, CODE_GEN_HTABLE_SIZE, mode); } =20 -/* call with @p->lock held */ -static inline void invalidate_page_bitmap(PageDesc *p) -{ - assert_page_locked(p); -#ifdef CONFIG_SOFTMMU - g_free(p->code_bitmap); - p->code_bitmap =3D NULL; - p->code_write_count =3D 0; -#endif -} - /* Set to NULL all the 'first_tb' fields in all PageDescs. */ static void page_flush_tb_1(int level, void **lp) { @@ -932,7 +914,6 @@ static void page_flush_tb_1(int level, void **lp) for (i =3D 0; i < V_L2_SIZE; ++i) { page_lock(&pd[i]); pd[i].first_tb =3D (uintptr_t)NULL; - invalidate_page_bitmap(pd + i); page_unlock(&pd[i]); } } else { @@ -1197,11 +1178,9 @@ static void do_tb_phys_invalidate(TranslationBlock *= tb, bool rm_from_page_list) if (rm_from_page_list) { p =3D page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); tb_page_remove(p, tb); - invalidate_page_bitmap(p); if (tb->page_addr[1] !=3D -1) { p =3D page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); tb_page_remove(p, tb); - invalidate_page_bitmap(p); } } =20 @@ -1246,35 +1225,6 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_pag= e_addr_t page_addr) } } =20 -#ifdef CONFIG_SOFTMMU -/* call with @p->lock held */ -static void build_page_bitmap(PageDesc *p) -{ - int n, tb_start, tb_end; - TranslationBlock *tb; - - assert_page_locked(p); - p->code_bitmap =3D bitmap_new(TARGET_PAGE_SIZE); - - PAGE_FOR_EACH_TB(p, tb, n) { - /* NOTE: this is subtle as a TB may span two physical pages */ - if (n =3D=3D 0) { - /* NOTE: tb_end may be after the end of the page, but - it is not a problem */ - tb_start =3D tb->pc & ~TARGET_PAGE_MASK; - tb_end =3D tb_start + tb->size; - if (tb_end > TARGET_PAGE_SIZE) { - tb_end =3D TARGET_PAGE_SIZE; - } - } else { - tb_start =3D 0; - tb_end =3D ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); - } - bitmap_set(p->code_bitmap, tb_start, tb_end - tb_start); - } -} -#endif - /* add the tb in the target page and protect it if necessary * * Called with mmap_lock held for user-mode emulation. @@ -1295,7 +1245,6 @@ static inline void tb_page_add(PageDesc *p, Translati= onBlock *tb, page_already_protected =3D p->first_tb !=3D (uintptr_t)NULL; #endif p->first_tb =3D (uintptr_t)tb | n; - invalidate_page_bitmap(p); =20 #if defined(CONFIG_USER_ONLY) /* translator_loop() must have made all TB pages non-writable */ @@ -1357,10 +1306,8 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t ph= ys_pc, /* remove TB from the page(s) if we couldn't insert it */ if (unlikely(existing_tb)) { tb_page_remove(p, tb); - invalidate_page_bitmap(p); if (p2) { tb_page_remove(p2, tb); - invalidate_page_bitmap(p2); } tb =3D existing_tb; } @@ -1731,7 +1678,6 @@ tb_invalidate_phys_page_range__locked(struct page_col= lection *pages, #if !defined(CONFIG_USER_ONLY) /* if no code remaining, no need to continue to use slow writes */ if (!p->first_tb) { - invalidate_page_bitmap(p); tlb_unprotect_code(start); } #endif @@ -1827,24 +1773,8 @@ void tb_invalidate_phys_page_fast(struct page_collec= tion *pages, } =20 assert_page_locked(p); - if (!p->code_bitmap && - ++p->code_write_count >=3D SMC_BITMAP_USE_THRESHOLD) { - build_page_bitmap(p); - } - if (p->code_bitmap) { - unsigned int nr; - unsigned long b; - - nr =3D start & ~TARGET_PAGE_MASK; - b =3D p->code_bitmap[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG - 1)); - if (b & ((1 << len) - 1)) { - goto do_invalidate; - } - } else { - do_invalidate: - tb_invalidate_phys_page_range__locked(pages, p, start, start + len, - retaddr); - } + tb_invalidate_phys_page_range__locked(pages, p, start, start + len, + retaddr); } #else /* Called with mmap_lock held. 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([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id l18-20020a05620a28d200b006ce813bb306sm3696370qkp.125.2022.09.30.14.26.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 14:26:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=cLUCkFTb6+JnLlWzn7HnttSYfDBpIhciH0RgPU16KNQ=; b=dpp0QS1Q/gtJ8GNcMr4xSFosa6KzRxwb+om6i4QYBGqJiWYYh8q57nKgjr86iSkZLY qkVF4DSpERyAqjutLT/UjNN5MCNc2NGwxEaDzZnac8kJiyCEOKckxz9N4/PFM4LNkkg+ tDEPuCj8TtJERBu366gWuIdJgrIU1vCVAlt1SODs+X0l/FhLfOoZJNsP5hpfDgUGmr// J2LFNUNqORUsS5VHTfHrv8MYxvPVUWzjsaAHdBg2fHZ48KDoH0fFzfczzsQt78gq7zWY cT0wn3C0Mp4s1cleneD/10AIwI1rO1M9X8zDngYsuU1m0iwkVUwmTV0vUDYXT0SpUWU8 Iwcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=cLUCkFTb6+JnLlWzn7HnttSYfDBpIhciH0RgPU16KNQ=; b=nqLAGGlTPGFAr0Gm+LfqtP9P3WyPwVMByuMCZgQxO1U/TPtAeJ/PAKW/NYSKeJ4tA+ efW4+djk0i1Hygt+FgJh534iYIt2Fjd36ILeMZbkGmFEQAYPrhy6eFNNckA0L3zOACyh WiiFbVL1NX4F3eQAlTYQfC2cOcYXsJcWNaIzpKlSY34uh+L+9aI+dSMPDiCLYI50D7Tc GDKv/OOlgaxlCSWdQxXrohCfy/2aWa6yxzW9cB1odUbp0Fq7zsvANeq56KB0CNV17qP4 K7KqzxLsXm61rWGRWsGcVLC7ULsmNJ/9sKsxD+ZW9UFhdBfq3c0Se6ZqyqNhFYgsPsr+ CAjQ== X-Gm-Message-State: ACrzQf3OBgg/xPkzpQkJ63MGa97AiRcfvDj7w9KpqYA1roufyyofx5s7 eWbhxnnImmB0EWN9HC/SD7P7SCMgGLAdCA== X-Google-Smtp-Source: AMsMyM5lV9eLCQWjIGDnN3hMr2iybl/J9bVl+uT4kvsb5/3A2YfjjdTU2oCw/qPzHb5O53apNNnzmg== X-Received: by 2002:a05:620a:404f:b0:6ce:8c88:406d with SMTP id i15-20020a05620a404f00b006ce8c88406dmr7584386qko.358.1664573211519; Fri, 30 Sep 2022 14:26:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linux.org, alex.bennee@linux.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 11/18] accel/tcg: Use bool for page_find_alloc Date: Fri, 30 Sep 2022 14:26:15 -0700 Message-Id: <20220930212622.108363-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930212622.108363-1-richard.henderson@linaro.org> References: <20220930212622.108363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::730; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x730.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664573781828100003 Bool is more appropriate type for the alloc parameter. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 59432dc558..ca685f6ede 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -465,7 +465,7 @@ void page_init(void) #endif } =20 -static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) +static PageDesc *page_find_alloc(tb_page_addr_t index, bool alloc) { PageDesc *pd; void **lp; @@ -533,11 +533,11 @@ static PageDesc *page_find_alloc(tb_page_addr_t index= , int alloc) =20 static inline PageDesc *page_find(tb_page_addr_t index) { - return page_find_alloc(index, 0); + return page_find_alloc(index, false); } =20 static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1, - PageDesc **ret_p2, tb_page_addr_t phys2, int al= loc); + PageDesc **ret_p2, tb_page_addr_t phys2, bool a= lloc); =20 /* In user-mode page locks aren't used; mmap_lock is enough */ #ifdef CONFIG_USER_ONLY @@ -651,7 +651,7 @@ static inline void page_unlock(PageDesc *pd) /* lock the page(s) of a TB in the correct acquisition order */ static inline void page_lock_tb(const TranslationBlock *tb) { - page_lock_pair(NULL, tb->page_addr[0], NULL, tb->page_addr[1], 0); + page_lock_pair(NULL, tb->page_addr[0], NULL, tb->page_addr[1], false); } =20 static inline void page_unlock_tb(const TranslationBlock *tb) @@ -840,7 +840,7 @@ void page_collection_unlock(struct page_collection *set) #endif /* !CONFIG_USER_ONLY */ =20 static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1, - PageDesc **ret_p2, tb_page_addr_t phys2, int al= loc) + PageDesc **ret_p2, tb_page_addr_t phys2, bool a= lloc) { PageDesc *p1, *p2; tb_page_addr_t page1; @@ -1290,7 +1290,7 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phy= s_pc, * Note that inserting into the hash table first isn't an option, since * we can only insert TBs that are fully initialized. */ - page_lock_pair(&p, phys_pc, &p2, phys_page2, 1); + page_lock_pair(&p, phys_pc, &p2, phys_page2, true); tb_page_add(p, tb, 0, phys_pc & TARGET_PAGE_MASK); if (p2) { tb_page_add(p2, tb, 1, phys_page2); @@ -2219,7 +2219,7 @@ void page_set_flags(target_ulong start, target_ulong = end, int flags) for (addr =3D start, len =3D end - start; len !=3D 0; len -=3D TARGET_PAGE_SIZE, addr +=3D TARGET_PAGE_SIZE) { - PageDesc *p =3D page_find_alloc(addr >> TARGET_PAGE_BITS, 1); + PageDesc *p =3D page_find_alloc(addr >> TARGET_PAGE_BITS, true); =20 /* If the write protection bit is set, then we invalidate the code inside. */ --=20 2.34.1 From nobody Sat Apr 27 07:51:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664574304; cv=none; d=zohomail.com; s=zohoarc; b=jPkVzjqCOvCfSwMA9CDXL7fE4G4zjnDwgzRYup5unIrj4vnB8SZxaScFAWeXLglgj29lFiZ3ItOqC6Zdo2yKK5vIsDtl6YaaUuieAoFdAX/1wWlecjLaD1iYKAjTcO71k4+mCH8F2i46oPcdj8CRBQHDcGAzcozh2ChX70q9jIE= ARC-Message-Signature: i=1; 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([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id l18-20020a05620a28d200b006ce813bb306sm3696370qkp.125.2022.09.30.14.26.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 14:26:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=Me0sYA03idIPAnR4K7d66qbwf2Tw0FB962wCcSsxCZU=; b=RpmLEvMQ3/Y5w0nbC4Baqc6zNnDUv028sttoNpg4ha3MbOccmLV//8z6p4329MMsUI ITt/lcRhZf5+hDtiNj+oyKgqjR8dqcIFk4HTwsDrf+uWajYUE01OGyz8obztrN+XWlW2 nPj6S+qSQoNZ0Bjq+wpYXUxJ0DW7x2i2f7+qq/6OMD1fqKSJx7yVeyQKsu0yp3zNd5Oe rYtiajF426kk4vxGzT9ffbqIe2FzxLLX3fcGfp9vODmYwjVao2ZOMQjxMWCDJk1rbMC0 Z2HcF/p1yBYzOxoKgYt9RiWj5hGqfJro7ZybLw35CgiwVZnH8WZhnmQTVSCUfZYQ/huu EIsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=Me0sYA03idIPAnR4K7d66qbwf2Tw0FB962wCcSsxCZU=; b=ppr2fc3NBhDBH0TTqBt0La5YK0HfZMGrqKEr+DEuemE3xSkeddB7ZoKGJwp0PCWPcU wi1RTxAwZeqczZ4nkwNeR2MTFPJ9vjOiRUajfi2a24WL3pWb68lwHQqyIzD4BSbYzkpc WcfLQtKeeFFjBdz6vfXfOeuoK8N57dCs5mDouVFaroW2JdeBUlPfZqthDhiBDibtkGbJ ZrHTlCB/62PVllcbTswMEWcCpbOQIV+Dw+KOxn/edPyhYBU9jPdd2QGItb/Aobd6FKxq mhrxfyd4+mPrg7dNT+7bAOGrTazwZmy6USVdSqiU665YGpPTTKqxkbw6Td9ywBQSVR6z peHw== X-Gm-Message-State: ACrzQf3Ya0oDfoEexnUWjucoB/+6g6rMcUWAnGddMZCHY5EzyD7nTggW Iw0ivfiG4+SaHop6idyiJjJ5snZYMBoSxw== X-Google-Smtp-Source: AMsMyM4udaKOBiQToKaHjvrGIPPO6Hc2jRyYGa36xXOZup2kmFplp/Kc1ReS3zVOSeD+ENpk567gPQ== X-Received: by 2002:a05:620a:1a14:b0:6ce:a65b:8e6 with SMTP id bk20-20020a05620a1a1400b006cea65b08e6mr7598325qkb.145.1664573213133; Fri, 30 Sep 2022 14:26:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linux.org, alex.bennee@linux.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v6 12/18] accel/tcg: Use DisasContextBase in plugin_gen_tb_start Date: Fri, 30 Sep 2022 14:26:16 -0700 Message-Id: <20220930212622.108363-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930212622.108363-1-richard.henderson@linaro.org> References: <20220930212622.108363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::734; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x734.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664574306033100001 Use the pc coming from db->pc_first rather than the TB. Use the cached host_addr rather than re-computing for the first page. We still need a separate lookup for the second page because it won't be computed for DisasContextBase until the translator actually performs a read from the page. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- include/exec/plugin-gen.h | 7 ++++--- accel/tcg/plugin-gen.c | 22 +++++++++++----------- accel/tcg/translator.c | 2 +- 3 files changed, 16 insertions(+), 15 deletions(-) diff --git a/include/exec/plugin-gen.h b/include/exec/plugin-gen.h index f92f169739..5004728c61 100644 --- a/include/exec/plugin-gen.h +++ b/include/exec/plugin-gen.h @@ -19,7 +19,8 @@ struct DisasContextBase; =20 #ifdef CONFIG_PLUGIN =20 -bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool s= upress); +bool plugin_gen_tb_start(CPUState *cpu, const struct DisasContextBase *db, + bool supress); void plugin_gen_tb_end(CPUState *cpu); void plugin_gen_insn_start(CPUState *cpu, const struct DisasContextBase *d= b); void plugin_gen_insn_end(void); @@ -48,8 +49,8 @@ static inline void plugin_insn_append(abi_ptr pc, const v= oid *from, size_t size) =20 #else /* !CONFIG_PLUGIN */ =20 -static inline -bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool s= upress) +static inline bool +plugin_gen_tb_start(CPUState *cpu, const struct DisasContextBase *db, bool= sup) { return false; } diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 3d0b101e34..80dff68934 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -852,7 +852,8 @@ static void plugin_gen_inject(const struct qemu_plugin_= tb *plugin_tb) pr_ops(); } =20 -bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool m= em_only) +bool plugin_gen_tb_start(CPUState *cpu, const DisasContextBase *db, + bool mem_only) { bool ret =3D false; =20 @@ -870,9 +871,9 @@ bool plugin_gen_tb_start(CPUState *cpu, const Translati= onBlock *tb, bool mem_onl =20 ret =3D true; =20 - ptb->vaddr =3D tb->pc; + ptb->vaddr =3D db->pc_first; ptb->vaddr2 =3D -1; - get_page_addr_code_hostp(cpu->env_ptr, tb->pc, &ptb->haddr1); + ptb->haddr1 =3D db->host_addr[0]; ptb->haddr2 =3D NULL; ptb->mem_only =3D mem_only; =20 @@ -898,16 +899,15 @@ void plugin_gen_insn_start(CPUState *cpu, const Disas= ContextBase *db) * Note that we skip this when haddr1 =3D=3D NULL, e.g. when we're * fetching instructions from a region not backed by RAM. */ - if (likely(ptb->haddr1 !=3D NULL && ptb->vaddr2 =3D=3D -1) && - unlikely((db->pc_next & TARGET_PAGE_MASK) !=3D - (db->pc_first & TARGET_PAGE_MASK))) { - get_page_addr_code_hostp(cpu->env_ptr, db->pc_next, - &ptb->haddr2); - ptb->vaddr2 =3D db->pc_next; - } - if (likely(ptb->vaddr2 =3D=3D -1)) { + if (ptb->haddr1 =3D=3D NULL) { + pinsn->haddr =3D NULL; + } else if (is_same_page(db, db->pc_next)) { pinsn->haddr =3D ptb->haddr1 + pinsn->vaddr - ptb->vaddr; } else { + if (ptb->vaddr2 =3D=3D -1) { + ptb->vaddr2 =3D TARGET_PAGE_ALIGN(db->pc_first); + get_page_addr_code_hostp(cpu->env_ptr, ptb->vaddr2, &ptb->hadd= r2); + } pinsn->haddr =3D ptb->haddr2 + pinsn->vaddr - ptb->vaddr2; } } diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index ca8a5f2d83..8e78fd7a9c 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -75,7 +75,7 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb,= int max_insns, ops->tb_start(db, cpu); tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ =20 - plugin_enabled =3D plugin_gen_tb_start(cpu, tb, cflags & CF_MEMI_ONLY); + plugin_enabled =3D plugin_gen_tb_start(cpu, db, cflags & CF_MEMI_ONLY); =20 while (true) { db->num_insns++; --=20 2.34.1 From nobody Sat Apr 27 07:51:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id l18-20020a05620a28d200b006ce813bb306sm3696370qkp.125.2022.09.30.14.26.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 14:26:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=afI0yCZR6Q1F/Wo9LMRayMhZyCvQGZF4DBhTJQzHUJ4=; b=BYXETcQXPfpyZazWDpDLtrnDUTDiSUgvaKcV6e0oPlZa6oRSRAIRLHUPlz7UkpePOK yNn1mCCZR1guJHlq0DdFsjY/U3IEbDO55rADf2sQLl4BhUeoNx+RMWePnv34PDWmgOd/ HepArF5oomiMnRRdWeXnkCzdXzLtjJQX2zR629xfXM5AB4ayW2fzfeJCg8n6x0+qkg1W c3LTM3RiJLIQZVeBUZWqlRwzEXjoghk6BwGFQ7fddXk7dbylCxNtqL3hRwI1Kb4rhxFc R5dyUksQd8DoHGttCqA4zRGmKJLu9sN2lIJR/JPy9G19vUmJMsvHVxT5DmyFrCYt+zl4 WCHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=afI0yCZR6Q1F/Wo9LMRayMhZyCvQGZF4DBhTJQzHUJ4=; b=dkfHc052ssZcWAMMTTdDA1xikqggJx6pny8WIekydNfDEyG1fPTCc3Iur0azKL6pM0 LvmuM3yhwzRi+Xm1J/qQQsx5e8Hm/zUlfatMDeQwu8NFIoj/mi2vr8s3E4tboHNOcQu0 IlaJqxOmDLu719zF3lMmMmKK7A/nh3ZT4Nen+Dg389610yZ5iWDWAFtLuRYmDq96FT8v epHY+yGZVXbuNblowDd0XVIkxT1NYk7hqCHemaz0gEogRzXkRNKICDWu7XgYwhcyWvtN vDVwA3zmwqjOh2ICyeP0no3DcaaWfYeITZMa3SvXXMOSKAHZYStaEXLz3mmL8rZa8t4w s8UA== X-Gm-Message-State: ACrzQf0xpU9Co9LJqCH09V+roDY1a8sjQOyLZyyNu1uoifx4iBZahfIl 3g8MJmdnOrAcV9UY9CcmbuJX0746ruJT+w== X-Google-Smtp-Source: AMsMyM5aSiPdrP4+e8C0XbBzG/g5ZcjbpbXfCvHJ3c3+Kp0VeYpViarCrx0L0Lei/qijuwKDBKwYLw== X-Received: by 2002:ad4:5ecc:0:b0:4b1:7959:d988 with SMTP id jm12-20020ad45ecc000000b004b17959d988mr1322104qvb.117.1664573214898; Fri, 30 Sep 2022 14:26:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linux.org, alex.bennee@linux.org Subject: [PATCH v6 13/18] accel/tcg: Do not align tb->page_addr[0] Date: Fri, 30 Sep 2022 14:26:17 -0700 Message-Id: <20220930212622.108363-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930212622.108363-1-richard.henderson@linaro.org> References: <20220930212622.108363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2f; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664574487364100001 Content-Type: text/plain; charset="utf-8" Let tb->page_addr[0] contain the offset within the page of the start of the translation block. We need to recover this value anyway at various points, and it is easier to discard the page offset when it's not needed, which happens naturally via the existing find_page shift. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- accel/tcg/cpu-exec.c | 16 ++++++++-------- accel/tcg/cputlb.c | 3 ++- accel/tcg/translate-all.c | 9 +++++---- 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5f43b9769a..dd58a144a8 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -174,7 +174,7 @@ struct tb_desc { target_ulong pc; target_ulong cs_base; CPUArchState *env; - tb_page_addr_t phys_page1; + tb_page_addr_t page_addr0; uint32_t flags; uint32_t cflags; uint32_t trace_vcpu_dstate; @@ -186,7 +186,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) const struct tb_desc *desc =3D d; =20 if (tb->pc =3D=3D desc->pc && - tb->page_addr[0] =3D=3D desc->phys_page1 && + tb->page_addr[0] =3D=3D desc->page_addr0 && tb->cs_base =3D=3D desc->cs_base && tb->flags =3D=3D desc->flags && tb->trace_vcpu_dstate =3D=3D desc->trace_vcpu_dstate && @@ -195,8 +195,8 @@ static bool tb_lookup_cmp(const void *p, const void *d) if (tb->page_addr[1] =3D=3D -1) { return true; } else { - tb_page_addr_t phys_page2; - target_ulong virt_page2; + tb_page_addr_t phys_page1; + target_ulong virt_page1; =20 /* * We know that the first page matched, and an otherwise valid= TB @@ -207,9 +207,9 @@ static bool tb_lookup_cmp(const void *p, const void *d) * is different for the new TB. Therefore any exception raised * here by the faulting lookup is not premature. */ - virt_page2 =3D TARGET_PAGE_ALIGN(desc->pc); - phys_page2 =3D get_page_addr_code(desc->env, virt_page2); - if (tb->page_addr[1] =3D=3D phys_page2) { + virt_page1 =3D TARGET_PAGE_ALIGN(desc->pc); + phys_page1 =3D get_page_addr_code(desc->env, virt_page1); + if (tb->page_addr[1] =3D=3D phys_page1) { return true; } } @@ -235,7 +235,7 @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu= , target_ulong pc, if (phys_pc =3D=3D -1) { return NULL; } - desc.phys_page1 =3D phys_pc & TARGET_PAGE_MASK; + desc.page_addr0 =3D phys_pc; h =3D tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate); return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); } diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 361078471b..a0db2d32a8 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -951,7 +951,8 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUS= tate *src_cpu, can be detected */ void tlb_protect_code(ram_addr_t ram_addr) { - cpu_physical_memory_test_and_clear_dirty(ram_addr, TARGET_PAGE_SIZE, + cpu_physical_memory_test_and_clear_dirty(ram_addr & TARGET_PAGE_MASK, + TARGET_PAGE_SIZE, DIRTY_MEMORY_CODE); } =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index ca685f6ede..3a63113c41 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1167,7 +1167,7 @@ static void do_tb_phys_invalidate(TranslationBlock *t= b, bool rm_from_page_list) qemu_spin_unlock(&tb->jmp_lock); =20 /* remove the TB from the hash list */ - phys_pc =3D tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); + phys_pc =3D tb->page_addr[0]; h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags, tb->trace_vcpu_dstate); if (!qht_remove(&tb_ctx.htable, tb, h)) { @@ -1291,7 +1291,7 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phy= s_pc, * we can only insert TBs that are fully initialized. */ page_lock_pair(&p, phys_pc, &p2, phys_page2, true); - tb_page_add(p, tb, 0, phys_pc & TARGET_PAGE_MASK); + tb_page_add(p, tb, 0, phys_pc); if (p2) { tb_page_add(p2, tb, 1, phys_page2); } else { @@ -1644,11 +1644,12 @@ tb_invalidate_phys_page_range__locked(struct page_c= ollection *pages, if (n =3D=3D 0) { /* NOTE: tb_end may be after the end of the page, but it is not a problem */ - tb_start =3D tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); 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([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id l18-20020a05620a28d200b006ce813bb306sm3696370qkp.125.2022.09.30.14.26.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 14:26:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=N5kqswpGeydfw7dvf5MO+UlFHzfp0nRUBM8Fh5E48cY=; b=kUUY5LuG62oTMUJWtVOk0p5BQRD4sZhamyDzxUIOJNAoc7soFvryWhijc4OuQ1ca6y tldoeFhXYb1Dx+R3Tsfl8Du0EYAPOnMVHBA0RWG6Ra4x64Cqs1EdzGazOOOEKqCCy0/P EAE62V833szwAptfEWD4X5g67YozNwJNpD0FhF1fqYh9USNpjmVRkhZKyJyaM/3JwxOK MEaM1l8+5cLYr0KflyomyO7UuKCmGfwvJefv9JvB6VKK0HLUdm9jmD+XHSFoID+IkDJu A7hS18119KLCcV9eP95hSjVeSdQVvCIUG3Wyw/cDpgELTfCoJVC32Ww/IQaA0feCVqJ7 zi/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=N5kqswpGeydfw7dvf5MO+UlFHzfp0nRUBM8Fh5E48cY=; b=cDDOUAvk9sjUNjH7NHcLrbtfqj5MhconMOeXyjX9j5GuFWBdZE4X2Ej90ByTwurtzV Di3ZWQwtPWwufd/JTPBc2GIZquH4n94CsEmlF9JIwY7E/nICTpgv6EWknlix35UnydLU CXv92u8eJAWSIymoho4OU1YtBamlPrJ+Z0OBmUxgXEh4nOy+28xR85hOIG1S62Xc8PWq kILUzf/tdN66NFWUN6iwCYZVuq4I+sZaGbOhp1g6YZEPqgKMVHa1642YQxPmKQSn1/p3 rVFmOcgzymNhvrKjR2Cj/isFaJvyiFbEFoaSEw5ZTNmEO7YY2gKDvUi02esY5pUa8L2O tvQQ== X-Gm-Message-State: ACrzQf1eoFC/I2cXDoBmTRVlCQwZhL1W5lPab/dGIaWfhV909YdNEjWB kSmiW3/NYs3qaP6arwzW0fb5cfCj1acD+Q== X-Google-Smtp-Source: AMsMyM4UkfzSBwYZVacdevNMRj5SCOhlhP/6eisfg/wFGFokv6Os8Jnib7vRD1xgCmYHIfgyiEk+tQ== X-Received: by 2002:a05:620a:31aa:b0:6ce:b6f8:e235 with SMTP id bi42-20020a05620a31aa00b006ceb6f8e235mr7673640qkb.733.1664573216811; Fri, 30 Sep 2022 14:26:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linux.org, alex.bennee@linux.org Subject: [PATCH v6 14/18] accel/tcg: Inline tb_flush_jmp_cache Date: Fri, 30 Sep 2022 14:26:18 -0700 Message-Id: <20220930212622.108363-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930212622.108363-1-richard.henderson@linaro.org> References: <20220930212622.108363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72a; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664574579651100001 Content-Type: text/plain; charset="utf-8" This function has two users, who use it incompatibly. In tlb_flush_page_by_mmuidx_async_0, when flushing a single page, we need to flush exactly two pages. In tlb_flush_range_by_mmuidx_async_0, when flushing a range of pages, we need to flush N+1 pages. This avoids double-flushing of jmp cache pages in a range. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- accel/tcg/cputlb.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a0db2d32a8..c7909fb619 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -107,14 +107,6 @@ static void tb_jmp_cache_clear_page(CPUState *cpu, tar= get_ulong page_addr) } } =20 -static void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr) -{ - /* Discard jump cache entries for any tb which might potentially - overlap the flushed page. */ - tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE); - tb_jmp_cache_clear_page(cpu, addr); -} - /** * tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if nec= essary * @desc: The CPUTLBDesc portion of the TLB @@ -541,7 +533,12 @@ static void tlb_flush_page_by_mmuidx_async_0(CPUState = *cpu, } qemu_spin_unlock(&env_tlb(env)->c.lock); =20 - tb_flush_jmp_cache(cpu, addr); + /* + * Discard jump cache entries for any tb which might potentially + * overlap the flushed page, which includes the previous. + */ + tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE); + tb_jmp_cache_clear_page(cpu, addr); } =20 /** @@ -792,8 +789,14 @@ static void tlb_flush_range_by_mmuidx_async_0(CPUState= *cpu, return; } =20 - for (target_ulong i =3D 0; i < d.len; i +=3D TARGET_PAGE_SIZE) { - tb_flush_jmp_cache(cpu, d.addr + i); + /* + * Discard jump cache entries for any tb which might potentially + * overlap the flushed pages, which includes the previous. + */ + d.addr -=3D TARGET_PAGE_SIZE; + for (target_ulong i =3D 0, n =3D d.len / TARGET_PAGE_SIZE + 1; i < n; = i++) { + tb_jmp_cache_clear_page(cpu, d.addr); + d.addr +=3D TARGET_PAGE_SIZE; } } =20 --=20 2.34.1 From nobody Sat Apr 27 07:51:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664574037; cv=none; d=zohomail.com; s=zohoarc; b=dyB5PPZ48ZTTScp1io9t++cP+Oyfm5fBIvda1qaBmX0rt2sqcd9Er1pDAC3cMkHM/1WpKzwCOBSPMS2fN7vv3qh4MFO81VCFLx1bm/HyL7guE+kiYUQXT9x98ES7njETi7KnFLm+AUXBV4mzqSr2Mgly+WydH54EJaggQ29wdcc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664574037; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xm/H8dVlrvt7LtgZnAs+u1OourzlqrDTZWD6nDKqSYw=; b=NDAqsmJ/UcKYQ266cdkPc3tw+X5bhtE/lSwRvMF3joGQeos6NsGBBdZ6ZWkUnw4Fj5lYlTriGAaws0yiNo0jPOSISFofGEEbDR8Hp2/UqfeofabdHJMdzIz85dxKp7IUoS1kTe0G/iw6mFiG5PNr2oiqfefPDWSrybED+OuRKMM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664574037033871.9575753185934; Fri, 30 Sep 2022 14:40:37 -0700 (PDT) Received: from localhost ([::1]:50768 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeNkJ-0007Z1-0M for importer@patchew.org; Fri, 30 Sep 2022 17:40:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46502) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeNXC-0007EH-04 for qemu-devel@nongnu.org; Fri, 30 Sep 2022 17:27:02 -0400 Received: from mail-qk1-x72b.google.com ([2607:f8b0:4864:20::72b]:35428) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeNX9-0005S9-JS for qemu-devel@nongnu.org; Fri, 30 Sep 2022 17:27:01 -0400 Received: by mail-qk1-x72b.google.com with SMTP id u28so3617511qku.2 for ; Fri, 30 Sep 2022 14:26:59 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- accel/tcg/tb-hash.h | 1 + accel/tcg/tb-jmp-cache.h | 24 ++++++++++++++++++++++++ include/exec/cpu-common.h | 1 + include/hw/core/cpu.h | 15 +-------------- include/qemu/typedefs.h | 1 + accel/tcg/cpu-exec.c | 10 +++++++--- accel/tcg/cputlb.c | 9 +++++---- accel/tcg/translate-all.c | 28 +++++++++++++++++++++++++--- hw/core/cpu-common.c | 3 +-- plugins/core.c | 2 +- trace/control-target.c | 2 +- 11 files changed, 68 insertions(+), 28 deletions(-) create mode 100644 accel/tcg/tb-jmp-cache.h diff --git a/accel/tcg/tb-hash.h b/accel/tcg/tb-hash.h index 0a273d9605..83dc610e4c 100644 --- a/accel/tcg/tb-hash.h +++ b/accel/tcg/tb-hash.h @@ -23,6 +23,7 @@ #include "exec/cpu-defs.h" #include "exec/exec-all.h" #include "qemu/xxhash.h" +#include "tb-jmp-cache.h" =20 #ifdef CONFIG_SOFTMMU =20 diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h new file mode 100644 index 0000000000..2d8fbb1bfe --- /dev/null +++ b/accel/tcg/tb-jmp-cache.h @@ -0,0 +1,24 @@ +/* + * The per-CPU TranslationBlock jump cache. + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef ACCEL_TCG_TB_JMP_CACHE_H +#define ACCEL_TCG_TB_JMP_CACHE_H + +#define TB_JMP_CACHE_BITS 12 +#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) + +/* + * Accessed in parallel; all accesses to 'tb' must be atomic. + */ +struct CPUJumpCache { + struct { + TranslationBlock *tb; + } array[TB_JMP_CACHE_SIZE]; +}; + +#endif /* ACCEL_TCG_TB_JMP_CACHE_H */ diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index d909429427..c493510ee9 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -38,6 +38,7 @@ void cpu_list_unlock(void); unsigned int cpu_list_generation_id_get(void); =20 void tcg_flush_softmmu_tlb(CPUState *cs); +void tcg_flush_jmp_cache(CPUState *cs); =20 void tcg_iommu_init_notifier_list(CPUState *cpu); void tcg_iommu_free_notifier_list(CPUState *cpu); diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 009dc0d336..18ca701b44 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -236,9 +236,6 @@ struct kvm_run; struct hax_vcpu_state; struct hvf_vcpu_state; =20 -#define TB_JMP_CACHE_BITS 12 -#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) - /* work queue */ =20 /* The union type allows passing of 64 bit target pointers on 32 bit @@ -369,8 +366,7 @@ struct CPUState { CPUArchState *env_ptr; IcountDecr *icount_decr_ptr; =20 - /* Accessed in parallel; all accesses must be atomic */ - TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; + CPUJumpCache *tb_jmp_cache; =20 struct GDBRegisterState *gdb_regs; int gdb_num_regs; @@ -456,15 +452,6 @@ extern CPUTailQ cpus; =20 extern __thread CPUState *current_cpu; =20 -static inline void cpu_tb_jmp_cache_clear(CPUState *cpu) -{ - unsigned int i; - - for (i =3D 0; i < TB_JMP_CACHE_SIZE; i++) { - qatomic_set(&cpu->tb_jmp_cache[i], NULL); - } -} - /** * qemu_tcg_mttcg_enabled: * Check whether we are running MultiThread TCG or not. diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 42f4ceb701..5449aaf483 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -41,6 +41,7 @@ typedef struct CoMutex CoMutex; typedef struct ConfidentialGuestSupport ConfidentialGuestSupport; typedef struct CPUAddressSpace CPUAddressSpace; typedef struct CPUArchState CPUArchState; +typedef struct CPUJumpCache CPUJumpCache; typedef struct CPUState CPUState; typedef struct DeviceListener DeviceListener; typedef struct DeviceState DeviceState; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index dd58a144a8..2d7e610ee2 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -42,6 +42,7 @@ #include "sysemu/replay.h" #include "sysemu/tcg.h" #include "exec/helper-proto.h" +#include "tb-jmp-cache.h" #include "tb-hash.h" #include "tb-context.h" #include "internal.h" @@ -252,7 +253,7 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu= , target_ulong pc, tcg_debug_assert(!(cflags & CF_INVALID)); =20 hash =3D tb_jmp_cache_hash_func(pc); - tb =3D qatomic_rcu_read(&cpu->tb_jmp_cache[hash]); + tb =3D qatomic_rcu_read(&cpu->tb_jmp_cache->array[hash].tb); =20 if (likely(tb && tb->pc =3D=3D pc && @@ -266,7 +267,7 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu= , target_ulong pc, if (tb =3D=3D NULL) { return NULL; } - qatomic_set(&cpu->tb_jmp_cache[hash], tb); + qatomic_set(&cpu->tb_jmp_cache->array[hash].tb, tb); return tb; } =20 @@ -987,6 +988,8 @@ int cpu_exec(CPUState *cpu) =20 tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb =3D=3D NULL) { + uint32_t h; + mmap_lock(); tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); mmap_unlock(); @@ -994,7 +997,8 @@ int cpu_exec(CPUState *cpu) * We add the TB in the virtual pc hash table * for the fast lookup */ - qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]= , tb); + h =3D tb_jmp_cache_hash_func(pc); + qatomic_set(&cpu->tb_jmp_cache->array[h].tb, tb); } =20 #ifndef CONFIG_USER_ONLY diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c7909fb619..6f1c00682b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -100,10 +100,11 @@ static void tlb_window_reset(CPUTLBDesc *desc, int64_= t ns, =20 static void tb_jmp_cache_clear_page(CPUState *cpu, target_ulong page_addr) { - unsigned int i, i0 =3D tb_jmp_cache_hash_page(page_addr); + int i, i0 =3D tb_jmp_cache_hash_page(page_addr); + CPUJumpCache *jc =3D cpu->tb_jmp_cache; =20 for (i =3D 0; i < TB_JMP_PAGE_SIZE; i++) { - qatomic_set(&cpu->tb_jmp_cache[i0 + i], NULL); + qatomic_set(&jc->array[i0 + i].tb, NULL); } } =20 @@ -356,7 +357,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cp= u, run_on_cpu_data data) =20 qemu_spin_unlock(&env_tlb(env)->c.lock); =20 - cpu_tb_jmp_cache_clear(cpu); + tcg_flush_jmp_cache(cpu); =20 if (to_clean =3D=3D ALL_MMUIDX_BITS) { qatomic_set(&env_tlb(env)->c.full_flush_count, @@ -785,7 +786,7 @@ static void tlb_flush_range_by_mmuidx_async_0(CPUState = *cpu, * longer to clear each entry individually than it will to clear it al= l. */ if (d.len >=3D (TARGET_PAGE_SIZE * TB_JMP_CACHE_SIZE)) { - cpu_tb_jmp_cache_clear(cpu); + tcg_flush_jmp_cache(cpu); return; } =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 3a63113c41..63ecc15236 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -58,6 +58,7 @@ #include "sysemu/tcg.h" #include "qapi/error.h" #include "hw/core/tcg-cpu-ops.h" +#include "tb-jmp-cache.h" #include "tb-hash.h" #include "tb-context.h" #include "internal.h" @@ -967,7 +968,7 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data = tb_flush_count) } =20 CPU_FOREACH(cpu) { - cpu_tb_jmp_cache_clear(cpu); + tcg_flush_jmp_cache(cpu); } =20 qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE); @@ -1187,8 +1188,9 @@ static void do_tb_phys_invalidate(TranslationBlock *t= b, bool rm_from_page_list) /* remove the TB from the hash list */ h =3D tb_jmp_cache_hash_func(tb->pc); CPU_FOREACH(cpu) { - if (qatomic_read(&cpu->tb_jmp_cache[h]) =3D=3D tb) { - qatomic_set(&cpu->tb_jmp_cache[h], NULL); + CPUJumpCache *jc =3D cpu->tb_jmp_cache; + if (qatomic_read(&jc->array[h].tb) =3D=3D tb) { + qatomic_set(&jc->array[h].tb, NULL); } } =20 @@ -2443,6 +2445,26 @@ int page_unprotect(target_ulong address, uintptr_t p= c) } #endif /* CONFIG_USER_ONLY */ =20 +/* + * Called by generic code at e.g. cpu reset after cpu creation, + * therefore we must be prepared to allocate the jump cache. + */ +void tcg_flush_jmp_cache(CPUState *cpu) +{ + CPUJumpCache *jc =3D cpu->tb_jmp_cache; + + if (likely(jc)) { + for (int i =3D 0; i < TB_JMP_CACHE_SIZE; i++) { + qatomic_set(&jc->array[i].tb, NULL); + } + } else { + /* This should happen once during realize, and thus never race. */ + jc =3D g_new0(CPUJumpCache, 1); + jc =3D qatomic_xchg(&cpu->tb_jmp_cache, jc); + assert(jc =3D=3D NULL); + } +} + /* This is a wrapper for common code that can not use CONFIG_SOFTMMU */ void tcg_flush_softmmu_tlb(CPUState *cs) { diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 9e3241b430..f9fdd46b9d 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -137,8 +137,7 @@ static void cpu_common_reset(DeviceState *dev) cpu->cflags_next_tb =3D -1; =20 if (tcg_enabled()) { - cpu_tb_jmp_cache_clear(cpu); - + tcg_flush_jmp_cache(cpu); tcg_flush_softmmu_tlb(cpu); } } diff --git a/plugins/core.c b/plugins/core.c index 792262da08..c3ae284994 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -56,7 +56,7 @@ struct qemu_plugin_ctx *plugin_id_to_ctx_locked(qemu_plug= in_id_t id) static void plugin_cpu_update__async(CPUState *cpu, run_on_cpu_data data) { bitmap_copy(cpu->plugin_mask, &data.host_ulong, QEMU_PLUGIN_EV_MAX); - cpu_tb_jmp_cache_clear(cpu); + tcg_flush_jmp_cache(cpu); } =20 static void plugin_cpu_update__locked(gpointer k, gpointer v, gpointer uda= ta) diff --git a/trace/control-target.c b/trace/control-target.c index 8418673c18..232c97a4a1 100644 --- a/trace/control-target.c +++ b/trace/control-target.c @@ -65,7 +65,7 @@ static void trace_event_synchronize_vcpu_state_dynamic( { bitmap_copy(vcpu->trace_dstate, vcpu->trace_dstate_delayed, CPU_TRACE_DSTATE_MAX_EVENTS); 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Iglesias" , Taylor Simpson , Song Gao , Xiaojuan Yang , Laurent Vivier , Jiaxun Yang , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , Yoshinori Sato , Mark Cave-Ayland , Bastian Koppelmann , Max Filippov , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v6 16/18] hw/core: Add CPUClass.get_pc Date: Fri, 30 Sep 2022 14:26:20 -0700 Message-Id: <20220930212622.108363-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930212622.108363-1-richard.henderson@linaro.org> References: <20220930212622.108363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2a; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664574053884100003 Populate this new method for all targets. Always match the result that would be given by cpu_get_tb_cpu_state, as we will want these values to correspond in the logs. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Mark Cave-Ayland Reviewed-by: Taylor Simpson --- Cc: Eduardo Habkost (supporter:Machine core) Cc: Marcel Apfelbaum (supporter:Machine core) Cc: "Philippe Mathieu-Daud=C3=A9" (reviewer:Machine core) Cc: Yanan Wang (reviewer:Machine core) Cc: Michael Rolnik (maintainer:AVR TCG CPUs) Cc: "Edgar E. Iglesias" (maintainer:CRIS TCG CPU= s) Cc: Taylor Simpson (supporter:Hexagon TCG CPUs) Cc: Song Gao (maintainer:LoongArch TCG CPUs) Cc: Xiaojuan Yang (maintainer:LoongArch TCG CPUs) Cc: Laurent Vivier (maintainer:M68K TCG CPUs) Cc: Jiaxun Yang (reviewer:MIPS TCG CPUs) Cc: Aleksandar Rikalo (reviewer:MIPS TCG CPU= s) Cc: Chris Wulff (maintainer:NiosII TCG CPUs) Cc: Marek Vasut (maintainer:NiosII TCG CPUs) Cc: Stafford Horne (odd fixer:OpenRISC TCG CPUs) Cc: Yoshinori Sato (reviewer:RENESAS RX CPUs) Cc: Mark Cave-Ayland (maintainer:SPARC TCG = CPUs) Cc: Bastian Koppelmann (maintainer:TriCore= TCG CPUs) Cc: Max Filippov (maintainer:Xtensa TCG CPUs) Cc: qemu-arm@nongnu.org (open list:ARM TCG CPUs) Cc: qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs) Cc: qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Cc: qemu-s390x@nongnu.org (open list:S390 TCG CPUs) --- include/hw/core/cpu.h | 3 +++ target/alpha/cpu.c | 9 +++++++++ target/arm/cpu.c | 13 +++++++++++++ target/avr/cpu.c | 8 ++++++++ target/cris/cpu.c | 8 ++++++++ target/hexagon/cpu.c | 8 ++++++++ target/hppa/cpu.c | 8 ++++++++ target/i386/cpu.c | 9 +++++++++ target/loongarch/cpu.c | 9 +++++++++ target/m68k/cpu.c | 8 ++++++++ target/microblaze/cpu.c | 8 ++++++++ target/mips/cpu.c | 8 ++++++++ target/nios2/cpu.c | 9 +++++++++ target/openrisc/cpu.c | 8 ++++++++ target/ppc/cpu_init.c | 8 ++++++++ target/riscv/cpu.c | 13 +++++++++++++ target/rx/cpu.c | 8 ++++++++ target/s390x/cpu.c | 8 ++++++++ target/sh4/cpu.c | 8 ++++++++ target/sparc/cpu.c | 8 ++++++++ target/tricore/cpu.c | 9 +++++++++ target/xtensa/cpu.c | 8 ++++++++ 22 files changed, 186 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 18ca701b44..f9b58773f7 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -115,6 +115,8 @@ struct SysemuCPUOps; * If the target behaviour here is anything other than "set * the PC register to the value passed in" then the target must * also implement the synchronize_from_tb hook. + * @get_pc: Callback for getting the Program Counter register. + * As above, with the semantics of the target architecture. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_adjust_breakpoint: Callback for adjusting the address of a @@ -151,6 +153,7 @@ struct CPUClass { void (*dump_state)(CPUState *cpu, FILE *, int flags); int64_t (*get_arch_id)(CPUState *cpu); void (*set_pc)(CPUState *cpu, vaddr value); + vaddr (*get_pc)(CPUState *cpu); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index a8990d401b..979a629d59 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -33,6 +33,14 @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc =3D value; } =20 +static vaddr alpha_cpu_get_pc(CPUState *cs) +{ + AlphaCPU *cpu =3D ALPHA_CPU(cs); + + return cpu->env.pc; +} + + static bool alpha_cpu_has_work(CPUState *cs) { /* Here we are checking to see if the CPU should wake up from HALT. @@ -244,6 +252,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->has_work =3D alpha_cpu_has_work; cc->dump_state =3D alpha_cpu_dump_state; cc->set_pc =3D alpha_cpu_set_pc; + cc->get_pc =3D alpha_cpu_get_pc; cc->gdb_read_register =3D alpha_cpu_gdb_read_register; cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7ec3281da9..fa67ba6647 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -60,6 +60,18 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) } } =20 +static vaddr arm_cpu_get_pc(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + if (is_a64(env)) { + return env->pc; + } else { + return env->regs[15]; + } +} + #ifdef CONFIG_TCG void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) @@ -2172,6 +2184,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->has_work =3D arm_cpu_has_work; cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; + cc->get_pc =3D arm_cpu_get_pc; cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 05b992ff73..6900444d03 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -32,6 +32,13 @@ static void avr_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc_w =3D value / 2; /* internally PC points to words */ } =20 +static vaddr avr_cpu_get_pc(CPUState *cs) +{ + AVRCPU *cpu =3D AVR_CPU(cs); + + return cpu->env.pc_w * 2; +} + static bool avr_cpu_has_work(CPUState *cs) { AVRCPU *cpu =3D AVR_CPU(cs); @@ -214,6 +221,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->has_work =3D avr_cpu_has_work; cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; + cc->get_pc =3D avr_cpu_get_pc; dc->vmsd =3D &vms_avr_cpu; cc->sysemu_ops =3D &avr_sysemu_ops; cc->disas_set_info =3D avr_cpu_disas_set_info; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index ed6c781342..22f5c70f39 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -35,6 +35,13 @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc =3D value; } =20 +static vaddr cris_cpu_get_pc(CPUState *cs) +{ + CRISCPU *cpu =3D CRIS_CPU(cs); + + return cpu->env.pc; +} + static bool cris_cpu_has_work(CPUState *cs) { return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI= ); @@ -297,6 +304,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->has_work =3D cris_cpu_has_work; cc->dump_state =3D cris_cpu_dump_state; cc->set_pc =3D cris_cpu_set_pc; + cc->get_pc =3D cris_cpu_get_pc; cc->gdb_read_register =3D cris_cpu_gdb_read_register; cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index fa9bd702d6..04a497db5e 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -251,6 +251,13 @@ static void hexagon_cpu_set_pc(CPUState *cs, vaddr val= ue) env->gpr[HEX_REG_PC] =3D value; } =20 +static vaddr hexagon_cpu_get_pc(CPUState *cs) +{ + HexagonCPU *cpu =3D HEXAGON_CPU(cs); + CPUHexagonState *env =3D &cpu->env; + return env->gpr[HEX_REG_PC]; +} + static void hexagon_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -337,6 +344,7 @@ static void hexagon_cpu_class_init(ObjectClass *c, void= *data) cc->has_work =3D hexagon_cpu_has_work; cc->dump_state =3D hexagon_dump_state; cc->set_pc =3D hexagon_cpu_set_pc; + cc->get_pc =3D hexagon_cpu_get_pc; cc->gdb_read_register =3D hexagon_gdb_read_register; cc->gdb_write_register =3D hexagon_gdb_write_register; cc->gdb_num_core_regs =3D TOTAL_PER_THREAD_REGS + NUM_VREGS + NUM_QREG= S; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index a6f52caf14..e25d3db6d5 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -36,6 +36,13 @@ static void hppa_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.iaoq_b =3D value + 4; } =20 +static vaddr hppa_cpu_get_pc(CPUState *cs) +{ + HPPACPU *cpu =3D HPPA_CPU(cs); + + return cpu->env.iaoq_f; +} + static void hppa_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -168,6 +175,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->has_work =3D hppa_cpu_has_work; cc->dump_state =3D hppa_cpu_dump_state; cc->set_pc =3D hppa_cpu_set_pc; + cc->get_pc =3D hppa_cpu_get_pc; cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1db1278a59..ad623d91e4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6824,6 +6824,14 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.eip =3D value; } =20 +static vaddr x86_cpu_get_pc(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + + /* Match cpu_get_tb_cpu_state. */ + return cpu->env.eip + cpu->env.segs[R_CS].base; +} + int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) { X86CPU *cpu =3D X86_CPU(cs); @@ -7106,6 +7114,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->has_work =3D x86_cpu_has_work; cc->dump_state =3D x86_cpu_dump_state; cc->set_pc =3D x86_cpu_set_pc; + cc->get_pc =3D x86_cpu_get_pc; cc->gdb_read_register =3D x86_cpu_gdb_read_register; cc->gdb_write_register =3D x86_cpu_gdb_write_register; cc->get_arch_id =3D x86_cpu_get_arch_id; diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 941e2772bc..20a92ea56c 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -82,6 +82,14 @@ static void loongarch_cpu_set_pc(CPUState *cs, vaddr val= ue) env->pc =3D value; } =20 +static vaddr loongarch_cpu_get_pc(CPUState *cs) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + CPULoongArchState *env =3D &cpu->env; + + return env->pc; +} + #ifndef CONFIG_USER_ONLY #include "hw/loongarch/virt.h" =20 @@ -680,6 +688,7 @@ static void loongarch_cpu_class_init(ObjectClass *c, vo= id *data) cc->has_work =3D loongarch_cpu_has_work; cc->dump_state =3D loongarch_cpu_dump_state; cc->set_pc =3D loongarch_cpu_set_pc; + cc->get_pc =3D loongarch_cpu_get_pc; #ifndef CONFIG_USER_ONLY dc->vmsd =3D &vmstate_loongarch_cpu; cc->sysemu_ops =3D &loongarch_sysemu_ops; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 25d610db21..1e902e1ef0 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -31,6 +31,13 @@ static void m68k_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc =3D value; } =20 +static vaddr m68k_cpu_get_pc(CPUState *cs) +{ + M68kCPU *cpu =3D M68K_CPU(cs); + + return cpu->env.pc; +} + static bool m68k_cpu_has_work(CPUState *cs) { return cs->interrupt_request & CPU_INTERRUPT_HARD; @@ -540,6 +547,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->has_work =3D m68k_cpu_has_work; cc->dump_state =3D m68k_cpu_dump_state; cc->set_pc =3D m68k_cpu_set_pc; + cc->get_pc =3D m68k_cpu_get_pc; cc->gdb_read_register =3D m68k_cpu_gdb_read_register; cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index aed200dcff..73af51769e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -84,6 +84,13 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.iflags =3D 0; } =20 +static vaddr mb_cpu_get_pc(CPUState *cs) +{ + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + + return cpu->env.pc; +} + static void mb_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -391,6 +398,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) =20 cc->dump_state =3D mb_cpu_dump_state; cc->set_pc =3D mb_cpu_set_pc; + cc->get_pc =3D mb_cpu_get_pc; cc->gdb_read_register =3D mb_cpu_gdb_read_register; cc->gdb_write_register =3D mb_cpu_gdb_write_register; =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index c15c955367..da58eb8892 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -128,6 +128,13 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value) mips_env_set_pc(&cpu->env, value); } =20 +static vaddr mips_cpu_get_pc(CPUState *cs) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + + return cpu->env.active_tc.PC; +} + static bool mips_cpu_has_work(CPUState *cs) { MIPSCPU *cpu =3D MIPS_CPU(cs); @@ -557,6 +564,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->has_work =3D mips_cpu_has_work; cc->dump_state =3D mips_cpu_dump_state; cc->set_pc =3D mips_cpu_set_pc; + cc->get_pc =3D mips_cpu_get_pc; cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 19b2409974..2b28429c08 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -34,6 +34,14 @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value) env->pc =3D value; } =20 +static vaddr nios2_cpu_get_pc(CPUState *cs) +{ + Nios2CPU *cpu =3D NIOS2_CPU(cs); + CPUNios2State *env =3D &cpu->env; + + return env->pc; +} + static bool nios2_cpu_has_work(CPUState *cs) { return cs->interrupt_request & CPU_INTERRUPT_HARD; @@ -362,6 +370,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->has_work =3D nios2_cpu_has_work; cc->dump_state =3D nios2_cpu_dump_state; cc->set_pc =3D nios2_cpu_set_pc; + cc->get_pc =3D nios2_cpu_get_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &nios2_sysemu_ops; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index cb9f35f408..33cf717210 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -31,6 +31,13 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr valu= e) cpu->env.dflag =3D 0; } =20 +static vaddr openrisc_cpu_get_pc(CPUState *cs) +{ + OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); + + return cpu->env.pc; +} + static void openrisc_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -218,6 +225,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->has_work =3D openrisc_cpu_has_work; cc->dump_state =3D openrisc_cpu_dump_state; cc->set_pc =3D openrisc_cpu_set_pc; + cc->get_pc =3D openrisc_cpu_get_pc; cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 6e080ebda0..763a8431be 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7214,6 +7214,13 @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.nip =3D value; } =20 +static vaddr ppc_cpu_get_pc(CPUState *cs) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + + return cpu->env.nip; +} + static bool ppc_cpu_has_work(CPUState *cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); @@ -7472,6 +7479,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void = *data) cc->has_work =3D ppc_cpu_has_work; cc->dump_state =3D ppc_cpu_dump_state; cc->set_pc =3D ppc_cpu_set_pc; + cc->get_pc =3D ppc_cpu_get_pc; cc->gdb_read_register =3D ppc_cpu_gdb_read_register; cc->gdb_write_register =3D ppc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b29c88b9f0..6ca05c6eaf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -462,6 +462,18 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value) } } =20 +static vaddr riscv_cpu_get_pc(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + + /* Match cpu_get_tb_cpu_state. */ + if (env->xl =3D=3D MXL_RV32) { + return env->pc & UINT32_MAX; + } + return env->pc; +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -1154,6 +1166,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) cc->has_work =3D riscv_cpu_has_work; cc->dump_state =3D riscv_cpu_dump_state; cc->set_pc =3D riscv_cpu_set_pc; + cc->get_pc =3D riscv_cpu_get_pc; cc->gdb_read_register =3D riscv_cpu_gdb_read_register; cc->gdb_write_register =3D riscv_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 33; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index fb30080ac4..134b4b6bb6 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -32,6 +32,13 @@ static void rx_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc =3D value; } =20 +static vaddr rx_cpu_get_pc(CPUState *cs) +{ + RXCPU *cpu =3D RX_CPU(cs); + + return cpu->env.pc; +} + static void rx_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -208,6 +215,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) cc->has_work =3D rx_cpu_has_work; cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; + cc->get_pc =3D rx_cpu_get_pc; =20 #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &rx_sysemu_ops; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index c31bb2351f..df00040e95 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -88,6 +88,13 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.psw.addr =3D value; } =20 +static vaddr s390_cpu_get_pc(CPUState *cs) +{ + S390CPU *cpu =3D S390_CPU(cs); + + return cpu->env.psw.addr; +} + static bool s390_cpu_has_work(CPUState *cs) { S390CPU *cpu =3D S390_CPU(cs); @@ -297,6 +304,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->has_work =3D s390_cpu_has_work; cc->dump_state =3D s390_cpu_dump_state; cc->set_pc =3D s390_cpu_set_pc; + cc->get_pc =3D s390_cpu_get_pc; cc->gdb_read_register =3D s390_cpu_gdb_read_register; cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 06b2691dc4..4bafbf8596 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -34,6 +34,13 @@ static void superh_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc =3D value; } =20 +static vaddr superh_cpu_get_pc(CPUState *cs) +{ + SuperHCPU *cpu =3D SUPERH_CPU(cs); + + return cpu->env.pc; +} + static void superh_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -261,6 +268,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->has_work =3D superh_cpu_has_work; cc->dump_state =3D superh_cpu_dump_state; cc->set_pc =3D superh_cpu_set_pc; + cc->get_pc =3D superh_cpu_get_pc; cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 55268ed2a1..1b2afb0cb8 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -693,6 +693,13 @@ static void sparc_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.npc =3D value + 4; } =20 +static vaddr sparc_cpu_get_pc(CPUState *cs) +{ + SPARCCPU *cpu =3D SPARC_CPU(cs); + + return cpu->env.pc; +} + static void sparc_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -896,6 +903,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->memory_rw_debug =3D sparc_cpu_memory_rw_debug; #endif cc->set_pc =3D sparc_cpu_set_pc; + cc->get_pc =3D sparc_cpu_get_pc; cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index b95682b7f0..91b16bdefc 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -41,6 +41,14 @@ static void tricore_cpu_set_pc(CPUState *cs, vaddr value) env->PC =3D value & ~(target_ulong)1; } =20 +static vaddr tricore_cpu_get_pc(CPUState *cs) +{ + TriCoreCPU *cpu =3D TRICORE_CPU(cs); + CPUTriCoreState *env =3D &cpu->env; + + return env->PC; +} + static void tricore_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -176,6 +184,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) =20 cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; + cc->get_pc =3D tricore_cpu_get_pc; cc->sysemu_ops =3D &tricore_sysemu_ops; cc->tcg_ops =3D &tricore_tcg_ops; } diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index fd553fdfb5..cbbe0e84a2 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -44,6 +44,13 @@ static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc =3D value; } =20 +static vaddr xtensa_cpu_get_pc(CPUState *cs) +{ + XtensaCPU *cpu =3D XTENSA_CPU(cs); + + return cpu->env.pc; +} + static bool xtensa_cpu_has_work(CPUState *cs) { #ifndef CONFIG_USER_ONLY @@ -233,6 +240,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->has_work =3D xtensa_cpu_has_work; cc->dump_state =3D xtensa_cpu_dump_state; cc->set_pc =3D xtensa_cpu_set_pc; + cc->get_pc =3D xtensa_cpu_get_pc; cc->gdb_read_register =3D xtensa_cpu_gdb_read_register; cc->gdb_write_register =3D xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint =3D true; --=20 2.34.1 From nobody Sat Apr 27 07:51:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664574244; cv=none; d=zohomail.com; s=zohoarc; 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([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id l18-20020a05620a28d200b006ce813bb306sm3696370qkp.125.2022.09.30.14.27.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 14:27:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=NSlhk7SgJVkwHakaDtBTkSg3oKeEyTlZf0cwFgre9N8=; b=gTVmC1lDipBqjudcO/EqZacGIDDRYQ4G2hT9GAF30ob1XlaZ3+yspKn427zs/m0IIr Tv7BJUoi6TE5XkULshkqlTC81C7KkDcSOloHawDfas8D62U/MlzixA1xqMM+Amu6uAsm ltv64rPbHFI8hnJUvJVn7X7vKRs2x8nzFogaZgw9VUK6/c58n0hGLu3WSiTmV3mQbYJ/ WlWNiywm7+qafCXT3AGlXHyc5wXghvuyBpMle4t8zmUY3LKzdx7aAwvNmFpNaiQpYVEJ 1uC2mtV55IPm/dKaP2pYE4I22Y+S9OgCv8FP2KS/3mAfxdKJMw8FIxSCdq6yef8fWQhe Vuvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=NSlhk7SgJVkwHakaDtBTkSg3oKeEyTlZf0cwFgre9N8=; b=rMV6jqZhjttUYPuGckS7ajIva8mLvs6KUjyASVL1fkhqJmzfX8M+TcN8cwMW1ABrMN IlhUU2Y32J/LTuBkLi5JL4ee5XFUtTn/413kGAmZl8QtfngTpbXp8Y4jSJyR9Jfzwunj eMzHbK6WDWoO4tcC30XL5GRvlOFUBuiaBrE3QaTnlxEQXLCVvIWjKvbz5hypwJj0BH8u aRxI3J5GKFgXL9+IOPBkVAUdeMlUqzQW8h+isRbIsyq6/heM08XxklAr5trzZyv6zjvN 1PpsYKFIRboIDDUIaPjeKlrRoh+QfkSXvtTggszyV2+CbsKtDIhdXyvNzQSBR74LEc0E jXxA== X-Gm-Message-State: ACrzQf0R+8qrQwxGvng7vkqJpEOXGwtKbfZ/VB1UDHZbpT5G9plOAZFk vvA3nq/+uxvLXUCyZUto1ioLz1URmzOkEw== X-Google-Smtp-Source: AMsMyM7pxm2v9ahJaI5chjteIh9lTjMU6RfGForfx0qmEFTCxgmCTetlsLqGW9BvlQBg5EyyKRpYww== X-Received: by 2002:ad4:5d43:0:b0:4af:9350:440d with SMTP id jk3-20020ad45d43000000b004af9350440dmr8698941qvb.115.1664573226293; Fri, 30 Sep 2022 14:27:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linux.org, alex.bennee@linux.org Subject: [PATCH v6 17/18] accel/tcg: Introduce tb_pc and log_pc Date: Fri, 30 Sep 2022 14:26:21 -0700 Message-Id: <20220930212622.108363-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930212622.108363-1-richard.henderson@linaro.org> References: <20220930212622.108363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2d; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664574245850100001 Content-Type: text/plain; charset="utf-8" The availability of tb->pc will shortly be conditional. Introduce accessor functions to minimize ifdefs. Pass around a known pc to places like tcg_gen_code, where the caller must already have the value. Signed-off-by: Richard Henderson --- accel/tcg/internal.h | 6 ++++ include/exec/exec-all.h | 6 ++++ include/tcg/tcg.h | 2 +- accel/tcg/cpu-exec.c | 46 ++++++++++++++----------- accel/tcg/translate-all.c | 37 +++++++++++--------- target/arm/cpu.c | 4 +-- target/avr/cpu.c | 2 +- target/hexagon/cpu.c | 2 +- target/hppa/cpu.c | 4 +-- target/i386/tcg/tcg-cpu.c | 2 +- target/loongarch/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/tcg/exception.c | 2 +- target/mips/tcg/sysemu/special_helper.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 4 +-- target/rx/cpu.c | 2 +- target/sh4/cpu.c | 4 +-- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- tcg/tcg.c | 8 ++--- 21 files changed, 82 insertions(+), 61 deletions(-) diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h index 3092bfa964..a3875a3b5a 100644 --- a/accel/tcg/internal.h +++ b/accel/tcg/internal.h @@ -18,4 +18,10 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_= t retaddr); void page_init(void); void tb_htable_init(void); =20 +/* Return the current PC from CPU, which may be cached in TB. */ +static inline target_ulong log_pc(CPUState *cpu, const TranslationBlock *t= b) +{ + return tb_pc(tb); +} + #endif /* ACCEL_TCG_INTERNAL_H */ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index b1b920a713..7ea6026ba9 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -570,6 +570,12 @@ struct TranslationBlock { uintptr_t jmp_dest[2]; }; =20 +/* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */ +static inline target_ulong tb_pc(const TranslationBlock *tb) +{ + return tb->pc; +} + /* Hide the qatomic_read to make code a little easier on the eyes */ static inline uint32_t tb_cflags(const TranslationBlock *tb) { diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 26a70526f1..d84bae6e3f 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -840,7 +840,7 @@ void tcg_register_thread(void); void tcg_prologue_init(TCGContext *s); void tcg_func_start(TCGContext *s); =20 -int tcg_gen_code(TCGContext *s, TranslationBlock *tb); +int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_star= t); =20 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t siz= e); =20 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 2d7e610ee2..8b3f8435fb 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -186,7 +186,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) const TranslationBlock *tb =3D p; const struct tb_desc *desc =3D d; =20 - if (tb->pc =3D=3D desc->pc && + if (tb_pc(tb) =3D=3D desc->pc && tb->page_addr[0] =3D=3D desc->page_addr0 && tb->cs_base =3D=3D desc->cs_base && tb->flags =3D=3D desc->flags && @@ -271,12 +271,10 @@ static inline TranslationBlock *tb_lookup(CPUState *c= pu, target_ulong pc, return tb; } =20 -static inline void log_cpu_exec(target_ulong pc, CPUState *cpu, - const TranslationBlock *tb) +static void log_cpu_exec(target_ulong pc, CPUState *cpu, + const TranslationBlock *tb) { - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) - && qemu_log_in_addr_range(pc)) { - + if (qemu_log_in_addr_range(pc)) { qemu_log_mask(CPU_LOG_EXEC, "Trace %d: %p [" TARGET_FMT_lx "/" TARGET_FMT_lx "/%08x/%08x] %s\n", @@ -400,7 +398,9 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) return tcg_code_gen_epilogue; } =20 - log_cpu_exec(pc, cpu, tb); + if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) { + log_cpu_exec(pc, cpu, tb); + } =20 return tb->tc.ptr; } @@ -423,7 +423,9 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *= tb_exit) TranslationBlock *last_tb; const void *tb_ptr =3D itb->tc.ptr; =20 - log_cpu_exec(itb->pc, cpu, itb); + if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) { + log_cpu_exec(log_pc(cpu, itb), cpu, itb); + } =20 qemu_thread_jit_execute(); ret =3D tcg_qemu_tb_exec(env, tb_ptr); @@ -447,16 +449,20 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int= *tb_exit) * of the start of the TB. */ CPUClass *cc =3D CPU_GET_CLASS(cpu); - qemu_log_mask_and_addr(CPU_LOG_EXEC, last_tb->pc, - "Stopped execution of TB chain before %p [" - TARGET_FMT_lx "] %s\n", - last_tb->tc.ptr, last_tb->pc, - lookup_symbol(last_tb->pc)); + if (cc->tcg_ops->synchronize_from_tb) { cc->tcg_ops->synchronize_from_tb(cpu, last_tb); } else { assert(cc->set_pc); - cc->set_pc(cpu, last_tb->pc); + cc->set_pc(cpu, tb_pc(last_tb)); + } + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + target_ulong pc =3D log_pc(cpu, last_tb); + if (qemu_log_in_addr_range(pc)) { + qemu_log("Stopped execution of TB chain before %p [" + TARGET_FMT_lx "] %s\n", + last_tb->tc.ptr, pc, lookup_symbol(pc)); + } } } =20 @@ -598,11 +604,8 @@ static inline void tb_add_jump(TranslationBlock *tb, i= nt n, =20 qemu_spin_unlock(&tb_next->jmp_lock); =20 - qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, - "Linking TBs %p [" TARGET_FMT_lx - "] index %d -> %p [" TARGET_FMT_lx "]\n", - tb->tc.ptr, tb->pc, n, - tb_next->tc.ptr, tb_next->pc); + qemu_log_mask(CPU_LOG_EXEC, "Linking TBs %p index %d -> %p\n", + tb->tc.ptr, n, tb_next->tc.ptr); return; =20 out_unlock_next: @@ -848,11 +851,12 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, } =20 static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, + target_ulong pc, TranslationBlock **last_tb, int *tb_ex= it) { int32_t insns_left; =20 - trace_exec_tb(tb, tb->pc); + trace_exec_tb(tb, pc); tb =3D cpu_tb_exec(cpu, tb, tb_exit); if (*tb_exit !=3D TB_EXIT_REQUESTED) { *last_tb =3D tb; @@ -1017,7 +1021,7 @@ int cpu_exec(CPUState *cpu) tb_add_jump(last_tb, tb_exit, tb); } =20 - cpu_loop_exec_tb(cpu, tb, &last_tb, &tb_exit); + cpu_loop_exec_tb(cpu, tb, pc, &last_tb, &tb_exit); =20 /* Try to align the host and virtual clocks if the guest is in advance */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 63ecc15236..13c964dcd8 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -299,7 +299,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) =20 for (j =3D 0; j < TARGET_INSN_START_WORDS; ++j) { if (i =3D=3D 0) { - prev =3D (j =3D=3D 0 ? tb->pc : 0); + prev =3D (j =3D=3D 0 ? tb_pc(tb) : 0); } else { prev =3D tcg_ctx->gen_insn_data[i - 1][j]; } @@ -327,7 +327,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t searched_pc, bool reset_ico= unt) { - target_ulong data[TARGET_INSN_START_WORDS] =3D { tb->pc }; + target_ulong data[TARGET_INSN_START_WORDS] =3D { tb_pc(tb) }; uintptr_t host_pc =3D (uintptr_t)tb->tc.ptr; CPUArchState *env =3D cpu->env_ptr; const uint8_t *p =3D tb->tc.ptr + tb->tc.size; @@ -885,7 +885,7 @@ static bool tb_cmp(const void *ap, const void *bp) const TranslationBlock *a =3D ap; const TranslationBlock *b =3D bp; =20 - return a->pc =3D=3D b->pc && + return tb_pc(a) =3D=3D tb_pc(b) && a->cs_base =3D=3D b->cs_base && a->flags =3D=3D b->flags && (tb_cflags(a) & ~CF_INVALID) =3D=3D (tb_cflags(b) & ~CF_INVALID) && @@ -1013,9 +1013,10 @@ static void do_tb_invalidate_check(void *p, uint32_t= hash, void *userp) TranslationBlock *tb =3D p; target_ulong addr =3D *(target_ulong *)userp; =20 - if (!(addr + TARGET_PAGE_SIZE <=3D tb->pc || addr >=3D tb->pc + tb->si= ze)) { + if (!(addr + TARGET_PAGE_SIZE <=3D tb_pc(tb) || + addr >=3D tb_pc(tb) + tb->size)) { printf("ERROR invalidate: address=3D" TARGET_FMT_lx - " PC=3D%08lx size=3D%04x\n", addr, (long)tb->pc, tb->size); + " PC=3D%08lx size=3D%04x\n", addr, (long)tb_pc(tb), tb->siz= e); } } =20 @@ -1034,11 +1035,11 @@ static void do_tb_page_check(void *p, uint32_t hash= , void *userp) TranslationBlock *tb =3D p; int flags1, flags2; =20 - flags1 =3D page_get_flags(tb->pc); - flags2 =3D page_get_flags(tb->pc + tb->size - 1); + flags1 =3D page_get_flags(tb_pc(tb)); + flags2 =3D page_get_flags(tb_pc(tb) + tb->size - 1); if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { printf("ERROR page flags: PC=3D%08lx size=3D%04x f1=3D%x f2=3D%x\n= ", - (long)tb->pc, tb->size, flags1, flags2); + (long)tb_pc(tb), tb->size, flags1, flags2); } } =20 @@ -1169,7 +1170,7 @@ static void do_tb_phys_invalidate(TranslationBlock *t= b, bool rm_from_page_list) =20 /* remove the TB from the hash list */ phys_pc =3D tb->page_addr[0]; - h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags, + h =3D tb_hash_func(phys_pc, tb_pc(tb), tb->flags, orig_cflags, tb->trace_vcpu_dstate); if (!qht_remove(&tb_ctx.htable, tb, h)) { return; @@ -1301,7 +1302,7 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phy= s_pc, } =20 /* add in the hash table */ - h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags, + h =3D tb_hash_func(phys_pc, tb_pc(tb), tb->flags, tb->cflags, tb->trace_vcpu_dstate); qht_insert(&tb_ctx.htable, tb, h, &existing_tb); =20 @@ -1401,7 +1402,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->cpu =3D NULL; max_insns =3D tb->icount; =20 - trace_translate_block(tb, tb->pc, tb->tc.ptr); + trace_translate_block(tb, pc, tb->tc.ptr); =20 /* generate machine code */ tb->jmp_reset_offset[0] =3D TB_JMP_RESET_OFFSET_INVALID; @@ -1422,7 +1423,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, ti =3D profile_getclock(); #endif =20 - gen_code_size =3D tcg_gen_code(tcg_ctx, tb); + gen_code_size =3D tcg_gen_code(tcg_ctx, tb, pc); if (unlikely(gen_code_size < 0)) { error_return: switch (gen_code_size) { @@ -1478,7 +1479,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, =20 #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) && - qemu_log_in_addr_range(tb->pc)) { + qemu_log_in_addr_range(pc)) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { int code_size, data_size; @@ -1918,9 +1919,13 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retad= dr) */ cpu->cflags_next_tb =3D curr_cflags(cpu) | CF_MEMI_ONLY | CF_LAST_IO |= n; =20 - qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, - "cpu_io_recompile: rewound execution of TB to " - TARGET_FMT_lx "\n", tb->pc); + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + target_ulong pc =3D log_pc(cpu, tb); + if (qemu_log_in_addr_range(pc)) { + qemu_log("cpu_io_recompile: rewound execution of TB to " + TARGET_FMT_lx "\n", pc); + } + } =20 cpu_loop_exit_noexc(cpu); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index fa67ba6647..94ca6f163f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -84,9 +84,9 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, * never possible for an AArch64 TB to chain to an AArch32 TB. */ if (is_a64(env)) { - env->pc =3D tb->pc; + env->pc =3D tb_pc(tb); } else { - env->regs[15] =3D tb->pc; + env->regs[15] =3D tb_pc(tb); } } #endif /* CONFIG_TCG */ diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 6900444d03..0d2861179d 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -54,7 +54,7 @@ static void avr_cpu_synchronize_from_tb(CPUState *cs, AVRCPU *cpu =3D AVR_CPU(cs); CPUAVRState *env =3D &cpu->env; =20 - env->pc_w =3D tb->pc / 2; /* internally PC points to words */ + env->pc_w =3D tb_pc(tb) / 2; /* internally PC points to words */ } =20 static void avr_cpu_reset(DeviceState *ds) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 04a497db5e..fa6d722555 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -263,7 +263,7 @@ static void hexagon_cpu_synchronize_from_tb(CPUState *c= s, { HexagonCPU *cpu =3D HEXAGON_CPU(cs); CPUHexagonState *env =3D &cpu->env; - env->gpr[HEX_REG_PC] =3D tb->pc; + env->gpr[HEX_REG_PC] =3D tb_pc(tb); } =20 static bool hexagon_cpu_has_work(CPUState *cs) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index e25d3db6d5..e677ca09d4 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -49,7 +49,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, HPPACPU *cpu =3D HPPA_CPU(cs); =20 #ifdef CONFIG_USER_ONLY - cpu->env.iaoq_f =3D tb->pc; + cpu->env.iaoq_f =3D tb_pc(tb); cpu->env.iaoq_b =3D tb->cs_base; #else /* Recover the IAOQ values from the GVA + PRIV. */ @@ -59,7 +59,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, int32_t diff =3D cs_base; =20 cpu->env.iasq_f =3D iasq_f; - cpu->env.iaoq_f =3D (tb->pc & ~iasq_f) + priv; + cpu->env.iaoq_f =3D (tb_pc(tb) & ~iasq_f) + priv; if (diff) { cpu->env.iaoq_b =3D cpu->env.iaoq_f + diff; } diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index d3c2b8fb49..6cf14c83ff 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -51,7 +51,7 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, { X86CPU *cpu =3D X86_CPU(cs); =20 - cpu->env.eip =3D tb->pc - tb->cs_base; + cpu->env.eip =3D tb_pc(tb) - tb->cs_base; } =20 #ifndef CONFIG_USER_ONLY diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 20a92ea56c..1722ed2a4d 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -317,7 +317,7 @@ static void loongarch_cpu_synchronize_from_tb(CPUState = *cs, LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); CPULoongArchState *env =3D &cpu->env; =20 - env->pc =3D tb->pc; + env->pc =3D tb_pc(tb); } #endif /* CONFIG_TCG */ =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 73af51769e..c10b8ac029 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -96,7 +96,7 @@ static void mb_cpu_synchronize_from_tb(CPUState *cs, { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); =20 - cpu->env.pc =3D tb->pc; + cpu->env.pc =3D tb_pc(tb); cpu->env.iflags =3D tb->flags & IFLAGS_TB_MASK; } =20 diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c index 2bd77a61de..96e61170e6 100644 --- a/target/mips/tcg/exception.c +++ b/target/mips/tcg/exception.c @@ -82,7 +82,7 @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const Tra= nslationBlock *tb) MIPSCPU *cpu =3D MIPS_CPU(cs); CPUMIPSState *env =3D &cpu->env; =20 - env->active_tc.PC =3D tb->pc; + env->active_tc.PC =3D tb_pc(tb); env->hflags &=3D ~MIPS_HFLAG_BMASK; env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; } diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/syse= mu/special_helper.c index f4f8fe8afc..3c5f35c759 100644 --- a/target/mips/tcg/sysemu/special_helper.c +++ b/target/mips/tcg/sysemu/special_helper.c @@ -94,7 +94,7 @@ bool mips_io_recompile_replay_branch(CPUState *cs, const = TranslationBlock *tb) CPUMIPSState *env =3D &cpu->env; =20 if ((env->hflags & MIPS_HFLAG_BMASK) !=3D 0 - && env->active_tc.PC !=3D tb->pc) { + && env->active_tc.PC !=3D tb_pc(tb)) { env->active_tc.PC -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); env->hflags &=3D ~MIPS_HFLAG_BMASK; return true; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 33cf717210..f6fd437785 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -43,7 +43,7 @@ static void openrisc_cpu_synchronize_from_tb(CPUState *cs, { OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); =20 - cpu->env.pc =3D tb->pc; + cpu->env.pc =3D tb_pc(tb); } =20 =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6ca05c6eaf..e6d9c706bb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -482,9 +482,9 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); =20 if (xl =3D=3D MXL_RV32) { - env->pc =3D (int32_t)tb->pc; + env->pc =3D (int32_t)tb_pc(tb); } else { - env->pc =3D tb->pc; + env->pc =3D tb_pc(tb); } } =20 diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 134b4b6bb6..2f28099723 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -44,7 +44,7 @@ static void rx_cpu_synchronize_from_tb(CPUState *cs, { RXCPU *cpu =3D RX_CPU(cs); =20 - cpu->env.pc =3D tb->pc; + cpu->env.pc =3D tb_pc(tb); } =20 static bool rx_cpu_has_work(CPUState *cs) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 4bafbf8596..a65a66de43 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -46,7 +46,7 @@ static void superh_cpu_synchronize_from_tb(CPUState *cs, { SuperHCPU *cpu =3D SUPERH_CPU(cs); =20 - cpu->env.pc =3D tb->pc; + cpu->env.pc =3D tb_pc(tb); cpu->env.flags =3D tb->flags & TB_FLAG_ENVFLAGS_MASK; } =20 @@ -58,7 +58,7 @@ static bool superh_io_recompile_replay_branch(CPUState *c= s, CPUSH4State *env =3D &cpu->env; =20 if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) !=3D 0 - && env->pc !=3D tb->pc) { + && env->pc !=3D tb_pc(tb)) { env->pc -=3D 2; env->flags &=3D ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); return true; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 1b2afb0cb8..1f9ef7afd8 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -705,7 +705,7 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, { SPARCCPU *cpu =3D SPARC_CPU(cs); =20 - cpu->env.pc =3D tb->pc; + cpu->env.pc =3D tb_pc(tb); cpu->env.npc =3D tb->cs_base; } =20 diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 91b16bdefc..ab7a1e3a6d 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -55,7 +55,7 @@ static void tricore_cpu_synchronize_from_tb(CPUState *cs, TriCoreCPU *cpu =3D TRICORE_CPU(cs); CPUTriCoreState *env =3D &cpu->env; =20 - env->PC =3D tb->pc; + env->PC =3D tb_pc(tb); } =20 static void tricore_cpu_reset(DeviceState *dev) diff --git a/tcg/tcg.c b/tcg/tcg.c index 0f9cfe96f2..612a12f58f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -4188,7 +4188,7 @@ int64_t tcg_cpu_exec_time(void) #endif =20 =20 -int tcg_gen_code(TCGContext *s, TranslationBlock *tb) +int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_star= t) { #ifdef CONFIG_PROFILER TCGProfile *prof =3D &s->prof; @@ -4218,7 +4218,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) =20 #ifdef DEBUG_DISAS if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP) - && qemu_log_in_addr_range(tb->pc))) { + && qemu_log_in_addr_range(pc_start))) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { fprintf(logfile, "OP:\n"); @@ -4265,7 +4265,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) if (s->nb_indirects > 0) { #ifdef DEBUG_DISAS if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND) - && qemu_log_in_addr_range(tb->pc))) { + && qemu_log_in_addr_range(pc_start))) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { fprintf(logfile, "OP before indirect lowering:\n"); @@ -4288,7 +4288,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) =20 #ifdef DEBUG_DISAS if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT) - && qemu_log_in_addr_range(tb->pc))) { + && qemu_log_in_addr_range(pc_start))) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { fprintf(logfile, "OP after optimization and liveness analysis:= \n"); --=20 2.34.1 From nobody Sat Apr 27 07:51:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id l18-20020a05620a28d200b006ce813bb306sm3696370qkp.125.2022.09.30.14.27.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 14:27:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=OXc7bZw1hWKlaxP04cgipk+ATzDDKbqBNu4egdi0b9s=; b=V51o3EHD7g64T9rHfR+NDTE1yEyG7m1p1IxcSCRTNBaukht7ImTFi28B2/VZkXN3uJ aAD/K34CrF9XqaEZIZDscqeqh88GMLo68MPtNehJVD3zE9q6GmhQSnAJykkvQ0XiWLLv yWMrECqhglfQrNSHkrbkKuqXS/UsU7lwbdSnMPRCxJUZPr5Ns+L0xSDPS3DqNkFBGrmQ c7yRnhm+dDa6u9uHdaTNa5nWGAFhkvJAABc8X5uXMcaK3Q1rhO/jmt1sTAGTLQ3zfo2Q UAxkUEcIi7pShv82TDqAwVvseEm+AWZ32fomPxWOX5/2lc//tnnhybNCQw0tMgjtvabJ 8Qsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=OXc7bZw1hWKlaxP04cgipk+ATzDDKbqBNu4egdi0b9s=; b=BEqfo8KyE1FMGuhR0JDgiIKYzHeuEQKH3xetozc21EuIIyznLFcrznBOnxQb4ubdPw YQhy3g0KtMfSB0QuZoLrm1nm56G6kyW1Pjjo1rmP5Bh/HxuYk9goHrr2CV4GhxL4SPbJ hkp3n4sbnMn2RpUpQm+7Uzbt6dPw5wRtFDrEvrdFNFdAr/GRCFxWmNp6hIo8gL3gMQWB w8psbMFwxIj3L2BquJ4T9jwA7ixyPG7DMYBtTyQTiv0n+P6IhqocmEAfoaTkBAEJk4Ir cOSakutDSWGYv0vVpnAHrSe988gCuJnNbKtc/1wGF2avCRJIlDLrFMvORoN0hwWI+YRF U8yg== X-Gm-Message-State: ACrzQf34QJC1p0kwnEM8420xlevHYDE3dhB7VJNNX8U4PiIExTL59B15 LZzp1Ab0zg1PPWwtvv0kTsgmaW0BCfR6mA== X-Google-Smtp-Source: AMsMyM6dr2O2NALZcnqe10WxqqqzSYtD7XVPr5ex/TXfAYMsyLhRuP/5m0gze9FoLebse6P/md+VvA== X-Received: by 2002:ac8:5c0b:0:b0:35c:e066:998d with SMTP id i11-20020ac85c0b000000b0035ce066998dmr8464723qti.336.1664573228071; Fri, 30 Sep 2022 14:27:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linux.org, alex.bennee@linux.org Subject: [PATCH v6 18/18] accel/tcg: Introduce TARGET_TB_PCREL Date: Fri, 30 Sep 2022 14:26:22 -0700 Message-Id: <20220930212622.108363-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930212622.108363-1-richard.henderson@linaro.org> References: <20220930212622.108363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::833; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x833.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664574211673100001 Content-Type: text/plain; charset="utf-8" Prepare for targets to be able to produce TBs that can run in more than one virtual context. Signed-off-by: Richard Henderson --- accel/tcg/internal.h | 4 +++ accel/tcg/tb-jmp-cache.h | 5 ++++ include/exec/cpu-defs.h | 3 +++ include/exec/exec-all.h | 32 ++++++++++++++++++++-- accel/tcg/cpu-exec.c | 56 +++++++++++++++++++++++++++++++-------- accel/tcg/translate-all.c | 50 +++++++++++++++++++++------------- 6 files changed, 119 insertions(+), 31 deletions(-) diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h index a3875a3b5a..dc800fd485 100644 --- a/accel/tcg/internal.h +++ b/accel/tcg/internal.h @@ -21,7 +21,11 @@ void tb_htable_init(void); /* Return the current PC from CPU, which may be cached in TB. */ static inline target_ulong log_pc(CPUState *cpu, const TranslationBlock *t= b) { +#if TARGET_TB_PCREL + return cpu->cc->get_pc(cpu); +#else return tb_pc(tb); +#endif } =20 #endif /* ACCEL_TCG_INTERNAL_H */ diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h index 2d8fbb1bfe..a7288150bc 100644 --- a/accel/tcg/tb-jmp-cache.h +++ b/accel/tcg/tb-jmp-cache.h @@ -14,10 +14,15 @@ =20 /* * Accessed in parallel; all accesses to 'tb' must be atomic. + * For TARGET_TB_PCREL, accesses to 'pc' must be protected by + * a load_acquire/store_release to 'tb'. */ struct CPUJumpCache { struct { TranslationBlock *tb; +#if TARGET_TB_PCREL + target_ulong pc; +#endif } array[TB_JMP_CACHE_SIZE]; }; =20 diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 67239b4e5e..21309cf567 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -54,6 +54,9 @@ # error TARGET_PAGE_BITS must be defined in cpu-param.h # endif #endif +#ifndef TARGET_TB_PCREL +# define TARGET_TB_PCREL 0 +#endif =20 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) =20 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 7ea6026ba9..e5f8b224a5 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -496,8 +496,32 @@ struct tb_tc { }; =20 struct TranslationBlock { - target_ulong pc; /* simulated PC corresponding to this block (EIP + = CS base) */ - target_ulong cs_base; /* CS base for this block */ +#if !TARGET_TB_PCREL + /* + * Guest PC corresponding to this block. This must be the true + * virtual address. Therefore e.g. x86 stores EIP + CS_BASE, and + * targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or + * privilege, must store those bits elsewhere. + * + * If TARGET_TB_PCREL, the opcodes for the TranslationBlock are + * written such that the TB is associated only with the physical + * page and may be run in any virtual address context. In this case, + * PC must always be taken from ENV in a target-specific manner. + * Unwind information is taken as offsets from the page, to be + * deposited into the "current" PC. + */ + target_ulong pc; +#endif + + /* + * Target-specific data associated with the TranslationBlock, e.g.: + * x86: the original user, the Code Segment virtual base, + * arm: an extension of tb->flags, + * s390x: instruction data for EXECUTE, + * sparc: the next pc of the instruction queue (for delay slots). + */ + target_ulong cs_base; + uint32_t flags; /* flags defining in which context the code was genera= ted */ uint32_t cflags; /* compile flags */ =20 @@ -573,7 +597,11 @@ struct TranslationBlock { /* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */ static inline target_ulong tb_pc(const TranslationBlock *tb) { +#if TARGET_TB_PCREL + qemu_build_not_reached(); +#else return tb->pc; +#endif } =20 /* Hide the qatomic_read to make code a little easier on the eyes */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8b3f8435fb..acb5646b03 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -186,7 +186,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) const TranslationBlock *tb =3D p; const struct tb_desc *desc =3D d; =20 - if (tb_pc(tb) =3D=3D desc->pc && + if ((TARGET_TB_PCREL || tb_pc(tb) =3D=3D desc->pc) && tb->page_addr[0] =3D=3D desc->page_addr0 && tb->cs_base =3D=3D desc->cs_base && tb->flags =3D=3D desc->flags && @@ -237,7 +237,8 @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu= , target_ulong pc, return NULL; } desc.page_addr0 =3D phys_pc; - h =3D tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate); + h =3D tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : pc), + flags, cflags, *cpu->trace_dstate); return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); } =20 @@ -247,27 +248,52 @@ static inline TranslationBlock *tb_lookup(CPUState *c= pu, target_ulong pc, uint32_t flags, uint32_t cflags) { TranslationBlock *tb; + CPUJumpCache *jc; uint32_t hash; =20 /* we should never be trying to look up an INVALID tb */ tcg_debug_assert(!(cflags & CF_INVALID)); =20 hash =3D tb_jmp_cache_hash_func(pc); - tb =3D qatomic_rcu_read(&cpu->tb_jmp_cache->array[hash].tb); + jc =3D cpu->tb_jmp_cache; +#if TARGET_TB_PCREL + /* Use acquire to ensure current load of pc from jc. */ + tb =3D qatomic_load_acquire(&jc->array[hash].tb); +#else + /* Use rcu_read to ensure current load of pc from *tb. */ + tb =3D qatomic_rcu_read(&jc->array[hash].tb); +#endif =20 - if (likely(tb && - tb->pc =3D=3D pc && - tb->cs_base =3D=3D cs_base && - tb->flags =3D=3D flags && - tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate && - tb_cflags(tb) =3D=3D cflags)) { - return tb; + if (likely(tb)) { + target_ulong jmp_pc; + +#if TARGET_TB_PCREL + jmp_pc =3D jc->array[hash].pc; +#else + jmp_pc =3D tb_pc(tb); +#endif + if (jmp_pc =3D=3D pc && + tb->cs_base =3D=3D cs_base && + tb->flags =3D=3D flags && + tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate && + tb_cflags(tb) =3D=3D cflags) { + return tb; + } } + tb =3D tb_htable_lookup(cpu, pc, cs_base, flags, cflags); if (tb =3D=3D NULL) { return NULL; } - qatomic_set(&cpu->tb_jmp_cache->array[hash].tb, tb); + +#if TARGET_TB_PCREL + jc->array[hash].pc =3D pc; + /* Use store_release on tb to ensure pc is written first. */ + qatomic_store_release(&jc->array[hash].tb, tb); +#else + qatomic_set(&jc->array[hash].tb, tb); +#endif + return tb; } =20 @@ -453,6 +479,7 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *= tb_exit) if (cc->tcg_ops->synchronize_from_tb) { cc->tcg_ops->synchronize_from_tb(cpu, last_tb); } else { + assert(!TARGET_TB_PCREL); assert(cc->set_pc); cc->set_pc(cpu, tb_pc(last_tb)); } @@ -1002,7 +1029,14 @@ int cpu_exec(CPUState *cpu) * for the fast lookup */ h =3D tb_jmp_cache_hash_func(pc); + +#if TARGET_TB_PCREL + cpu->tb_jmp_cache->array[h].pc =3D pc; + /* Use store_release on tb to ensure pc is current. */ + qatomic_store_release(&cpu->tb_jmp_cache->array[h].tb, tb); +#else qatomic_set(&cpu->tb_jmp_cache->array[h].tb, tb); +#endif } =20 #ifndef CONFIG_USER_ONLY diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 13c964dcd8..776ac9efe4 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -299,7 +299,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) =20 for (j =3D 0; j < TARGET_INSN_START_WORDS; ++j) { if (i =3D=3D 0) { - prev =3D (j =3D=3D 0 ? tb_pc(tb) : 0); + prev =3D (!TARGET_TB_PCREL && j =3D=3D 0 ? tb_pc(tb) : 0); } else { prev =3D tcg_ctx->gen_insn_data[i - 1][j]; } @@ -327,7 +327,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t searched_pc, bool reset_ico= unt) { - target_ulong data[TARGET_INSN_START_WORDS] =3D { tb_pc(tb) }; + target_ulong data[TARGET_INSN_START_WORDS]; uintptr_t host_pc =3D (uintptr_t)tb->tc.ptr; CPUArchState *env =3D cpu->env_ptr; const uint8_t *p =3D tb->tc.ptr + tb->tc.size; @@ -343,6 +343,11 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tr= anslationBlock *tb, return -1; } =20 + memset(data, 0, sizeof(data)); + if (!TARGET_TB_PCREL) { + data[0] =3D tb_pc(tb); + } + /* Reconstruct the stored insn data while looking for the point at which the end of the insn exceeds the searched_pc. */ for (i =3D 0; i < num_insns; ++i) { @@ -885,13 +890,13 @@ static bool tb_cmp(const void *ap, const void *bp) const TranslationBlock *a =3D ap; const TranslationBlock *b =3D bp; =20 - return tb_pc(a) =3D=3D tb_pc(b) && - a->cs_base =3D=3D b->cs_base && - a->flags =3D=3D b->flags && - (tb_cflags(a) & ~CF_INVALID) =3D=3D (tb_cflags(b) & ~CF_INVALID) && - a->trace_vcpu_dstate =3D=3D b->trace_vcpu_dstate && - a->page_addr[0] =3D=3D b->page_addr[0] && - a->page_addr[1] =3D=3D b->page_addr[1]; + return ((TARGET_TB_PCREL || tb_pc(a) =3D=3D tb_pc(b)) && + a->cs_base =3D=3D b->cs_base && + a->flags =3D=3D b->flags && + (tb_cflags(a) & ~CF_INVALID) =3D=3D (tb_cflags(b) & ~CF_INVALI= D) && + a->trace_vcpu_dstate =3D=3D b->trace_vcpu_dstate && + a->page_addr[0] =3D=3D b->page_addr[0] && + a->page_addr[1] =3D=3D b->page_addr[1]); } =20 void tb_htable_init(void) @@ -1170,8 +1175,8 @@ static void do_tb_phys_invalidate(TranslationBlock *t= b, bool rm_from_page_list) =20 /* remove the TB from the hash list */ phys_pc =3D tb->page_addr[0]; - h =3D tb_hash_func(phys_pc, tb_pc(tb), tb->flags, orig_cflags, - tb->trace_vcpu_dstate); + h =3D tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : tb_pc(tb)), + tb->flags, orig_cflags, tb->trace_vcpu_dstate); if (!qht_remove(&tb_ctx.htable, tb, h)) { return; } @@ -1187,11 +1192,18 @@ static void do_tb_phys_invalidate(TranslationBlock = *tb, bool rm_from_page_list) } =20 /* remove the TB from the hash list */ - h =3D tb_jmp_cache_hash_func(tb->pc); - CPU_FOREACH(cpu) { - CPUJumpCache *jc =3D cpu->tb_jmp_cache; - if (qatomic_read(&jc->array[h].tb) =3D=3D tb) { - qatomic_set(&jc->array[h].tb, NULL); + if (TARGET_TB_PCREL) { + /* A TB may be at any virtual address */ + CPU_FOREACH(cpu) { + tcg_flush_jmp_cache(cpu); + } + } else { + h =3D tb_jmp_cache_hash_func(tb_pc(tb)); + CPU_FOREACH(cpu) { + CPUJumpCache *jc =3D cpu->tb_jmp_cache; + if (qatomic_read(&jc->array[h].tb) =3D=3D tb) { + qatomic_set(&jc->array[h].tb, NULL); + } } } =20 @@ -1302,8 +1314,8 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phy= s_pc, } =20 /* add in the hash table */ - h =3D tb_hash_func(phys_pc, tb_pc(tb), tb->flags, tb->cflags, - tb->trace_vcpu_dstate); + h =3D tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : tb_pc(tb)), + tb->flags, tb->cflags, tb->trace_vcpu_dstate); qht_insert(&tb_ctx.htable, tb, h, &existing_tb); =20 /* remove TB from the page(s) if we couldn't insert it */ @@ -1373,7 +1385,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, =20 gen_code_buf =3D tcg_ctx->code_gen_ptr; tb->tc.ptr =3D tcg_splitwx_to_rx(gen_code_buf); +#if !TARGET_TB_PCREL tb->pc =3D pc; +#endif tb->cs_base =3D cs_base; tb->flags =3D flags; tb->cflags =3D cflags; --=20 2.34.1