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Fri, 30 Sep 2022 18:42:00 +0000 Received: by hu-devc-lv-u18-c.qualcomm.com (Postfix, from userid 47164) id 099E65000A8; Fri, 30 Sep 2022 11:42:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=8+VHY6k91gOHRJylBEyLnrgL7SOHQ0nxy0AsoCSVYuY=; b=Bnzds9md2+3jGtOWB/vWnuKLmag9NxFT+V9ibSFH7XTUSobF8VD07/viSGSnjERVW2bT YAgbm70MP0VxV/IDapwxfKqqvpa5Jt7sL3UobBcl1VSLsQDBv8itJLUt42AKxRISGucH DpVAZvgh5AhT+8vfw+JLjV5O32dFAJUh7kb23b8EZB38wtAFDajkDVFwmoXIKQD6KLY0 Au9qfQAhDmIQJf4wbCeXEVsZ1zlQRQePio7DmAcIw8cXpducsYvkKtL0a2hmSX9vtwaX kcLrQELEdp479FXmaeFOgkcSn8FwECKJLBv6sqFKPeVuzEf8iH3iW34siq7yX0WYh/Wi qw== From: Taylor Simpson To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, richard.henderson@linaro.org, f4bug@amsat.org, peter.maydell@linaro.org, bcain@quicinc.com, quic_mathbern@quicinc.com, stefanha@redhat.com Subject: [PULL v2 1/3] Hexagon (target/hexagon) add instruction attributes from archlib Date: Fri, 30 Sep 2022 11:41:55 -0700 Message-Id: <20220930184157.30429-2-tsimpson@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220930184157.30429-1-tsimpson@quicinc.com> References: <20220930184157.30429-1-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=tsimpson@qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_LOW=-0.7, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1664563666388100001 The imported files from the architecture library have added some instruction attributes. Some of these will be used in a subsequent patch for determing the size of a store. Signed-off-by: Taylor Simpson Acked-by: Richard Henderson Message-Id: <20220920080746.26791-2-tsimpson@quicinc.com> --- target/hexagon/attribs_def.h.inc | 37 +++++++- target/hexagon/imported/ldst.idef | 122 +++++++++++++------------- target/hexagon/imported/subinsns.idef | 72 +++++++-------- 3 files changed, 133 insertions(+), 98 deletions(-) diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.= h.inc index dc890a557f..222ad95fb0 100644 --- a/target/hexagon/attribs_def.h.inc +++ b/target/hexagon/attribs_def.h.inc @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Res= erved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,6 +38,16 @@ DEF_ATTRIB(SUBINSN, "sub-instruction", "", "") /* Load and Store attributes */ DEF_ATTRIB(LOAD, "Loads from memory", "", "") DEF_ATTRIB(STORE, "Stores to memory", "", "") +DEF_ATTRIB(STOREIMMED, "Stores immed to memory", "", "") +DEF_ATTRIB(MEMSIZE_0B, "Memory width is 0 byte", "", "") +DEF_ATTRIB(MEMSIZE_1B, "Memory width is 1 byte", "", "") +DEF_ATTRIB(MEMSIZE_2B, "Memory width is 2 bytes", "", "") +DEF_ATTRIB(MEMSIZE_4B, "Memory width is 4 bytes", "", "") +DEF_ATTRIB(MEMSIZE_8B, "Memory width is 8 bytes", "", "") +DEF_ATTRIB(REGWRSIZE_1B, "Memory width is 1 byte", "", "") +DEF_ATTRIB(REGWRSIZE_2B, "Memory width is 2 bytes", "", "") +DEF_ATTRIB(REGWRSIZE_4B, "Memory width is 4 bytes", "", "") +DEF_ATTRIB(REGWRSIZE_8B, "Memory width is 8 bytes", "", "") DEF_ATTRIB(MEMLIKE, "Memory-like instruction", "", "") DEF_ATTRIB(MEMLIKE_PACKET_RULES, "follows Memory-like packet rules", "", "= ") =20 @@ -71,6 +81,11 @@ DEF_ATTRIB(COF, "Change-of-flow instruction", "", "") DEF_ATTRIB(CONDEXEC, "May be cancelled by a predicate", "", "") DEF_ATTRIB(DOTNEWVALUE, "Uses a register value generated in this pkt", "",= "") DEF_ATTRIB(NEWCMPJUMP, "Compound compare and jump", "", "") +DEF_ATTRIB(NVSTORE, "New-value store", "", "") +DEF_ATTRIB(MEMOP, "memop", "", "") + +DEF_ATTRIB(ROPS_2, "Compound instruction worth 2 RISC-ops", "", "") +DEF_ATTRIB(ROPS_3, "Compound instruction worth 3 RISC-ops", "", "") =20 /* access to implicit registers */ DEF_ATTRIB(IMPLICIT_WRITES_LR, "Writes the link register", "", "UREG.LR") @@ -87,6 +102,9 @@ DEF_ATTRIB(IMPLICIT_WRITES_P3, "May write Predicate 3", = "", "UREG.P3") DEF_ATTRIB(IMPLICIT_READS_PC, "Reads the PC register", "", "") DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "") DEF_ATTRIB(WRITES_PRED_REG, "Writes a predicate register", "", "") +DEF_ATTRIB(COMMUTES, "The operation is communitive", "", "") +DEF_ATTRIB(DEALLOCRET, "dealloc_return", "", "") +DEF_ATTRIB(DEALLOCFRAME, "deallocframe", "", "") =20 DEF_ATTRIB(CRSLOT23, "Can execute in slot 2 or slot 3 (CR)", "", "") DEF_ATTRIB(IT_NOP, "nop instruction", "", "") @@ -94,17 +112,21 @@ DEF_ATTRIB(IT_EXTENDER, "constant extender instruction= ", "", "") =20 =20 /* Restrictions to make note of */ +DEF_ATTRIB(RESTRICT_COF_MAX1, "One change-of-flow per packet", "", "") +DEF_ATTRIB(RESTRICT_NOPACKET, "Not allowed in a packet", "", "") DEF_ATTRIB(RESTRICT_SLOT0ONLY, "Must execute on slot0", "", "") DEF_ATTRIB(RESTRICT_SLOT1ONLY, "Must execute on slot1", "", "") DEF_ATTRIB(RESTRICT_SLOT2ONLY, "Must execute on slot2", "", "") DEF_ATTRIB(RESTRICT_SLOT3ONLY, "Must execute on slot3", "", "") DEF_ATTRIB(RESTRICT_NOSLOT1, "No slot 1 instruction in parallel", "", "") DEF_ATTRIB(RESTRICT_PREFERSLOT0, "Try to encode into slot 0", "", "") +DEF_ATTRIB(RESTRICT_PACKET_AXOK, "May exist with A-type or X-type", "", "") =20 DEF_ATTRIB(ICOP, "Instruction cache op", "", "") =20 DEF_ATTRIB(HWLOOP0_END, "Ends HW loop0", "", "") DEF_ATTRIB(HWLOOP1_END, "Ends HW loop1", "", "") +DEF_ATTRIB(RET_TYPE, "return type", "", "") DEF_ATTRIB(DCZEROA, "dczeroa type", "", "") DEF_ATTRIB(ICFLUSHOP, "icflush op type", "", "") DEF_ATTRIB(DCFLUSHOP, "dcflush op type", "", "") @@ -116,5 +138,18 @@ DEF_ATTRIB(L2FETCH, "Instruction is l2fetch type", "",= "") DEF_ATTRIB(ICINVA, "icinva", "", "") DEF_ATTRIB(DCCLEANINVA, "dccleaninva", "", "") =20 +/* Documentation Notes */ +DEF_ATTRIB(NOTE_CONDITIONAL, "can be conditionally executed", "", "") +DEF_ATTRIB(NOTE_NEWVAL_SLOT0, "New-value oprnd must execute on slot 0", ""= , "") +DEF_ATTRIB(NOTE_PRIV, "Monitor-level feature", "", "") +DEF_ATTRIB(NOTE_NOPACKET, "solo instruction", "", "") +DEF_ATTRIB(NOTE_AXOK, "May only be grouped with ALU32 or non-FP XTYPE.", "= ", "") +DEF_ATTRIB(NOTE_LATEPRED, "The predicate can not be used as a .new", "", "= ") +DEF_ATTRIB(NOTE_NVSLOT0, "Can execute only in slot 0 (ST)", "", "") + +/* Restrictions to make note of */ +DEF_ATTRIB(RESTRICT_NOSLOT1_STORE, "Packet must not have slot 1 store", ""= , "") +DEF_ATTRIB(RESTRICT_LATEPRED, "Predicate can not be used as a .new.", "", = "") + /* Keep this as the last attribute: */ DEF_ATTRIB(ZZ_LASTATTRIB, "Last attribute in the file", "", "") diff --git a/target/hexagon/imported/ldst.idef b/target/hexagon/imported/ld= st.idef index 359d3b744e..237634bdd9 100644 --- a/target/hexagon/imported/ldst.idef +++ b/target/hexagon/imported/ldst.idef @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Res= erved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,12 +31,12 @@ Q6INSN(L2_##TAG##_pci, OPER"(Rx32++#s4:"SHFT":circ(Mu2)= )",ATTRIB,DESCR,{fEA_REG( Q6INSN(L2_##TAG##_pcr, OPER"(Rx32++I:circ(Mu2))", ATTRIB,DESCR,{fEA_REG(R= xV); fPM_CIRR(RxV,fREAD_IREG(MuV)< (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664563489696960.1012743417144; Fri, 30 Sep 2022 11:44:49 -0700 (PDT) Received: from localhost ([::1]:41380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeL0C-0002LL-Hp for importer@patchew.org; Fri, 30 Sep 2022 14:44:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40970) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeKxj-0006tt-Bf for qemu-devel@nongnu.org; Fri, 30 Sep 2022 14:42:15 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]:14622) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeKxa-0006Zl-Td for qemu-devel@nongnu.org; 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Fri, 30 Sep 2022 18:42:00 +0000 Received: by hu-devc-lv-u18-c.qualcomm.com (Postfix, from userid 47164) id 0C94A5000AE; Fri, 30 Sep 2022 11:42:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=X1JOR3HjK0v2S1ImrEOu4rf0RxPnNx36TsoITvRsSgE=; b=OvPV5wf6mzvJmR+G4W51BoHA6TS7kykOjm8dHnnuE8IPfOEMdKqJD6eOhU/iQucFzJAm JzOYMfjcdC9kVR+hlm4itMOCmhyYlcL8zLBUa+8dsogGBQZG/GXUFFrYSq7397l6xEtE 65fPXcerhQRGhgQf5sAtd1ZE0ltGYxwMEQ0GtWnnv5UxHvidwjqAtPD295WI7jxi62AS ukZTNUfoHkDMdLX/RwZy7CkAMV7AjqvhiK33u7/kiK2ql3QFbknGuFdQteqHwcFyvFDH aUqc+U026TEejFH+xg2ZFF/iJ+lO3hhTRDDsLBbu/r8kbam+HWPOQDAHLrLBK7UMaitr 3w== From: Taylor Simpson To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, richard.henderson@linaro.org, f4bug@amsat.org, peter.maydell@linaro.org, bcain@quicinc.com, quic_mathbern@quicinc.com, stefanha@redhat.com Subject: [PULL v2 2/3] Hexagon (target/hexagon) Change decision to set pkt_has_store_s[01] Date: Fri, 30 Sep 2022 11:41:56 -0700 Message-Id: <20220930184157.30429-3-tsimpson@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220930184157.30429-1-tsimpson@quicinc.com> References: <20220930184157.30429-1-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=tsimpson@qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1664563491591100001 We have found cases where pkt_has_store_s[01] is set incorrectly. This leads to generating an unnecessary store that is left over from a previous packet. Add an attribute to determine if an instruction is a scalar store The attribute is attached to the fSTORE macro (hex_common.py) Update the logic in decode.c that sets pkt_has_store_s[01] Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20220920080746.26791-4-tsimpson@quicinc.com> --- target/hexagon/attribs_def.h.inc | 1 + target/hexagon/decode.c | 13 ++++++++----- target/hexagon/translate.c | 10 ++++++---- target/hexagon/hex_common.py | 3 ++- 4 files changed, 17 insertions(+), 10 deletions(-) diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.= h.inc index 222ad95fb0..5d2a102c18 100644 --- a/target/hexagon/attribs_def.h.inc +++ b/target/hexagon/attribs_def.h.inc @@ -44,6 +44,7 @@ DEF_ATTRIB(MEMSIZE_1B, "Memory width is 1 byte", "", "") DEF_ATTRIB(MEMSIZE_2B, "Memory width is 2 bytes", "", "") DEF_ATTRIB(MEMSIZE_4B, "Memory width is 4 bytes", "", "") DEF_ATTRIB(MEMSIZE_8B, "Memory width is 8 bytes", "", "") +DEF_ATTRIB(SCALAR_STORE, "Store is scalar", "", "") DEF_ATTRIB(REGWRSIZE_1B, "Memory width is 1 byte", "", "") DEF_ATTRIB(REGWRSIZE_2B, "Memory width is 2 bytes", "", "") DEF_ATTRIB(REGWRSIZE_4B, "Memory width is 4 bytes", "", "") diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c index 6f0f27b4ba..6b73b5c60c 100644 --- a/target/hexagon/decode.c +++ b/target/hexagon/decode.c @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Res= erved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -402,10 +402,13 @@ static void decode_set_insn_attr_fields(Packet *pkt) } =20 if (GET_ATTRIB(opcode, A_STORE)) { - if (pkt->insn[i].slot =3D=3D 0) { - pkt->pkt_has_store_s0 =3D true; - } else { - pkt->pkt_has_store_s1 =3D true; + if (GET_ATTRIB(opcode, A_SCALAR_STORE) && + !GET_ATTRIB(opcode, A_MEMSIZE_0B)) { + if (pkt->insn[i].slot =3D=3D 0) { + pkt->pkt_has_store_s0 =3D true; + } else { + pkt->pkt_has_store_s1 =3D true; + } } } =20 diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 0e8a0772f7..b6b834b4ee 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Res= erved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -499,10 +499,12 @@ static void process_store_log(DisasContext *ctx, Pack= et *pkt) * slot 1 and then slot 0. This will be important when * the memory accesses overlap. */ - if (pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa) { + if (pkt->pkt_has_store_s1) { + g_assert(!pkt->pkt_has_dczeroa); process_store(ctx, pkt, 1); } - if (pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa) { + if (pkt->pkt_has_store_s0) { + g_assert(!pkt->pkt_has_dczeroa); process_store(ctx, pkt, 0); } } @@ -665,7 +667,7 @@ static void gen_commit_packet(CPUHexagonState *env, Dis= asContext *ctx, * The dczeroa will be the store in slot 0, check that we don't ha= ve * a store in slot 1 or an HVX store. */ - g_assert(has_store_s0 && !has_store_s1 && !has_hvx_store); + g_assert(!has_store_s1 && !has_hvx_store); process_dczeroa(ctx, pkt); } else if (has_hvx_store) { TCGv mem_idx =3D tcg_constant_tl(ctx->mem_idx); diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index c81aca8d2a..d9ba7df786 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 =20 ## -## Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. +## Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Res= erved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -75,6 +75,7 @@ def calculate_attribs(): add_qemu_macro_attrib('fWRITE_P3', 'A_WRITES_PRED_REG') add_qemu_macro_attrib('fSET_OVERFLOW', 'A_IMPLICIT_WRITES_USR') add_qemu_macro_attrib('fSET_LPCFG', 'A_IMPLICIT_WRITES_USR') + add_qemu_macro_attrib('fSTORE', 'A_SCALAR_STORE') =20 # Recurse down macros, find attributes from sub-macros macroValues =3D list(macros.values()) --=20 2.17.1 From nobody Mon May 6 06:17:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1664563438; cv=none; d=zohomail.com; s=zohoarc; b=QdOpEwaAQwCwX1PFQUbMGlNyViRcpkDnjS7uKwbwclw8N7NzQG53J6Sidx1i9k9+EQpo6LahHf5/8bGJAo6u/IQzqrdTT6zM94H5T1aR7nEn3rg/x2tJkUCdql4gyvLjx+OXnKm21geH4n8reSI/Z4Uu06kUpNxjtPDsL17LMis= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=tsimpson@qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1664563439538100003 The store width is needed for packet commit, so it is stored in ctx->store_width. Currently, it is set when a store has a TCG override instead of a QEMU helper. In the QEMU helper case, the ctx->store_width is not set, we invoke a helper during packet commit that uses the runtime store width. This patch ensures ctx->store_width is set for all store instructions, so performance is improved because packet commit can generate the proper TCG store rather than the generic helper. We do this by - Use the attributes from the instructions during translation to set ctx->store_width - Remove setting of ctx->store_width from genptr.c Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20220920080746.26791-3-tsimpson@quicinc.com> --- target/hexagon/macros.h | 8 ++++---- target/hexagon/genptr.c | 36 ++++++++++++------------------------ target/hexagon/translate.c | 25 +++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 28 deletions(-) diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 92eb8bbf05..c8805bdaeb 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -156,7 +156,7 @@ __builtin_choose_expr(TYPE_TCGV(X), \ gen_store1, (void)0)) #define MEM_STORE1(VA, DATA, SLOT) \ - MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT) + MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, SLOT) =20 #define MEM_STORE2_FUNC(X) \ __builtin_choose_expr(TYPE_INT(X), \ @@ -164,7 +164,7 @@ __builtin_choose_expr(TYPE_TCGV(X), \ gen_store2, (void)0)) #define MEM_STORE2(VA, DATA, SLOT) \ - MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT) + MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, SLOT) =20 #define MEM_STORE4_FUNC(X) \ __builtin_choose_expr(TYPE_INT(X), \ @@ -172,7 +172,7 @@ __builtin_choose_expr(TYPE_TCGV(X), \ gen_store4, (void)0)) #define MEM_STORE4(VA, DATA, SLOT) \ - MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT) + MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, SLOT) =20 #define MEM_STORE8_FUNC(X) \ __builtin_choose_expr(TYPE_INT(X), \ @@ -180,7 +180,7 @@ __builtin_choose_expr(TYPE_TCGV_I64(X), \ gen_store8, (void)0)) #define MEM_STORE8(VA, DATA, SLOT) \ - MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT) + MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, SLOT) #else #define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, slot, VA)) #define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, slot, VA)) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 8a334ba07b..806d0974ff 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -401,62 +401,50 @@ static inline void gen_store32(TCGv vaddr, TCGv src, = int width, int slot) tcg_gen_mov_tl(hex_store_val32[slot], src); } =20 -static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, - DisasContext *ctx, int slot) +static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, int = slot) { gen_store32(vaddr, src, 1, slot); - ctx->store_width[slot] =3D 1; } =20 -static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, - DisasContext *ctx, int slot) +static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, = int slot) { TCGv tmp =3D tcg_constant_tl(src); - gen_store1(cpu_env, vaddr, tmp, ctx, slot); + gen_store1(cpu_env, vaddr, tmp, slot); } =20 -static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, - DisasContext *ctx, int slot) +static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, int = slot) { gen_store32(vaddr, src, 2, slot); - ctx->store_width[slot] =3D 2; } =20 -static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, - DisasContext *ctx, int slot) +static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, = int slot) { TCGv tmp =3D tcg_constant_tl(src); - gen_store2(cpu_env, vaddr, tmp, ctx, slot); + gen_store2(cpu_env, vaddr, tmp, slot); } =20 -static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, - DisasContext *ctx, int slot) +static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, int = slot) { gen_store32(vaddr, src, 4, slot); - ctx->store_width[slot] =3D 4; } =20 -static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, - DisasContext *ctx, int slot) +static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, = int slot) { TCGv tmp =3D tcg_constant_tl(src); - gen_store4(cpu_env, vaddr, tmp, ctx, slot); + gen_store4(cpu_env, vaddr, tmp, slot); } =20 -static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, - DisasContext *ctx, int slot) +static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, = int slot) { tcg_gen_mov_tl(hex_store_addr[slot], vaddr); tcg_gen_movi_tl(hex_store_width[slot], 8); tcg_gen_mov_i64(hex_store_val64[slot], src); - ctx->store_width[slot] =3D 8; } =20 -static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, - DisasContext *ctx, int slot) +static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, = int slot) { TCGv_i64 tmp =3D tcg_constant_i64(src); - gen_store8(cpu_env, vaddr, tmp, ctx, slot); + gen_store8(cpu_env, vaddr, tmp, slot); } =20 static TCGv gen_8bitsof(TCGv result, TCGv value) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index b6b834b4ee..2329177537 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -327,6 +327,30 @@ static void mark_implicit_pred_writes(DisasContext *ct= x, Insn *insn) mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P3, 3); } =20 +static void mark_store_width(DisasContext *ctx, Insn *insn) +{ + uint16_t opcode =3D insn->opcode; + uint32_t slot =3D insn->slot; + uint8_t width =3D 0; + + if (GET_ATTRIB(opcode, A_SCALAR_STORE)) { + if (GET_ATTRIB(opcode, A_MEMSIZE_1B)) { + width |=3D 1; + } + if (GET_ATTRIB(opcode, A_MEMSIZE_2B)) { + width |=3D 2; + } + if (GET_ATTRIB(opcode, A_MEMSIZE_4B)) { + width |=3D 4; + } + if (GET_ATTRIB(opcode, A_MEMSIZE_8B)) { + width |=3D 8; + } + tcg_debug_assert(is_power_of_2(width)); + ctx->store_width[slot] =3D width; + } +} + static void gen_insn(CPUHexagonState *env, DisasContext *ctx, Insn *insn, Packet *pkt) { @@ -334,6 +358,7 @@ static void gen_insn(CPUHexagonState *env, DisasContext= *ctx, mark_implicit_reg_writes(ctx, insn); insn->generate(env, ctx, insn, pkt); mark_implicit_pred_writes(ctx, insn); + mark_store_width(ctx, insn); } else { gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE); } --=20 2.17.1