From nobody Thu Dec 18 19:37:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664545436; cv=none; d=zohomail.com; s=zohoarc; b=YeUpwxytY4nM5ySBxkeHguL3vMsbvUPDc86l9nJfj2JdBSprM8DmFvrBaM+FucnQNp8NVaUzRZQ1FAmBRv7rKYgl3WulzSAz9HdCzRf9jr902JrHN/IoLym0auglQQFH4+SwmbqJlg+4xd//v9S1ETjZgUaBxE/7cQbpGDXLsLY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664545436; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zIYyLttiMxXsI1PS6r70HgPPTwCLHw1LURXuIZ6Iitc=; b=I/fY9+ILn4KoFQLnNWp8sWVNCmhOvxx5F9TN9Sdsg6oHl4640QayPpnIVU6GZ9fmvmVsaZw4WsuKBQsBuCe6vKPxnwX7jARpVSuCgGNStM2bgtsAJCWl6uLG3jVicaKofYKW9sV+BLlAM6yvtNHgr2ny8FBOdU87/We1885Yhp0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664545436648569.8364037187432; Fri, 30 Sep 2022 06:43:56 -0700 (PDT) Received: from localhost ([::1]:47462 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeGJ0-0000lX-K6 for importer@patchew.org; Fri, 30 Sep 2022 09:43:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51938) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeGAm-00008y-Hd for qemu-devel@nongnu.org; Fri, 30 Sep 2022 09:35:24 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:33422) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeGAh-0006UG-M7 for qemu-devel@nongnu.org; Fri, 30 Sep 2022 09:35:22 -0400 Received: by mail-wr1-x42b.google.com with SMTP id s14so6930326wro.0 for ; Fri, 30 Sep 2022 06:35:19 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id q12-20020adfcd8c000000b0021e4829d359sm1982551wrj.39.2022.09.30.06.35.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 06:35:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date; bh=zIYyLttiMxXsI1PS6r70HgPPTwCLHw1LURXuIZ6Iitc=; b=QigvXEk6SMIrIYF5Kf0axRlLVotO0sGhoMnpvDRTGaTBxuRppp2zCzR/Ly7F+Kmsek fP0kOMH2oVUyE4jHg8Jk/ZA9A95PsiYziJdopUoxehasqTFOT0JndtvXE8Awd7+AsnJN gXiWLlOd4G3ehVy66RFuHfOWU+Dy67EYwqkUpK9FqsfOS8fuSkCksV8ae/mSRXxPYapr Ll7FRaMfxWd1WJk74mC4GlaPsaYVVA/grN25NIO06RhdT8uNlHMaYPVdEZW9O5mFSnKC X7AZ92xyCLF6+1tCqaEDTNNQqR3WIEHHrMoHqY6VL68FhuVVwIFy98uV6MP7Gcmkk+VX E8Xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date; bh=zIYyLttiMxXsI1PS6r70HgPPTwCLHw1LURXuIZ6Iitc=; b=XEYTrk17HLs1ualD/O8xsENYUfJ0GSpk92MLTrqRlVzE/oswjwG4VHX1RGwXYV3TBb pU8D8ZPd0k9KGbGtL61AuSSfMzTvfKpuQU1H2cQvhNMIzs+jha8vYEhDaLLxcUNvaxkH 7Sqxxvg/7Mty048PvA0aejgl4hka3W2Obx5xm+oA4AH61PRbO04PvVNzvEuuFJkYpXpk y3HWge0dPCSYnNYoxGwMvy6iRBJLdUFuQIWZnnm2N2Tj9hYwQ5siHTRn8+18ntrVbJB4 ONMJb6iJ+hIWB+swbT+KuPiwXzBACov8kn3BFmVyq48PgK2iniFafJqrH4wTO3Cv99V/ u17g== X-Gm-Message-State: ACrzQf0RnO0b/yiI7upiNXZ9+zMq7yWEdIQ0PbtgzPnNsTxCNQp4ZYHK 4e0+2dpBWWVWa5KbuUl1WaHpLci5GhnxHA== X-Google-Smtp-Source: AMsMyM6ciPc5Bak5y3IrfplPWvgJkq7iVdhPSwz97PWGWGRX8q0Cjgk8C9aD9NerMjJs9svjkClfAQ== X-Received: by 2002:adf:f58b:0:b0:22e:3c4:cf83 with SMTP id f11-20020adff58b000000b0022e03c4cf83mr1362985wro.379.1664544917879; Fri, 30 Sep 2022 06:35:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/10] target/arm: Rearrange cpu64.c so all the CPU initfns are together Date: Fri, 30 Sep 2022 14:35:05 +0100 Message-Id: <20220930133511.2112734-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220930133511.2112734-1-peter.maydell@linaro.org> References: <20220930133511.2112734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664545438120100001 cpu64.c has ended up in a slightly odd order -- it starts with the initfns for most of the models-real-hardware CPUs; after that comes a bunch of support code for SVE, SME, pauth and LPA2 properties. Then come the initfns for the 'host' and 'max' CPU types, and then after that one more models-real-hardware CPU initfn, for a64fx. (This ordering is partly historical and partly required because a64fx needs the SVE properties.) Reorder the file into: * CPU property support functions * initfns for real hardware CPUs * initfns for host and max * class boilerplate Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 712 ++++++++++++++++++++++----------------------- 1 file changed, 356 insertions(+), 356 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e6314e86d20..85e0d1daf1c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -116,313 +116,6 @@ static void aarch64_a35_initfn(Object *obj) define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 -static void aarch64_a57_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a57"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A57; - cpu->midr =3D 0x411fd070; - cpu->revidr =3D 0x00000000; - cpu->reset_fpsid =3D 0x41034070; - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x12111111; - cpu->isar.mvfr2 =3D 0x00000043; - cpu->ctr =3D 0x8444c004; - cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_dfr0 =3D 0x03010066; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10101105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_isar6 =3D 0; - cpu->isar.id_aa64pfr0 =3D 0x00002222; - cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64isar0 =3D 0x00011120; - cpu->isar.id_aa64mmfr0 =3D 0x00001124; - cpu->isar.dbgdidr =3D 0x3516d000; - cpu->isar.dbgdevid =3D 0x01110f13; - cpu->isar.dbgdevid1 =3D 0x2; - cpu->isar.reset_pmcr_el0 =3D 0x41013000; - cpu->clidr =3D 0x0a200023; - cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ - cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ - cpu->dcz_blocksize =3D 4; /* 64 bytes */ - cpu->gic_num_lrs =3D 4; - cpu->gic_vpribits =3D 5; - cpu->gic_vprebits =3D 5; - cpu->gic_pribits =3D 5; - define_cortex_a72_a57_a53_cp_reginfo(cpu); -} - -static void aarch64_a53_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a53"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A53; - cpu->midr =3D 0x410fd034; - cpu->revidr =3D 0x00000000; - cpu->reset_fpsid =3D 0x41034070; - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x12111111; - cpu->isar.mvfr2 =3D 0x00000043; - cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ - cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_dfr0 =3D 0x03010066; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10101105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_isar6 =3D 0; - cpu->isar.id_aa64pfr0 =3D 0x00002222; - cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64isar0 =3D 0x00011120; - cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ - cpu->isar.dbgdidr =3D 0x3516d000; - cpu->isar.dbgdevid =3D 0x00110f13; - cpu->isar.dbgdevid1 =3D 0x1; - cpu->isar.reset_pmcr_el0 =3D 0x41033000; - cpu->clidr =3D 0x0a200023; - cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe00a; /* 32KB L1 icache */ - cpu->ccsidr[2] =3D 0x707fe07a; /* 1024KB L2 cache */ - cpu->dcz_blocksize =3D 4; /* 64 bytes */ - cpu->gic_num_lrs =3D 4; - cpu->gic_vpribits =3D 5; - cpu->gic_vprebits =3D 5; - cpu->gic_pribits =3D 5; - define_cortex_a72_a57_a53_cp_reginfo(cpu); -} - -static void aarch64_a72_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a72"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->midr =3D 0x410fd083; - cpu->revidr =3D 0x00000000; - cpu->reset_fpsid =3D 0x41034080; - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x12111111; - cpu->isar.mvfr2 =3D 0x00000043; - cpu->ctr =3D 0x8444c004; - cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_dfr0 =3D 0x03010066; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_aa64pfr0 =3D 0x00002222; - cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64isar0 =3D 0x00011120; - cpu->isar.id_aa64mmfr0 =3D 0x00001124; - cpu->isar.dbgdidr =3D 0x3516d000; - cpu->isar.dbgdevid =3D 0x01110f13; - cpu->isar.dbgdevid1 =3D 0x2; - cpu->isar.reset_pmcr_el0 =3D 0x41023000; - cpu->clidr =3D 0x0a200023; - cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ - cpu->ccsidr[2] =3D 0x707fe07a; /* 1MB L2 cache */ - cpu->dcz_blocksize =3D 4; /* 64 bytes */ - cpu->gic_num_lrs =3D 4; - cpu->gic_vpribits =3D 5; - cpu->gic_vprebits =3D 5; - cpu->gic_pribits =3D 5; - define_cortex_a72_a57_a53_cp_reginfo(cpu); -} - -static void aarch64_a76_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a76"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - - /* Ordered by B2.4 AArch64 registers by functional group */ - cpu->clidr =3D 0x82000023; - cpu->ctr =3D 0x8444C004; - cpu->dcz_blocksize =3D 4; - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; - cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; - cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; - cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x04010088; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x01011121; - cpu->isar.id_isar6 =3D 0x00000010; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_mmfr4 =3D 0x00021110; - cpu->isar.id_pfr0 =3D 0x10010131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ - cpu->isar.id_pfr2 =3D 0x00000011; - cpu->midr =3D 0x414fd0b1; /* r4p1 */ - cpu->revidr =3D 0; - - /* From B2.18 CCSIDR_EL1 */ - cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ - cpu->ccsidr[2] =3D 0x707fe03a; /* 512KB L2 cache */ - - /* From B2.93 SCTLR_EL3 */ - cpu->reset_sctlr =3D 0x30c50838; - - /* From B4.23 ICH_VTR_EL2 */ - cpu->gic_num_lrs =3D 4; - cpu->gic_vpribits =3D 5; - cpu->gic_vprebits =3D 5; - cpu->gic_pribits =3D 5; - - /* From B5.1 AdvSIMD AArch64 register summary */ - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x13211111; - cpu->isar.mvfr2 =3D 0x00000043; - - /* From D5.1 AArch64 PMU register summary */ - cpu->isar.reset_pmcr_el0 =3D 0x410b3000; -} - -static void aarch64_neoverse_n1_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,neoverse-n1"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - - /* Ordered by B2.4 AArch64 registers by functional group */ - cpu->clidr =3D 0x82000023; - cpu->ctr =3D 0x8444c004; - cpu->dcz_blocksize =3D 4; - cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; - cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; - cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; - cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000020ull; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x04010088; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x01011121; - cpu->isar.id_isar6 =3D 0x00000010; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_mmfr4 =3D 0x00021110; - cpu->isar.id_pfr0 =3D 0x10010131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ - cpu->isar.id_pfr2 =3D 0x00000011; - cpu->midr =3D 0x414fd0c1; /* r4p1 */ - cpu->revidr =3D 0; - - /* From B2.23 CCSIDR_EL1 */ - cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ - cpu->ccsidr[2] =3D 0x70ffe03a; /* 1MB L2 cache */ - - /* From B2.98 SCTLR_EL3 */ - cpu->reset_sctlr =3D 0x30c50838; - - /* From B4.23 ICH_VTR_EL2 */ - cpu->gic_num_lrs =3D 4; - cpu->gic_vpribits =3D 5; - cpu->gic_vprebits =3D 5; - cpu->gic_pribits =3D 5; - - /* From B5.1 AdvSIMD AArch64 register summary */ - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x13211111; - cpu->isar.mvfr2 =3D 0x00000043; - - /* From D5.1 AArch64 PMU register summary */ - cpu->isar.reset_pmcr_el0 =3D 0x410c3000; -} - void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* @@ -985,6 +678,362 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) cpu->isar.id_aa64mmfr0 =3D t; } =20 +static void aarch64_a57_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a57"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A57; + cpu->midr =3D 0x411fd070; + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034070; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x12111111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x8444c004; + cpu->reset_sctlr =3D 0x00c50838; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x03010066; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10101105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00011142; + cpu->isar.id_isar5 =3D 0x00011121; + cpu->isar.id_isar6 =3D 0; + cpu->isar.id_aa64pfr0 =3D 0x00002222; + cpu->isar.id_aa64dfr0 =3D 0x10305106; + cpu->isar.id_aa64isar0 =3D 0x00011120; + cpu->isar.id_aa64mmfr0 =3D 0x00001124; + cpu->isar.dbgdidr =3D 0x3516d000; + cpu->isar.dbgdevid =3D 0x01110f13; + cpu->isar.dbgdevid1 =3D 0x2; + cpu->isar.reset_pmcr_el0 =3D 0x41013000; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ + cpu->dcz_blocksize =3D 4; /* 64 bytes */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + define_cortex_a72_a57_a53_cp_reginfo(cpu); +} + +static void aarch64_a53_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a53"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A53; + cpu->midr =3D 0x410fd034; + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034070; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x12111111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ + cpu->reset_sctlr =3D 0x00c50838; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x03010066; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10101105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00011142; + cpu->isar.id_isar5 =3D 0x00011121; + cpu->isar.id_isar6 =3D 0; + cpu->isar.id_aa64pfr0 =3D 0x00002222; + cpu->isar.id_aa64dfr0 =3D 0x10305106; + cpu->isar.id_aa64isar0 =3D 0x00011120; + cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ + cpu->isar.dbgdidr =3D 0x3516d000; + cpu->isar.dbgdevid =3D 0x00110f13; + cpu->isar.dbgdevid1 =3D 0x1; + cpu->isar.reset_pmcr_el0 =3D 0x41033000; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe00a; /* 32KB L1 icache */ + cpu->ccsidr[2] =3D 0x707fe07a; /* 1024KB L2 cache */ + cpu->dcz_blocksize =3D 4; /* 64 bytes */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + define_cortex_a72_a57_a53_cp_reginfo(cpu); +} + +static void aarch64_a72_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a72"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x410fd083; + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034080; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x12111111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x8444c004; + cpu->reset_sctlr =3D 0x00c50838; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x03010066; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00011142; + cpu->isar.id_isar5 =3D 0x00011121; + cpu->isar.id_aa64pfr0 =3D 0x00002222; + cpu->isar.id_aa64dfr0 =3D 0x10305106; + cpu->isar.id_aa64isar0 =3D 0x00011120; + cpu->isar.id_aa64mmfr0 =3D 0x00001124; + cpu->isar.dbgdidr =3D 0x3516d000; + cpu->isar.dbgdevid =3D 0x01110f13; + cpu->isar.dbgdevid1 =3D 0x2; + cpu->isar.reset_pmcr_el0 =3D 0x41023000; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] =3D 0x707fe07a; /* 1MB L2 cache */ + cpu->dcz_blocksize =3D 4; /* 64 bytes */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + define_cortex_a72_a57_a53_cp_reginfo(cpu); +} + +static void aarch64_a76_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a76"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr =3D 0x82000023; + cpu->ctr =3D 0x8444C004; + cpu->dcz_blocksize =3D 4; + cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_dfr0 =3D 0x04010088; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x01011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_mmfr4 =3D 0x00021110; + cpu->isar.id_pfr0 =3D 0x10010131; + cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->midr =3D 0x414fd0b1; /* r4p1 */ + cpu->revidr =3D 0; + + /* From B2.18 CCSIDR_EL1 */ + cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x707fe03a; /* 512KB L2 cache */ + + /* From B2.93 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; + + /* From D5.1 AArch64 PMU register summary */ + cpu->isar.reset_pmcr_el0 =3D 0x410b3000; +} + +static void aarch64_a64fx_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,a64fx"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x461f0010; + cpu->revidr =3D 0x00000000; + cpu->ctr =3D 0x86668006; + cpu->reset_sctlr =3D 0x30000180; + cpu->isar.id_aa64pfr0 =3D 0x0000000101111111; /* No RAS Extensions */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000000; + cpu->isar.id_aa64dfr0 =3D 0x0000000010305408; + cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; + cpu->id_aa64afr0 =3D 0x0000000000000000; + cpu->id_aa64afr1 =3D 0x0000000000000000; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000001122; + cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; + cpu->isar.id_aa64isar0 =3D 0x0000000010211120; + cpu->isar.id_aa64isar1 =3D 0x0000000000010001; + cpu->isar.id_aa64zfr0 =3D 0x0000000000000000; + cpu->clidr =3D 0x0000000080000023; + cpu->ccsidr[0] =3D 0x7007e01c; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x2007e01c; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe07c; /* 8MB L2 cache */ + cpu->dcz_blocksize =3D 6; /* 256 bytes */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + + /* The A64FX supports only 128, 256 and 512 bit vector lengths */ + aarch64_add_sve_properties(obj); + cpu->sve_vq.supported =3D (1 << 0) /* 128bit */ + | (1 << 1) /* 256bit */ + | (1 << 3); /* 512bit */ + + cpu->isar.reset_pmcr_el0 =3D 0x46014040; + + /* TODO: Add A64FX specific HPC extension registers */ +} + +static void aarch64_neoverse_n1_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,neoverse-n1"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr =3D 0x82000023; + cpu->ctr =3D 0x8444c004; + cpu->dcz_blocksize =3D 4; + cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; + cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000020ull; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_dfr0 =3D 0x04010088; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x01011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_mmfr4 =3D 0x00021110; + cpu->isar.id_pfr0 =3D 0x10010131; + cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->midr =3D 0x414fd0c1; /* r4p1 */ + cpu->revidr =3D 0; + + /* From B2.23 CCSIDR_EL1 */ + cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe03a; /* 1MB L2 cache */ + + /* From B2.98 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; + + /* From D5.1 AArch64 PMU register summary */ + cpu->isar.reset_pmcr_el0 =3D 0x410c3000; +} + static void aarch64_host_initfn(Object *obj) { #if defined(CONFIG_KVM) @@ -1188,55 +1237,6 @@ static void aarch64_max_initfn(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); } =20 -static void aarch64_a64fx_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,a64fx"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->midr =3D 0x461f0010; - cpu->revidr =3D 0x00000000; - cpu->ctr =3D 0x86668006; - cpu->reset_sctlr =3D 0x30000180; - cpu->isar.id_aa64pfr0 =3D 0x0000000101111111; /* No RAS Extensions */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000000; - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408; - cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; - cpu->id_aa64afr0 =3D 0x0000000000000000; - cpu->id_aa64afr1 =3D 0x0000000000000000; - cpu->isar.id_aa64mmfr0 =3D 0x0000000000001122; - cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; - cpu->isar.id_aa64isar0 =3D 0x0000000010211120; - cpu->isar.id_aa64isar1 =3D 0x0000000000010001; - cpu->isar.id_aa64zfr0 =3D 0x0000000000000000; - cpu->clidr =3D 0x0000000080000023; - cpu->ccsidr[0] =3D 0x7007e01c; /* 64KB L1 dcache */ - cpu->ccsidr[1] =3D 0x2007e01c; /* 64KB L1 icache */ - cpu->ccsidr[2] =3D 0x70ffe07c; /* 8MB L2 cache */ - cpu->dcz_blocksize =3D 6; /* 256 bytes */ - cpu->gic_num_lrs =3D 4; - cpu->gic_vpribits =3D 5; - cpu->gic_vprebits =3D 5; - cpu->gic_pribits =3D 5; - - /* The A64FX supports only 128, 256 and 512 bit vector lengths */ - aarch64_add_sve_properties(obj); - cpu->sve_vq.supported =3D (1 << 0) /* 128bit */ - | (1 << 1) /* 256bit */ - | (1 << 3); /* 512bit */ - - cpu->isar.reset_pmcr_el0 =3D 0x46014040; - - /* TODO: Add A64FX specific HPC extension registers */ -} - static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a35", .initfn =3D aarch64_a35_initfn }, { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, --=20 2.25.1