From nobody Sun May 5 18:48:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664545706; cv=none; d=zohomail.com; s=zohoarc; b=Wv85JiCJScOhaSQiJ7O0qCnYsS32tHQQMgeW0gorvBNDah8AAbVXHN0zP3eCeLXRbWgdoTC3UnLKEd4uw+wJ2+5Bio/TLDzc5+czvJ35EDBwlJwCRbdXasnzpdfyxxUfuNtV7HmfJzAKus8C3Xqqcj4XWtIkYScEdv5Q4FF3WDY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664545706; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lv5Lub/tmu9xYSAhxszM5djlTRTAdvotsyGEEogoZns=; b=lo55LBRCIpblgtjyw6ICMRLyt1+2yOVphvouH1gtBDRm8IFLmcmTqtBDLalw1j2MzQOlhmjoLNSPIBnOlh1P6Zsp5UjSv2CNTEo6ObZtuOce6rR1eL5D3YS6d6lAqCKyjY0fcpqAlBCXySBLjNBvBE3gxiK1cuZ489xp6PJAzt4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664545706924580.9115329901451; Fri, 30 Sep 2022 06:48:26 -0700 (PDT) Received: from localhost ([::1]:46152 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeGNN-0006oV-Pw for importer@patchew.org; Fri, 30 Sep 2022 09:48:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51940) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeGAm-0000A7-Nk for qemu-devel@nongnu.org; Fri, 30 Sep 2022 09:35:24 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:54067) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeGAf-0006Tb-Dr for qemu-devel@nongnu.org; Fri, 30 Sep 2022 09:35:24 -0400 Received: by mail-wm1-x336.google.com with SMTP id e18so2934107wmq.3 for ; Fri, 30 Sep 2022 06:35:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id q12-20020adfcd8c000000b0021e4829d359sm1982551wrj.39.2022.09.30.06.35.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 06:35:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date; bh=lv5Lub/tmu9xYSAhxszM5djlTRTAdvotsyGEEogoZns=; b=B7vC++4mX/zs1oygXxXKAuL/UX6VAnNzKMFnvJOLKhUA+CxxoZ8bVNgIo/LdqtRX1y bak6c8XksAjg/qw2+wJGEAE6ab0JSxXuxDfRcouN8G3pTPOMSzmpiE9pMd0VIcL9TSoj 6p517zGT2sfKe5UH0iLbtx7z/aW9H569XLiKuotGUX9SfxDH7SvDTyYVPIrpqrGS9+v5 /FS7WEgfT2bq/7yK1uqHrc7ltmpuPsLJuOHnOW5i2aLByUIy+aLOuLyqysUa2vFDL3xt uveY2cbHLaP2u7P0CkPG+awUUuytgi4jljT0Osz2StBLkGnUDD13lwZ2dnFOZzcf/x/L nwHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date; bh=lv5Lub/tmu9xYSAhxszM5djlTRTAdvotsyGEEogoZns=; b=NLwuT8e0qaR+TW9wdCoQpYKPwEuukYrltzdB5IRot1nI7FkzwNW3m7KyDcaZwjQ2ja kJ743E553wvDPqkztYGdB7THm4Z4SeQLVCTWbGJaSo+cKP88lQ8jDCiVkd5PF24abKgf SazYUdwAzQFlxRckwZZHwV9byXoSoLuNQZhu/FGd7GLCN2UOV8ub8Bf0eSb3Rj9kyNis iplrWHRkkUqmzfArYHPB57LjozKAPD4eodw+hRO0FBtG5UNWd9qdfhJvMm2w0XkWNysH JtK21ZQgGsP8z5nALfOvVpqjx+P3mR4tp3NZXqu1AjwEk+SMVrSNzydBhFxrWGesAmpK i9bg== X-Gm-Message-State: ACrzQf0XPxVcBYMUU54eifxDOgQLArEtao1msRi9yj8niZp1zAcibffF Ex9sCjVkVwkoml7yp09+y8u7KGdTHEv1XA== X-Google-Smtp-Source: AMsMyM5MMczs1PT+1BZRSYufXAZAppXk/upUe4wKSM+lmH7y2NqywQdQaMYKkAp9Faz0dGFyt4znIQ== X-Received: by 2002:a05:600c:3d13:b0:3b4:be25:9236 with SMTP id bh19-20020a05600c3d1300b003b4be259236mr5936139wmb.65.1664544915069; Fri, 30 Sep 2022 06:35:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/10] target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO Date: Fri, 30 Sep 2022 14:35:02 +0100 Message-Id: <20220930133511.2112734-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220930133511.2112734-1-peter.maydell@linaro.org> References: <20220930133511.2112734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664545708426100001 Content-Type: text/plain; charset="utf-8" In commit 01765386a888 we made some system register write functions call pmu_op_start()/pmu_op_finish(). This means that they now touch timers, so for icount to work these registers must have the ARM_CP_IO flag set. This fixes a bug where when icount is enabled a guest that touches MDCR_EL3, MDCR_EL2, PMCNTENSET_EL0 or PMCNTENCLR_EL0 would cause QEMU to print an error message and exit, for example: [ 2.495971] TCP: Hash tables configured (established 1024 bind 1024) [ 2.496213] UDP hash table entries: 256 (order: 1, 8192 bytes) [ 2.496386] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes) [ 2.496917] NET: Registered protocol family 1 qemu-system-aarch64: Bad icount read Reported-by: Thomas Huth Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220923123412.1214041-2-peter.maydell@linaro.org --- target/arm/helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b5dac651e75..fadeed0b6bb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1927,12 +1927,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. */ { .name =3D "PMCNTENSET", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 1, - .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, + .access =3D PL0_RW, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), .writefn =3D pmcntenset_write, .accessfn =3D pmreg_access, .raw_writefn =3D raw_write }, - { .name =3D "PMCNTENSET_EL0", .state =3D ARM_CP_STATE_AA64, + { .name =3D "PMCNTENSET_EL0", .state =3D ARM_CP_STATE_AA64, .type =3D = ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 1, .access =3D PL0_RW, .accessfn =3D pmreg_access, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue= =3D 0, @@ -1942,11 +1942,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), .accessfn =3D pmreg_access, .writefn =3D pmcntenclr_write, - .type =3D ARM_CP_ALIAS }, + .type =3D ARM_CP_ALIAS | ARM_CP_IO }, { .name =3D "PMCNTENCLR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 2, .access =3D PL0_RW, .accessfn =3D pmreg_access, - .type =3D ARM_CP_ALIAS, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .writefn =3D pmcntenclr_write }, { .name =3D "PMOVSR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 3, @@ -5125,7 +5125,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 3, .opc2 =3D 1, .resetvalue =3D 0, .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr= _el3) }, - { .name =3D "SDCR", .type =3D ARM_CP_ALIAS, + { .name =3D "SDCR", .type =3D ARM_CP_ALIAS | ARM_CP_IO, .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, .writefn =3D sdcr_write, @@ -7832,7 +7832,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) * value is MDCR_EL2.HPMN which should reset to the value of PMCR_= EL0.N. */ ARMCPRegInfo mdcr_el2 =3D { - .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, + .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, .type =3D = ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, .writefn =3D mdcr_el2_write, .access =3D PL2_RW, .resetvalue =3D pmu_num_counters(env), --=20 2.25.1 From nobody Sun May 5 18:48:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664545996; cv=none; d=zohomail.com; s=zohoarc; b=axj8X2dTospwpiU0cz9y87TJIIvBiH2oKqG1sVn7JUB8yJX45Txh919Lg0sKZdfTTcmfgfqPiMxuzuOBEQZ08SI5VMOgHa8HnaPFX3NqB9PfZGA1h2piuFLRCTnJDjphXIee88Erpj9gSRq5QZcFJLuZ3nkFiLcpDwMwnXqf9Kw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664545996; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=73I/YN0PohfN/LqwegA1J/BEgnb2qX8LZ5lHJjg4/5M=; b=bw11bL61l+oTLv/eqPSLXDYxXFD9nX6zEGhCda+jkJmSUVbmymAKKEs1H8j+DYxjg7DT8lvzr03mbBxAtS6vcrdx7OKdthpthXC1SkoAx0PcH500HBk23fnTdkhfyxEibdNECO1dDG4Cw3uebQVU4ePvUfaTCguBLwDWyJKD/28= ARC-Authentication-Results: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id q12-20020adfcd8c000000b0021e4829d359sm1982551wrj.39.2022.09.30.06.35.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 06:35:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date; bh=73I/YN0PohfN/LqwegA1J/BEgnb2qX8LZ5lHJjg4/5M=; b=eHwEFu3esV1/kGkXdAd0JUt3YzZ/nRMkSZXGloMvmZrksYcJUSiaxGPejnxYkzqJtz 0BxCU1cdpx5KSKfYiF1Jp209m6xzuEH1Cr8wj4rOvfY1WBgDFYaiMWmS+eFnt9XOjOv4 6y8glS9llj/HHtEcOo6Io3vJJHWqhDr5atxc8B7p404C7gVHhVGmh/56oiuEFLczvFHk 3itvkTVCd9SJlCQGVaZAIpSgcX3aeANl0CBLap9sil4eOcrI92UcLPwEpPTUXgmLDOIC ieOAubo9TjtI5CqmgqAxSvGvp2hEdUCxuDKIWi4DbIT0yvJFTSclZB+Jev6TCsxXnwuJ bGmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date; bh=73I/YN0PohfN/LqwegA1J/BEgnb2qX8LZ5lHJjg4/5M=; b=xU0GViN+/UxkhT3WiIzieOUKYP5H29Yu9AScHlKzB7Xb+Y8nF54HDI3tSPfIyDLrEt iRBu5m/FL326RV75bUvQHk96NWTKZCfIZEBgH0kpUCFjk/lkbm71rG0zNBW6U3KMwpLS OUWnNcBLiQLq/QC9NELvbqt6xpF5VUoupDbFA0CynH5QST3sB6BqixnSsPfItS2beGwE QFEdyjeSHtqKwlw7iF5aBEMY9WOp2bXIsI9cZ79/DY0KwOVOR8LWmF8Kb8ITJRpV6kZx ZEuV1ndC8DpR6diSqfP1hTLO+820PGlIEfjfK1r6L8qdQtNpFxpOuDmwPyt2gX+HDvgZ zIrA== X-Gm-Message-State: ACrzQf2JMEscsnHCeq3+Y+UppMHNFmMEpXl63+NQVN/tPw/AdOJipEWw 6afczj6NQqTHXByTjKtF6bivl79qineB3Q== X-Google-Smtp-Source: AMsMyM6pJQFkIjmUTe1SZtrn1e1PT276kbL0J5NYfdqgIDm0cPMx6SDCPk2DN3/S/aSxASpqOo3BgQ== X-Received: by 2002:a7b:c3c8:0:b0:3b4:7279:c2c2 with SMTP id t8-20020a7bc3c8000000b003b47279c2c2mr6062202wmj.186.1664544915942; Fri, 30 Sep 2022 06:35:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/10] target/arm: Make writes to MDCR_EL3 use PMU start/finish calls Date: Fri, 30 Sep 2022 14:35:03 +0100 Message-Id: <20220930133511.2112734-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220930133511.2112734-1-peter.maydell@linaro.org> References: <20220930133511.2112734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664545997028100001 Content-Type: text/plain; charset="utf-8" In commit 01765386a88868 we fixed a bug where we weren't correctly bracketing changes to some registers with pmu_op_start() and pmu_op_finish() calls for changes which affect whether the PMU counters might be enabled. However, we missed the case of writes to the AArch64 MDCR_EL3 register, because (unlike its AArch32 counterpart) they are currently done directly to the CPU state struct without going through the sdcr_write() function. Give MDCR_EL3 a writefn which handles the PMU start/finish calls. The SDCR writefn then simplfies to "call the MDCR_EL3 writefn after masking off the bits which don't exist in the AArch32 register". Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220923123412.1214041-3-peter.maydell@linaro.org --- target/arm/helper.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index fadeed0b6bb..24c592ffef8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4756,8 +4756,8 @@ static void sctlr_write(CPUARMState *env, const ARMCP= RegInfo *ri, } } =20 -static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void mdcr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { /* * Some MDCR_EL3 bits affect whether PMU counters are running: @@ -4769,12 +4769,19 @@ static void sdcr_write(CPUARMState *env, const ARMC= PRegInfo *ri, if (pmu_op) { pmu_op_start(env); } - env->cp15.mdcr_el3 =3D value & SDCR_VALID_MASK; + env->cp15.mdcr_el3 =3D value; if (pmu_op) { pmu_op_finish(env); } } =20 +static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */ + mdcr_el3_write(env, ri, value & SDCR_VALID_MASK); +} + static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -5122,9 +5129,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, { .name =3D "MDCR_EL3", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 3, .opc2 =3D 1, .resetvalue =3D 0, - .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr= _el3) }, + .access =3D PL3_RW, + .writefn =3D mdcr_el3_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr_el3) }, { .name =3D "SDCR", .type =3D ARM_CP_ALIAS | ARM_CP_IO, .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, --=20 2.25.1 From nobody Sun May 5 18:48:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664545598; cv=none; d=zohomail.com; s=zohoarc; b=MxjPdIs0vTr0X7i1LaHmVLY0nTIa8FvcJoz6HO+urGiFlB+ITIsb9fnn507GhD7nTt/28kwp9YpceZtLI/4Lh0xZNFxR6N8E/SSn7WxJbQgxPcR2+ax/rHNHTFFsZTrMRRF9J5XYR9gDfNO+HrK72bACREzKTbHlVmc/RQ5bjV8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664545598; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=imEm8w++jV+IWXUhacU2AqCzT3xaB4Wyvb08UtO6IHo=; b=eqHvTZtlNwthUZi3D+g/WgiSWGf8bJQ16FEp6Mqk4ENRtTuJwyPptkNyQj1L4PVv8VFKi6y0nFwoTASmTFSil0hrK9OWKBQ07LjSrHJjeM0bKJOVTXpq5+djilrHI0mDVSX65nL9+VZlZ9sMAm1YZitIPr/OEzgx5O81uVd7yKI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664545598243643.788636366533; Fri, 30 Sep 2022 06:46:38 -0700 (PDT) Received: from localhost ([::1]:47922 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeGLd-0003Nl-3n for importer@patchew.org; Fri, 30 Sep 2022 09:46:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51888) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeGAw-0000a3-35 for qemu-devel@nongnu.org; Fri, 30 Sep 2022 09:35:34 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:36485) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeGAg-0006Tn-HL for qemu-devel@nongnu.org; Fri, 30 Sep 2022 09:35:33 -0400 Received: by mail-wm1-x32d.google.com with SMTP id i203-20020a1c3bd4000000b003b3df9a5ecbso5064701wma.1 for ; Fri, 30 Sep 2022 06:35:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id q12-20020adfcd8c000000b0021e4829d359sm1982551wrj.39.2022.09.30.06.35.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 06:35:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date; bh=imEm8w++jV+IWXUhacU2AqCzT3xaB4Wyvb08UtO6IHo=; b=pSaYEbaDPim8DBnGM4T3g7g+xU9Mzd9sMWRyzC1JNWBuV4FaWWiEE7/K9z73vyKO6t em2Yjrtq+XLSh06ET3BMBT8s7OGNVcRZHYF9QTXh9XE4NsnEvT1oEALWeak8pqDYUJYG 8aFw8FKkBUyanpviGgrkVOUU0AwJtiKp+dkm9VWYt0P6wcoY0Zscz3Cd0pQI577xuzuc 8jIvtzHaz1S02CvsN8s/QVBu1IX2xtWC+RypN1IEGba3cQJdb6E/BOdsCT9An+7vZ1ZJ zDWi/HbAGsmkvaNjGJB34QvtLz9eUjSCX2psduej/iWiWPKwzPEDbtVBeBWLtpXYQsvN Y1KQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date; bh=imEm8w++jV+IWXUhacU2AqCzT3xaB4Wyvb08UtO6IHo=; b=BtkgXHSD3fs0TTQmtPVDMq31AiOz/QMocx/r7zox/GOw8QuXWFZ4YHszUAPCb6DuYv bTyoCZsDNPJmSP3ZD4yn/+mgwJZ+6HkrGINt9bmpZBQDrM3+FyOIRAdIOvSvsYTPX8RI 56HW6gUwHxN3Th8i/UXPUrsq9Bp0g1QfArxzVnpXfwEGoIpjuD4fwdE+9xv+rHaqADcZ qwmlv+QQEzlG7YlD8SOFEo3rZhiXLpGnIVPGpCj3oFCtLRltw5gJ5+gVYe4sA/qf/+VK J8j1JYuUaBsZPCRessy3nMaDqOBsKh1DKSx+wd4dikCbgwGFeSLqziWESOstYsE/MeJp PWcw== X-Gm-Message-State: ACrzQf1w3TJhUjFsMCVuFPgjJ2/frrttVcGR8sdTzAcnZW4plnt26e8A kxHb7AhALNItFgA7xdHWL4Nz1e3ClV3spg== X-Google-Smtp-Source: AMsMyM7LDoTazrIHb2H87S05nk33ubaWeoOUycSFKAvFkrImFSgOtRoWxtGm6giG+1nLHWrsXJmXiQ== X-Received: by 2002:a7b:ce97:0:b0:3b3:4136:59fe with SMTP id q23-20020a7bce97000000b003b3413659femr5956569wmj.24.1664544916646; Fri, 30 Sep 2022 06:35:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/10] target/arm: Update SDCR_VALID_MASK to include SCCD Date: Fri, 30 Sep 2022 14:35:04 +0100 Message-Id: <20220930133511.2112734-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220930133511.2112734-1-peter.maydell@linaro.org> References: <20220930133511.2112734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664545599215100003 Content-Type: text/plain; charset="utf-8" Our SDCR_VALID_MASK doesn't include all of the bits which are defined by the current architecture. In particular in commit 0b42f4fab9d3 we forgot to add SCCD, which meant that an AArch32 guest couldn't actually use the SCCD bit to disable counting in Secure state. Add all the currently defined bits; we don't implement all of them, but this makes them be reads-as-written, which is architecturally valid and matches how we currently handle most of the others in the mask. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220923123412.1214041-4-peter.maydell@linaro.org --- target/arm/cpu.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 33cdbc0143e..429ed42eece 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1334,11 +1334,15 @@ FIELD(CPTR_EL3, TTA, 20, 1) FIELD(CPTR_EL3, TAM, 30, 1) FIELD(CPTR_EL3, TCPAC, 31, 1) =20 +#define MDCR_MTPME (1U << 28) +#define MDCR_TDCC (1U << 27) #define MDCR_HLP (1U << 26) /* MDCR_EL2 */ #define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ #define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ #define MDCR_EPMAD (1U << 21) #define MDCR_EDAD (1U << 20) +#define MDCR_TTRF (1U << 19) +#define MDCR_STE (1U << 18) /* MDCR_EL3 */ #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ #define MDCR_SDD (1U << 16) @@ -1353,7 +1357,9 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) #define MDCR_HPMN (0x1fU) =20 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ -#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) +#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ + MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ + MDCR_STE | MDCR_SPME | MDCR_SPD) =20 #define CPSR_M (0x1fU) #define CPSR_T (1U << 5) --=20 2.25.1 From nobody Sun May 5 18:48:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664545436; cv=none; d=zohomail.com; s=zohoarc; b=YeUpwxytY4nM5ySBxkeHguL3vMsbvUPDc86l9nJfj2JdBSprM8DmFvrBaM+FucnQNp8NVaUzRZQ1FAmBRv7rKYgl3WulzSAz9HdCzRf9jr902JrHN/IoLym0auglQQFH4+SwmbqJlg+4xd//v9S1ETjZgUaBxE/7cQbpGDXLsLY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664545436; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zIYyLttiMxXsI1PS6r70HgPPTwCLHw1LURXuIZ6Iitc=; b=I/fY9+ILn4KoFQLnNWp8sWVNCmhOvxx5F9TN9Sdsg6oHl4640QayPpnIVU6GZ9fmvmVsaZw4WsuKBQsBuCe6vKPxnwX7jARpVSuCgGNStM2bgtsAJCWl6uLG3jVicaKofYKW9sV+BLlAM6yvtNHgr2ny8FBOdU87/We1885Yhp0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664545436648569.8364037187432; Fri, 30 Sep 2022 06:43:56 -0700 (PDT) Received: from localhost ([::1]:47462 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeGJ0-0000lX-K6 for importer@patchew.org; Fri, 30 Sep 2022 09:43:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51938) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeGAm-00008y-Hd for qemu-devel@nongnu.org; Fri, 30 Sep 2022 09:35:24 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:33422) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeGAh-0006UG-M7 for qemu-devel@nongnu.org; Fri, 30 Sep 2022 09:35:22 -0400 Received: by mail-wr1-x42b.google.com with SMTP id s14so6930326wro.0 for ; Fri, 30 Sep 2022 06:35:19 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id q12-20020adfcd8c000000b0021e4829d359sm1982551wrj.39.2022.09.30.06.35.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 06:35:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date; bh=zIYyLttiMxXsI1PS6r70HgPPTwCLHw1LURXuIZ6Iitc=; b=QigvXEk6SMIrIYF5Kf0axRlLVotO0sGhoMnpvDRTGaTBxuRppp2zCzR/Ly7F+Kmsek fP0kOMH2oVUyE4jHg8Jk/ZA9A95PsiYziJdopUoxehasqTFOT0JndtvXE8Awd7+AsnJN gXiWLlOd4G3ehVy66RFuHfOWU+Dy67EYwqkUpK9FqsfOS8fuSkCksV8ae/mSRXxPYapr Ll7FRaMfxWd1WJk74mC4GlaPsaYVVA/grN25NIO06RhdT8uNlHMaYPVdEZW9O5mFSnKC X7AZ92xyCLF6+1tCqaEDTNNQqR3WIEHHrMoHqY6VL68FhuVVwIFy98uV6MP7Gcmkk+VX E8Xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date; bh=zIYyLttiMxXsI1PS6r70HgPPTwCLHw1LURXuIZ6Iitc=; b=XEYTrk17HLs1ualD/O8xsENYUfJ0GSpk92MLTrqRlVzE/oswjwG4VHX1RGwXYV3TBb pU8D8ZPd0k9KGbGtL61AuSSfMzTvfKpuQU1H2cQvhNMIzs+jha8vYEhDaLLxcUNvaxkH 7Sqxxvg/7Mty048PvA0aejgl4hka3W2Obx5xm+oA4AH61PRbO04PvVNzvEuuFJkYpXpk y3HWge0dPCSYnNYoxGwMvy6iRBJLdUFuQIWZnnm2N2Tj9hYwQ5siHTRn8+18ntrVbJB4 ONMJb6iJ+hIWB+swbT+KuPiwXzBACov8kn3BFmVyq48PgK2iniFafJqrH4wTO3Cv99V/ u17g== X-Gm-Message-State: ACrzQf0RnO0b/yiI7upiNXZ9+zMq7yWEdIQ0PbtgzPnNsTxCNQp4ZYHK 4e0+2dpBWWVWa5KbuUl1WaHpLci5GhnxHA== X-Google-Smtp-Source: AMsMyM6ciPc5Bak5y3IrfplPWvgJkq7iVdhPSwz97PWGWGRX8q0Cjgk8C9aD9NerMjJs9svjkClfAQ== X-Received: by 2002:adf:f58b:0:b0:22e:3c4:cf83 with SMTP id f11-20020adff58b000000b0022e03c4cf83mr1362985wro.379.1664544917879; Fri, 30 Sep 2022 06:35:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/10] target/arm: Rearrange cpu64.c so all the CPU initfns are together Date: Fri, 30 Sep 2022 14:35:05 +0100 Message-Id: <20220930133511.2112734-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220930133511.2112734-1-peter.maydell@linaro.org> References: <20220930133511.2112734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664545438120100001 cpu64.c has ended up in a slightly odd order -- it starts with the initfns for most of the models-real-hardware CPUs; after that comes a bunch of support code for SVE, SME, pauth and LPA2 properties. Then come the initfns for the 'host' and 'max' CPU types, and then after that one more models-real-hardware CPU initfn, for a64fx. (This ordering is partly historical and partly required because a64fx needs the SVE properties.) Reorder the file into: * CPU property support functions * initfns for real hardware CPUs * initfns for host and max * class boilerplate Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 712 ++++++++++++++++++++++----------------------- 1 file changed, 356 insertions(+), 356 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e6314e86d20..85e0d1daf1c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -116,313 +116,6 @@ static void aarch64_a35_initfn(Object *obj) define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 -static void aarch64_a57_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a57"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A57; - cpu->midr =3D 0x411fd070; - cpu->revidr =3D 0x00000000; - cpu->reset_fpsid =3D 0x41034070; - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x12111111; - cpu->isar.mvfr2 =3D 0x00000043; - cpu->ctr =3D 0x8444c004; - cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_dfr0 =3D 0x03010066; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10101105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_isar6 =3D 0; - cpu->isar.id_aa64pfr0 =3D 0x00002222; - cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64isar0 =3D 0x00011120; - cpu->isar.id_aa64mmfr0 =3D 0x00001124; - cpu->isar.dbgdidr =3D 0x3516d000; - cpu->isar.dbgdevid =3D 0x01110f13; - cpu->isar.dbgdevid1 =3D 0x2; - cpu->isar.reset_pmcr_el0 =3D 0x41013000; - cpu->clidr =3D 0x0a200023; - cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ - cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ - cpu->dcz_blocksize =3D 4; /* 64 bytes */ - cpu->gic_num_lrs =3D 4; - cpu->gic_vpribits =3D 5; - cpu->gic_vprebits =3D 5; - cpu->gic_pribits =3D 5; - define_cortex_a72_a57_a53_cp_reginfo(cpu); -} - -static void aarch64_a53_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a53"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A53; - cpu->midr =3D 0x410fd034; - cpu->revidr =3D 0x00000000; - cpu->reset_fpsid =3D 0x41034070; - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x12111111; - cpu->isar.mvfr2 =3D 0x00000043; - cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ - cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_dfr0 =3D 0x03010066; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10101105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_isar6 =3D 0; - cpu->isar.id_aa64pfr0 =3D 0x00002222; - cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64isar0 =3D 0x00011120; - cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ - cpu->isar.dbgdidr =3D 0x3516d000; - cpu->isar.dbgdevid =3D 0x00110f13; - cpu->isar.dbgdevid1 =3D 0x1; - cpu->isar.reset_pmcr_el0 =3D 0x41033000; - cpu->clidr =3D 0x0a200023; - cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe00a; /* 32KB L1 icache */ - cpu->ccsidr[2] =3D 0x707fe07a; /* 1024KB L2 cache */ - cpu->dcz_blocksize =3D 4; /* 64 bytes */ - cpu->gic_num_lrs =3D 4; - cpu->gic_vpribits =3D 5; - cpu->gic_vprebits =3D 5; - cpu->gic_pribits =3D 5; - define_cortex_a72_a57_a53_cp_reginfo(cpu); -} - -static void aarch64_a72_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a72"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->midr =3D 0x410fd083; - cpu->revidr =3D 0x00000000; - cpu->reset_fpsid =3D 0x41034080; - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x12111111; - cpu->isar.mvfr2 =3D 0x00000043; - cpu->ctr =3D 0x8444c004; - cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_dfr0 =3D 0x03010066; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_aa64pfr0 =3D 0x00002222; - cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64isar0 =3D 0x00011120; - cpu->isar.id_aa64mmfr0 =3D 0x00001124; - cpu->isar.dbgdidr =3D 0x3516d000; - cpu->isar.dbgdevid =3D 0x01110f13; - cpu->isar.dbgdevid1 =3D 0x2; - cpu->isar.reset_pmcr_el0 =3D 0x41023000; - cpu->clidr =3D 0x0a200023; - cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ - cpu->ccsidr[2] =3D 0x707fe07a; /* 1MB L2 cache */ - cpu->dcz_blocksize =3D 4; /* 64 bytes */ - cpu->gic_num_lrs =3D 4; - cpu->gic_vpribits =3D 5; - cpu->gic_vprebits =3D 5; - cpu->gic_pribits =3D 5; - define_cortex_a72_a57_a53_cp_reginfo(cpu); -} - -static void aarch64_a76_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a76"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - - /* Ordered by B2.4 AArch64 registers by functional group */ - cpu->clidr =3D 0x82000023; - cpu->ctr =3D 0x8444C004; - cpu->dcz_blocksize =3D 4; - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; - cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; - cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; - cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x04010088; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x01011121; - cpu->isar.id_isar6 =3D 0x00000010; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_mmfr4 =3D 0x00021110; - cpu->isar.id_pfr0 =3D 0x10010131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ - cpu->isar.id_pfr2 =3D 0x00000011; - cpu->midr =3D 0x414fd0b1; /* r4p1 */ - cpu->revidr =3D 0; - - /* From B2.18 CCSIDR_EL1 */ - cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ - cpu->ccsidr[2] =3D 0x707fe03a; /* 512KB L2 cache */ - - /* From B2.93 SCTLR_EL3 */ - cpu->reset_sctlr =3D 0x30c50838; - - /* From B4.23 ICH_VTR_EL2 */ - cpu->gic_num_lrs =3D 4; - cpu->gic_vpribits =3D 5; - cpu->gic_vprebits =3D 5; - cpu->gic_pribits =3D 5; - - /* From B5.1 AdvSIMD AArch64 register summary */ - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x13211111; - cpu->isar.mvfr2 =3D 0x00000043; - - /* From D5.1 AArch64 PMU register summary */ - cpu->isar.reset_pmcr_el0 =3D 0x410b3000; -} - -static void aarch64_neoverse_n1_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,neoverse-n1"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - - /* Ordered by B2.4 AArch64 registers by functional group */ - cpu->clidr =3D 0x82000023; - cpu->ctr =3D 0x8444c004; - cpu->dcz_blocksize =3D 4; - cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; - cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; - cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; - cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000020ull; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x04010088; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x01011121; - cpu->isar.id_isar6 =3D 0x00000010; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_mmfr4 =3D 0x00021110; - cpu->isar.id_pfr0 =3D 0x10010131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ - cpu->isar.id_pfr2 =3D 0x00000011; - cpu->midr =3D 0x414fd0c1; /* r4p1 */ - cpu->revidr =3D 0; - - /* From B2.23 CCSIDR_EL1 */ - cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ - cpu->ccsidr[2] =3D 0x70ffe03a; /* 1MB L2 cache */ - - /* From B2.98 SCTLR_EL3 */ - cpu->reset_sctlr =3D 0x30c50838; - - /* From B4.23 ICH_VTR_EL2 */ - cpu->gic_num_lrs =3D 4; - cpu->gic_vpribits =3D 5; - cpu->gic_vprebits =3D 5; - cpu->gic_pribits =3D 5; - - /* From B5.1 AdvSIMD AArch64 register summary */ - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x13211111; - cpu->isar.mvfr2 =3D 0x00000043; - - /* From D5.1 AArch64 PMU register summary */ - cpu->isar.reset_pmcr_el0 =3D 0x410c3000; -} - void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* @@ -985,6 +678,362 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) cpu->isar.id_aa64mmfr0 =3D t; } =20 +static void aarch64_a57_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a57"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A57; + cpu->midr =3D 0x411fd070; + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034070; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x12111111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x8444c004; + cpu->reset_sctlr =3D 0x00c50838; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x03010066; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10101105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00011142; + cpu->isar.id_isar5 =3D 0x00011121; + cpu->isar.id_isar6 =3D 0; + cpu->isar.id_aa64pfr0 =3D 0x00002222; + cpu->isar.id_aa64dfr0 =3D 0x10305106; + cpu->isar.id_aa64isar0 =3D 0x00011120; + cpu->isar.id_aa64mmfr0 =3D 0x00001124; + cpu->isar.dbgdidr =3D 0x3516d000; + cpu->isar.dbgdevid =3D 0x01110f13; + cpu->isar.dbgdevid1 =3D 0x2; + cpu->isar.reset_pmcr_el0 =3D 0x41013000; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ + cpu->dcz_blocksize =3D 4; /* 64 bytes */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + define_cortex_a72_a57_a53_cp_reginfo(cpu); +} + +static void aarch64_a53_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a53"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A53; + cpu->midr =3D 0x410fd034; + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034070; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x12111111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ + cpu->reset_sctlr =3D 0x00c50838; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x03010066; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10101105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00011142; + cpu->isar.id_isar5 =3D 0x00011121; + cpu->isar.id_isar6 =3D 0; + cpu->isar.id_aa64pfr0 =3D 0x00002222; + cpu->isar.id_aa64dfr0 =3D 0x10305106; + cpu->isar.id_aa64isar0 =3D 0x00011120; + cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ + cpu->isar.dbgdidr =3D 0x3516d000; + cpu->isar.dbgdevid =3D 0x00110f13; + cpu->isar.dbgdevid1 =3D 0x1; + cpu->isar.reset_pmcr_el0 =3D 0x41033000; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe00a; /* 32KB L1 icache */ + cpu->ccsidr[2] =3D 0x707fe07a; /* 1024KB L2 cache */ + cpu->dcz_blocksize =3D 4; /* 64 bytes */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + define_cortex_a72_a57_a53_cp_reginfo(cpu); +} + +static void aarch64_a72_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a72"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x410fd083; + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034080; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x12111111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x8444c004; + cpu->reset_sctlr =3D 0x00c50838; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x03010066; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00011142; + cpu->isar.id_isar5 =3D 0x00011121; + cpu->isar.id_aa64pfr0 =3D 0x00002222; + cpu->isar.id_aa64dfr0 =3D 0x10305106; + cpu->isar.id_aa64isar0 =3D 0x00011120; + cpu->isar.id_aa64mmfr0 =3D 0x00001124; + cpu->isar.dbgdidr =3D 0x3516d000; + cpu->isar.dbgdevid =3D 0x01110f13; + cpu->isar.dbgdevid1 =3D 0x2; + cpu->isar.reset_pmcr_el0 =3D 0x41023000; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] =3D 0x707fe07a; /* 1MB L2 cache */ + cpu->dcz_blocksize =3D 4; /* 64 bytes */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + define_cortex_a72_a57_a53_cp_reginfo(cpu); +} + +static void aarch64_a76_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a76"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr =3D 0x82000023; + cpu->ctr =3D 0x8444C004; + cpu->dcz_blocksize =3D 4; + cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_dfr0 =3D 0x04010088; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x01011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_mmfr4 =3D 0x00021110; + cpu->isar.id_pfr0 =3D 0x10010131; + cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->midr =3D 0x414fd0b1; /* r4p1 */ + cpu->revidr =3D 0; + + /* From B2.18 CCSIDR_EL1 */ + cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x707fe03a; /* 512KB L2 cache */ + + /* From B2.93 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; + + /* From D5.1 AArch64 PMU register summary */ + cpu->isar.reset_pmcr_el0 =3D 0x410b3000; +} + +static void aarch64_a64fx_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,a64fx"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x461f0010; + cpu->revidr =3D 0x00000000; + cpu->ctr =3D 0x86668006; + cpu->reset_sctlr =3D 0x30000180; + cpu->isar.id_aa64pfr0 =3D 0x0000000101111111; /* No RAS Extensions */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000000; + cpu->isar.id_aa64dfr0 =3D 0x0000000010305408; + cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; + cpu->id_aa64afr0 =3D 0x0000000000000000; + cpu->id_aa64afr1 =3D 0x0000000000000000; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000001122; + cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; + cpu->isar.id_aa64isar0 =3D 0x0000000010211120; + cpu->isar.id_aa64isar1 =3D 0x0000000000010001; + cpu->isar.id_aa64zfr0 =3D 0x0000000000000000; + cpu->clidr =3D 0x0000000080000023; + cpu->ccsidr[0] =3D 0x7007e01c; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x2007e01c; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe07c; /* 8MB L2 cache */ + cpu->dcz_blocksize =3D 6; /* 256 bytes */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + + /* The A64FX supports only 128, 256 and 512 bit vector lengths */ + aarch64_add_sve_properties(obj); + cpu->sve_vq.supported =3D (1 << 0) /* 128bit */ + | (1 << 1) /* 256bit */ + | (1 << 3); /* 512bit */ + + cpu->isar.reset_pmcr_el0 =3D 0x46014040; + + /* TODO: Add A64FX specific HPC extension registers */ +} + +static void aarch64_neoverse_n1_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,neoverse-n1"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr =3D 0x82000023; + cpu->ctr =3D 0x8444c004; + cpu->dcz_blocksize =3D 4; + cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; + cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000020ull; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_dfr0 =3D 0x04010088; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x01011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_mmfr4 =3D 0x00021110; + cpu->isar.id_pfr0 =3D 0x10010131; + cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->midr =3D 0x414fd0c1; /* r4p1 */ + cpu->revidr =3D 0; + + /* From B2.23 CCSIDR_EL1 */ + cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe03a; /* 1MB L2 cache */ + + /* From B2.98 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; + + /* From D5.1 AArch64 PMU register summary */ + cpu->isar.reset_pmcr_el0 =3D 0x410c3000; +} + static void aarch64_host_initfn(Object *obj) { #if defined(CONFIG_KVM) @@ -1188,55 +1237,6 @@ static void aarch64_max_initfn(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); } =20 -static void aarch64_a64fx_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,a64fx"; - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->midr =3D 0x461f0010; - cpu->revidr =3D 0x00000000; - cpu->ctr =3D 0x86668006; - cpu->reset_sctlr =3D 0x30000180; - cpu->isar.id_aa64pfr0 =3D 0x0000000101111111; /* No RAS Extensions */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000000; - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408; - cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; - cpu->id_aa64afr0 =3D 0x0000000000000000; - cpu->id_aa64afr1 =3D 0x0000000000000000; - cpu->isar.id_aa64mmfr0 =3D 0x0000000000001122; - cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; - cpu->isar.id_aa64isar0 =3D 0x0000000010211120; - cpu->isar.id_aa64isar1 =3D 0x0000000000010001; - cpu->isar.id_aa64zfr0 =3D 0x0000000000000000; - cpu->clidr =3D 0x0000000080000023; - cpu->ccsidr[0] =3D 0x7007e01c; /* 64KB L1 dcache */ - cpu->ccsidr[1] =3D 0x2007e01c; /* 64KB L1 icache */ - cpu->ccsidr[2] =3D 0x70ffe07c; /* 8MB L2 cache */ - cpu->dcz_blocksize =3D 6; /* 256 bytes */ - cpu->gic_num_lrs =3D 4; - cpu->gic_vpribits =3D 5; - cpu->gic_vprebits =3D 5; - cpu->gic_pribits =3D 5; - - /* The A64FX supports only 128, 256 and 512 bit vector lengths */ - aarch64_add_sve_properties(obj); - cpu->sve_vq.supported =3D (1 << 0) /* 128bit */ - | (1 << 1) /* 256bit */ - | (1 << 3); /* 512bit */ - - cpu->isar.reset_pmcr_el0 =3D 0x46014040; - - /* TODO: Add A64FX specific HPC extension registers */ -} - static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a35", .initfn =3D aarch64_a35_initfn }, { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, --=20 2.25.1 From nobody Sun May 5 18:48:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id q12-20020adfcd8c000000b0021e4829d359sm1982551wrj.39.2022.09.30.06.35.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 06:35:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date; bh=N8vtTQ3zUp3DG5L43ho2EWTv6EglyCyi6wXcYwDvg7k=; b=HqTz1bK8LmMkNYcls62PQCWGNuVOdKneH1qEBlLcHcHzlcd95H+WlL4MFBmxL+g+qY VAtxCCDZ0bFt15969MJQ+9f+bFkNeSSl2e1x0DJO/bzFSX1MDSbmRtFjLRCd5FQ0Rsw0 G9Ks6iEBQnuXkH7x0+DOVOPSCZiQqyVMzpih6XDZ1ZwUt0PvrlR44vQysFszs+4mks4g eqOPf8IFaxn7cTQ1CIV3dfaKBkZ2Hu4G24p/S8e6MKL3E6Zz0+j5tHDIAnVh5k/N3eA1 OOrHYq0TdowooFYR/D30qWuk7VBJ37xYd47NNEENfYrs4eryynsBtCvSddQ7Edsr8LxZ uNdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date; bh=N8vtTQ3zUp3DG5L43ho2EWTv6EglyCyi6wXcYwDvg7k=; b=OS8ZZaZAfM3KQ5Ycp4ixUCgGKe5pIdXP2OXBnBlk/6WsuCPIC1JTHZE8P8m0D9trPs ICFPYLykC5y8KTeVN345NjIj/nfGHOz2nARJjohbfOp1adpjwJcNaOixsYCpSyVWeuSp sb+7EKs/rctLe7MvW88hVOGcS594XbTENOkdHowChXSE4a9KwRBsSiupKCP/j/lsXGo7 T2V0EJKFqKm/7WkFFRfjpLe8bFRpSDrtAtmMmBd8Oz5DkFlf+2M0sq7ZBMGiKARzkmaD Cvc1lPJVWKZ8A2PjeLGFpwyZSywr4J87ipXvD4W3bsaOYyJ0mn5/YPY8SvTay4Kkjipm fEJg== X-Gm-Message-State: ACrzQf23bgg62vJDtRyzxL15N02k2V4A8I1vL+Kj+XwZUftOV+d5Efsk ZX029hvQPSatoaSrDofOILNvJ6PLSLiQEg== X-Google-Smtp-Source: AMsMyM5HAU9Ob0GzFuWKQouZ5kHXpgs0oGH5tHKQmcTelmvXKYvTypsY1Fy+cgKZOxwVxMrRQlHi3w== X-Received: by 2002:a5d:5611:0:b0:228:e1d2:81d with SMTP id l17-20020a5d5611000000b00228e1d2081dmr5979429wrv.210.1664544918499; Fri, 30 Sep 2022 06:35:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/10] hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers Date: Fri, 30 Sep 2022 14:35:06 +0100 Message-Id: <20220930133511.2112734-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220930133511.2112734-1-peter.maydell@linaro.org> References: <20220930133511.2112734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664545520640100001 Content-Type: text/plain; charset="utf-8" From: Francisco Iglesias Connect ZynqMP's USB controllers. Signed-off-by: Francisco Iglesias Acked-by: Alistair Francis Message-id: 20220920081517.25401-1-frasse.iglesias@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-zynqmp.h | 3 +++ hw/arm/xlnx-zynqmp.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 85fd9f53daa..20bdf894aa0 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -42,6 +42,7 @@ #include "hw/misc/xlnx-zynqmp-apu-ctrl.h" #include "hw/misc/xlnx-zynqmp-crf.h" #include "hw/timer/cadence_ttc.h" +#include "hw/usb/hcd-dwc3.h" =20 #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) @@ -56,6 +57,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) #define XLNX_ZYNQMP_NUM_SPIS 2 #define XLNX_ZYNQMP_NUM_GDMA_CH 8 #define XLNX_ZYNQMP_NUM_ADMA_CH 8 +#define XLNX_ZYNQMP_NUM_USB 2 =20 #define XLNX_ZYNQMP_NUM_QSPI_BUS 2 #define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2 @@ -132,6 +134,7 @@ struct XlnxZynqMPState { XlnxZynqMPAPUCtrl apu_ctrl; XlnxZynqMPCRF crf; CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC]; + USBDWC3 usb[XLNX_ZYNQMP_NUM_USB]; =20 char *boot_cpu; ARMCPU *boot_cpu_ptr; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 383e177a001..335cfc417d7 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -143,6 +143,14 @@ static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH]= =3D { 77, 78, 79, 80, 81, 82, 83, 84 }; =20 +static const uint64_t usb_addr[XLNX_ZYNQMP_NUM_USB] =3D { + 0xFE200000, 0xFE300000 +}; + +static const int usb_intr[XLNX_ZYNQMP_NUM_USB] =3D { + 65, 70 +}; + typedef struct XlnxZynqMPGICRegion { int region_index; uint32_t address; @@ -428,6 +436,10 @@ static void xlnx_zynqmp_init(Object *obj) object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_D= MA); object_initialize_child(obj, "qspi-irq-orgate", &s->qspi_irq_orgate, TYPE_OR_IRQ); + + for (i =3D 0; i < XLNX_ZYNQMP_NUM_USB; i++) { + object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3); + } } =20 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) @@ -814,6 +826,30 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Erro= r **errp) object_property_add_alias(OBJECT(s), bus_name, OBJECT(&s->qspi), target_bus); } + + for (i =3D 0; i < XLNX_ZYNQMP_NUM_USB; i++) { + if (!object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma= ", + OBJECT(system_memory), errp)) { + return; + } + + qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "intrs", 4); + qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_addr[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0, + gic_spi[usb_intr[i]]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 1, + gic_spi[usb_intr[i] + 1]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 2, + gic_spi[usb_intr[i] + 2]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 3, + gic_spi[usb_intr[i] + 3]); + } } =20 static Property xlnx_zynqmp_props[] =3D { --=20 2.25.1 From nobody Sun May 5 18:48:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id q12-20020adfcd8c000000b0021e4829d359sm1982551wrj.39.2022.09.30.06.35.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 06:35:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date; bh=jr87nJMzzfca3E2PzEslVhn0XLR18CLB+4vwfpurK38=; b=cF5+Faz5d8rlFmIeCb+0Tx2JpPPnghhgNtpBS0AqSyGdkbWTW0XPyXRKyfagp6ulTQ Q2RWgLFjFTSMK9j6RTffS01Oy+DD6sCQfiLqouj5GzPLmpRRjtGJ6uQN5An1YpnOuUnc LwhoXF5IyMhytiCpIfpN5lmeBiTx7aar6Zvuyp9peysRtjwuTdobaIA4cgbzyhp280cJ HoKLoa2G029Dax0iqHILi6JDg/FVv2D1ijAYj41kCwPp7IItAk8kzEyrlTazwv1ywYbo 3yms5LpF7Tt53vJjELEmAZIoY1GPdcUCAM58YvKabfXrpTt5ySrphLvrKZNR2oyW+69X mmPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date; bh=jr87nJMzzfca3E2PzEslVhn0XLR18CLB+4vwfpurK38=; b=PcN28Y57H5DY38mfnWovinoOg+tdF4pD5VcCFfUfYbKSgMgVhY0rhZsS0AdJNHHEln JczPuPpbpNjPFalIalSgClVSDqJ8XnRMOEUkuVlQUTEGm2ietvxc9ZXvUYCdSbldNWHs Mgam/r9Rg1oBr9KyoEZeI1++eBardBPeYpRlb9UKSgAIykFs3L8IVaAM2gvwKXXOc1nH bbR2RR2cFLCVT1abvnf/pd3WAYS6obk8sxi3IeG1OzjcjmnKUX4Kplft+z0X9vrv2H4H MFL8s+3d9UuGuf4txVstuGnSXpXGDFZrn6avi+GWwlq1sIHIJuSAWx/e62NOUQvr+xCt WDdw== X-Gm-Message-State: ACrzQf36kKuXgIQ7+K6z3mBJ/6+9LXHBXHWfax1WHwwrjFPbldYDKNWL 1Q/Y/pDvyscx4CQfTxK4LiUoWCpbQLSFnA== X-Google-Smtp-Source: AMsMyM5pZ4vALLTiUEWNtKe+xb0PXB5Z9kpccZ26yU2bcQINi+ULlkgMsN/JAJwGAa4MZPO6NG3G9A== X-Received: by 2002:a5d:620b:0:b0:22c:9eb4:d6ed with SMTP id y11-20020a5d620b000000b0022c9eb4d6edmr6118525wru.530.1664544919170; Fri, 30 Sep 2022 06:35:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/10] hw/arm/virt: Fix devicetree warning about the root node Date: Fri, 30 Sep 2022 14:35:07 +0100 Message-Id: <20220930133511.2112734-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220930133511.2112734-1-peter.maydell@linaro.org> References: <20220930133511.2112734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664545365490100001 Content-Type: text/plain; charset="utf-8" From: Jean-Philippe Brucker The devicetree specification requires a 'model' property in the root node. Fix the corresponding dt-validate warning: /: 'model' is a required property From schema: dtschema/schemas/root-node.yaml Use the same name for model as for compatible. The specification recommends that 'compatible' follows the format 'manufacturer,model' and 'model' follows the format 'manufacturer,model-number'. Since our 'compatible' doesn't observe this, 'model' doesn't really need to either. Signed-off-by: Jean-Philippe Brucker Reviewed-by: Peter Maydell Reviewed-by: Eric Auger Message-id: 20220927100347.176606-2-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- hw/arm/virt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 0961e053e5d..f4ee71cda18 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -253,6 +253,7 @@ static void create_fdt(VirtMachineState *vms) qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); + qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt"); =20 /* /chosen must exist for load_dtb to fill in necessary properties lat= er */ qemu_fdt_add_subnode(fdt, "/chosen"); --=20 2.25.1 From nobody Sun May 5 18:48:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664545374; cv=none; d=zohomail.com; s=zohoarc; b=CVvNvwMZHQ9t44QVBxOAqUSzpLAxO79D6FjhYDTRReKLjNqe7t0pwB99HrrFSp1E67TH+st0ER2n0WdqSBNM3Hdju3HwSQFA+kTQN6Sn4TO/15LCeWrSbpeIK9TYsK4nAV6KgG+GwXn+igdmSv3Q1dhv/dG5BaDGxmr3gL/CSF0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664545374; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BI4FnRPteZ9TB6kG7Wp0H8/Z1m3ozSZQ6DVgXaBdi4w=; b=cg2ntNtaqMCPwxCI9c4Csv2XyRMvomlUEacKIfTKCy2d14aU3QfN+7OplK0VvI9sVCin/gY5IVDk3wYJy2bqwYAZ+pQg0rbjAvANzHlZfvKBt/RNoeMSY3OuE6LK9fmJGQxp7rlloFSBizGRjkbyaKo/6DU23o1szxf2sG/OEmg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166454537466888.9716297962982; Fri, 30 Sep 2022 06:42:54 -0700 (PDT) Received: from localhost ([::1]:55972 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeGI0-00063c-LI for importer@patchew.org; Fri, 30 Sep 2022 09:42:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51876) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeGAn-0000Cc-TH for qemu-devel@nongnu.org; Fri, 30 Sep 2022 09:35:25 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:34385) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeGAj-0006Uw-9d for qemu-devel@nongnu.org; Fri, 30 Sep 2022 09:35:25 -0400 Received: by mail-wm1-x32e.google.com with SMTP id n35-20020a05600c502300b003b4924c6868so4785116wmr.1 for ; Fri, 30 Sep 2022 06:35:20 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id q12-20020adfcd8c000000b0021e4829d359sm1982551wrj.39.2022.09.30.06.35.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 06:35:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date; bh=BI4FnRPteZ9TB6kG7Wp0H8/Z1m3ozSZQ6DVgXaBdi4w=; b=yfkFPbUjGcBfhILqmFn2yup3V/CxOqEnuk1CWnpm9IcGvUmXwXUKiBrFrcCchCU+go VxVC2693tIPWsdwsgnKo1mW++gU3yPQ6t0KSAjBcKKxuquA17NnBmiIMpBKBxNEHkaA+ VJg+tG2tIr7j7n00RHORVvZRu3Mi7wkntnl3WIfLJ+oqKx0A4GxNqRgUHT2loRGBjuWa faFlV0ASQRxH4lkYb9jGVrdXNrkMLB+BmFv5puT200RUK1vcqCTVb+vOaOzHiSMkEJxn UJey0U80wtXPaxwvtj6wlJnxgUpNgPjwFpKFo1EGxzZAoGgig1tkaI+YryyZQKbwrEvU wpXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date; bh=BI4FnRPteZ9TB6kG7Wp0H8/Z1m3ozSZQ6DVgXaBdi4w=; b=GqE9xnnLB7ja3nmpgk0yYrwqfCLrT78Uxp8ROeLaVdhtURfFgry1IqDtM4DRdn7Ncu +BdgG/Ccj62F/dhzRQlxXZLcglY/BPkTsYAvbEfjgx7E4A8z3xxkcKutZFSiTJT/wN3q PypC6Dgqs/n4uu9Lh7YMHnJrnWKrQ3G8xcr/7PGxUjBfseOC1IjVJRJMHbi+DhO6GaYS +woeBpQGyoejzIOt/QctUCN/DfH9Q9wKeA81aT/4IggfNoKO35YBCUtXgSpJLQsYnJyr DjrGlIzIvLw9+9hBp11bctmh/5oFJ2pMpOr11/h9qGZ+h9/qyqgE4+ofnSCghbWI/hVm 4cbQ== X-Gm-Message-State: ACrzQf09yTJ5hkATRfNkGHslS2J5cPBzq4xCymvyg7N4eMGRdXHczWSl 3GscWSeT9Dd3/WUIh4oFSkD5pXnwDod1EA== X-Google-Smtp-Source: AMsMyM60I/DLBYQNbJuYv2JgTHhFp0x3H+LMrwaHW92iXM7JGU6eFv+Y4fKJd6V2ur95slNpTKHCsQ== X-Received: by 2002:a05:600c:3c82:b0:3b5:60a6:c80f with SMTP id bg2-20020a05600c3c8200b003b560a6c80fmr5993003wmb.199.1664544919853; Fri, 30 Sep 2022 06:35:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/10] hw/arm/virt: Fix devicetree warning about the GIC node Date: Fri, 30 Sep 2022 14:35:08 +0100 Message-Id: <20220930133511.2112734-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220930133511.2112734-1-peter.maydell@linaro.org> References: <20220930133511.2112734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664545375638100001 Content-Type: text/plain; charset="utf-8" From: Jean-Philippe Brucker The GICv3 bindings requires a #msi-cells property for the ITS node. Fix the corresponding dt-validate warning: interrupt-controller@8000000: msi-controller@8080000: '#msi-cells' is a r= equired property From schema: linux/Documentation/devicetree/bindings/interrupt-controller= /arm,gic-v3.yaml Signed-off-by: Jean-Philippe Brucker Reviewed-by: Peter Maydell Reviewed-by: Eric Auger Message-id: 20220927100347.176606-3-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- hw/arm/virt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index f4ee71cda18..41b88dd1444 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -488,6 +488,7 @@ static void fdt_add_its_gic_node(VirtMachineState *vms) qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "arm,gic-v3-its"); qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, vms->memmap[VIRT_GIC_ITS].base, 2, vms->memmap[VIRT_GIC_ITS].size); --=20 2.25.1 From nobody Sun May 5 18:48:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664545692; cv=none; d=zohomail.com; s=zohoarc; b=kgzH0xDQbXedxrUVa8w30GUi7vSFKUYDpH5qcoqOxp0CW6NVgtgrJzRHf2k8k1dE0PoT4PggePNAzGoIfcs7Ms5PJ0E0vKHlQsZ6ffLhLNmRHvqFYZlyT3PBld1/xlncOru+QhUd7d4+8sTPQQfUZNyCOufAx8y/QemND9daxBE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664545692; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bEjgbbis8HDtfHwdnQyjjDEk0rJVjNDHCCAMGdaHTE8=; b=bYm0QLumED/LXp2kwGmwQPDLlJLBd8k3e5xFpF8e+aiSXhZNXNFb24cRpcVE2yvZwPmAGb5J9zrA6unUp1DkNpI+1IO/ZLmxFfeP63jCNJ6zX12TNItOOlgZ6BTkacrpwpOTFBBFYAzZPEtw33b0kxVGtPxk8+tVUg3ENEvADEY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664545692560249.7336988529314; Fri, 30 Sep 2022 06:48:12 -0700 (PDT) Received: from localhost ([::1]:52858 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeGN8-0006If-Fp for importer@patchew.org; Fri, 30 Sep 2022 09:48:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51878) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeGAo-0000E4-BZ for qemu-devel@nongnu.org; Fri, 30 Sep 2022 09:35:26 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:42859) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeGAj-0006V9-Ua for qemu-devel@nongnu.org; Fri, 30 Sep 2022 09:35:26 -0400 Received: by mail-wm1-x32f.google.com with SMTP id o20-20020a05600c4fd400b003b4a516c479so2263401wmq.1 for ; Fri, 30 Sep 2022 06:35:21 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id q12-20020adfcd8c000000b0021e4829d359sm1982551wrj.39.2022.09.30.06.35.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 06:35:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date; bh=bEjgbbis8HDtfHwdnQyjjDEk0rJVjNDHCCAMGdaHTE8=; b=pbWqfiwyqiwpF2/TnGMRK6K7nAUpBXcKchoqsTB2Y0mnyi+3QFjt3+m/q6pgBua+1S seMWYZ3WEW0ZZkSjy17ODk9ji2EREtvwgR9QX0PANl+Ekz/0mEVZMoxV9TK/5+2c1l4j I2obtGv37uUo3q9qo2eKt+Ea+6fKqGcWCyCRh9Dng9f2Y3CDLmjJx6D9HdEpP/2Y5YD+ qjA6SmKxRNki3nANACjD8XXxfvdE8MIIIbiuhf59wet4qvbfDIuZ4hsebjapK53DqNEm XIKH/0ZYho7VEgYlrluf8kvB3KWUjpkLQ6v0qQEmBTf3wsqiTpxij4f6Z2SLFIG83dyC AYsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date; bh=bEjgbbis8HDtfHwdnQyjjDEk0rJVjNDHCCAMGdaHTE8=; b=rDXarXTGwWrNsEhOYDOJUC0ZrhK3kPNknT3nMwK4umYliua7m3qFwG0PlP+GGj1MXY oFpzmabkJmDAbIpN3hqDUcTo8I9ELymvnJY0clbA7tvAEUlCoY0Frx5GhJH5PozwpdyH aq83+k4rXdRrVHBP2+Jfj2p3GYILD2ybxoTEV+VuM1oqHYAdHQagCRx0V1kBdmXN3Lko zoITb/eydxYf/Jm22V++KZLSox12jGfhIToc5o0cbSbRF6zK3JlLous4GjXM9l58fxAF cm8i/tgckRTVGYNUBMPIen2qWyFICjmvIEfjtSo8Xuae5fB5Cy91JZcxOiiaLRcYUjPL EUKQ== X-Gm-Message-State: ACrzQf2+oYuAEiizw5eRGXDEX2YDCS94+1bdcd+tIjtsIZsAFat1057F AI+IOcLO6Z2gS9/5V+GXmU7MLwSPUHeIlA== X-Google-Smtp-Source: AMsMyM59HDri5LXbEVthLjoV3l9itESVP2pmGUTcNJs6mMpcUmS33b+EziMALF6weGTcQglkAEPWFA== X-Received: by 2002:a7b:c392:0:b0:3b4:acef:3523 with SMTP id s18-20020a7bc392000000b003b4acef3523mr6027973wmj.37.1664544920490; Fri, 30 Sep 2022 06:35:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/10] hw/arm/virt: Use "msi-map" devicetree property for PCI Date: Fri, 30 Sep 2022 14:35:09 +0100 Message-Id: <20220930133511.2112734-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220930133511.2112734-1-peter.maydell@linaro.org> References: <20220930133511.2112734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664545694297100001 Content-Type: text/plain; charset="utf-8" From: Jean-Philippe Brucker The "msi-parent" property can be used on the PCI node when MSIs do not contain sideband data (device IDs) [1]. In QEMU, MSI transactions contain the requester ID, so the PCI node should use the "msi-map" property instead of "msi-parent". In our case the property describes an identity map between requester ID and sideband data. This fixes a warning when passing the DTB generated by QEMU to dtc, following a recent change to the GICv3 node: Warning (msi_parent_property): /pcie@10000000:msi-parent: property size (= 4) too small for cell size 1 [1] linux/Documentation/devicetree/bindings/pci/pci-msi.txt Signed-off-by: Jean-Philippe Brucker Reviewed-by: Peter Maydell Reviewed-by: Eric Auger Message-id: 20220927100347.176606-4-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- hw/arm/virt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 41b88dd1444..b67ba0f2a10 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1490,8 +1490,8 @@ static void create_pcie(VirtMachineState *vms) qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); =20 if (vms->msi_phandle) { - qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent", - vms->msi_phandle); + qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", + 0, vms->msi_phandle, 0, 0x10000); } =20 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", --=20 2.25.1 From nobody Sun May 5 18:48:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664545770; cv=none; d=zohomail.com; s=zohoarc; b=Aeh9TdISp32ViQiBW9td9pBfoCDakuYOGDYJJDfWW1IbrpGzQrYtung5V9w2wv2DL3nzTa8Xie5N6FUzIL+9mpQ2q7kG2LXjmOYrckQU79iIcduLW+LpBwgU/xNw/A9u7XqtKdts24zXwAuarUnDklTkEotYdoJQIks2EI93ecM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664545770; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=c+FYVmj0JEyf0MfnmUSKTWHaE3vpV75V3WufrP8RknE=; b=Nt+LfqPA/A0CUqKOr1qmbiJMITf1hIoc+Rlts+DKpxTYjvG2mX/XFSLclNQIYhBF5CjH2c7YOtZMZdmTyOSm0Qh6x1UStjCArRJv42x+HD9JJsMvFcmk6dtCuzmdDueI43UDB8qomZKPMZUZQLzI57k8rUJpHTPu9WDMu9g/bL8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664545770717157.8706684697138; Fri, 30 Sep 2022 06:49:30 -0700 (PDT) Received: from localhost ([::1]:50930 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeGOP-0008Te-Mw for importer@patchew.org; Fri, 30 Sep 2022 09:49:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51880) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeGAo-0000GK-TY for qemu-devel@nongnu.org; Fri, 30 Sep 2022 09:35:26 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:41556) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeGAk-0006Vw-G9 for qemu-devel@nongnu.org; Fri, 30 Sep 2022 09:35:26 -0400 Received: by mail-wr1-x42c.google.com with SMTP id r6so6900918wru.8 for ; Fri, 30 Sep 2022 06:35:22 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id q12-20020adfcd8c000000b0021e4829d359sm1982551wrj.39.2022.09.30.06.35.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 06:35:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date; bh=c+FYVmj0JEyf0MfnmUSKTWHaE3vpV75V3WufrP8RknE=; b=y8U8iaSI72QCuJuIz1uL/WKFmpJDBIxQZxGn/MTH6byzgzaRH2AbkeTJ5XgbfrwFOE vzNB7yu5FZrnhiv1GlgAiqaNoVusgPdWyuc0koprKr5vcMPrqlmUqnPSuk9PlHg4Ndjn hHWYA9Ca6Rmy93WU8/Lm8TZ7NMjO2KA+7dgDgt3o8Whw1CjV9l8P/XLmLQ2HyHSENYq5 6ofq4u9rCmWgG5tVnnnFQmNTYiNvG1WXfA4FTsU0qqWPixS/ulCzUAuGqFpIen/h0aqV 5gUA7cFGdhSlBS3M6rLswYyuAJcFatpph+FjjcjYdkS57X+z58lQEhRAeadUlXN2+Ubj uWJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date; bh=c+FYVmj0JEyf0MfnmUSKTWHaE3vpV75V3WufrP8RknE=; b=uELLOSafRW+YsR+aK+jHGkdYN5spXvC/eRULR1OAStE5UgIWTnLBMwh3O9X0vV/iHb 4e/Adj7dhHVW0E9jl3li829XH96x/uNWJ/0tnliUrYpQxlVOKMRCYD/t8WpYdqFeW2Zm +Xu4ZXcJdD4cj0OLFlBqyDMjYOKPPllQ4vJsEr+T5imNLHBYJuKymO64FisXYHf8/fLd X+SxDVjsjUjaPMjNwB57yWh8xwa9mbUnYq+EcMUG1cRc5jiPwzMkHFF08CqYXjWEyTZh UfqhCGx5sTml2PTC/qsYveiTXwwBTumZ3PhdNnyg2S8/QeKd/mA9uLyQVCNKhPzUqpx4 oQlw== X-Gm-Message-State: ACrzQf2navrjfhDBfNT1zZzxKzFCsD/uXp/SUTlr/G/V1zBRQron2Ran R/Auu3By4VnWFa4XxYuKU0tjw5JznlHt6g== X-Google-Smtp-Source: AMsMyM56qTEggK89qCCyuf8YkYyndoYp3HZwRL/3DUoeXpCKigQWmLrY3vU4AS714rFpG++M9k4eTQ== X-Received: by 2002:a05:6000:69d:b0:22a:fa56:86b9 with SMTP id bo29-20020a056000069d00b0022afa5686b9mr5944894wrb.193.1664544921074; Fri, 30 Sep 2022 06:35:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/10] hw/arm/virt: Fix devicetree warning about the SMMU node Date: Fri, 30 Sep 2022 14:35:10 +0100 Message-Id: <20220930133511.2112734-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220930133511.2112734-1-peter.maydell@linaro.org> References: <20220930133511.2112734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664545772829100001 Content-Type: text/plain; charset="utf-8" From: Jean-Philippe Brucker The SMMUv3 node isn't expected to have clock properties (unlike the SMMUv2). Fix the corresponding dt-validate warning: smmuv3@9050000: 'clock-names', 'clocks' do not match any of the regexes: = 'pinctrl-[0-9]+' From schema: linux/Documentation/devicetree/bindings/iommu/arm,smmu-v3.ya= ml Signed-off-by: Jean-Philippe Brucker Reviewed-by: Peter Maydell [PMM: tweaked commit message as suggested by Eric] Reviewed-by: Eric Auger Message-id: 20220927100347.176606-7-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- hw/arm/virt.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b67ba0f2a10..cda9defe8f0 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1361,8 +1361,6 @@ static void create_smmu(const VirtMachineState *vms, qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, sizeof(irq_names)); =20 - qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle); - qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk"); qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); =20 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); --=20 2.25.1 From nobody Sun May 5 18:48:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1664545965; cv=none; d=zohomail.com; s=zohoarc; b=LswaBrd/DV88JLp2QiBIJPV8YsSxb1mISPjt2NyJf6ukaXzKVQ6ov8vO4U7LzlPxs2bY2WZ89xKbNX9oboOAVI7EMJJ2dXg/9YBw8m/W8dFPOJ7fcjmOrM1PGIeuHzuyCqZ7lnkx4EvDeijlXRN5j0OOOc1NIYJbJxL7l16iucs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1664545965; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NhqIrzhBpcl574rWKiDGts78z115WmBNREKOX97NyXE=; b=My5c3XGrizgwsXPTrtMWYgPGV3nP7ZNwgNFYNoeFWdUPGVy915rAnnS4vEoFJeZYbU1xGABMKMREr4kmroto8ZgnPqI7TKb1VenEKh454V0wCsOsPIrYkqapsz7UFtAZ9Rluf77AbmKXyONkmWH2VrT0EieyX+3fJQUHD1L61O4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664545965782180.12678390477208; Fri, 30 Sep 2022 06:52:45 -0700 (PDT) Received: from localhost ([::1]:32978 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeGRY-0003gm-Mm for importer@patchew.org; Fri, 30 Sep 2022 09:52:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51882) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeGAp-0000HS-6q for qemu-devel@nongnu.org; Fri, 30 Sep 2022 09:35:27 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:36676) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeGAl-0006WR-Sa for qemu-devel@nongnu.org; Fri, 30 Sep 2022 09:35:26 -0400 Received: by mail-wr1-x42f.google.com with SMTP id j7so1512148wrr.3 for ; Fri, 30 Sep 2022 06:35:22 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id q12-20020adfcd8c000000b0021e4829d359sm1982551wrj.39.2022.09.30.06.35.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 06:35:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date; bh=NhqIrzhBpcl574rWKiDGts78z115WmBNREKOX97NyXE=; b=xYIhCA1lDFNWkEalEw6EWIGnRJMJNdPQFwGza0I9HnF+tEJs/UClkxTrE4kbWXljx8 o17nqeKFXFhXUAGas13qsh9n8OFQTLSNpCRJvQJPOxPqLq+DLwr34NCCuSoyD/qQ4Q0H AlBFhrS4G25BrNTxy3y6bkOmtCkZPpQl7ljtc3gBKhaR6xr1q/UQBUv0s8WRr7JnG0sN EMjM7MLomQRAevsKlfYQ1uWrM2bFwG/91vVN9SNh0zfLffI81rcVBCzYnRw2c5JhFytx E6bR97eAWR7D+RlUn+k/gOrfPBoLlQFxHAUvt1YqDQG0sxVQaJvUGApL/5DmndLZth5t JBWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date; bh=NhqIrzhBpcl574rWKiDGts78z115WmBNREKOX97NyXE=; b=DSt/CfoRc6Vadciz6ooYUIre/kit6paq324Nq5Wmdh1/qzd5kh2y0Vy11laynxfdXu PZBARsxgLnCJh0NkzTS2qxltRl/6fJAMTSZ3yUqSxkAOtsNyl2/Iam6vSGeG5fUC9RS7 G0SrlscIOpWPPtgX49+9719UXeA2/x8vF6bKTDLT+uYEHPByyDkIyvLcCWEad7BJqt+p d015SkVOVKIsYqjeCzXcEsqUGaWHPTHVME+i/IvPp4M16proTLCBEWblOhdf929OdxvV e7jOr0h9Stx36Jgdh3v8Cyk/VkkFXdlNP1DWLtE+u5srTu2ImS3upkFbynOk3MkJCZnq 5lTw== X-Gm-Message-State: ACrzQf2/iW3w16H2KpFypFukFBAKlQDuT/GULeSaEGdWDPCeGxqDhoQc gXtGZGj1H4JY/2uz0mXvYSIakvRqfzRhVQ== X-Google-Smtp-Source: AMsMyM7Oh5IYSfARUm4xRrfwvr8VuQ5EqEAW6dltwOjPcnLSIVNY7kOgChvTAD+S00D/evozETJvFg== X-Received: by 2002:a05:6000:1881:b0:22b:262f:ee2a with SMTP id a1-20020a056000188100b0022b262fee2amr5811470wri.432.1664544921851; Fri, 30 Sep 2022 06:35:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/10] target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP Date: Fri, 30 Sep 2022 14:35:11 +0100 Message-Id: <20220930133511.2112734-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220930133511.2112734-1-peter.maydell@linaro.org> References: <20220930133511.2112734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1664545966645100001 Content-Type: text/plain; charset="utf-8" From: Jerome Forissier SP_EL1 must be kept when EL3 is present but EL2 is not. Therefore mark it with ARM_CP_EL3_NO_EL2_KEEP. Cc: qemu-stable@nongnu.org Fixes: 696ba3771894 ("target/arm: Handle cpreg registration for missing EL") Signed-off-by: Jerome Forissier Reviewed-by: Richard Henderson Message-id: 20220927120058.670901-1-jerome.forissier@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 24c592ffef8..db3b1ea72da 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5088,7 +5088,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, sp_el[0]) }, { .name =3D "SP_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_ALIAS, + .access =3D PL2_RW, .type =3D ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_KEEP, .fieldoffset =3D offsetof(CPUARMState, sp_el[1]) }, { .name =3D "SPSel", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 2, .opc2 =3D 0, --=20 2.25.1