From nobody Tue May 7 01:18:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664509057362575.6442162677304; Thu, 29 Sep 2022 20:37:37 -0700 (PDT) Received: from localhost ([::1]:50502 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oe6qE-0006qZ-Q5 for importer@patchew.org; Thu, 29 Sep 2022 23:37:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41866) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oe6mc-00043Q-Qm for qemu-devel@nongnu.org; Thu, 29 Sep 2022 23:33:51 -0400 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:43257) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oe6ma-0001cH-CE for qemu-devel@nongnu.org; Thu, 29 Sep 2022 23:33:50 -0400 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 30 Sep 2022 11:33:41 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Sep 2022 19:53:35 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Sep 2022 20:33:41 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Mdwn10ktnz1Rwrq for ; Thu, 29 Sep 2022 20:33:41 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id x5E-0Z08uG9s for ; Thu, 29 Sep 2022 20:33:39 -0700 (PDT) Received: from fedora.wdc.com (unknown [10.225.165.55]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Mdwmw58dPz1RvLy; Thu, 29 Sep 2022 20:33:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1664508828; x=1696044828; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E8bRBXJM2CYdcA4IjvhSjuvCa2JM//rykvWTyVLaQe4=; b=IIDhVBM0NRacyUqRum1CZ9XXcdmaI8sR1S1WZwx4+Kx/rleq+9+xY4aY ctG5UWMX81ctYLtyIhzHxWUV8kXzEzQ330WH0//tKi8SsUhny4wcnHFFT 9lGjPD0ykeOei9gIoak14848Vr5yIE89fO90W8+6yiT9HB2tEEPl2CDQ9 ZqxvcoLvW3DZF5jdCTrDWLSdi2VGK/v9t13EpkIVn5CNTCsxDbVoY43jn VX11S/0MHS5iSeDf9ww5O8odeEGVVKWn0Qg4JwUAjcPIklhielG0/DoMp 7nprY3CX5yhzdTDUaYedXxUUkLPrcaQYX5CoHN39/nY2rjBG5IXDtSQPP A==; X-IronPort-AV: E=Sophos;i="5.93,357,1654531200"; d="scan'208";a="212638615" IronPort-SDR: 6KH8wdQV7PNsV6ZpHAZlPwawnTGglpIAM8MIbuc9XfAsiOP/xhkc41UYUGJyu4tXHgg5UowA/q p0aSO68KtDrLW5ExlKds+nSI4i7AWBHhYx+LyHDjGgeh+2RdkU9WIk/CHV/cvqKaTWMrWxnpFS s51ePe5QyntR0kgSMAp6sTf1Uvz215KbK3px2JEm97OUUtUglLzJHsOvFWsBAj+Koc9ELb2JmK SYGlpyC9XwwN3y3RIECsZN9Ag6zVDF0wP+K9t8ZAJlhxoYCIBU4eF5frjCM8OYkR5VgLw68Wed zbU9RveUp8pP63tMeFemBFFr IronPort-SDR: 0wE7aFJ55OrQaKH6p5/vgeBZBZ5Fj9KX9s5cSUZrliB70O46h2GJKIjDB8uZnsE0a0Sb26WASt 3jbl2JsAmiy455XWIusE4pAWkOZQPRHpzR6PkaWMe8/fpnYcrT/xcWgDqMupmz7gN621BW62ZB H2c6YL0qyB9A97gQKbFnRVv94L84dOAZtWIN9F+2UnChJhdksD73CbUkwuLgwGpSWp6mZyuRmK uwJDlIVqfZc5+I1cYTBMycOn1MUsp9YoUNS5VxzUxvwYgbTSxtfYindylRe3kwsEpFf4smVjT8 0PA= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1664508819; x=1667100820; bh=E8bRBXJM2CYdcA4Ijv hSjuvCa2JM//rykvWTyVLaQe4=; b=PoN+Lk8T3kCiZbZ7Jx2diqhUCnDpd+fc2y +kpzzOkzsS+MZHB/XZMO44Jxy2u9seMFSWqr2LfTydOPETKHTtiRQTvxemqrwOal Bx0/xJXhE+XoLGTltB+K5BN/Fk76oCDuztkT1XNdY5qHRxsIuVBNwxNcA/a8kpgq f0+m3KzuuLmDtgsDUa5sMjmUh5378jx2JSLBp5I5s7Ni93V6EYX39cWvaWI+P4QZ hLipSkcpw9d1BMiyqUFrb6cJi809bDuJg0kshCD/SkOtJJmjWmRBvmhX3Rr3h8+e 44H9esY2K7DNWYhr+KUAWZ1MwoeA0d6jJnSv4AcvJ3vafywSGSOw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Wilfred Mallawa To: Alistair.Francis@wdc.com, qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org, Wilfred Mallawa , Alistair Francis , Andrew Jones Subject: [PATCH v5 1/2] hw/ssi: ibex_spi: fixup coverity issue Date: Fri, 30 Sep 2022 13:32:42 +1000 Message-Id: <20220930033241.206581-2-wilfred.mallawa@opensource.wdc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220930033241.206581-1-wilfred.mallawa@opensource.wdc.com> References: <20220930033241.206581-1-wilfred.mallawa@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=265e2c498=wilfred.mallawa@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1664509059302100001 Content-Type: text/plain; charset="utf-8" From: Wilfred Mallawa This patch addresses the coverity issues specified in [1], as suggested, `FIELD_DP32()`/`FIELD_EX32()` macros have been implemented to clean up the code. [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg887713.html Fixes: Coverity CID 1488107 Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones --- hw/ssi/ibex_spi_host.c | 132 +++++++++++++++++++++-------------------- 1 file changed, 68 insertions(+), 64 deletions(-) diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c index 94d7da9cc2..d145a4cdbd 100644 --- a/hw/ssi/ibex_spi_host.c +++ b/hw/ssi/ibex_spi_host.c @@ -108,18 +108,22 @@ static inline uint8_t div4_round_up(uint8_t dividend) =20 static void ibex_spi_rxfifo_reset(IbexSPIHostState *s) { + uint32_t data =3D s->regs[IBEX_SPI_HOST_STATUS]; /* Empty the RX FIFO and assert RXEMPTY */ fifo8_reset(&s->rx_fifo); - s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_RXFULL_MASK; - s->regs[IBEX_SPI_HOST_STATUS] |=3D R_STATUS_RXEMPTY_MASK; + data =3D FIELD_DP32(data, STATUS, RXFULL, 0); + data =3D FIELD_DP32(data, STATUS, RXEMPTY, 1); + s->regs[IBEX_SPI_HOST_STATUS] =3D data; } =20 static void ibex_spi_txfifo_reset(IbexSPIHostState *s) { + uint32_t data =3D s->regs[IBEX_SPI_HOST_STATUS]; /* Empty the TX FIFO and assert TXEMPTY */ fifo8_reset(&s->tx_fifo); - s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_TXFULL_MASK; - s->regs[IBEX_SPI_HOST_STATUS] |=3D R_STATUS_TXEMPTY_MASK; + data =3D FIELD_DP32(data, STATUS, TXFULL, 0); + data =3D FIELD_DP32(data, STATUS, TXEMPTY, 1); + s->regs[IBEX_SPI_HOST_STATUS] =3D data; } =20 static void ibex_spi_host_reset(DeviceState *dev) @@ -162,37 +166,38 @@ static void ibex_spi_host_reset(DeviceState *dev) */ static void ibex_spi_host_irq(IbexSPIHostState *s) { - bool error_en =3D s->regs[IBEX_SPI_HOST_INTR_ENABLE] - & R_INTR_ENABLE_ERROR_MASK; - bool event_en =3D s->regs[IBEX_SPI_HOST_INTR_ENABLE] - & R_INTR_ENABLE_SPI_EVENT_MASK; - bool err_pending =3D s->regs[IBEX_SPI_HOST_INTR_STATE] - & R_INTR_STATE_ERROR_MASK; - bool status_pending =3D s->regs[IBEX_SPI_HOST_INTR_STATE] - & R_INTR_STATE_SPI_EVENT_MASK; + uint32_t intr_test_reg =3D s->regs[IBEX_SPI_HOST_INTR_TEST]; + uint32_t intr_en_reg =3D s->regs[IBEX_SPI_HOST_INTR_ENABLE]; + uint32_t intr_state_reg =3D s->regs[IBEX_SPI_HOST_INTR_STATE]; + + uint32_t err_en_reg =3D s->regs[IBEX_SPI_HOST_ERROR_ENABLE]; + uint32_t event_en_reg =3D s->regs[IBEX_SPI_HOST_EVENT_ENABLE]; + uint32_t err_status_reg =3D s->regs[IBEX_SPI_HOST_ERROR_STATUS]; + uint32_t status_reg =3D s->regs[IBEX_SPI_HOST_STATUS]; + + + bool error_en =3D FIELD_EX32(intr_en_reg, INTR_ENABLE, ERROR); + bool event_en =3D FIELD_EX32(intr_en_reg, INTR_ENABLE, SPI_EVENT); + bool err_pending =3D FIELD_EX32(intr_state_reg, INTR_STATE, ERROR); + bool status_pending =3D FIELD_EX32(intr_state_reg, INTR_STATE, SPI_EVE= NT); + int err_irq =3D 0, event_irq =3D 0; =20 /* Error IRQ enabled and Error IRQ Cleared */ if (error_en && !err_pending) { /* Event enabled, Interrupt Test Error */ - if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_ERROR_MASK) { + if (FIELD_EX32(intr_test_reg, INTR_TEST, ERROR)) { err_irq =3D 1; - } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE] - & R_ERROR_ENABLE_CMDBUSY_MASK) && - s->regs[IBEX_SPI_HOST_ERROR_STATUS] - & R_ERROR_STATUS_CMDBUSY_MASK) { + } else if (FIELD_EX32(err_en_reg, ERROR_ENABLE, CMDBUSY) && + FIELD_EX32(err_status_reg, ERROR_STATUS, CMDBUSY)) { /* Wrote to COMMAND when not READY */ err_irq =3D 1; - } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE] - & R_ERROR_ENABLE_CMDINVAL_MASK) && - s->regs[IBEX_SPI_HOST_ERROR_STATUS] - & R_ERROR_STATUS_CMDINVAL_MASK) { + } else if (FIELD_EX32(err_en_reg, ERROR_ENABLE, CMDINVAL) && + FIELD_EX32(err_status_reg, ERROR_STATUS, CMDINVAL)) { /* Invalid command segment */ err_irq =3D 1; - } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE] - & R_ERROR_ENABLE_CSIDINVAL_MASK) && - s->regs[IBEX_SPI_HOST_ERROR_STATUS] - & R_ERROR_STATUS_CSIDINVAL_MASK) { + } else if (FIELD_EX32(err_en_reg, ERROR_ENABLE, CSIDINVAL) && + FIELD_EX32(err_status_reg, ERROR_STATUS, CSIDINVAL)) { /* Invalid value for CSID */ err_irq =3D 1; } @@ -204,22 +209,19 @@ static void ibex_spi_host_irq(IbexSPIHostState *s) =20 /* Event IRQ Enabled and Event IRQ Cleared */ if (event_en && !status_pending) { - if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_SPI_EVENT_MASK)= { + if (FIELD_EX32(intr_test_reg, INTR_STATE, SPI_EVENT)) { /* Event enabled, Interrupt Test Event */ event_irq =3D 1; - } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE] - & R_EVENT_ENABLE_READY_MASK) && - (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_READY_MASK))= { + } else if (FIELD_EX32(event_en_reg, EVENT_ENABLE, READY) && + FIELD_EX32(status_reg, STATUS, READY)) { /* SPI Host ready for next command */ event_irq =3D 1; - } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE] - & R_EVENT_ENABLE_TXEMPTY_MASK) && - (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_TXEMPTY_MASK= )) { + } else if (FIELD_EX32(event_en_reg, EVENT_ENABLE, TXEMPTY) && + FIELD_EX32(status_reg, STATUS, TXEMPTY)) { /* SPI TXEMPTY, TXFIFO drained */ event_irq =3D 1; - } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE] - & R_EVENT_ENABLE_RXFULL_MASK) && - (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_RXFULL_MASK)= ) { + } else if (FIELD_EX32(event_en_reg, EVENT_ENABLE, RXFULL) && + FIELD_EX32(status_reg, STATUS, RXFULL)) { /* SPI RXFULL, RXFIFO full */ event_irq =3D 1; } @@ -232,10 +234,11 @@ static void ibex_spi_host_irq(IbexSPIHostState *s) =20 static void ibex_spi_host_transfer(IbexSPIHostState *s) { - uint32_t rx, tx; + uint32_t rx, tx, data; /* Get num of one byte transfers */ - uint8_t segment_len =3D ((s->regs[IBEX_SPI_HOST_COMMAND] & R_COMMAND_L= EN_MASK) - >> R_COMMAND_LEN_SHIFT); + uint8_t segment_len =3D FIELD_EX32(s->regs[IBEX_SPI_HOST_COMMAND], + COMMAND, LEN); + while (segment_len > 0) { if (fifo8_is_empty(&s->tx_fifo)) { /* Assert Stall */ @@ -262,22 +265,21 @@ static void ibex_spi_host_transfer(IbexSPIHostState *= s) --segment_len; } =20 + data =3D s->regs[IBEX_SPI_HOST_STATUS]; /* Assert Ready */ - s->regs[IBEX_SPI_HOST_STATUS] |=3D R_STATUS_READY_MASK; + data =3D FIELD_DP32(data, STATUS, READY, 1); /* Set RXQD */ - s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_RXQD_MASK; - s->regs[IBEX_SPI_HOST_STATUS] |=3D (R_STATUS_RXQD_MASK - & div4_round_up(segment_len)); + data =3D FIELD_DP32(data, STATUS, RXQD, div4_round_up(segment_len)); /* Set TXQD */ - s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_TXQD_MASK; - s->regs[IBEX_SPI_HOST_STATUS] |=3D (fifo8_num_used(&s->tx_fifo) / 4) - & R_STATUS_TXQD_MASK; + data =3D FIELD_DP32(data, STATUS, TXQD, fifo8_num_used(&s->tx_fifo) / = 4); /* Clear TXFULL */ - s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_TXFULL_MASK; - /* Assert TXEMPTY and drop remaining bytes that exceed segment_len */ - ibex_spi_txfifo_reset(s); + data =3D FIELD_DP32(data, STATUS, TXFULL, 0); /* Reset RXEMPTY */ - s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_RXEMPTY_MASK; + data =3D FIELD_DP32(data, STATUS, RXEMPTY, 0); + /* Update register status */ + s->regs[IBEX_SPI_HOST_STATUS] =3D data; + /* Drop remaining bytes that exceed segment_len */ + ibex_spi_txfifo_reset(s); =20 ibex_spi_host_irq(s); } @@ -340,7 +342,7 @@ static void ibex_spi_host_write(void *opaque, hwaddr ad= dr, { IbexSPIHostState *s =3D opaque; uint32_t val32 =3D val64; - uint32_t shift_mask =3D 0xff; + uint32_t shift_mask =3D 0xff, status =3D 0; uint8_t txqd_len; =20 trace_ibex_spi_host_write(addr, size, val64); @@ -397,22 +399,24 @@ static void ibex_spi_host_write(void *opaque, hwaddr = addr, s->regs[addr] =3D val32; =20 /* STALL, IP not enabled */ - if (!(s->regs[IBEX_SPI_HOST_CONTROL] & R_CONTROL_SPIEN_MASK)) { + if (!(FIELD_EX32(s->regs[IBEX_SPI_HOST_CONTROL], + CONTROL, SPIEN))) { return; } =20 /* SPI not ready, IRQ Error */ - if (!(s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_READY_MASK)) { + if (!(FIELD_EX32(s->regs[IBEX_SPI_HOST_STATUS], + STATUS, READY))) { s->regs[IBEX_SPI_HOST_ERROR_STATUS] |=3D R_ERROR_STATUS_CMDBUS= Y_MASK; ibex_spi_host_irq(s); return; } + /* Assert Not Ready */ s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_READY_MASK; =20 - if (((val32 & R_COMMAND_DIRECTION_MASK) >> R_COMMAND_DIRECTION_SHI= FT) - !=3D BIDIRECTIONAL_TRANSFER) { - qemu_log_mask(LOG_UNIMP, + if (FIELD_EX32(val32, COMMAND, DIRECTION) !=3D BIDIRECTIONAL_TRANS= FER) { + qemu_log_mask(LOG_UNIMP, "%s: Rx Only/Tx Only are not supported\n", __fun= c__); } =20 @@ -452,8 +456,8 @@ static void ibex_spi_host_write(void *opaque, hwaddr ad= dr, return; } /* Byte ordering is set by the IP */ - if ((s->regs[IBEX_SPI_HOST_STATUS] & - R_STATUS_BYTEORDER_MASK) =3D=3D 0) { + status =3D s->regs[IBEX_SPI_HOST_STATUS]; + if (FIELD_EX32(status, STATUS, BYTEORDER) =3D=3D 0) { /* LE: LSB transmitted first (default for ibex processor) = */ shift_mask =3D 0xff << (i * 8); } else { @@ -464,18 +468,18 @@ static void ibex_spi_host_write(void *opaque, hwaddr = addr, =20 fifo8_push(&s->tx_fifo, (val32 & shift_mask) >> (i * 8)); } - + status =3D s->regs[IBEX_SPI_HOST_STATUS]; /* Reset TXEMPTY */ - s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_TXEMPTY_MASK; + status =3D FIELD_DP32(status, STATUS, TXEMPTY, 0); /* Update TXQD */ - txqd_len =3D (s->regs[IBEX_SPI_HOST_STATUS] & - R_STATUS_TXQD_MASK) >> R_STATUS_TXQD_SHIFT; + txqd_len =3D FIELD_EX32(status, STATUS, TXQD); /* Partial bytes (size < 4) are padded, in words. */ txqd_len +=3D 1; - s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_TXQD_MASK; - s->regs[IBEX_SPI_HOST_STATUS] |=3D txqd_len; + status =3D FIELD_DP32(status, STATUS, TXQD, txqd_len); /* Assert Ready */ - s->regs[IBEX_SPI_HOST_STATUS] |=3D R_STATUS_READY_MASK; + status =3D FIELD_DP32(status, STATUS, READY, 1); + /* Update register status */ + s->regs[IBEX_SPI_HOST_STATUS] =3D status; break; case IBEX_SPI_HOST_ERROR_ENABLE: s->regs[addr] =3D val32; --=20 2.37.3 From nobody Tue May 7 01:18:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1664509128217361.14056459899655; Thu, 29 Sep 2022 20:38:48 -0700 (PDT) Received: from localhost ([::1]:60948 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oe6rP-0008NG-55 for importer@patchew.org; Thu, 29 Sep 2022 23:38:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41872) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oe6mh-00044h-BJ for qemu-devel@nongnu.org; Thu, 29 Sep 2022 23:33:55 -0400 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:4397) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oe6mf-0001d5-Mu for qemu-devel@nongnu.org; Thu, 29 Sep 2022 23:33:55 -0400 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 30 Sep 2022 11:33:51 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Sep 2022 19:53:45 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Sep 2022 20:33:52 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4MdwnC3tTkz1RwqL for ; Thu, 29 Sep 2022 20:33:51 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id fHfEfkNI9Lyv for ; Thu, 29 Sep 2022 20:33:51 -0700 (PDT) Received: from fedora.wdc.com (unknown [10.225.165.55]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Mdwn84HxWz1RvLy; Thu, 29 Sep 2022 20:33:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1664508833; x=1696044833; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dk0sp7z3kDPth8yYGVQNx7ek/N0UtJjbzNJ1wI8KZlc=; b=PT1Uecj+gS0KfO3MIBuT0G9ZGRjFOdOK+jMCN9d48lGNCS/bQMI7ijyy YcMmt2ylDRwGWBifcdALEOrBZc8HBsSWPVYV6aan86+/7UYhq1Ktuhy6K BK6mZDzbnIj72CYK/37DQfJK71cKNFHOl2wuaao4R3xaGBUFzuJTDrWiM T82va2UhxOXmJQW6ZAc759ipAx3l7eqiV8If7OCmXNXUZ2MfCLPyNlt4B lYiyXiO2Vh4umRW8znU/seer5nZbsnHRGPMofZ6iD6sJnRy5CCBysWm86 e5+l0jJHNXSqYqX/uVUsWYkjUsfK1aZC9wlnYRYmG65rY2qqVko/1q+ne A==; X-IronPort-AV: E=Sophos;i="5.93,357,1654531200"; d="scan'208";a="210991994" IronPort-SDR: qa0DcZSxXvoOXCe8VEGtOtKT34AVUYPj/yZEEOTPDVwHqq2vi8MIkaYzdRvO2lSBYt1ZBGZ04f iwbJSARkWNzCx4r6iZdpfxS4Yyo2vG2z2mcNfFSWgMZcFyXlWWA2d5WSJrOUuZ/XxRFa3/cAEE 9UvwnvdfIoOa6GOlt+JAjyqrpJUeT+tS5iI6QifvZpcAYgUhdiQX8cugF4+8PjGmGECLClgtiC w6s5COWWCSLIz3ihFsGicypwUVgz1c1J72qxMQaMx8Nw+lfLNwTVXCDJWi0C54Z97ewl10LI8q CZ6Y+YU16PTxfZLHfXA+PSiI IronPort-SDR: WvmTJj5aI9NLa2YETdQLl+qmyiOjTeKz4oTnsdjjiN0m+7raOvAPqom0FV4BVZYDMKD4IqN2uA g9Ka2Qv7PrCU1EXuDtmzmlMis5BMBymGYFG0xrn3LWUsymP6l348NGi1Px/GrGI5bVv3Whv7wm gG5mtuOaxmfBlVYoNYxNzhb6Ew2e32Avf33ivOU01BJZWjeM3HcGhJFLnVRJ84YRU6wpMcesNi 0M5VTmfwZb8osI5FJsCBgkr6mvFLHbQMVt4YNJue9qbNbnAsaVsBjOAmRiCSqeaaK2gySLBjjK 0iQ= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1664508831; x=1667100832; bh=dk0sp7z3kDPth8yYGV QNx7ek/N0UtJjbzNJ1wI8KZlc=; b=IgFZS+/4a1d4kVQu0fIcZEybm+p+1TvbEv OGhI+4Nxo0n9BLCU9y0q9DYGn4GlWZm4x8C9xY5sOTytPks/p7tI5eCbDs7yOynf YhlrpfU+fCXGDnZwa00xXlHDJa1evZLhpCSJJCGvV3dfYrQ9uTElIc9W+UvrM1gQ B904UHWl2sAJCXKWkUpAN52D1Pn80mtUWzwReUKILrwaIj8IHJB4e9BmNsVUV75D X8hY5BprFGUOsSyZGGd8bYkmpEjEGwjda1X8QUL0x4UaF6Dz5EkpgNu17j5sgAQc OfDe0ShQSxBKjJteIbNIhORQpYRzeWU+hih2zgGG8QWkp8z579tQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Wilfred Mallawa To: Alistair.Francis@wdc.com, qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org, Wilfred Mallawa , Alistair Francis Subject: [PATCH v5 2/2] hw/ssi: ibex_spi: fixup/add rw1c functionality Date: Fri, 30 Sep 2022 13:32:44 +1000 Message-Id: <20220930033241.206581-3-wilfred.mallawa@opensource.wdc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220930033241.206581-1-wilfred.mallawa@opensource.wdc.com> References: <20220930033241.206581-1-wilfred.mallawa@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=265e2c498=wilfred.mallawa@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1664509129784100001 Content-Type: text/plain; charset="utf-8" From: Wilfred Mallawa This patch adds the `rw1c` functionality to the respective registers. The status fields are cleared when the respective field is set. Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis --- hw/ssi/ibex_spi_host.c | 36 +++++++++++++++++++++++++++++++--- include/hw/ssi/ibex_spi_host.h | 4 ++-- 2 files changed, 35 insertions(+), 5 deletions(-) diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c index d145a4cdbd..57df462e3c 100644 --- a/hw/ssi/ibex_spi_host.c +++ b/hw/ssi/ibex_spi_host.c @@ -342,7 +342,7 @@ static void ibex_spi_host_write(void *opaque, hwaddr ad= dr, { IbexSPIHostState *s =3D opaque; uint32_t val32 =3D val64; - uint32_t shift_mask =3D 0xff, status =3D 0; + uint32_t shift_mask =3D 0xff, status =3D 0, data =3D 0; uint8_t txqd_len; =20 trace_ibex_spi_host_write(addr, size, val64); @@ -352,7 +352,17 @@ static void ibex_spi_host_write(void *opaque, hwaddr a= ddr, =20 switch (addr) { /* Skipping any R/O registers */ - case IBEX_SPI_HOST_INTR_STATE...IBEX_SPI_HOST_INTR_ENABLE: + case IBEX_SPI_HOST_INTR_STATE: + /* rw1c status register */ + if (FIELD_EX32(val32, INTR_STATE, ERROR)) { + data =3D FIELD_DP32(data, INTR_STATE, ERROR, 0); + } + if (FIELD_EX32(val32, INTR_STATE, SPI_EVENT)) { + data =3D FIELD_DP32(data, INTR_STATE, SPI_EVENT, 0); + } + s->regs[addr] =3D data; + break; + case IBEX_SPI_HOST_INTR_ENABLE: s->regs[addr] =3D val32; break; case IBEX_SPI_HOST_INTR_TEST: @@ -495,7 +505,27 @@ static void ibex_spi_host_write(void *opaque, hwaddr a= ddr, * When an error occurs, the corresponding bit must be cleared * here before issuing any further commands */ - s->regs[addr] =3D val32; + status =3D s->regs[addr]; + /* rw1c status register */ + if (FIELD_EX32(val32, ERROR_STATUS, CMDBUSY)) { + status =3D FIELD_DP32(status, ERROR_STATUS, CMDBUSY, 0); + } + if (FIELD_EX32(val32, ERROR_STATUS, OVERFLOW)) { + status =3D FIELD_DP32(status, ERROR_STATUS, OVERFLOW, 0); + } + if (FIELD_EX32(val32, ERROR_STATUS, UNDERFLOW)) { + status =3D FIELD_DP32(status, ERROR_STATUS, UNDERFLOW, 0); + } + if (FIELD_EX32(val32, ERROR_STATUS, CMDINVAL)) { + status =3D FIELD_DP32(status, ERROR_STATUS, CMDINVAL, 0); + } + if (FIELD_EX32(val32, ERROR_STATUS, CSIDINVAL)) { + status =3D FIELD_DP32(status, ERROR_STATUS, CSIDINVAL, 0); + } + if (FIELD_EX32(val32, ERROR_STATUS, ACCESSINVAL)) { + status =3D FIELD_DP32(status, ERROR_STATUS, ACCESSINVAL, 0); + } + s->regs[addr] =3D status; break; case IBEX_SPI_HOST_EVENT_ENABLE: /* Controls which classes of SPI events raise an interrupt. */ diff --git a/include/hw/ssi/ibex_spi_host.h b/include/hw/ssi/ibex_spi_host.h index 3fedcb6805..1f6d077766 100644 --- a/include/hw/ssi/ibex_spi_host.h +++ b/include/hw/ssi/ibex_spi_host.h @@ -40,7 +40,7 @@ OBJECT_CHECK(IbexSPIHostState, (obj), TYPE_IBEX_SPI_HOST) =20 /* SPI Registers */ -#define IBEX_SPI_HOST_INTR_STATE (0x00 / 4) /* rw */ +#define IBEX_SPI_HOST_INTR_STATE (0x00 / 4) /* rw1c */ #define IBEX_SPI_HOST_INTR_ENABLE (0x04 / 4) /* rw */ #define IBEX_SPI_HOST_INTR_TEST (0x08 / 4) /* wo */ #define IBEX_SPI_HOST_ALERT_TEST (0x0c / 4) /* wo */ @@ -54,7 +54,7 @@ #define IBEX_SPI_HOST_TXDATA (0x28 / 4) =20 #define IBEX_SPI_HOST_ERROR_ENABLE (0x2c / 4) /* rw */ -#define IBEX_SPI_HOST_ERROR_STATUS (0x30 / 4) /* rw */ +#define IBEX_SPI_HOST_ERROR_STATUS (0x30 / 4) /* rw1c */ #define IBEX_SPI_HOST_EVENT_ENABLE (0x34 / 4) /* rw */ =20 /* FIFO Len in Bytes */ --=20 2.37.3