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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=262caef14=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1664262376420100001 Content-Type: text/plain; charset="utf-8" From: Frank Chang tinfo.info: One bit for each possible type enumerated in tdata1. If the bit is set, then that type is supported by the currently selected trigger. Signed-off-by: Frank Chang Reviewed-by: Bin Meng Signed-off-by: Bin Meng Reviewed-by: LIU Zhiwei Message-Id: <20220909134215.1843865-6-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/debug.h | 2 ++ target/riscv/csr.c | 8 ++++++++ target/riscv/debug.c | 10 +++++++--- 4 files changed, 18 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b762807e4e..d8f5f0abed 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -319,6 +319,7 @@ #define CSR_TDATA1 0x7a1 #define CSR_TDATA2 0x7a2 #define CSR_TDATA3 0x7a3 +#define CSR_TINFO 0x7a4 =20 /* Debug Mode Registers */ #define CSR_DCSR 0x7b0 diff --git a/target/riscv/debug.h b/target/riscv/debug.h index 76146f373a..9f69c64591 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -95,6 +95,8 @@ void tselect_csr_write(CPURISCVState *env, target_ulong v= al); target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index); void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val= ); =20 +target_ulong tinfo_csr_read(CPURISCVState *env); + void riscv_cpu_debug_excp_handler(CPUState *cs); bool riscv_cpu_debug_check_breakpoint(CPUState *cs); bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 2c84c29bf0..5c9a7ee287 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3094,6 +3094,13 @@ static RISCVException write_tdata(CPURISCVState *env= , int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_tinfo(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D tinfo_csr_read(env); + return RISCV_EXCP_NONE; +} + /* * Functions to access Pointer Masking feature registers * We have to check if current priv lvl could modify @@ -3898,6 +3905,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_TDATA1] =3D { "tdata1", debug, read_tdata, write_tdata }, [CSR_TDATA2] =3D { "tdata2", debug, read_tdata, write_tdata }, [CSR_TDATA3] =3D { "tdata3", debug, read_tdata, write_tdata }, + [CSR_TINFO] =3D { "tinfo", debug, read_tinfo, write_ignore }, =20 /* User Pointer Masking */ [CSR_UMTE] =3D { "umte", pointer_masking, read_umte, write_u= mte }, diff --git a/target/riscv/debug.c b/target/riscv/debug.c index d6666164cd..7d546ace42 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -37,9 +37,7 @@ * - tdata1 * - tdata2 * - tdata3 - * - * We don't support writable 'type' field in the tdata1 register, so there= is - * no need to implement the "tinfo" CSR. + * - tinfo * * The following triggers are implemented: * @@ -372,6 +370,12 @@ void tdata_csr_write(CPURISCVState *env, int tdata_ind= ex, target_ulong val) } } =20 +target_ulong tinfo_csr_read(CPURISCVState *env) +{ + /* assume all triggers support the same types of triggers */ + return BIT(TRIGGER_TYPE_AD_MATCH); +} + void riscv_cpu_debug_excp_handler(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); --=20 2.37.3