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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1664260295; x=1666852296; bh=E5lScHhR2kpKa0jugk oNB8Y7Nx/X7x7dhg4eM1YwfwM=; b=kIBktA3FtGJuqNo8vgpx9Vid6pD3XqduCg ixCrktrR3bhnM/VNab5qOdkMK1VLCp/5iceJ5dgvTBSTHEUy9KeLqKC+2o5lxyDk PzjHbIIEckaNVeBq2M17eOfR3LSnFVvImCqlhHfBq950qbIyQh0Ml97IBM2PDJkv LetYhjGD7GyfVq065118+f+F/NH2RxVmcutJ38H3z6e14BADzvrJbOTDI/VF4Kyc ZeCMdGTpHMdy469/aXSvB3jtWFeT1gy5sQdEKtkJ4SY2dCc+ez2ZvjzpvAqgdagN fkn9YDep9PoM4nXVGULDlLKvgOwcgTnVfN3zxRxJIcWSB4U4f9yw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Frank Chang , Bin Meng , LIU Zhiwei , Alistair Francis Subject: [PULL v2 15/22] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs Date: Tue, 27 Sep 2022 16:30:57 +1000 Message-Id: <20220927063104.2846825-16-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220927063104.2846825-1-alistair.francis@opensource.wdc.com> References: <20220927063104.2846825-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=262caef14=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1664262627661100001 Content-Type: text/plain; charset="utf-8" From: Frank Chang Replace type2_trigger_t with the real tdata1, tdata2, and tdata3 CSRs, which allows us to support more types of triggers in the future. Signed-off-by: Frank Chang Reviewed-by: Bin Meng Signed-off-by: Bin Meng Reviewed-by: LIU Zhiwei Message-Id: <20220909134215.1843865-4-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 6 ++- target/riscv/debug.h | 7 --- target/riscv/debug.c | 103 +++++++++++++++-------------------------- target/riscv/machine.c | 20 ++------ 4 files changed, 48 insertions(+), 88 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 73bcad3c9b..b131fa8c8e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -324,7 +324,11 @@ struct CPUArchState { =20 /* trigger module */ target_ulong trigger_cur; - type2_trigger_t type2_trig[RV_MAX_TRIGGERS]; + target_ulong tdata1[RV_MAX_TRIGGERS]; + target_ulong tdata2[RV_MAX_TRIGGERS]; + target_ulong tdata3[RV_MAX_TRIGGERS]; + struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; + struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; =20 /* machine specific rdtime callback */ uint64_t (*rdtime_fn)(void *); diff --git a/target/riscv/debug.h b/target/riscv/debug.h index c422553c27..76146f373a 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -44,13 +44,6 @@ typedef enum { TRIGGER_TYPE_NUM } trigger_type_t; =20 -typedef struct { - target_ulong mcontrol; - target_ulong maddress; - struct CPUBreakpoint *bp; - struct CPUWatchpoint *wp; -} type2_trigger_t; - /* tdata1 field masks */ =20 #define RV32_TYPE(t) ((uint32_t)(t) << 28) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 45aae87ec3..06feef7d67 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -91,8 +91,7 @@ static inline target_ulong extract_trigger_type(CPURISCVS= tate *env, static inline target_ulong get_trigger_type(CPURISCVState *env, target_ulong trigger_index) { - target_ulong tdata1 =3D env->type2_trig[trigger_index].mcontrol; - return extract_trigger_type(env, tdata1); + return extract_trigger_type(env, env->tdata1[trigger_index]); } =20 static inline target_ulong build_tdata1(CPURISCVState *env, @@ -188,6 +187,8 @@ static inline void warn_always_zero_bit(target_ulong va= l, target_ulong mask, } } =20 +/* type 2 trigger */ + static uint32_t type2_breakpoint_size(CPURISCVState *env, target_ulong ctr= l) { uint32_t size, sizelo, sizehi =3D 0; @@ -247,8 +248,8 @@ static target_ulong type2_mcontrol_validate(CPURISCVSta= te *env, =20 static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index) { - target_ulong ctrl =3D env->type2_trig[index].mcontrol; - target_ulong addr =3D env->type2_trig[index].maddress; + target_ulong ctrl =3D env->tdata1[index]; + target_ulong addr =3D env->tdata2[index]; bool enabled =3D type2_breakpoint_enabled(ctrl); CPUState *cs =3D env_cpu(env); int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; @@ -259,7 +260,7 @@ static void type2_breakpoint_insert(CPURISCVState *env,= target_ulong index) } =20 if (ctrl & TYPE2_EXEC) { - cpu_breakpoint_insert(cs, addr, flags, &env->type2_trig[index].bp); + cpu_breakpoint_insert(cs, addr, flags, &env->cpu_breakpoint[index]= ); } =20 if (ctrl & TYPE2_LOAD) { @@ -273,10 +274,10 @@ static void type2_breakpoint_insert(CPURISCVState *en= v, target_ulong index) size =3D type2_breakpoint_size(env, ctrl); if (size !=3D 0) { cpu_watchpoint_insert(cs, addr, size, flags, - &env->type2_trig[index].wp); + &env->cpu_watchpoint[index]); } else { cpu_watchpoint_insert(cs, addr, 8, flags, - &env->type2_trig[index].wp); + &env->cpu_watchpoint[index]); } } } @@ -285,36 +286,17 @@ static void type2_breakpoint_remove(CPURISCVState *en= v, target_ulong index) { CPUState *cs =3D env_cpu(env); =20 - if (env->type2_trig[index].bp) { - cpu_breakpoint_remove_by_ref(cs, env->type2_trig[index].bp); - env->type2_trig[index].bp =3D NULL; + if (env->cpu_breakpoint[index]) { + cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]); + env->cpu_breakpoint[index] =3D NULL; } =20 - if (env->type2_trig[index].wp) { - cpu_watchpoint_remove_by_ref(cs, env->type2_trig[index].wp); - env->type2_trig[index].wp =3D NULL; + if (env->cpu_watchpoint[index]) { + cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]); + env->cpu_watchpoint[index] =3D NULL; } } =20 -static target_ulong type2_reg_read(CPURISCVState *env, - target_ulong index, int tdata_index) -{ - target_ulong tdata; - - switch (tdata_index) { - case TDATA1: - tdata =3D env->type2_trig[index].mcontrol; - break; - case TDATA2: - tdata =3D env->type2_trig[index].maddress; - break; - default: - g_assert_not_reached(); - } - - return tdata; -} - static void type2_reg_write(CPURISCVState *env, target_ulong index, int tdata_index, target_ulong val) { @@ -323,19 +305,23 @@ static void type2_reg_write(CPURISCVState *env, targe= t_ulong index, switch (tdata_index) { case TDATA1: new_val =3D type2_mcontrol_validate(env, val); - if (new_val !=3D env->type2_trig[index].mcontrol) { - env->type2_trig[index].mcontrol =3D new_val; + if (new_val !=3D env->tdata1[index]) { + env->tdata1[index] =3D new_val; type2_breakpoint_remove(env, index); type2_breakpoint_insert(env, index); } break; case TDATA2: - if (val !=3D env->type2_trig[index].maddress) { - env->type2_trig[index].maddress =3D val; + if (val !=3D env->tdata2[index]) { + env->tdata2[index] =3D val; type2_breakpoint_remove(env, index); type2_breakpoint_insert(env, index); } break; + case TDATA3: + qemu_log_mask(LOG_UNIMP, + "tdata3 is not supported for type 2 trigger\n"); + break; default: g_assert_not_reached(); } @@ -345,30 +331,16 @@ static void type2_reg_write(CPURISCVState *env, targe= t_ulong index, =20 target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index) { - int trigger_type =3D get_trigger_type(env, env->trigger_cur); - - switch (trigger_type) { - case TRIGGER_TYPE_AD_MATCH: - return type2_reg_read(env, env->trigger_cur, tdata_index); - break; - case TRIGGER_TYPE_INST_CNT: - case TRIGGER_TYPE_INT: - case TRIGGER_TYPE_EXCP: - case TRIGGER_TYPE_AD_MATCH6: - case TRIGGER_TYPE_EXT_SRC: - qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n", - trigger_type); - break; - case TRIGGER_TYPE_NO_EXIST: - case TRIGGER_TYPE_UNAVAIL: - qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n", - trigger_type); - break; + switch (tdata_index) { + case TDATA1: + return env->tdata1[env->trigger_cur]; + case TDATA2: + return env->tdata2[env->trigger_cur]; + case TDATA3: + return env->tdata3[env->trigger_cur]; default: g_assert_not_reached(); } - - return 0; } =20 void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val) @@ -436,8 +408,8 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) =20 switch (trigger_type) { case TRIGGER_TYPE_AD_MATCH: - ctrl =3D env->type2_trig[i].mcontrol; - pc =3D env->type2_trig[i].maddress; + ctrl =3D env->tdata1[i]; + pc =3D env->tdata2[i]; =20 if ((ctrl & TYPE2_EXEC) && (bp->pc =3D=3D pc)) { /* check U/S/M bit against current privilege level */ @@ -471,8 +443,8 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPU= Watchpoint *wp) =20 switch (trigger_type) { case TRIGGER_TYPE_AD_MATCH: - ctrl =3D env->type2_trig[i].mcontrol; - addr =3D env->type2_trig[i].maddress; + ctrl =3D env->tdata1[i]; + addr =3D env->tdata2[i]; flags =3D 0; =20 if (ctrl & TYPE2_LOAD) { @@ -518,9 +490,10 @@ void riscv_trigger_init(CPURISCVState *env) * chain =3D 0 (unimplemented, always 0) * match =3D 0 (always 0, when any compare value equals tdata2) */ - env->type2_trig[i].mcontrol =3D tdata1; - env->type2_trig[i].maddress =3D 0; - env->type2_trig[i].bp =3D NULL; - env->type2_trig[i].wp =3D NULL; + env->tdata1[i] =3D tdata1; + env->tdata2[i] =3D 0; + env->tdata3[i] =3D 0; + env->cpu_breakpoint[i] =3D NULL; + env->cpu_watchpoint[i] =3D NULL; } } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index a23cff4424..c2a94a82b3 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -229,26 +229,16 @@ static bool debug_needed(void *opaque) return riscv_feature(env, RISCV_FEATURE_DEBUG); } =20 -static const VMStateDescription vmstate_debug_type2 =3D { - .name =3D "cpu/debug/type2", - .version_id =3D 1, - .minimum_version_id =3D 1, - .fields =3D (VMStateField[]) { - VMSTATE_UINTTL(mcontrol, type2_trigger_t), - VMSTATE_UINTTL(maddress, type2_trigger_t), - VMSTATE_END_OF_LIST() - } -}; - static const VMStateDescription vmstate_debug =3D { .name =3D "cpu/debug", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .needed =3D debug_needed, .fields =3D (VMStateField[]) { VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), - VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, RV_MAX_TRIGGERS, - 0, vmstate_debug_type2, type2_trigger_t), + VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS), + VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS), + VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS), VMSTATE_END_OF_LIST() } }; --=20 2.37.3