From nobody Mon Feb 9 10:11:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1663937854; cv=none; d=zohomail.com; s=zohoarc; b=JWFnBUD63jMB22k2pOWOSJjVVwMmHTDFXrCnUADddf2R48msM0kgvRVBfezcJ0SXvmi5ay1d2ip2bKRT+6yR3smOnjAqTQbh06CsgHZbHEzbnsMaiTtkke6XT5iYbGH/SLt7QOoA7mr0uvtnbpr9K3k09U6WQKgEl8mabNxDKlU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1663937854; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9bX1U7fCCWCM+RDd/fzqQav05Uxy455tmNKKT/hfAUQ=; b=n1W8I+57IyboeOYOjhmFJkim3AZrXrqKLr7Q/sLhARZtHvmF9HMH4Y5YyGohgHd0MafI04Om/KFwbJ5c2knCccb3AbMQV38uSeGs8PxrrqPuAHwIQk19ZH5e1k0iHrd5aSGd8pf0xCpWaFTTQMGRxLaJDM4cKNjB2JVHy/y9fYE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663937854025432.1078173630834; Fri, 23 Sep 2022 05:57:34 -0700 (PDT) Received: from localhost ([::1]:56026 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1obiFF-0004DX-7d for importer@patchew.org; Fri, 23 Sep 2022 08:57:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33562) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1obhsq-0006QI-4Y for qemu-devel@nongnu.org; Fri, 23 Sep 2022 08:34:24 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:43898) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1obhsn-0007VT-AM for qemu-devel@nongnu.org; Fri, 23 Sep 2022 08:34:19 -0400 Received: by mail-wr1-x42e.google.com with SMTP id t7so20173896wrm.10 for ; Fri, 23 Sep 2022 05:34:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n43-20020a05600c502b00b003b486027c8asm2504555wmr.20.2022.09.23.05.34.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Sep 2022 05:34:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=9bX1U7fCCWCM+RDd/fzqQav05Uxy455tmNKKT/hfAUQ=; b=rWEgCWnUdgamXStSyyzCw0RZPP/GBIXNbLE2tfhMqzjfhtI7L1aC0NQ/7Xj4kV/zbI dFugSZKhhBYQZyPeaOzMR+tcnQu0J7JnQ6QM+cijrBCjHIYURZPdtr6vYxqQ7aV7NZT4 cSNi75VYK2qZ7B61anc2O32zV1ijU/WPVI/luNzP8KwXwIXvzdAwewZIxedLFuQ6ggJG 44lr5gjkvGCfGmPsoImiAc6jmbrZ5gr8+wE6+5dzjkgreMLrP90+Z3gIyi6hvfqk/3mo a9np/YKtVH6dqdYRRCbJhaCG+Gevj4AYKQ1YG4o/8xBU5oE446lNBJjl3+g6GN5PrLB0 xo8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=9bX1U7fCCWCM+RDd/fzqQav05Uxy455tmNKKT/hfAUQ=; b=VzHbJqA57fAgSNVWgVopRRwYR4jXe9iCp2hypMw1lzqbnI2zEUmlECDjkOnxDFQ76U a1yk4bh9rSQUaxuY45Mw899L+NfWvx0+1yGNIIkN336n13fSqqT3QTm6eESjJYfoXhBm 4EiO1spSnK1URBNXgvcyRUgaBkMx45AJxRiJcGiD4rNhlvQo7Gd10R/2R23NX7n/i8Ss RwfY+Ho4Sa1cXy3GhQEo3xOoF9ALTVhZpqIwlhGjhALMJF/af0cy+mKfMp4+3xpiAh3H IPhUqDWyPzixWw2uuMTvYs8gwWdNBGZ6QuvevGrNfyRQiWkt/g5h+FRf1gkkJixJYvbo JHHQ== X-Gm-Message-State: ACrzQf0I+LxFpT/K8IwGxTyL6tRqdn+dcHhnAqVTLI7k/Pvd/LqfQFMY /tNHyKQc/c5Fqurb5xFngqo2HI9nEjbb4g== X-Google-Smtp-Source: AMsMyM52L4HLXMAxKJOLO4QxENItqfX7QEeWqusWCB4cxbKsmjhyZVHykt5AbazPwlKdfNdbeCG0Yg== X-Received: by 2002:adf:fa81:0:b0:224:f260:2523 with SMTP id h1-20020adffa81000000b00224f2602523mr5057563wrr.26.1663936455843; Fri, 23 Sep 2022 05:34:15 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Thomas Huth Subject: [PATCH 1/3] target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO Date: Fri, 23 Sep 2022 13:34:10 +0100 Message-Id: <20220923123412.1214041-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220923123412.1214041-1-peter.maydell@linaro.org> References: <20220923123412.1214041-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1663937854553100001 Content-Type: text/plain; charset="utf-8" In commit 01765386a888 we made some system register write functions call pmu_op_start()/pmu_op_finish(). This means that they now touch timers, so for icount to work these registers must have the ARM_CP_IO flag set. This fixes a bug where when icount is enabled a guest that touches MDCR_EL3, MDCR_EL2, PMCNTENSET_EL0 or PMCNTENCLR_EL0 would cause QEMU to print an error message and exit, for example: [ 2.495971] TCP: Hash tables configured (established 1024 bind 1024) [ 2.496213] UDP hash table entries: 256 (order: 1, 8192 bytes) [ 2.496386] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes) [ 2.496917] NET: Registered protocol family 1 qemu-system-aarch64: Bad icount read Reported-by: Thomas Huth Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1a57d2e1d60..7c7ba328d6d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1927,12 +1927,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. */ { .name =3D "PMCNTENSET", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 1, - .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, + .access =3D PL0_RW, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), .writefn =3D pmcntenset_write, .accessfn =3D pmreg_access, .raw_writefn =3D raw_write }, - { .name =3D "PMCNTENSET_EL0", .state =3D ARM_CP_STATE_AA64, + { .name =3D "PMCNTENSET_EL0", .state =3D ARM_CP_STATE_AA64, .type =3D = ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 1, .access =3D PL0_RW, .accessfn =3D pmreg_access, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue= =3D 0, @@ -1942,11 +1942,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), .accessfn =3D pmreg_access, .writefn =3D pmcntenclr_write, - .type =3D ARM_CP_ALIAS }, + .type =3D ARM_CP_ALIAS | ARM_CP_IO }, { .name =3D "PMCNTENCLR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 2, .access =3D PL0_RW, .accessfn =3D pmreg_access, - .type =3D ARM_CP_ALIAS, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .writefn =3D pmcntenclr_write }, { .name =3D "PMOVSR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 3, @@ -5130,7 +5130,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 3, .opc2 =3D 1, .resetvalue =3D 0, .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr= _el3) }, - { .name =3D "SDCR", .type =3D ARM_CP_ALIAS, + { .name =3D "SDCR", .type =3D ARM_CP_ALIAS | ARM_CP_IO, .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, .writefn =3D sdcr_write, @@ -7837,7 +7837,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) * value is MDCR_EL2.HPMN which should reset to the value of PMCR_= EL0.N. */ ARMCPRegInfo mdcr_el2 =3D { - .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, + .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, .type =3D = ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, .writefn =3D mdcr_el2_write, .access =3D PL2_RW, .resetvalue =3D pmu_num_counters(env), --=20 2.25.1 From nobody Mon Feb 9 10:11:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n43-20020a05600c502b00b003b486027c8asm2504555wmr.20.2022.09.23.05.34.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Sep 2022 05:34:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=nzYcMZmeofPl1Va3UQhOnDEUNbpieLRg2NI1ebwCrJo=; b=bHOjSLctZxqkuac3QdDYqDSBx32cnfv3NAeNOdY4v0jX5TayIc9HoYS8ZeI1MaUmf1 bJqvXwLF6vBqfxxJxRaMxbrpkTH/Ha1mHchQ4ZcLGA7L+Jf1/AjDoHa5oWRV+OzuAzD8 ZOnYpOC/uhqb4lWzh4PiI+jqoU38GBVGYSAWMATPeXyfopyUnzLnZXufqv4W2F9J9QWy iiaVgOHpqw7VF63shxgMqMLXDglCxo+AOiJU+Q2ER7tifqT/y0nWPpsWH35Bdux+z1ku +GOVF45+L8VB1yJAEYRZdFBSgxDGBu7EeFEIqTNkwGfmCCoBSinDggUgZ3EZ6uwJZP5u rI8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=nzYcMZmeofPl1Va3UQhOnDEUNbpieLRg2NI1ebwCrJo=; b=QphVTpjJebUelcyZiaLqus7aWFA0PncNdpoBLhMh5UGnbq7sI0OTQ2p+HVF/ToZ5R6 C+xxpNeVuFcCySwJ8W6p4BnmVikEiBoZ0VPiODxljwaPAK5XWCrsDOQQ0rhqElCoR/r0 HH60qrT3kBBymdBhDjHAgC61mW780+tvO2KuwxBt5A/MNkA0pmye7u6eRoM4LWcqLewd Lq1RULyrmgkzwryoBNgFn9h5HqC5mohtEvpqaTsJVAJxszp39I2+J9hoC6LELf4afhw8 wqSBxLtGsOFONV5F3aX+csWV4oVdnZUsMsSU9BSdRevx9/UjkK+wYRexE1y3s/h4DmxZ 7Gkw== X-Gm-Message-State: ACrzQf2pG9wrROHsUaUY16NwB5Aj1op21W1GzMQmXHBGgMo17RpCLktc dK/EuH5Ce0/gdxDTB9c+uIASRbOGJEBTEA== X-Google-Smtp-Source: AMsMyM7g81j5/AZ29gnmGoKhLtty9j4/7hnXRQ30jSiNUvX2goHN+lhwZTcTmxjAqGsE4BTC3qtK8Q== X-Received: by 2002:a05:600c:444b:b0:3b4:fdbd:5965 with SMTP id v11-20020a05600c444b00b003b4fdbd5965mr5791299wmn.128.1663936456603; Fri, 23 Sep 2022 05:34:16 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Thomas Huth Subject: [PATCH 2/3] target/arm: Make writes to MDCR_EL3 use PMU start/finish calls Date: Fri, 23 Sep 2022 13:34:11 +0100 Message-Id: <20220923123412.1214041-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220923123412.1214041-1-peter.maydell@linaro.org> References: <20220923123412.1214041-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1663937860530100001 Content-Type: text/plain; charset="utf-8" In commit 01765386a88868 we fixed a bug where we weren't correctly bracketing changes to some registers with pmu_op_start() and pmu_op_finish() calls for changes which affect whether the PMU counters might be enabled. However, we missed the case of writes to the AArch64 MDCR_EL3 register, because (unlike its AArch32 counterpart) they are currently done directly to the CPU state struct without going through the sdcr_write() function. Give MDCR_EL3 a writefn which handles the PMU start/finish calls. The SDCR writefn then simplfies to "call the MDCR_EL3 writefn after masking off the bits which don't exist in the AArch32 register". Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7c7ba328d6d..cebce23da07 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4761,8 +4761,8 @@ static void sctlr_write(CPUARMState *env, const ARMCP= RegInfo *ri, } } =20 -static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void mdcr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { /* * Some MDCR_EL3 bits affect whether PMU counters are running: @@ -4774,12 +4774,19 @@ static void sdcr_write(CPUARMState *env, const ARMC= PRegInfo *ri, if (pmu_op) { pmu_op_start(env); } - env->cp15.mdcr_el3 =3D value & SDCR_VALID_MASK; + env->cp15.mdcr_el3 =3D value; if (pmu_op) { pmu_op_finish(env); } } =20 +static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */ + mdcr_el3_write(env, ri, value & SDCR_VALID_MASK); +} + static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -5127,9 +5134,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, { .name =3D "MDCR_EL3", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 3, .opc2 =3D 1, .resetvalue =3D 0, - .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr= _el3) }, + .access =3D PL3_RW, + .writefn =3D mdcr_el3_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr_el3) }, { .name =3D "SDCR", .type =3D ARM_CP_ALIAS | ARM_CP_IO, .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, --=20 2.25.1 From nobody Mon Feb 9 10:11:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1663937197; cv=none; d=zohomail.com; s=zohoarc; b=l2YBXUml0mTxR9kJCRoFu0piJKNFGMSvR+JZ2Fg+h3BK/69r8ULeR/IwrbdA/EFoEvqBbsTYdS5t0ur3Oi9953VbGSoY3xXLTXm22MElwlh48reG+OO6VXm73ASNfhov2lZJoIXnursJjaUpggvdAnvGx7fEYQKPygSt2M5yJCY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1663937197; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OWwd1ae/Kt3B1uUkttuDu4lRYoyOUHwwnpD54tfsuag=; b=O9PzTMIMKgHVLoJhNSVj6JmSlJKEz6f77rlKAY0m/CK0KuO9tc+8iOCXU3Lkt1qGDOQFcC6GbHivrL3KVseJ/NNTUunrM5xnerzuNMN2rt1OAIGGoHuQQCvUVf7jl+zT1bMEKbmBVmb0BEB+4Tbg2yh+7I+dVFG6/IeW/SHb7zk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663937197048674.4833256921951; Fri, 23 Sep 2022 05:46:37 -0700 (PDT) Received: from localhost ([::1]:45132 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1obi4h-0006UW-R6 for importer@patchew.org; Fri, 23 Sep 2022 08:46:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33566) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1obhsu-0006QL-IK for qemu-devel@nongnu.org; Fri, 23 Sep 2022 08:34:24 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:40655) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1obhso-0007Vx-JW for qemu-devel@nongnu.org; Fri, 23 Sep 2022 08:34:21 -0400 Received: by mail-wr1-x430.google.com with SMTP id x18so14224760wrm.7 for ; Fri, 23 Sep 2022 05:34:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n43-20020a05600c502b00b003b486027c8asm2504555wmr.20.2022.09.23.05.34.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Sep 2022 05:34:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=OWwd1ae/Kt3B1uUkttuDu4lRYoyOUHwwnpD54tfsuag=; b=oACL8tsMncuYTcTb53fmmARg/PxgWhjhhIn9FCmPg6u0PXvBOR9+oG4EKnqUIWYbxN TKxE9bPdln4EG2Zxxq+gmywqEUa/ODwO7HvPGH+dPv9znLiuYmkls13bRaTGYqKN7hzA nXY3oi+n5z8lVKPuvNDuhghCRxWLTy5nVU+331clyCiy7rfobJxt0PeMSihzWeoWang3 Jh0ErRHVL69XKmIhng+jGGUBy6kEmeWsetnWn3yMJ1KhGMRnsYhKhU21x1Qp+UTFRtUm jefRAP0o1aqhTH6Wv3VqQaiMw/48M31+WHmbsaFpU6C8KUdGmrBACbREQ1KkUEGHecbr +YQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=OWwd1ae/Kt3B1uUkttuDu4lRYoyOUHwwnpD54tfsuag=; b=IewDKj4oO1Y5vAxB2ZP5zoqMhVclcdMRjfOzCcFtYGB7A95Wvm23wCmcn/v8E7UIjH hKPpMD88af3iLL7K1EBEDNJ4zhDGkn07IZXk7F8Z8yGn0nMx22yH5etRjqsNhrE7FhZA sNc/VdE6LGzsGyA9bk+Ul4PL/oSAhTprWxB1gINlRNX5PphIfyzGn3rxEMOHw6JmONGN nHwOBRdMk6CvS1iypFzCV8mbt+hok/hUR9JpfROR0y8C2Fx613ZW0YkHxG5MJzlARkku 7fZ2COUQUYvB6v1obvrQriPclVpzoyG+2FmL9H0DlFXgB3bj7B4V+7A2mSsUk/Y4XJ4S Ftmg== X-Gm-Message-State: ACrzQf0sCABYA9KJ886Rp6eE30CUpGl4jIUtwjzbXQdcGWSPIMAoYHpl NZ19vENqy1KXgDh+0b4NQ6wTWA== X-Google-Smtp-Source: AMsMyM6BZ7+xazRJ3RnSOV3SEJ98Ed1Q2PttWRI8YNXfvuwpmDciuA9xf3k5bPlafjuAxL3XyqEnRw== X-Received: by 2002:adf:d1e3:0:b0:22a:b9e2:8841 with SMTP id g3-20020adfd1e3000000b0022ab9e28841mr5065032wrd.184.1663936457240; Fri, 23 Sep 2022 05:34:17 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Thomas Huth Subject: [PATCH 3/3] target/arm: Update SDCR_VALID_MASK to include SCCD Date: Fri, 23 Sep 2022 13:34:12 +0100 Message-Id: <20220923123412.1214041-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220923123412.1214041-1-peter.maydell@linaro.org> References: <20220923123412.1214041-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1663937199162100001 Content-Type: text/plain; charset="utf-8" Our SDCR_VALID_MASK doesn't include all of the bits which are defined by the current architecture. In particular in commit 0b42f4fab9d3 we forgot to add SCCD, which meant that an AArch32 guest couldn't actually use the SCCD bit to disable counting in Secure state. Add all the currently defined bits; we don't implement all of them, but this makes them be reads-as-written, which is architecturally valid and matches how we currently handle most of the others in the mask. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 33cdbc0143e..429ed42eece 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1334,11 +1334,15 @@ FIELD(CPTR_EL3, TTA, 20, 1) FIELD(CPTR_EL3, TAM, 30, 1) FIELD(CPTR_EL3, TCPAC, 31, 1) =20 +#define MDCR_MTPME (1U << 28) +#define MDCR_TDCC (1U << 27) #define MDCR_HLP (1U << 26) /* MDCR_EL2 */ #define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ #define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ #define MDCR_EPMAD (1U << 21) #define MDCR_EDAD (1U << 20) +#define MDCR_TTRF (1U << 19) +#define MDCR_STE (1U << 18) /* MDCR_EL3 */ #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ #define MDCR_SDD (1U << 16) @@ -1353,7 +1357,9 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) #define MDCR_HPMN (0x1fU) =20 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ -#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) +#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ + MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ + MDCR_STE | MDCR_SPME | MDCR_SPD) =20 #define CPSR_M (0x1fU) #define CPSR_T (1U << 5) --=20 2.25.1