From nobody Fri Apr 26 23:26:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663775612929381.91944473047226; Wed, 21 Sep 2022 08:53:32 -0700 (PDT) Received: from localhost ([::1]:35258 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ob22V-0007qT-6k for importer@patchew.org; Wed, 21 Sep 2022 11:53:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ob21J-0006U9-In for qemu-devel@nongnu.org; Wed, 21 Sep 2022 11:52:17 -0400 Received: from mout.kundenserver.de ([212.227.126.134]:43497) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ob21H-0006Bq-N5 for qemu-devel@nongnu.org; Wed, 21 Sep 2022 11:52:17 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue011 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MkpKR-1ozcO33t3n-00mMLw; Wed, 21 Sep 2022 17:52:13 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Laurent Vivier , Richard Henderson Subject: [PULL 1/5] target/m68k: Implement atomic test-and-set Date: Wed, 21 Sep 2022 17:52:07 +0200 Message-Id: <20220921155211.402559-2-laurent@vivier.eu> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220921155211.402559-1-laurent@vivier.eu> References: <20220921155211.402559-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:6g1DQtSzF3ueHZP2WMd66+ue6bRt88KX6gJwkXxaIktn3qtXkZT CWXA0VkHvn8DRymwjjstskEtRVeRPYfDrJUx0NjUQG3iEZt3VqSvZvrWjQWSHIgVWxcPup3 Ow7JDr4KRCW+iLxCS84VrHTUCUf+5Q+QpiVKTd/LuJiFuBfXsGoo615peRn1M//G6P4RLlF QcUAiA4jAHxIVCqbQ4xOg== X-UI-Out-Filterresults: notjunk:1;V03:K0:R5YDnkGOocw=:bFaqdpWZxeeWuO9IapIbk4 IB92YUYuI+/l0vp3Kj+KS0rB49U6KwxbBRX7SZntXeOONi4Gobli/P7WNsJb34x5y3uGmPoJ6 /D+niHZEfxF4yA3ZETpiCIxtEZSXtoxiUo5x7bKHQBWPrZFen2dHGU/qlW+SyFZIyF2jwC//H lSNfpC0n3F9HAbcevoyUN+/Q2k69Zrz1DuWgoB9p8AJfMxISWonQxhSdCfZMUcIwJATDXTlBh pCCKfGICqnxC/dLuciV07DNFfIc/hHSGQU0MueoeXYvVRPUVPL5HO6K5s27twx5Z5JEYRY3GU 8NkXS4TweQz2vAKMmKGmZ3kqtUAjL8DLa+W/+j3t2WzYfys7RG3j8fEK/Yv+M6jD2178I27vW QJsUPHulBTWYJ3EaBkArqVYLOa3Ni6eVVUt37cIvfVI18RU8U2NLXZowyGaKYOgXTf8smi+mX 8s/BQcGrsvwXuF6O6lgYTBZz8yKzVZuEZB9+pJzI6KUXZJepwdn5cZIEMvqNSvccS/ZUBJ86H +z16fMKzjboPWa24ri7rbtrsEWGfbprKQLhxmPXE2sGWOCb/76hBM6GDCfnDtwPxJflYhHtVI TA6S0kJ2YFLUjaXqVBo4bI8l4KMcgj2xijn9Fr+ZIdy8/QJSF5QDQGdQ+kjA689dI3whyWy3u ZucGSOTfCzii9g6K9+ipGOQIoDk8soowz4TMdmuJy2jndhHdhiSLaIp+c4XSUuJ0j+NN0lDLV WewUZcwBJphPF6Gd81FFhSXEcR+sclOa3qDLh3x0ksewcEg3XDXbVP+3R18Qo8MwHfaCcViCL g0ljapu Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=212.227.126.134; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663775614985100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is slightly more complicated than cas, because tas is allowed on data registers. Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier Message-Id: <20220829051746.227094-1-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- target/m68k/translate.c | 40 ++++++++++++++++++++++++++++++---------- 1 file changed, 30 insertions(+), 10 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 5098f7e570e0..ffcc761d6011 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -2825,19 +2825,39 @@ DISAS_INSN(illegal) gen_exception(s, s->base.pc_next, EXCP_ILLEGAL); } =20 -/* ??? This should be atomic. */ DISAS_INSN(tas) { - TCGv dest; - TCGv src1; - TCGv addr; + int mode =3D extract32(insn, 3, 3); + int reg0 =3D REG(insn, 0); =20 - dest =3D tcg_temp_new(); - SRC_EA(env, src1, OS_BYTE, 1, &addr); - gen_logic_cc(s, src1, OS_BYTE); - tcg_gen_ori_i32(dest, src1, 0x80); - DEST_EA(env, insn, OS_BYTE, dest, &addr); - tcg_temp_free(dest); + if (mode =3D=3D 0) { + /* data register direct */ + TCGv dest =3D cpu_dregs[reg0]; + gen_logic_cc(s, dest, OS_BYTE); + tcg_gen_ori_tl(dest, dest, 0x80); + } else { + TCGv src1, addr; + + addr =3D gen_lea_mode(env, s, mode, reg0, OS_BYTE); + if (IS_NULL_QREG(addr)) { + gen_addr_fault(s); + return; + } + src1 =3D tcg_temp_new(); + tcg_gen_atomic_fetch_or_tl(src1, addr, tcg_constant_tl(0x80), + IS_USER(s), MO_SB); + gen_logic_cc(s, src1, OS_BYTE); + tcg_temp_free(src1); + + switch (mode) { + case 3: /* Indirect postincrement. */ + tcg_gen_addi_i32(AREG(insn, 0), addr, 1); + break; + case 4: /* Indirect predecrememnt. */ + tcg_gen_mov_i32(AREG(insn, 0), addr); + break; + } + } } =20 DISAS_INSN(mull) --=20 2.37.3 From nobody Fri Apr 26 23:26:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663775615349250.81508602603571; Wed, 21 Sep 2022 08:53:35 -0700 (PDT) Received: from localhost ([::1]:35254 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ob22V-0007na-Vj for importer@patchew.org; Wed, 21 Sep 2022 11:53:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43862) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ob21J-0006UA-JZ for qemu-devel@nongnu.org; Wed, 21 Sep 2022 11:52:17 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:41293) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ob21H-0006Bt-NC for qemu-devel@nongnu.org; Wed, 21 Sep 2022 11:52:17 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue011 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MZCrZ-1onyKS1P0L-00V4ac; Wed, 21 Sep 2022 17:52:13 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Laurent Vivier , Richard Henderson Subject: [PULL 2/5] target/m68k: Fix MACSR to CCR Date: Wed, 21 Sep 2022 17:52:08 +0200 Message-Id: <20220921155211.402559-3-laurent@vivier.eu> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220921155211.402559-1-laurent@vivier.eu> References: <20220921155211.402559-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:nnqJ3MrRMuBEcK2Kv0wFZ2GPdzC+MoASgbQT9b0fR59pF15zrzG jO3A4SwFWpeQLOFW3C7R4yKyjiQkfRTteCPNgO1tR5MHsLzZz9iYxpM9l2I0LYkZnsHgEZo gXKv8odzFnugt++p+5DgBVHmJfxjeWnMYSD2fUYDSewpo2vwE5GoeIzB6GBZZSngusNYA0/ p766PK1GzoFV2Z9SMG93w== X-UI-Out-Filterresults: notjunk:1;V03:K0:Rya1V/2mp4I=:OkGzkoeAUiJZceb/QqkN91 RMn9cubIeJKNddODLXZnz9PoZXpnAArDtDI36kaQU42oXjMNJ8LI1U/PgKNHFmL0w6WhGfHq0 ZKHpHfDRhtIN+2H0cmYntTbwLYPpZRGytOg3ePqod9T8n048nxWh2rRuLx8wqVwrqqJ7Ehs8J YBvPN7yE1aB1M64ZZnGcjPpN7/wK3K/1DACYGxAc7m24h923pO7rMVFms0bXxP2/QeRWG2tIk C4WYsDBcQaZFgPxL5GR3o2H5YB8zsXfOH1AYD5P47+aQCnHkRkqrggOFT8s/94cUzZ1l1xP8I Y2pNxdqxvPWO+RTzyf3axZKH3ciLbHD8GbhJF/XJOcX3XifnWPx9bf9fxDdE+UQzLhJk//VuR +FS23jZy0TisEL2ZQLykuUR0O8nQ1WNJNLdC3V639eT1Yf9Gc/VCzRGILWugCUjVEr8KZiHI0 wd95K4NAjreQGijL3Yfed59g1eiI3RCehZ1Y+T9VBShVWWna/l8P+zfCs+ai6z8KjzPCV0WcG iXp8xcwmd2NO9nsALm6JC4XmS7Q5eoO+YcGCA169hHj0NHj20F3cEPKffkHw5dQqnYRGAgqsX QKhSQ5tGkMUDnpPh10Rkzk5dzOWgu6uVVwshcnZtxLVMSyxGyEQlvwxaDawGjgWhhlikRZX1Z Z7db8aOHAi5HmkF8rzvF5JM9ZBWnfpIAMGgBfdlukA87zXEHkNeXeJcoMpotlPK8Q3b9oLFq4 l7//KVD7D7CZW4ulV4kFV1VImvYmluzfk+QL4FWJyuofnIyZ+FTcZdfPCxyG9rlYfpnlt2rpi l2yRC4N Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=212.227.126.187; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663775616950100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson First, we were writing to the entire SR register, instead of only the flags portion. Second, we were not clearing C as per the documentation (X was cleared via the 0xf mask). Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier Message-Id: <20220913142818.7802-2-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- target/m68k/translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index ffcc761d6011..c9bb05380323 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -5912,8 +5912,10 @@ DISAS_INSN(from_mext) DISAS_INSN(macsr_to_ccr) { TCGv tmp =3D tcg_temp_new(); - tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf); - gen_helper_set_sr(cpu_env, tmp); + + /* Note that X and C are always cleared. */ + tcg_gen_andi_i32(tmp, QREG_MACSR, CCF_N | CCF_Z | CCF_V); + gen_helper_set_ccr(cpu_env, tmp); tcg_temp_free(tmp); set_cc_op(s, CC_OP_FLAGS); } --=20 2.37.3 From nobody Fri Apr 26 23:26:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166377576694753.28001566867465; Wed, 21 Sep 2022 08:56:06 -0700 (PDT) Received: from localhost ([::1]:57924 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ob24w-000200-LV for importer@patchew.org; Wed, 21 Sep 2022 11:56:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43864) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ob21J-0006UB-Pm for qemu-devel@nongnu.org; Wed, 21 Sep 2022 11:52:17 -0400 Received: from mout.kundenserver.de ([212.227.126.135]:49489) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ob21I-0006Bw-0F for qemu-devel@nongnu.org; Wed, 21 Sep 2022 11:52:17 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue011 [212.227.15.167]) with ESMTPSA (Nemesis) id 1Mdva2-1pAv4F3UTW-00b70D; Wed, 21 Sep 2022 17:52:14 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Laurent Vivier , Richard Henderson , Mark Cave-Ayland Subject: [PULL 3/5] target/m68k: Perform writback before modifying SR Date: Wed, 21 Sep 2022 17:52:09 +0200 Message-Id: <20220921155211.402559-4-laurent@vivier.eu> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220921155211.402559-1-laurent@vivier.eu> References: <20220921155211.402559-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:pzxou0mKXGsU7dP4/b0wxckJpZ5QMQKU1mHG1wVpJuHBOi3SOCL kHqxoxYvxwTFQ0G7zuKkPq5pEJiYjKFRd5qxsE6CSa2ha10PqJBNc7a2jOzLuViZS2aPrme fjHYrsKAlqYqH8oM43Ez3A+e7avbmg3MvcHCQhiH2jwQIE5lP0BmAlzQ4vizOWeOTWfr54x j41eo/vDqbbwOL7ZT4Sow== X-UI-Out-Filterresults: notjunk:1;V03:K0:jxz/plHLh+M=:xsXndB3r1UogomeNHTeF7+ 7W7OV8yC58bcwYFvCH3f0MqAw+21A0qhi9M+YOg6Geyy+hs2+UPRoyfpDFVKbfadYzySwdnxA Wqd7CiglZ5fOcIHxzPAqTaSrmHWqzwysksK3lLWV2Lj5D5qIUFqcOoVtGotpQBSI5JlYkyxXm wNStFxHAJJNWonxjPPEbFnHYiddyxn8/h85dLLSN35T9xJOzO8ULGUaqdFlyyIH9liOlLqSpe g+QUk1FFwK67ZVUsCtwntxOgn2RaxBdIfhaMdBvAIwA1QV+fYA6HCps6znF/pKSuK52D8EfLL BnbA9RW+BCJlC+eyBBgknTVpI9aAnOv5HoMEHXB3lZoE/Q4j64Vg0niXksamR0s+73w6c3MRI 4NwuktSfggm6Mc27mB3ueUEICjzOorz0VNoZSI2np58gvJsnQdCBhPxrAvZ25pNHka2GGZv37 MeOg+56JSYA/jaOuer5OsHaI5VkKh/GJmoYlxYaUP74klMTx4pFY1tpJrztwIfJI7eKN/wvr/ Wf5YxMywW2a2jNtg5iGhQVNKkhlBMjruXl506ECQqA/ohaD01sknE/oTq7DjWmGAhdtwJ3tgG LzKUY4ZcpKj0ljw26tevRrN0zZwEmzUx9fKRs9W54crzrXYPod47XlAbOnuQzZWRuSZ8M8ZZo IM4nGFQALnzYC2JCKyUE+/NYMjpHwBDgD8eeeM1AOD1yny+bbxmYNboASop6g+tF2wbHC9zAP 1XjInxOEbByRuZy1npDgtoUV48crYxG8bOVNFhZo+w7ok70eFsbl9CQIPzezAXj/fF8dpeR88 xA7L46B Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=212.227.126.135; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663775767627100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Writes to SR may change security state, which may involve a swap of %ssp with %usp as reflected in %a7. Finish the writeback of %sp@+ before swapping stack pointers. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1206 Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier Reviewed-by: Mark Cave-Ayland Message-Id: <20220913142818.7802-3-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- target/m68k/translate.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index c9bb05380323..4640eadf78e1 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -2285,9 +2285,9 @@ static void gen_set_sr_im(DisasContext *s, uint16_t v= al, int ccr_only) tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0); tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0); } else { - TCGv sr =3D tcg_const_i32(val); - gen_helper_set_sr(cpu_env, sr); - tcg_temp_free(sr); + /* Must writeback before changing security state. */ + do_writebacks(s); + gen_helper_set_sr(cpu_env, tcg_constant_i32(val)); } set_cc_op(s, CC_OP_FLAGS); } @@ -2297,6 +2297,8 @@ static void gen_set_sr(DisasContext *s, TCGv val, int= ccr_only) if (ccr_only) { gen_helper_set_ccr(cpu_env, val); } else { + /* Must writeback before changing security state. */ + do_writebacks(s); gen_helper_set_sr(cpu_env, val); } set_cc_op(s, CC_OP_FLAGS); --=20 2.37.3 From nobody Fri Apr 26 23:26:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663776753496183.88500277527544; Wed, 21 Sep 2022 09:12:33 -0700 (PDT) Received: from localhost ([::1]:44388 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ob2Ks-0001Uv-QT for importer@patchew.org; Wed, 21 Sep 2022 12:12:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43870) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ob21O-0006a4-0M for qemu-devel@nongnu.org; Wed, 21 Sep 2022 11:52:22 -0400 Received: from mout.kundenserver.de ([212.227.126.134]:49629) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ob21L-0006CW-Ht for qemu-devel@nongnu.org; Wed, 21 Sep 2022 11:52:21 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue011 [212.227.15.167]) with ESMTPSA (Nemesis) id 1McGtA-1p9HRC21q0-00clhL; Wed, 21 Sep 2022 17:52:14 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Laurent Vivier , Mark Cave-Ayland , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 4/5] target/m68k: rename M68K_FEATURE_M68000 to M68K_FEATURE_M68K Date: Wed, 21 Sep 2022 17:52:10 +0200 Message-Id: <20220921155211.402559-5-laurent@vivier.eu> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220921155211.402559-1-laurent@vivier.eu> References: <20220921155211.402559-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:cTcylAB8T0lzUaA93KXWXri9YRAEAaDBSk01vOW6//SJ7Nt7fHv Bartpj7daMJ9AJhdwr0q3l+1Y9Fvjjx4SsfREziOEAagfEoNpTDBHELgugMayRQTl1oP/oY VcSGxxyzAfwAnT255aQJUMXJLhPhrTk3pYW6HLHEK0xO7oBiQLfGdC8HjHBgvCa2tXOkCOs macG3y/QhQ+xUeM48g/BQ== X-UI-Out-Filterresults: notjunk:1;V03:K0:bdsI9RUW6WM=:Zs+ps+DaPjc1QWb5ymEax1 OSsFgCGFEqTuinOtEZhiSvmca46omRhhUysvOhvja0gAFVoRj3lGHKM9DQpS+u9JpODWRkpO2 yO3KTF9S/rKt+aWaioP/GrY4Y2jRBQ2T8ZvJ6v7TH/yYDXGJy9Pq3bGzYuL4p9tzZZmMViHxo sU0pCTrPpOBYbWETPnjPkBQhnwh4S+EzvmAshoiwN3yYytGrYNhbcPwgBccdDCBbFwY1U5TCf M4VIX9eNxx+FZPYs1wNidKdTNwxjIggHojHiSjl1plJW5uFV2gXDDLL3yW7htj6cNPo5v1QNE S85s73ikj7XV/UqgBd0RJMyjccPcP7lKjdRh8SIIfeUjCKoD1WSv3x8UxK1v2zAI2QHL6rsgd FprmEA8Yk+pCtID/FmE/GPdcX6T3dAhH6JqNqREycWgWkc+nLEi9Y6JDxfrNxi3iPbUqL4V3+ Ya0h2aFd2QgFmcAvBVqdEzt94pOQXx+hI7DVzh7HSaZEp5ruq6a13YNO1+hC0n3YY2keGcNCZ kL37oXukG3Mj0LW8aek8jHAT2L5NrceaRiYdWU77J+0ZOHGEwp9rWHfrrhX/NvG4/UZUlmqJ5 bmnEZEp0Ft9Qc8zkmAAqunZAqPYk6/W+MLuIOYnJp6Z4M3CgQHjgEBoOrrVEX9aNnfvb7FlDV l4cAW8v5ax9qwweap0NXsrRMf+aVHIyNwVdfzEzV/FUDJKw9cJ+BQyYMNMwiHdNV7l2rok625 hpxGRIj7vG3AbJ+nh62caHx6+BVxx3bMxmJeAIJ+4ssuxxhwjKoaDrfIu3ApO/1cneC/RyCK/ yu0Kn+M Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=212.227.126.134; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663776758148100001 From: Mark Cave-Ayland The M68K_FEATURE_M68000 feature is misleading in that its name suggests the= feature is defined just for Motorola 68000 CPUs, whilst in fact it is defined for a= ll Motorola 680X0 CPUs. In order to avoid confusion with the other M68K_FEATURE_M680X0 constants wh= ich define the features available for specific Motorola CPU models, rename M68K_FEATURE_M68000 to M68K_FEATURE_M68K and add comments to clarify its us= age. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220917112515.83905-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- target/m68k/cpu.h | 5 +- target/m68k/cpu.c | 2 +- target/m68k/helper.c | 2 +- target/m68k/op_helper.c | 2 +- target/m68k/translate.c | 138 ++++++++++++++++++++-------------------- 5 files changed, 75 insertions(+), 74 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 4d8f48e8c747..67b6c12c2892 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -480,8 +480,9 @@ void do_m68k_semihosting(CPUM68KState *env, int nr); */ =20 enum m68k_features { - /* Base m68k instruction set */ - M68K_FEATURE_M68000, + /* Base Motorola CPU set (not set for Coldfire CPUs) */ + M68K_FEATURE_M68K, + /* Motorola CPU feature sets */ M68K_FEATURE_M68010, M68K_FEATURE_M68020, M68K_FEATURE_M68030, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 5bbefda5752d..f681be3a2a58 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -110,7 +110,7 @@ static void m68000_cpu_initfn(Object *obj) M68kCPU *cpu =3D M68K_CPU(obj); CPUM68KState *env =3D &cpu->env; =20 - m68k_set_feature(env, M68K_FEATURE_M68000); + m68k_set_feature(env, M68K_FEATURE_M68K); m68k_set_feature(env, M68K_FEATURE_USP); m68k_set_feature(env, M68K_FEATURE_WORD_INDEX); m68k_set_feature(env, M68K_FEATURE_MOVEP); diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 5728e48585fc..4621cf24027e 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -460,7 +460,7 @@ void m68k_switch_sp(CPUM68KState *env) int new_sp; =20 env->sp[env->current_sp] =3D env->aregs[7]; - if (m68k_feature(env, M68K_FEATURE_M68000)) { + if (m68k_feature(env, M68K_FEATURE_M68K)) { if (env->sr & SR_S) { /* SR:Master-Mode bit unimplemented then ISP is not available = */ if (!m68k_feature(env, M68K_FEATURE_MSP) || env->sr & SR_M) { diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index a96a03405060..5da176d6425a 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -432,7 +432,7 @@ static void m68k_interrupt_all(CPUM68KState *env, int i= s_hw) =20 static void do_interrupt_all(CPUM68KState *env, int is_hw) { - if (m68k_feature(env, M68K_FEATURE_M68000)) { + if (m68k_feature(env, M68K_FEATURE_M68K)) { m68k_interrupt_all(env, is_hw); return; } diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 4640eadf78e1..0b618e8eb2bd 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -471,7 +471,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasCon= text *s, TCGv base) if ((ext & 0x800) =3D=3D 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_= INDEX)) return NULL_QREG; =20 - if (m68k_feature(s->env, M68K_FEATURE_M68000) && + if (m68k_feature(s->env, M68K_FEATURE_M68K) && !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) { ext &=3D ~(3 << 9); } @@ -804,7 +804,7 @@ static TCGv gen_lea_mode(CPUM68KState *env, DisasContex= t *s, reg =3D get_areg(s, reg0); tmp =3D mark_to_release(s, tcg_temp_new()); if (reg0 =3D=3D 7 && opsize =3D=3D OS_BYTE && - m68k_feature(s->env, M68K_FEATURE_M68000)) { + m68k_feature(s->env, M68K_FEATURE_M68K)) { tcg_gen_subi_i32(tmp, reg, 2); } else { tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize)); @@ -888,7 +888,7 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext= *s, int mode, int reg0, if (what =3D=3D EA_STORE || !addrp) { TCGv tmp =3D tcg_temp_new(); if (reg0 =3D=3D 7 && opsize =3D=3D OS_BYTE && - m68k_feature(s->env, M68K_FEATURE_M68000)) { + m68k_feature(s->env, M68K_FEATURE_M68K)) { tcg_gen_addi_i32(tmp, reg, 2); } else { tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize)); @@ -2210,7 +2210,7 @@ DISAS_INSN(bitop_im) op =3D (insn >> 6) & 3; =20 bitnum =3D read_im16(env, s); - if (m68k_feature(s->env, M68K_FEATURE_M68000)) { + if (m68k_feature(s->env, M68K_FEATURE_M68K)) { if (bitnum & 0xfe00) { disas_undef(env, s, insn); return; @@ -2897,7 +2897,7 @@ DISAS_INSN(mull) return; } SRC_EA(env, src1, OS_LONG, 0, NULL); - if (m68k_feature(s->env, M68K_FEATURE_M68000)) { + if (m68k_feature(s->env, M68K_FEATURE_M68K)) { tcg_gen_movi_i32(QREG_CC_C, 0); if (sign) { tcg_gen_muls2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12)); @@ -3492,7 +3492,7 @@ static inline void shift_im(DisasContext *s, uint16_t= insn, int opsize) * while M68000 sets if the most significant bit is changed at * any time during the shift operation. */ - if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { + if (!logical && m68k_feature(s->env, M68K_FEATURE_M68K)) { /* if shift count >=3D bits, V is (reg !=3D 0) */ if (count >=3D bits) { tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, reg, QREG_CC_V= ); @@ -3576,7 +3576,7 @@ static inline void shift_reg(DisasContext *s, uint16_= t insn, int opsize) * int64_t t =3D (int64_t)(intN_t)reg << count; * V =3D ((s ^ t) & (-1 << (bits - 1))) !=3D 0 */ - if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { + if (!logical && m68k_feature(s->env, M68K_FEATURE_M68K)) { TCGv_i64 tt =3D tcg_const_i64(32); /* if shift is greater than 32, use 32 */ tcg_gen_movcond_i64(TCG_COND_GT, s64, s64, tt, tt, s64); @@ -3669,7 +3669,7 @@ DISAS_INSN(shift_mem) * while M68000 sets if the most significant bit is changed at * any time during the shift operation */ - if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { + if (!logical && m68k_feature(s->env, M68K_FEATURE_M68K)) { src =3D gen_extend(s, src, OS_WORD, 1); tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src); } @@ -4620,7 +4620,7 @@ DISAS_INSN(move_from_sr) { TCGv sr; =20 - if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) { + if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68K)) { gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE); return; } @@ -6035,7 +6035,7 @@ void register_m68k_insns (CPUM68KState *env) } while(0) BASE(undef, 0000, 0000); INSN(arith_im, 0080, fff8, CF_ISA_A); - INSN(arith_im, 0000, ff00, M68000); + INSN(arith_im, 0000, ff00, M68K); INSN(chk2, 00c0, f9c0, CHK2); INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC); BASE(bitop_reg, 0100, f1c0); @@ -6044,26 +6044,26 @@ void register_m68k_insns (CPUM68KState *env) BASE(bitop_reg, 01c0, f1c0); INSN(movep, 0108, f138, MOVEP); INSN(arith_im, 0280, fff8, CF_ISA_A); - INSN(arith_im, 0200, ff00, M68000); - INSN(undef, 02c0, ffc0, M68000); + INSN(arith_im, 0200, ff00, M68K); + INSN(undef, 02c0, ffc0, M68K); INSN(byterev, 02c0, fff8, CF_ISA_APLUSC); INSN(arith_im, 0480, fff8, CF_ISA_A); - INSN(arith_im, 0400, ff00, M68000); - INSN(undef, 04c0, ffc0, M68000); - INSN(arith_im, 0600, ff00, M68000); - INSN(undef, 06c0, ffc0, M68000); + INSN(arith_im, 0400, ff00, M68K); + INSN(undef, 04c0, ffc0, M68K); + INSN(arith_im, 0600, ff00, M68K); + INSN(undef, 06c0, ffc0, M68K); INSN(ff1, 04c0, fff8, CF_ISA_APLUSC); INSN(arith_im, 0680, fff8, CF_ISA_A); INSN(arith_im, 0c00, ff38, CF_ISA_A); - INSN(arith_im, 0c00, ff00, M68000); + INSN(arith_im, 0c00, ff00, M68K); BASE(bitop_im, 0800, ffc0); BASE(bitop_im, 0840, ffc0); BASE(bitop_im, 0880, ffc0); BASE(bitop_im, 08c0, ffc0); INSN(arith_im, 0a80, fff8, CF_ISA_A); - INSN(arith_im, 0a00, ff00, M68000); + INSN(arith_im, 0a00, ff00, M68K); #if defined(CONFIG_SOFTMMU) - INSN(moves, 0e00, ff00, M68000); + INSN(moves, 0e00, ff00, M68K); #endif INSN(cas, 0ac0, ffc0, CAS); INSN(cas, 0cc0, ffc0, CAS); @@ -6073,44 +6073,44 @@ void register_m68k_insns (CPUM68KState *env) BASE(move, 1000, f000); BASE(move, 2000, f000); BASE(move, 3000, f000); - INSN(chk, 4000, f040, M68000); + INSN(chk, 4000, f040, M68K); INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC); INSN(negx, 4080, fff8, CF_ISA_A); - INSN(negx, 4000, ff00, M68000); - INSN(undef, 40c0, ffc0, M68000); + INSN(negx, 4000, ff00, M68K); + INSN(undef, 40c0, ffc0, M68K); INSN(move_from_sr, 40c0, fff8, CF_ISA_A); - INSN(move_from_sr, 40c0, ffc0, M68000); + INSN(move_from_sr, 40c0, ffc0, M68K); BASE(lea, 41c0, f1c0); BASE(clr, 4200, ff00); BASE(undef, 42c0, ffc0); INSN(move_from_ccr, 42c0, fff8, CF_ISA_A); - INSN(move_from_ccr, 42c0, ffc0, M68000); + INSN(move_from_ccr, 42c0, ffc0, M68K); INSN(neg, 4480, fff8, CF_ISA_A); - INSN(neg, 4400, ff00, M68000); - INSN(undef, 44c0, ffc0, M68000); + INSN(neg, 4400, ff00, M68K); + INSN(undef, 44c0, ffc0, M68K); BASE(move_to_ccr, 44c0, ffc0); INSN(not, 4680, fff8, CF_ISA_A); - INSN(not, 4600, ff00, M68000); + INSN(not, 4600, ff00, M68K); #if defined(CONFIG_SOFTMMU) BASE(move_to_sr, 46c0, ffc0); #endif - INSN(nbcd, 4800, ffc0, M68000); - INSN(linkl, 4808, fff8, M68000); + INSN(nbcd, 4800, ffc0, M68K); + INSN(linkl, 4808, fff8, M68K); BASE(pea, 4840, ffc0); BASE(swap, 4840, fff8); INSN(bkpt, 4848, fff8, BKPT); INSN(movem, 48d0, fbf8, CF_ISA_A); INSN(movem, 48e8, fbf8, CF_ISA_A); - INSN(movem, 4880, fb80, M68000); + INSN(movem, 4880, fb80, M68K); BASE(ext, 4880, fff8); BASE(ext, 48c0, fff8); BASE(ext, 49c0, fff8); BASE(tst, 4a00, ff00); INSN(tas, 4ac0, ffc0, CF_ISA_B); - INSN(tas, 4ac0, ffc0, M68000); + INSN(tas, 4ac0, ffc0, M68K); #if defined(CONFIG_SOFTMMU) INSN(halt, 4ac8, ffff, CF_ISA_A); - INSN(halt, 4ac8, ffff, M68060); + INSN(halt, 4ac8, ffff, M68K); #endif INSN(pulse, 4acc, ffff, CF_ISA_A); BASE(illegal, 4afc, ffff); @@ -6125,7 +6125,7 @@ void register_m68k_insns (CPUM68KState *env) #if defined(CONFIG_SOFTMMU) INSN(move_to_usp, 4e60, fff8, USP); INSN(move_from_usp, 4e68, fff8, USP); - INSN(reset, 4e70, ffff, M68000); + INSN(reset, 4e70, ffff, M68K); BASE(stop, 4e72, ffff); BASE(rte, 4e73, ffff); INSN(cf_movec, 4e7b, ffff, CF_ISA_A); @@ -6134,15 +6134,15 @@ void register_m68k_insns (CPUM68KState *env) BASE(nop, 4e71, ffff); INSN(rtd, 4e74, ffff, RTD); BASE(rts, 4e75, ffff); - INSN(trapv, 4e76, ffff, M68000); - INSN(rtr, 4e77, ffff, M68000); + INSN(trapv, 4e76, ffff, M68K); + INSN(rtr, 4e77, ffff, M68K); BASE(jump, 4e80, ffc0); BASE(jump, 4ec0, ffc0); - INSN(addsubq, 5000, f080, M68000); + INSN(addsubq, 5000, f080, M68K); BASE(addsubq, 5080, f0c0); INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */ - INSN(scc, 50c0, f0c0, M68000); /* Scc.B */ - INSN(dbcc, 50c8, f0f8, M68000); + INSN(scc, 50c0, f0c0, M68K); /* Scc.B */ + INSN(dbcc, 50c8, f0f8, M68K); INSN(trapcc, 50fa, f0fe, TRAPCC); /* opmode 010, 011 */ INSN(trapcc, 50fc, f0ff, TRAPCC); /* opmode 100 */ INSN(trapcc, 51fa, fffe, CF_ISA_A); /* TPF (trapf) opmode 010, 011 = */ @@ -6161,15 +6161,15 @@ void register_m68k_insns (CPUM68KState *env) INSN(mvzs, 7100, f100, CF_ISA_B); BASE(or, 8000, f000); BASE(divw, 80c0, f0c0); - INSN(sbcd_reg, 8100, f1f8, M68000); - INSN(sbcd_mem, 8108, f1f8, M68000); + INSN(sbcd_reg, 8100, f1f8, M68K); + INSN(sbcd_mem, 8108, f1f8, M68K); BASE(addsub, 9000, f000); INSN(undef, 90c0, f0c0, CF_ISA_A); INSN(subx_reg, 9180, f1f8, CF_ISA_A); - INSN(subx_reg, 9100, f138, M68000); - INSN(subx_mem, 9108, f138, M68000); + INSN(subx_reg, 9100, f138, M68K); + INSN(subx_mem, 9108, f138, M68K); INSN(suba, 91c0, f1c0, CF_ISA_A); - INSN(suba, 90c0, f0c0, M68000); + INSN(suba, 90c0, f0c0, M68K); =20 BASE(undef_mac, a000, f000); INSN(mac, a000, f100, CF_EMAC); @@ -6190,41 +6190,41 @@ void register_m68k_insns (CPUM68KState *env) INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */ INSN(cmp, b080, f1c0, CF_ISA_A); INSN(cmpa, b1c0, f1c0, CF_ISA_A); - INSN(cmp, b000, f100, M68000); - INSN(eor, b100, f100, M68000); - INSN(cmpm, b108, f138, M68000); - INSN(cmpa, b0c0, f0c0, M68000); + INSN(cmp, b000, f100, M68K); + INSN(eor, b100, f100, M68K); + INSN(cmpm, b108, f138, M68K); + INSN(cmpa, b0c0, f0c0, M68K); INSN(eor, b180, f1c0, CF_ISA_A); BASE(and, c000, f000); - INSN(exg_dd, c140, f1f8, M68000); - INSN(exg_aa, c148, f1f8, M68000); - INSN(exg_da, c188, f1f8, M68000); + INSN(exg_dd, c140, f1f8, M68K); + INSN(exg_aa, c148, f1f8, M68K); + INSN(exg_da, c188, f1f8, M68K); BASE(mulw, c0c0, f0c0); - INSN(abcd_reg, c100, f1f8, M68000); - INSN(abcd_mem, c108, f1f8, M68000); + INSN(abcd_reg, c100, f1f8, M68K); + INSN(abcd_mem, c108, f1f8, M68K); BASE(addsub, d000, f000); INSN(undef, d0c0, f0c0, CF_ISA_A); INSN(addx_reg, d180, f1f8, CF_ISA_A); - INSN(addx_reg, d100, f138, M68000); - INSN(addx_mem, d108, f138, M68000); + INSN(addx_reg, d100, f138, M68K); + INSN(addx_mem, d108, f138, M68K); INSN(adda, d1c0, f1c0, CF_ISA_A); - INSN(adda, d0c0, f0c0, M68000); + INSN(adda, d0c0, f0c0, M68K); INSN(shift_im, e080, f0f0, CF_ISA_A); INSN(shift_reg, e0a0, f0f0, CF_ISA_A); - INSN(shift8_im, e000, f0f0, M68000); - INSN(shift16_im, e040, f0f0, M68000); - INSN(shift_im, e080, f0f0, M68000); - INSN(shift8_reg, e020, f0f0, M68000); - INSN(shift16_reg, e060, f0f0, M68000); - INSN(shift_reg, e0a0, f0f0, M68000); - INSN(shift_mem, e0c0, fcc0, M68000); - INSN(rotate_im, e090, f0f0, M68000); - INSN(rotate8_im, e010, f0f0, M68000); - INSN(rotate16_im, e050, f0f0, M68000); - INSN(rotate_reg, e0b0, f0f0, M68000); - INSN(rotate8_reg, e030, f0f0, M68000); - INSN(rotate16_reg, e070, f0f0, M68000); - INSN(rotate_mem, e4c0, fcc0, M68000); + INSN(shift8_im, e000, f0f0, M68K); + INSN(shift16_im, e040, f0f0, M68K); + INSN(shift_im, e080, f0f0, M68K); + INSN(shift8_reg, e020, f0f0, M68K); + INSN(shift16_reg, e060, f0f0, M68K); + INSN(shift_reg, e0a0, f0f0, M68K); + INSN(shift_mem, e0c0, fcc0, M68K); + INSN(rotate_im, e090, f0f0, M68K); + INSN(rotate8_im, e010, f0f0, M68K); + INSN(rotate16_im, e050, f0f0, M68K); + INSN(rotate_reg, e0b0, f0f0, M68K); + INSN(rotate8_reg, e030, f0f0, M68K); + INSN(rotate16_reg, e070, f0f0, M68K); + INSN(rotate_mem, e4c0, fcc0, M68K); INSN(bfext_mem, e9c0, fdc0, BITFIELD); /* bfextu & bfexts */ INSN(bfext_reg, e9c0, fdf8, BITFIELD); INSN(bfins_mem, efc0, ffc0, BITFIELD); --=20 2.37.3 From nobody Fri Apr 26 23:26:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663776449034382.7936634243133; Wed, 21 Sep 2022 09:07:29 -0700 (PDT) Received: from localhost ([::1]:59132 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ob2Fx-0007mn-Gy for importer@patchew.org; Wed, 21 Sep 2022 12:07:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43868) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ob21N-0006Z5-K9 for qemu-devel@nongnu.org; Wed, 21 Sep 2022 11:52:21 -0400 Received: from mout.kundenserver.de ([212.227.126.131]:37319) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ob21M-0006CY-0b for qemu-devel@nongnu.org; Wed, 21 Sep 2022 11:52:21 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue011 [212.227.15.167]) with ESMTPSA (Nemesis) id 1M277h-1oYZ2k0iM5-002bT4; Wed, 21 Sep 2022 17:52:15 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Laurent Vivier , Mark Cave-Ayland , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 5/5] target/m68k: always call gen_exit_tb() after writes to SR Date: Wed, 21 Sep 2022 17:52:11 +0200 Message-Id: <20220921155211.402559-6-laurent@vivier.eu> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220921155211.402559-1-laurent@vivier.eu> References: <20220921155211.402559-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=212.227.126.131; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663776450285100001 From: Mark Cave-Ayland Any write to SR can change the security state so always call gen_exit_tb() = when this occurs. In particular MacOS makes use of andiw/oriw in a few places to handle the switch between user and supervisor mode. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220917112515.83905-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- target/m68k/translate.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 0b618e8eb2bd..233b9d8e5783 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -2375,6 +2375,7 @@ DISAS_INSN(arith_im) tcg_gen_or_i32(dest, src1, im); if (with_SR) { gen_set_sr(s, dest, opsize =3D=3D OS_BYTE); + gen_exit_tb(s); } else { DEST_EA(env, insn, opsize, dest, &addr); gen_logic_cc(s, dest, opsize); @@ -2384,6 +2385,7 @@ DISAS_INSN(arith_im) tcg_gen_and_i32(dest, src1, im); if (with_SR) { gen_set_sr(s, dest, opsize =3D=3D OS_BYTE); + gen_exit_tb(s); } else { DEST_EA(env, insn, opsize, dest, &addr); gen_logic_cc(s, dest, opsize); @@ -2407,6 +2409,7 @@ DISAS_INSN(arith_im) tcg_gen_xor_i32(dest, src1, im); if (with_SR) { gen_set_sr(s, dest, opsize =3D=3D OS_BYTE); + gen_exit_tb(s); } else { DEST_EA(env, insn, opsize, dest, &addr); gen_logic_cc(s, dest, opsize); @@ -4614,6 +4617,7 @@ DISAS_INSN(strldsr) } gen_push(s, gen_get_sr(s)); gen_set_sr_im(s, ext, 0); + gen_exit_tb(s); } =20 DISAS_INSN(move_from_sr) --=20 2.37.3