From nobody Tue Feb 10 06:29:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663400958269711.6327458124988; Sat, 17 Sep 2022 00:49:18 -0700 (PDT) Received: from localhost ([::1]:33874 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oZSZh-0003Jt-60 for importer@patchew.org; Sat, 17 Sep 2022 03:49:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47546) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oZSVR-0000Sn-3x for qemu-devel@nongnu.org; Sat, 17 Sep 2022 03:44:53 -0400 Received: from mail.loongson.cn ([114.242.206.163]:56086 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oZSVK-0006Hi-5h for qemu-devel@nongnu.org; Sat, 17 Sep 2022 03:44:52 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Cx72uVeiVjfgQcAA--.38083S3; Sat, 17 Sep 2022 15:43:18 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, peter.maydell@linaro.org, alex.bennee@linaro.org, maobibo@loongson.cn Subject: [RISU PATCH 1/5] risu: Use alternate stack Date: Sat, 17 Sep 2022 15:43:13 +0800 Message-Id: <20220917074317.1410274-2-gaosong@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220917074317.1410274-1-gaosong@loongson.cn> References: <20220917074317.1410274-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8Cx72uVeiVjfgQcAA--.38083S3 X-Coremail-Antispam: 1UD129KBjvJXoW7AryUWw45JryDWw1xCw17ZFb_yoW8JF43pw 43Ca4ftrZ8JrW2q39xCrWkW39xJwn7AryUuF43u3yUXayDGr9Yv3Z8GFy3uFyxGFs8A3yD ArZYka15uF4DCrJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663400959213100001 Content-Type: text/plain; charset="utf-8" We can use alternate stack, so that we can use sp register as intput/ouput = register. I had tested aarch64/LoongArch architecture. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- risu.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/risu.c b/risu.c index 1c096a8..714074e 100644 --- a/risu.c +++ b/risu.c @@ -329,7 +329,7 @@ static void set_sigill_handler(void (*fn) (int, siginfo= _t *, void *)) memset(&sa, 0, sizeof(struct sigaction)); =20 sa.sa_sigaction =3D fn; - sa.sa_flags =3D SA_SIGINFO; + sa.sa_flags =3D SA_SIGINFO | SA_ONSTACK; sigemptyset(&sa.sa_mask); if (sigaction(SIGILL, &sa, 0) !=3D 0) { perror("sigaction"); @@ -550,6 +550,7 @@ int main(int argc, char **argv) char *trace_fn =3D NULL; struct option *longopts; char *shortopts; + stack_t ss; =20 longopts =3D setup_options(&shortopts); =20 @@ -617,6 +618,19 @@ int main(int argc, char **argv) =20 load_image(imgfile); =20 + /* create alternate stack */ + ss.ss_sp =3D malloc(SIGSTKSZ); + if (ss.ss_sp =3D=3D NULL) { + perror("malloc"); + exit(EXIT_FAILURE); + } + ss.ss_size =3D SIGSTKSZ; + ss.ss_flags =3D 0; + if (sigaltstack(&ss, NULL) =3D=3D -1) { + perror("sigaltstac"); + exit(EXIT_FAILURE); + } + /* E.g. select requested SVE vector length. */ arch_init(); =20 --=20 2.31.1 From nobody Tue Feb 10 06:29:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663400688393246.52351024322468; Sat, 17 Sep 2022 00:44:48 -0700 (PDT) Received: from localhost ([::1]:52366 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oZSVK-0007OE-Oz for importer@patchew.org; Sat, 17 Sep 2022 03:44:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53844) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oZSU7-0004eh-FG for qemu-devel@nongnu.org; Sat, 17 Sep 2022 03:43:31 -0400 Received: from mail.loongson.cn ([114.242.206.163]:55866 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oZSU3-0006BA-4Q for qemu-devel@nongnu.org; Sat, 17 Sep 2022 03:43:31 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Cx72uVeiVjfgQcAA--.38083S4; Sat, 17 Sep 2022 15:43:19 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, peter.maydell@linaro.org, alex.bennee@linaro.org, maobibo@loongson.cn Subject: [RISU PATCH 2/5] loongarch: Add LoongArch basic test support Date: Sat, 17 Sep 2022 15:43:14 +0800 Message-Id: <20220917074317.1410274-3-gaosong@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220917074317.1410274-1-gaosong@loongson.cn> References: <20220917074317.1410274-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8Cx72uVeiVjfgQcAA--.38083S4 X-Coremail-Antispam: 1UD129KBjvJXoW3CryfWry8KF4xXrW8KFykXwb_yoWDuFy5pa 1fG34rJr4UXw13Zr4fJ3yqvF15Kr1rJw17GF9xGw1jyFy8Jw1vqrn5Gr1UAF1UJw1UKr9I 9F1DtFW5Wr1rJrJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663400689573100002 Content-Type: text/plain; charset="utf-8" This patch adds LoongArch server, client support, and basic test file. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- risu_loongarch64.c | 50 ++++++++++ risu_reginfo_loongarch64.c | 183 +++++++++++++++++++++++++++++++++++++ risu_reginfo_loongarch64.h | 25 +++++ test_loongarch64.s | 92 +++++++++++++++++++ 4 files changed, 350 insertions(+) create mode 100644 risu_loongarch64.c create mode 100644 risu_reginfo_loongarch64.c create mode 100644 risu_reginfo_loongarch64.h create mode 100644 test_loongarch64.s diff --git a/risu_loongarch64.c b/risu_loongarch64.c new file mode 100644 index 0000000..24599e1 --- /dev/null +++ b/risu_loongarch64.c @@ -0,0 +1,50 @@ +/*************************************************************************= ***** + * Copyright (c) 2022 Loongson Technology Corporation Limited + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * based on Peter Maydell's risu_arm.c + *************************************************************************= ****/ + +#include +#include +#include + +#include "risu.h" + +void advance_pc(void *vuc) +{ + struct ucontext *uc =3D vuc; + uc->uc_mcontext.sc_pc +=3D 4; +} + +void set_ucontext_paramreg(void *vuc, uint64_t value) +{ + struct ucontext *uc =3D vuc; + uc->uc_mcontext.sc_regs[4] =3D value; +} + +uint64_t get_reginfo_paramreg(struct reginfo *ri) +{ + return ri->regs[4]; +} + +int get_risuop(struct reginfo *ri) +{ + /* Return the risuop we have been asked to do + * (or -1 if this was a SIGILL for a non-risuop insn) + */ + uint32_t insn =3D ri->faulting_insn; + uint32_t op =3D insn & 0xf; + uint32_t key =3D insn & ~0xf; + uint32_t risukey =3D 0x000001f0; + return (key !=3D risukey) ? -1 : op; +} + +uintptr_t get_pc(struct reginfo *ri) +{ + return ri->pc; +} diff --git a/risu_reginfo_loongarch64.c b/risu_reginfo_loongarch64.c new file mode 100644 index 0000000..af6ab77 --- /dev/null +++ b/risu_reginfo_loongarch64.c @@ -0,0 +1,183 @@ +/*************************************************************************= ***** + * Copyright (c) 2022 Loongson Technology Corporation Limited + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * based on Peter Maydell's risu_reginfo_arm.c + *************************************************************************= ****/ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "risu.h" +#include "risu_reginfo_loongarch64.h" + +const struct option * const arch_long_opts; +const char * const arch_extra_help; + +struct _ctx_layout { + struct sctx_info *addr; + unsigned int size; +}; + +struct extctx_layout { + unsigned long size; + unsigned int flags; + struct _ctx_layout fpu; + struct _ctx_layout end; +}; + +void process_arch_opt(int opt, const char *arg) +{ + abort(); +} + +void arch_init(void) +{ +} + +int reginfo_size(struct reginfo *ri) +{ + return sizeof(*ri); +} + +static int parse_extcontext(struct sigcontext *sc, struct extctx_layout *e= xtctx) +{ + uint32_t magic, size; + struct sctx_info *info =3D (struct sctx_info *)&sc->sc_extcontext; + + while(1) { + magic =3D (uint32_t)info->magic; + size =3D (uint32_t)info->size; + switch (magic) { + case 0: /* END*/ + return 0; + case FPU_CTX_MAGIC: + if (size < (sizeof(struct sctx_info) + + sizeof(struct fpu_context))) { + return -1; + } + extctx->fpu.addr =3D info; + break; + default: + return -1; + } + info =3D (struct sctx_info *)((char *)info +size); + } + return 0; +} + +/* reginfo_init: initialize with a ucontext */ +void reginfo_init(struct reginfo *ri, ucontext_t *context) +{ + int i; + struct ucontext *uc =3D (struct ucontext *)context; + struct extctx_layout extctx; + + memset(&extctx, 0, sizeof(struct extctx_layout)); + memset(ri, 0, sizeof(*ri)); + + for (i =3D 1; i < 32; i++) { + ri->regs[i] =3D uc->uc_mcontext.sc_regs[i]; //sp:r3, tp:r2 + } + + ri->regs[2] =3D 0xdeadbeefdeadbeef; + ri->pc =3D uc->uc_mcontext.sc_pc - (unsigned long)image_start_address; + ri->flags =3D uc->uc_mcontext.sc_flags; + ri->faulting_insn =3D *(uint32_t *)uc->uc_mcontext.sc_pc; + + parse_extcontext(&uc->uc_mcontext, &extctx); + if (extctx.fpu.addr) { + struct sctx_info *info =3D extctx.fpu.addr; + struct fpu_context *fpu_ctx =3D (struct fpu_context *)((char *)inf= o + + sizeof(struct sctx_info)); + for(i =3D 0; i < 32; i++) { + ri->fpregs[i] =3D fpu_ctx->regs[i]; + } + ri->fcsr =3D fpu_ctx->fcsr; + ri->fcc =3D fpu_ctx->fcc; + } +} + +/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */ +int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2) +{ + return !memcmp(r1, r2, sizeof(*r1)); +} + +/* reginfo_dump: print state to a stream, returns nonzero on success */ +int reginfo_dump(struct reginfo *ri, FILE * f) +{ + int i; + fprintf(f, " faulting insn %08x\n", ri->faulting_insn); + + for (i =3D 0; i < 32; i++) { + fprintf(f, " r%-2d : %016" PRIx64 "\n", i, ri->regs[i]); + } + + fprintf(f, " pc : %016" PRIx64 "\n", ri->pc); + fprintf(f, " flags : %08x\n", ri->flags); + fprintf(f, " fcc : %016" PRIx64 "\n", ri->fcc); + fprintf(f, " fcsr : %08x\n", ri->fcsr); + + for (i =3D 0; i < 32; i++) { + fprintf(f, " f%-2d : %016lx\n", i, ri->fpregs[i]); + } + + return !ferror(f); +} + +/* reginfo_dump_mismatch: print mismatch details to a stream, ret nonzero= =3Dok */ +int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f) +{ + int i; + fprintf(f, "mismatch detail (master : apprentice):\n"); + if (m->faulting_insn !=3D a->faulting_insn) { + fprintf(f, " faulting insn mismatch %08x vs %08x\n", + m->faulting_insn, a->faulting_insn); + } + /* r2:tp, r3:sp */ + for (i =3D 0; i < 32; i++) { + if (m->regs[i] !=3D a->regs[i]) { + fprintf(f, " r%-2d : %016" PRIx64 " vs %016" PRIx64 "\n", + i, m->regs[i], a->regs[i]); + } + } + + if (m->pc !=3D a->pc) { + fprintf(f, " pc : %016" PRIx64 " vs %016" PRIx64 "\n", + m->pc, a->pc); + } + if (m->flags !=3D a->flags) { + fprintf(f, " flags : %08x vs %08x\n", m->flags, a->flags); + } + if (m->fcc !=3D a->fcc) { + fprintf(f, " fcc : %016" PRIx64 " vs %016" PRIx64 "\n", + m->fcc, a->fcc); + } + if (m->fcsr !=3D a->fcsr) { + fprintf(f, " fcsr : %08x vs %08x\n", m->fcsr, a->fcsr); + } + + for (i =3D 0; i < 32; i++) { + if (m->fpregs[i]!=3D a->fpregs[i]) { + fprintf(f, " f%-2d : %016lx vs %016lx\n", + i, m->fpregs[i], a->fpregs[i]); + } + } + + return !ferror(f); +} diff --git a/risu_reginfo_loongarch64.h b/risu_reginfo_loongarch64.h new file mode 100644 index 0000000..b6c5aaa --- /dev/null +++ b/risu_reginfo_loongarch64.h @@ -0,0 +1,25 @@ +/*************************************************************************= ***** + * Copyright (c) 2022 Loongson Technology Corporation Limited + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * based on Peter Maydell's risu_reginfo_arm.h + *************************************************************************= ****/ + +#ifndef RISU_REGINFO_LOONGARCH64_H +#define RISU_REGINFO_LOONGARCH64_H + +struct reginfo { + uint64_t regs[32]; + uint64_t pc; + uint64_t fcc; + uint32_t flags; + uint32_t fcsr; + uint32_t faulting_insn; + uint64_t fpregs[32]; +}; + +#endif /* RISU_REGINFO_LOONGARCH64_H */ diff --git a/test_loongarch64.s b/test_loongarch64.s new file mode 100644 index 0000000..431416d --- /dev/null +++ b/test_loongarch64.s @@ -0,0 +1,92 @@ +/*************************************************************************= **** + * Copyright (c) 2022 Loongson Technology Corporation Limited + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * rhich accompanies this distribution, and is available at + * http://rrr.eclipse.org/legal/epl-v10.html + * + * Contributors: + * based on test_arm.s by Peter Maydell + *************************************************************************= ****/ + +/* Initialise the gp regs */ +# $r0 is always 0 +addi.w $r1, $r0, 1 +#r2 tp skip r2 +#r3 sp +addi.w $r3, $r0, 3 +addi.w $r4, $r0, 4 +addi.w $r5, $r0, 5 +addi.w $r6, $r0, 6 +addi.w $r7, $r0, 7 +addi.w $r8, $r0, 8 +addi.w $r9, $r0, 9 +addi.w $r10, $r0, 10 +addi.w $r11, $r0, 11 +addi.w $r12, $r0, 12 +addi.w $r13, $r0, 13 +addi.w $r14, $r0, 14 +addi.w $r15, $r0, 15 +addi.w $r16, $r0, 16 +addi.w $r17, $r0, 17 +addi.w $r18, $r0, 18 +addi.w $r19, $r0, 19 +addi.w $r20, $r0, 20 +addi.w $r21, $r0, 21 +addi.w $r22, $r0, 22 +addi.w $r23, $r0, 23 +addi.w $r24, $r0, 24 +addi.w $r25, $r0, 25 +addi.w $r26, $r0, 26 +addi.w $r27, $r0, 27 +addi.w $r28, $r0, 28 +addi.w $r29, $r0, 29 +addi.w $r30, $r0, 30 +addi.w $r31, $r0, 31 + +/* Initialise the fp regs */ +movgr2fr.d $f0, $r0 +movgr2fr.d $f1, $r1 +movgr2fr.d $f2, $r0 +movgr2fr.d $f3, $r0 +movgr2fr.d $f4, $r4 +movgr2fr.d $f5, $r5 +movgr2fr.d $f6, $r6 +movgr2fr.d $f7, $r7 +movgr2fr.d $f8, $r8 +movgr2fr.d $f9, $r9 +movgr2fr.d $f10, $r10 +movgr2fr.d $f11, $r11 +movgr2fr.d $f12, $r12 +movgr2fr.d $f13, $r13 +movgr2fr.d $f14, $r14 +movgr2fr.d $f15, $r15 +movgr2fr.d $f16, $r16 +movgr2fr.d $f17, $r17 +movgr2fr.d $f18, $r18 +movgr2fr.d $f19, $r19 +movgr2fr.d $f20, $r20 +movgr2fr.d $f21, $r21 +movgr2fr.d $f22, $r22 +movgr2fr.d $f23, $r23 +movgr2fr.d $f24, $r24 +movgr2fr.d $f25, $r25 +movgr2fr.d $f26, $r26 +movgr2fr.d $f27, $r27 +movgr2fr.d $f28, $r28 +movgr2fr.d $f29, $r29 +movgr2fr.d $f30, $r30 +movgr2fr.d $f31, $r31 +movgr2cf $fcc0, $r0 +movgr2cf $fcc1, $r0 +movgr2cf $fcc2, $r0 +movgr2cf $fcc3, $r0 +movgr2cf $fcc4, $r0 +movgr2cf $fcc5, $r0 +movgr2cf $fcc6, $r0 +movgr2cf $fcc7, $r0 + +/* do compare. */ +.int 0x000001f0 +/* exit test */ +.int 0x000001f1 --=20 2.31.1 From nobody Tue Feb 10 06:29:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663400687477548.9728569039107; Sat, 17 Sep 2022 00:44:47 -0700 (PDT) Received: from localhost ([::1]:52362 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oZSVK-0007I2-22 for importer@patchew.org; Sat, 17 Sep 2022 03:44:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oZSU6-0004e8-5c for qemu-devel@nongnu.org; Sat, 17 Sep 2022 03:43:30 -0400 Received: from mail.loongson.cn ([114.242.206.163]:55876 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oZSU2-0006BB-Fy for qemu-devel@nongnu.org; Sat, 17 Sep 2022 03:43:29 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Cx72uVeiVjfgQcAA--.38083S5; Sat, 17 Sep 2022 15:43:19 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, peter.maydell@linaro.org, alex.bennee@linaro.org, maobibo@loongson.cn Subject: [RISU PATCH 3/5] loongarch: Implement risugen module Date: Sat, 17 Sep 2022 15:43:15 +0800 Message-Id: <20220917074317.1410274-4-gaosong@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220917074317.1410274-1-gaosong@loongson.cn> References: <20220917074317.1410274-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8Cx72uVeiVjfgQcAA--.38083S5 X-Coremail-Antispam: 1UD129KBjvAXoW3CryxtF1kKr1DGw1DtF1DZFb_yoW8JF18to Wfuw4xXF1rtw18Zrn5Crn7J347ZFZ5Gan8A3W5Gr4a9Fy8Xr1Yga4293sxur13Jay5CF18 u34vq3WfJay8tas3n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjDUYxBIdaVFxhVjvjDU0xZFpf9x0zRUUUUUUUUU= X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663400689572100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- risugen_loongarch64.pm | 502 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 502 insertions(+) create mode 100644 risugen_loongarch64.pm diff --git a/risugen_loongarch64.pm b/risugen_loongarch64.pm new file mode 100644 index 0000000..693fb71 --- /dev/null +++ b/risugen_loongarch64.pm @@ -0,0 +1,502 @@ +#!/usr/bin/perl -w +##########################################################################= ##### +# Copyright (c) 2022 Loongson Technology Corporation Limited +# All rights reserved. This program and the accompanying materials +# are made available under the terms of the Eclipse Public License v1.0 +# which accompanies this distribution, and is available at +# http://www.eclipse.org/legal/epl-v10.html +# +# Contributors: +# based on Peter Maydell (Linaro) - initial implementation +##########################################################################= ##### + +# risugen -- generate a test binary file for use with risu +# See 'risugen --help' for usage information. +package risugen_loongarch64; + +use strict; +use warnings; + +use risugen_common; + +require Exporter; + +our @ISA =3D qw(Exporter); +our @EXPORT =3D qw(write_test_code); + +my $periodic_reg_random =3D 1; + +# Maximum alignment restriction permitted for a memory op. +my $MAXALIGN =3D 64; + +my $OP_COMPARE =3D 0; # compare registers +my $OP_TESTEND =3D 1; # end of test, stop +my $OP_SETMEMBLOCK =3D 2; # r4 is address of memory block (8192 bytes) +my $OP_GETMEMBLOCK =3D 3; # add the address of memory block to r4 +my $OP_COMPAREMEM =3D 4; # compare memory block + +sub write_risuop($) +{ + my ($op) =3D @_; + insn32(0x000001f0 | $op); +} + +sub write_set_fcsr($) +{ + my ($fcsr) =3D @_; + # movgr2fcsr r0, r0 + insn32(0x0114c000); +} + +# Global used to communicate between align(x) and reg() etc. +my $alignment_restriction; + +sub set_reg_w($) +{ + my($reg)=3D@_; + # Set reg [0x0, 0x7FFFFFFF] + + # $reg << 33 + # slli.d $reg, $reg, 33 + insn32(0x410000 | 33 << 10 | $reg << 5 | $reg); + # $reg >> 33 + # srli.d $reg, $reg, 33 + insn32(0x450000 | 33 << 10 | $reg << 5 | $reg); + + return $reg; +} + +sub align($) +{ + my ($a) =3D @_; + if (!is_pow_of_2($a) || ($a < 0) || ($a > $MAXALIGN)) { + die "bad align() value $a\n"; + } + $alignment_restriction =3D $a; +} + +sub write_sub_rrr($$$) +{ + my ($rd, $rj, $rk) =3D @_; + # sub.d rd, rj, rk + insn32(0x00118000 | $rk << 10 | $rj << 5 | $rd); +} + +sub write_mov_rr($$$) +{ + my($rd, $rj, $rk) =3D @_; + # add.d rd, rj, r0 + insn32(0x00108000 | 0 << 10 | $rj << 5 | $rd); +} + +sub write_mov_positive_ri($$) +{ + # Use lu12i.w and ori instruction + my ($rd, $imm) =3D @_; + my $high_20 =3D ($imm >> 12) & 0xfffff; + + if ($high_20) { + # lu12i.w rd, si20 + insn32(0x14000000 | $high_20 << 5 | $rd); + # ori rd, rd, ui12 + insn32(0x03800000 | ($imm & 0xfff) << 10 | $rd << 5 | $rd); + } else { + # ori rd, 0, ui12 + insn32(0x03800000 | ($imm & 0xfff) << 10 | 0 << 5 | $rd); + } +} + +sub write_mov_ri($$) +{ + my ($rd, $imm) =3D @_; + + if ($imm < 0) { + my $tmp =3D 0 - $imm ; + write_mov_positive_ri($rd, $tmp); + write_sub_rrr($rd, 0, $rd); + } else { + write_mov_positive_ri($rd, $imm); + } +} + +sub write_get_offset() +{ + # Emit code to get a random offset within the memory block, of the + # right alignment, into r4 + # We require the offset to not be within 256 bytes of either + # end, to (more than) allow for the worst case data transfer, which is + # 16 * 64 bit regs + my $offset =3D (rand(2048 - 512) + 256) & ~($alignment_restriction - 1= ); + write_mov_ri(4, $offset); + write_risuop($OP_GETMEMBLOCK); +} + +sub reg_plus_reg($$@) +{ + my ($base, $idx, @trashed) =3D @_; + my $savedidx =3D 0; + if ($idx =3D=3D 4) { + # Save the index into some other register for the + # moment, because the risuop will trash r4. + $idx =3D 5; + $idx++ if $idx =3D=3D $base; + $savedidx =3D 1; + write_mov_rr($idx, 4, 0); + } + # Get a random offset within the memory block, of the + # right alignment. + write_get_offset(); + + write_sub_rrr($base, 4, $idx); + if ($base !=3D 4) { + if ($savedidx) { + write_mov_rr(4, $idx, 0); + write_mov_ri($idx, 0); + } else { + write_mov_ri(4, 0); + } + } else { + if ($savedidx) { + write_mov_ri($idx, 0); + } + } + + if (grep $_ =3D=3D $base, @trashed) { + return -1; + } + return $base; +} + +sub reg_plus_imm($$@) +{ + # Handle reg + immediate addressing mode + my ($base, $imm, @trashed) =3D @_; + + write_get_offset(); + # Now r4 is the address we want to do the access to, + # so set the basereg by doing the inverse of the + # addressing mode calculation, ie base =3D r4 - imm + # We could do this more cleverly with a sub immediate. + if ($base !=3D 4) { + write_mov_ri($base, $imm); + write_sub_rrr($base, 4, $base); + # Clear r4 to avoid register compare mismatches + # when the memory block location differs between machines. + write_mov_ri(4, 0); + }else { + # We borrow r1 as a temporary (not a problem + # as long as we don't leave anything in a register + # which depends on the location of the memory block) + write_mov_ri(1, $imm); + write_sub_rrr($base, 4, 1); + } + + if (grep $_ =3D=3D $base, @trashed) { + return -1; + } + return $base; +} + +sub write_pc_adr($$) +{ + my($rd, $imm) =3D @_; + # pcaddi (si20 | 2bit 0) + pc + insn32(0x18000000 | $imm << 5 | $rd); +} + +sub write_and($$$) +{ + my($rd, $rj, $rk) =3D @_; + # and rd, rj, rk + insn32(0x148000 | $rk << 10 | $rj << 5 | $rd); +} + +sub write_align_reg($$) +{ + my ($rd, $align) =3D @_; + # rd =3D rd & ~($align -1); + # use r1 as a temp register. + write_mov_ri(1, $align -1); + write_sub_rrr(1, 0, 1); + write_and($rd, $rd, 1); +} + +sub write_jump_fwd($) +{ + my($len) =3D @_; + # b pc + len + my ($offslo, $offshi) =3D (($len / 4 + 1) & 0xffff, ($len / 4 + 1) >> = 16); + insn32(0x50000000 | $offslo << 10 | $offshi); +} + +sub write_memblock_setup() +{ + my $align =3D $MAXALIGN; + my $datalen =3D 8192 + $align; + if (($align > 255) || !is_pow_of_2($align) || $align < 4) { + die "bad alignment!"; + } + + # Set r4 to (datablock + (align-1)) & ~(align-1) + # datablock is at PC + (4 * 4 instructions) =3D PC + 16 + write_pc_adr(4, (4 * 4) + ($align - 1)); #insn 1 + write_align_reg(4, $align); #insn 2 + write_risuop($OP_SETMEMBLOCK); #insn 3 + write_jump_fwd($datalen); #insn 4 + + for(my $i =3D 0; $i < $datalen / 4; $i++) { + insn32(rand(0xffffffff)); + } +} + +# Write random fp value of passed precision (1=3Dsingle, 2=3Ddouble, 4=3Dq= uad) +sub write_random_fpreg_var($) +{ + my ($precision) =3D @_; + my $randomize_low =3D 0; + + if ($precision !=3D 1 && $precision !=3D 2 && $precision !=3D 4) { + die "write_random_fpreg: invalid precision.\n"; + } + + my ($low, $high); + my $r =3D rand(100); + if ($r < 5) { + # +-0 (5%) + $low =3D $high =3D 0; + $high |=3D 0x80000000 if (rand() < 0.5); + } elsif ($r < 10) { + # NaN (5%) + # (plus a tiny chance of generating +-Inf) + $randomize_low =3D 1; + $high =3D rand(0xffffffff) | 0x7ff00000; + } elsif ($r < 15) { + # Infinity (5%) + $low =3D 0; + $high =3D 0x7ff00000; + $high |=3D 0x80000000 if (rand() < 0.5); + } elsif ($r < 30) { + # Denormalized number (15%) + # (plus tiny chance of +-0) + $randomize_low =3D 1; + $high =3D rand(0xffffffff) & ~0x7ff00000; + } else { + # Normalized number (70%) + # (plus a small chance of the other cases) + $randomize_low =3D 1; + $high =3D rand(0xffffffff); + } + + for (my $i =3D 1; $i < $precision; $i++) { + if ($randomize_low) { + $low =3D rand(0xffffffff); + } + insn32($low); + } + insn32($high); +} + +sub write_random_loongarch64_fpdata() +{ + # Load floating point registers + my $align =3D 16; + my $datalen =3D 32 * 16 + $align; + my $off =3D 0; + write_pc_adr(5, (4 * 4) + $align); # insn 1 pcaddi + write_pc_adr(4, (3 * 4) + ($align - 1)); # insn 2 pcaddi + write_align_reg(4, $align); # insn 3 andi + write_jump_fwd($datalen); # insn 4 b pc + len + + # Align safety + for (my $i =3D 0; $i < ($align / 4); $i++) { + insn32(rand(0xffffffff)); + } + + for (my $i =3D 0; $i < 32; $i++) { + write_random_fpreg_var(4); # double + } + + $off =3D 0; + for (my $i =3D 0; $i < 32; $i++) { + my $tmp_reg =3D 6; + # r5 is fp register initial val + # r4 is aligned base address + # copy memory from r5 to r4 + # ld.d r6, r5, $off + # st.d r6, r4, $off + # $off =3D $off + 16 + insn32(0x28c00000 | $off << 10 | 5 << 5 | $tmp_reg); + insn32(0x29c00000 | $off << 10 | 4 << 5 | $tmp_reg); + $off =3D $off + 8; + insn32(0x28c00000 | $off << 10 | 5 << 5 | $tmp_reg); + insn32(0x29c00000 | $off << 10 | 4 << 5 | $tmp_reg); + $off =3D $off + 8; + } + + $off =3D 0; + for (my $i =3D 0; $i < 32; $i++) { + # fld.d fd, r4, $off + insn32(0x2b800000 | $off << 10 | 4 << 5 | $i); + $off =3D $off + 16; + } +} + +sub write_random_regdata() +{ + # General purpose registers, skip r2 + write_mov_ri(1, rand(0xffffffff)); # init r1 + for (my $i =3D 3; $i < 32; $i++) { + write_mov_ri($i, rand(0xffffffff)); + } +} + +sub write_random_register_data($) +{ + my ($fp_enabled) =3D @_; + + # Set fcc0 ~ fcc7 + # movgr2cf $fcc0, $zero + insn32(0x114d800); + # movgr2cf $fcc1, $zero + insn32(0x114d801); + # movgr2cf $fcc2, $zero + insn32(0x114d802); + # movgr2cf $fcc3, $zero + insn32(0x114d803); + # movgr2cf $fcc4, $zero + insn32(0x114d804); + # movgr2cf $fcc5, $zero + insn32(0x114d805); + # movgr2cf $fcc6, $zero + insn32(0x114d806); + # movgr2cf $fcc7, $zero + insn32(0x114d807); + + if ($fp_enabled) { + # Load floating point registers + write_random_loongarch64_fpdata(); + } + + write_random_regdata(); + write_risuop($OP_COMPARE); +} + +sub gen_one_insn($$) +{ + # Given an instruction-details array, generate an instruction + my $constraintfailures =3D 0; + + INSN: while(1) { + my ($forcecond, $rec) =3D @_; + my $insn =3D int(rand(0xffffffff)); + my $insnname =3D $rec->{name}; + my $insnwidth =3D $rec->{width}; + my $fixedbits =3D $rec->{fixedbits}; + my $fixedbitmask =3D $rec->{fixedbitmask}; + my $constraint =3D $rec->{blocks}{"constraints"}; + my $memblock =3D $rec->{blocks}{"memory"}; + + $insn &=3D ~$fixedbitmask; + $insn |=3D $fixedbits; + + if (defined $constraint) { + # User-specified constraint: evaluate in an environment + # with variables set corresponding to the variable fields. + my $v =3D eval_with_fields($insnname, $insn, $rec, "constraint= s", $constraint); + if(!$v) { + $constraintfailures++; + if ($constraintfailures > 10000) { + print "10000 consecutive constraint failures for $insn= name constraints string:\n$constraint\n"; + exit (1); + } + next INSN; + } + } + + # OK, we got a good one + $constraintfailures =3D 0; + + my $basereg; + + if (defined $memblock) { + # This is a load or store. We simply evaluate the block, + # which is expected to be a call to a function which emits + # the code to set up the base register and returns the + # number of the base register. + # Default alignment requirement for ARM is 4 bytes, + # we use 16 for Aarch64, although often unnecessary and overki= ll. + align(16); + $basereg =3D eval_with_fields($insnname, $insn, $rec, "memory"= , $memblock); + } + + insn32($insn); + + if (defined $memblock) { + # Clean up following a memory access instruction: + # we need to turn the (possibly written-back) basereg + # into an offset from the base of the memory block, + # to avoid making register values depend on memory layout. + # $basereg -1 means the basereg was a target of a load + # (and so it doesn't contain a memory address after the op) + if ($basereg !=3D -1) { + write_mov_ri($basereg, 0); + } + write_risuop($OP_COMPAREMEM); + } + return; + } +} + +sub write_test_code($) +{ + my ($params) =3D @_; + + my $condprob =3D $params->{ 'condprob' }; + my $fcsr =3D $params->{'fpscr'}; + my $numinsns =3D $params->{ 'numinsns' }; + my $fp_enabled =3D $params->{ 'fp_enabled' }; + my $outfile =3D $params->{ 'outfile' }; + + my %insn_details =3D %{ $params->{ 'details' } }; + my @keys =3D @{ $params->{ 'keys' } }; + + open_bin($outfile); + + # Convert from probability that insn will be conditional to + # probability of forcing insn to unconditional + $condprob =3D 1 - $condprob; + + # TODO better random number generator? + srand(0); + + print "Generating code using patterns: @keys...\n"; + progress_start(78, $numinsns); + + if ($fp_enabled) { + write_set_fcsr($fcsr); + } + + if (grep { defined($insn_details{$_}->{blocks}->{"memory"}) } @keys) { + write_memblock_setup(); + } + # Memblock setup doesn't clean its registers, so this must come afterw= ards. + write_random_register_data($fp_enabled); + + for my $i (1..$numinsns) { + my $insn_enc =3D $keys[int rand (@keys)]; + my $forcecond =3D (rand() < $condprob) ? 1 : 0; + gen_one_insn($forcecond, $insn_details{$insn_enc}); + write_risuop($OP_COMPARE); + # Rewrite the registers periodically. This avoids the tendency + # for the VFP registers to decay to NaNs and zeroes. + if ($periodic_reg_random && ($i % 100) =3D=3D 0) { + write_random_register_data($fp_enabled); + } + progress_update($i); + } + write_risuop($OP_TESTEND); + progress_end(); + close_bin(); +} + +1; --=20 2.31.1 From nobody Tue Feb 10 06:29:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663400960305619.7628410096395; Sat, 17 Sep 2022 00:49:20 -0700 (PDT) Received: from localhost ([::1]:33872 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oZSZj-0003Ja-0m for importer@patchew.org; Sat, 17 Sep 2022 03:49:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53846) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oZSU8-0004gs-RR for qemu-devel@nongnu.org; Sat, 17 Sep 2022 03:43:32 -0400 Received: from mail.loongson.cn ([114.242.206.163]:55882 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oZSU3-0006BC-5x for qemu-devel@nongnu.org; Sat, 17 Sep 2022 03:43:32 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Cx72uVeiVjfgQcAA--.38083S6; Sat, 17 Sep 2022 15:43:20 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, peter.maydell@linaro.org, alex.bennee@linaro.org, maobibo@loongson.cn Subject: [RISU PATCH 4/5] loongarch: Add risufile with loongarch instructions Date: Sat, 17 Sep 2022 15:43:16 +0800 Message-Id: <20220917074317.1410274-5-gaosong@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220917074317.1410274-1-gaosong@loongson.cn> References: <20220917074317.1410274-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8Cx72uVeiVjfgQcAA--.38083S6 X-Coremail-Antispam: 1UD129KBjvAXoWfAF45CF47CF1xAF1xAFWxtFb_yoW5XFWkuo W0y34fZa18K343Xr95Kw1UJw1DCws0vFsFyFy5J34Fy348ZryDtw15t3Z5Cw45J3y7W3Wr Jry3Z3ZxC345twn3n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjDUYxBIdaVFxhVjvjDU0xZFpf9x0zRUUUUUUUUU= X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663400961200100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Song Gao Acked-by: Richard Henderson --- loongarch64.risu | 573 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 573 insertions(+) create mode 100644 loongarch64.risu diff --git a/loongarch64.risu b/loongarch64.risu new file mode 100644 index 0000000..d059811 --- /dev/null +++ b/loongarch64.risu @@ -0,0 +1,573 @@ +##########################################################################= ##### +# Copyright (c) 2022 Loongson Technology Corporation Limited +# All rights reserved. This program and the accompanying materials +# are made available under the terms of the Eclipse Public License v1.0 +# which accompanies this distribution, and is available at +# http://www.eclipse.org/legal/epl-v10.html +# +# Contributors: +# based on aarch64.risu by Claudio Fontana +# based on arm.risu by Peter Maydell +##########################################################################= ##### + +# Input file for risugen defining LoongArch64 instructions +.mode loongarch64 + +# +# Fixed point arithmetic operation instruction +# +add_w LA64 0000 00000001 00000 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +add_d LA64 0000 00000001 00001 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +sub_w LA64 0000 00000001 00010 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +sub_d LA64 0000 00000001 00011 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +slt LA64 0000 00000001 00100 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +sltu LA64 0000 00000001 00101 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +slti LA64 0000 001000 si12:12 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +sltui LA64 0000 001001 si12:12 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +nor LA64 0000 00000001 01000 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +and LA64 0000 00000001 01001 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +or LA64 0000 00000001 01010 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +xor LA64 0000 00000001 01011 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +orn LA64 0000 00000001 01100 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +andn LA64 0000 00000001 01101 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +mul_w LA64 0000 00000001 11000 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +mul_d LA64 0000 00000001 11011 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +mulh_w LA64 0000 00000001 11001 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +mulh_d LA64 0000 00000001 11100 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +mulh_wu LA64 0000 00000001 11010 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +mulh_du LA64 0000 00000001 11101 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +mulw_d_w LA64 0000 00000001 11110 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +mulw_d_wu LA64 0000 00000001 11111 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } + +#div.{w[u]/d[u]} rd,rj,rk +# the docement 2.2.13, rk, rj, need in 32bit [0x0 ~0x7FFFFFFF] +# use function set_reg_w($reg) +div_w LA64 0000 00000010 00000 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { set_reg_w($rj); set_reg_w($rk); } +div_wu LA64 0000 00000010 00010 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { set_reg_w($rj); set_reg_w($rk); } +div_d LA64 0000 00000010 00100 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +div_du LA64 0000 00000010 00110 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +mod_w LA64 0000 00000010 00001 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { set_reg_w($rj); set_reg_w($rk); } +mod_wu LA64 0000 00000010 00011 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { set_reg_w($rj); set_reg_w($rk); } +mod_d LA64 0000 00000010 00101 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +mod_du LA64 0000 00000010 00111 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } + +alsl_w LA64 0000 00000000 010 sa2:2 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +alsl_wu LA64 0000 00000000 011 sa2:2 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +alsl_d LA64 0000 00000010 110 sa2:2 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +lu12i_w LA64 0001 010 si20:20 rd:5 \ + !constraints { $rd !=3D 2; } +lu32i_d LA64 0001 011 si20:20 rd:5 \ + !constraints { $rd !=3D 2; } +lu52i_d LA64 0000 001100 si12:12 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +addi_w LA64 0000 001010 si12:12 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +addi_d LA64 0000 001011 si12:12 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +addu16i_d LA64 0001 00 si16:16 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +andi LA64 0000 001101 ui12:12 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +ori LA64 0000 001110 ui12:12 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +xori LA64 0000 001111 ui12:12 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } + +# +# Fixed point shift operation instruction +# +sll_w LA64 0000 00000001 01110 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +sll_d LA64 0000 00000001 10001 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +srl_w LA64 0000 00000001 01111 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +srl_d LA64 0000 00000001 10010 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +sra_w LA64 0000 00000001 10000 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +sra_d LA64 0000 00000001 10011 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +rotr_w LA64 0000 00000001 10110 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +rotr_d LA64 0000 00000001 10111 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +slli_w LA64 0000 00000100 00001 ui5:5 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +slli_d LA64 0000 00000100 0001 ui6:6 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +srli_w LA64 0000 00000100 01001 ui5:5 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +srli_d LA64 0000 00000100 0101 ui6:6 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +srai_w LA64 0000 00000100 10001 ui5:5 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +srai_d LA64 0000 00000100 1001 ui6:6 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +rotri_w LA64 0000 00000100 11001 ui5:5 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +rotri_d LA64 0000 00000100 1101 ui6:6 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } + +# +# Fixed point bit operation instruction +# +ext_w_h LA64 0000 00000000 00000 10110 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +ext_w_b LA64 0000 00000000 00000 10111 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +clo_w LA64 0000 00000000 00000 00100 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +clz_w LA64 0000 00000000 00000 00101 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +cto_w LA64 0000 00000000 00000 00110 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +ctz_w LA64 0000 00000000 00000 00111 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +clo_d LA64 0000 00000000 00000 01000 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +clz_d LA64 0000 00000000 00000 01001 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +cto_d LA64 0000 00000000 00000 01010 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +ctz_d LA64 0000 00000000 00000 01011 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +revb_2h LA64 0000 00000000 00000 01100 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +revb_4h LA64 0000 00000000 00000 01101 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +revb_2w LA64 0000 00000000 00000 01110 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +revb_d LA64 0000 00000000 00000 01111 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +revh_2w LA64 0000 00000000 00000 10000 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +revh_d LA64 0000 00000000 00000 10001 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +bitrev_4b LA64 0000 00000000 00000 10010 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +bitrev_8b LA64 0000 00000000 00000 10011 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +bitrev_w LA64 0000 00000000 00000 10100 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +bitrev_d LA64 0000 00000000 00000 10101 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2; } +bytepick_w LA64 0000 00000000 100 sa2:2 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +bytepick_d LA64 0000 00000000 11 sa3:3 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +maskeqz LA64 0000 00000001 00110 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +masknez LA64 0000 00000001 00111 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +bstrins_w LA64 0000 0000011 msbw:5 0 lsbw:5 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2 && $msbw >=3D $lsbw; } +bstrins_d LA64 0000 000010 msbd:6 lsbd:6 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2 && $msbd >=3D $lsbd; } +bstrpick_w LA64 0000 0000011 msbw:5 1 lsbw:5 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2 && $msbw >=3D $lsbw; } +bstrpick_d LA64 0000 000011 msbd:6 lsbd:6 rj:5 rd:5 \ + !constraints { $rj !=3D 2 && $rd !=3D 2 && $msbd >=3D $lsbd; } + +# +# Fixed point load/store instruction +# +ld_b LA64 0010 100000 si12:12 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_imm($rj, sextract($si12, 12)); } +ld_h LA64 0010 100001 si12:12 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_imm($rj, sextract($si12, 12)); } +ld_w LA64 0010 100010 si12:12 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_imm($rj, sextract($si12, 12)); } +ld_d LA64 0010 100011 si12:12 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_imm($rj, sextract($si12, 12)); } +ld_bu LA64 0010 101000 si12:12 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_imm($rj, sextract($si12, 12)); } +ld_hu LA64 0010 101001 si12:12 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_imm($rj, sextract($si12, 12)); } +ld_wu LA64 0010 101010 si12:12 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_imm($rj, sextract($si12, 12)); } +st_b LA64 0010 100100 si12:12 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rd && $rj !=3D 2 && $rd !=3D 2;= } \ + !memory { reg_plus_imm($rj, sextract($si12, 12)); } +st_h LA64 0010 100101 si12:12 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rd && $rj !=3D 2 && $rd !=3D 2;= } \ + !memory { reg_plus_imm($rj, sextract($si12, 12)); } +st_w LA64 0010 100110 si12:12 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rd && $rj !=3D 2 && $rd !=3D 2;= } \ + !memory { reg_plus_imm($rj, sextract($si12, 12)); } +st_d LA64 0010 100111 si12:12 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rd && $rj !=3D 2 && $rd !=3D 2;= } \ + !memory { reg_plus_imm($rj, sextract($si12, 12)); } +ldx_b LA64 0011 10000000 00000 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rk && $rk !=3D 2 && $rj !=3D 2 = && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, $rk); } +ldx_h LA64 0011 10000000 01000 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rk && $rk !=3D 2 && $rj !=3D 2 = && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, $rk); } +ldx_w LA64 0011 10000000 10000 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rk && $rk !=3D 2 && $rj !=3D 2 = && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, $rk); } +ldx_d LA64 0011 10000000 11000 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rk && $rk !=3D 2 && $rj !=3D 2 = && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, $rk); } +ldx_bu LA64 0011 10000010 00000 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rk && $rk !=3D 2 && $rj !=3D 2 = && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, $rk); } +ldx_hu LA64 0011 10000010 01000 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rk && $rk !=3D 2 && $rj !=3D 2 = && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, $rk); } +ldx_wu LA64 0011 10000010 10000 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rk && $rk !=3D 2 && $rj !=3D 2 = && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, $rk); } +stx_b LA64 0011 10000001 00000 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rk && $rd !=3D $rj && $rk !=3D = 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, $rk); } +stx_h LA64 0011 10000001 01000 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rk && $rd !=3D $rj && $rk !=3D = 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, $rk); } +stx_w LA64 0011 10000001 10000 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rk && $rd !=3D $rj && $rk !=3D = 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, $rk); } +stx_d LA64 0011 10000001 11000 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rk && $rd !=3D $rj && $rk !=3D = 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, $rk); } +preld LA64 0010 101011 si12:12 rj:5 hint:5 \ + !constraints { $rj !=3D 2; } \ + !memory { reg_plus_imm($rj, sextract($si12, 12)); } +dbar LA64 0011 10000111 00100 hint:15 +ibar LA64 0011 10000111 00101 hint:15 +ldptr_w LA64 0010 0100 si14:14 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_imm($rj, sextract($si14, 14) * 4); } +ldptr_d LA64 0010 0110 si14:14 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_imm($rj, sextract($si14, 14) * 4); } +stptr_w LA64 0010 0101 si14:14 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rd && $rj !=3D 2 && $rd !=3D 2;= } \ + !memory { reg_plus_imm($rj, sextract($si14, 14) * 4); } +stptr_d LA64 0010 0111 si14:14 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rd && $rj !=3D 2 && $rd !=3D 2;= } \ + !memory { reg_plus_imm($rj, sextract($si14, 14) * 4); } + +# +# Fixed point atomic instruction +# +ll_w LA64 0010 0000 si14:14 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_imm($rj, sextract($si14, 14) * 4); } +ll_d LA64 0010 0010 si14:14 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_imm($rj, sextract($si14, 14) * 4); } + +amswap_w LA64 0011 10000110 00000 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +amswap_d LA64 0011 10000110 00001 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +amadd_w LA64 0011 10000110 00010 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +amadd_d LA64 0011 10000110 00011 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +amand_w LA64 0011 10000110 00100 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +amand_d LA64 0011 10000110 00101 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +amor_w LA64 0011 10000110 00110 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +amor_d LA64 0011 10000110 00111 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +amxor_w LA64 0011 10000110 01000 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +amxor_d LA64 0011 10000110 01001 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +ammax_w LA64 0011 10000110 01010 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +ammax_d LA64 0011 10000110 01011 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +ammin_w LA64 0011 10000110 01100 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +ammin_d LA64 0011 10000110 01101 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +ammax_wu LA64 0011 10000110 01110 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +ammax_du LA64 0011 10000110 01111 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +ammin_wu LA64 0011 10000110 10000 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +ammin_du LA64 0011 10000110 10001 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } + +amswap_db_w LA64 0011 10000110 10010 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +amswap_db_d LA64 0011 10000110 10011 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +amadd_db_w LA64 0011 10000110 10100 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +amadd_db_d LA64 0011 10000110 10101 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +amand_db_w LA64 0011 10000110 10110 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +amand_db_d LA64 0011 10000110 10111 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +amor_db_w LA64 0011 10000110 11000 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +amor_db_d LA64 0011 10000110 11001 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +amxor_db_w LA64 0011 10000110 11010 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +amxor_db_d LA64 0011 10000110 11011 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +ammax_db_w LA64 0011 10000110 11100 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +ammax_db_d LA64 0011 10000110 11101 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +ammin_db_w LA64 0011 10000110 11110 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +ammin_db_d LA64 0011 10000110 11111 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +ammax_db_wu LA64 0011 10000111 00000 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +ammax_db_du LA64 0011 10000111 00001 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +ammin_db_wu LA64 0011 10000111 00010 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } +ammin_db_du LA64 0011 10000111 00011 rk:5 rj:5 rd:5 \ + !constraints { $rj !=3D 0 && $rd !=3D $rj && $rj !=3D $rk && $rd !=3D = $rk && $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ + !memory { reg_plus_reg($rj, 0); } + +# +# Fixed point extra instruction +# +crc_w_b_w LA64 0000 00000010 01000 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +crc_w_h_w LA64 0000 00000010 01001 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +crc_w_w_w LA64 0000 00000010 01010 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +crc_w_d_w LA64 0000 00000010 01011 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +crcc_w_b_w LA64 0000 00000010 01100 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +crcc_w_h_w LA64 0000 00000010 01101 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +crcc_w_w_w LA64 0000 00000010 01110 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } +crcc_w_d_w LA64 0000 00000010 01111 rk:5 rj:5 rd:5 \ + !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } + +# +# Floating point arithmetic operation instruction +# +fadd_s LA64 0000 00010000 00001 fk:5 fj:5 fd:5 +fadd_d LA64 0000 00010000 00010 fk:5 fj:5 fd:5 +fsub_s LA64 0000 00010000 00101 fk:5 fj:5 fd:5 +fsub_d LA64 0000 00010000 00110 fk:5 fj:5 fd:5 +fmul_s LA64 0000 00010000 01001 fk:5 fj:5 fd:5 +fmul_d LA64 0000 00010000 01010 fk:5 fj:5 fd:5 +fdiv_s LA64 0000 00010000 01101 fk:5 fj:5 fd:5 +fdiv_d LA64 0000 00010000 01110 fk:5 fj:5 fd:5 +fmadd_s LA64 0000 10000001 fa:5 fk:5 fj:5 fd:5 +fmadd_d LA64 0000 10000010 fa:5 fk:5 fj:5 fd:5 +fmsub_s LA64 0000 10000101 fa:5 fk:5 fj:5 fd:5 +fmsub_d LA64 0000 10000110 fa:5 fk:5 fj:5 fd:5 +fnmadd_s LA64 0000 10001001 fa:5 fk:5 fj:5 fd:5 +fnmadd_d LA64 0000 10001010 fa:5 fk:5 fj:5 fd:5 +fnmsub_s LA64 0000 10001101 fa:5 fk:5 fj:5 fd:5 +fnmsub_d LA64 0000 10001110 fa:5 fk:5 fj:5 fd:5 +fmax_s LA64 0000 00010000 10001 fk:5 fj:5 fd:5 +fmax_d LA64 0000 00010000 10010 fk:5 fj:5 fd:5 +fmin_s LA64 0000 00010000 10101 fk:5 fj:5 fd:5 +fmin_d LA64 0000 00010000 10110 fk:5 fj:5 fd:5 +fmaxa_s LA64 0000 00010000 11001 fk:5 fj:5 fd:5 +fmaxa_d LA64 0000 00010000 11010 fk:5 fj:5 fd:5 +fmina_s LA64 0000 00010000 11101 fk:5 fj:5 fd:5 +fmina_d LA64 0000 00010000 11110 fk:5 fj:5 fd:5 +fabs_s LA64 0000 00010001 01000 00001 fj:5 fd:5 +fabs_d LA64 0000 00010001 01000 00010 fj:5 fd:5 +fneg_s LA64 0000 00010001 01000 00101 fj:5 fd:5 +fneg_d LA64 0000 00010001 01000 00110 fj:5 fd:5 +fsqrt_s LA64 0000 00010001 01000 10001 fj:5 fd:5 +fsqrt_d LA64 0000 00010001 01000 10010 fj:5 fd:5 +frecip_s LA64 0000 00010001 01000 10101 fj:5 fd:5 +frecip_d LA64 0000 00010001 01000 10110 fj:5 fd:5 +frsqrt_s LA64 0000 00010001 01000 11001 fj:5 fd:5 +frsqrt_d LA64 0000 00010001 01000 11010 fj:5 fd:5 +fscaleb_s LA64 0000 00010001 00001 fk:5 fj:5 fd:5 +fscaleb_d LA64 0000 00010001 00010 fk:5 fj:5 fd:5 +flogb_s LA64 0000 00010001 01000 01001 fj:5 fd:5 +flogb_d LA64 0000 00010001 01000 01010 fj:5 fd:5 +fcopysign_s LA64 0000 00010001 00101 fk:5 fj:5 fd:5 +fcopysign_d LA64 0000 00010001 00110 fk:5 fj:5 fd:5 +fclass_s LA64 0000 00010001 01000 01101 fj:5 fd:5 +fclass_d LA64 0000 00010001 01000 01110 fj:5 fd:5 + +# +# Floating point compare instruction +# +fcmp_cond_s LA64 0000 11000001 cond:5 fk:5 fj:5 00 cd:3 \ + !constraints { $cond > 0 && $cond < 0x12; } +fcmp_cond_d LA64 0000 11000010 cond:5 fk:5 fj:5 00 cd:3 \ + !constraints { $cond > 0 && $cond < 0x12; } + +# +# Floating point conversion instruction +# +fcvt_s_d LA64 0000 00010001 10010 00110 fj:5 fd:5 +fcvt_d_s LA64 0000 00010001 10010 01001 fj:5 fd:5 +ftintrm_w_s LA64 0000 00010001 10100 00001 fj:5 fd:5 +ftintrm_w_d LA64 0000 00010001 10100 00010 fj:5 fd:5 +ftintrm_l_s LA64 0000 00010001 10100 01001 fj:5 fd:5 +ftintrm_l_d LA64 0000 00010001 10100 01010 fj:5 fd:5 +ftintrp_w_s LA64 0000 00010001 10100 10001 fj:5 fd:5 +ftintrp_w_d LA64 0000 00010001 10100 10010 fj:5 fd:5 +ftintrp_l_s LA64 0000 00010001 10100 11001 fj:5 fd:5 +ftintrp_l_d LA64 0000 00010001 10100 11010 fj:5 fd:5 +ftintrz_w_s LA64 0000 00010001 10101 00001 fj:5 fd:5 +ftintrz_w_d LA64 0000 00010001 10101 00010 fj:5 fd:5 +ftintrz_l_s LA64 0000 00010001 10101 01001 fj:5 fd:5 +ftintrz_l_d LA64 0000 00010001 10101 01010 fj:5 fd:5 +ftintrne_w_s LA64 0000 00010001 10101 10001 fj:5 fd:5 +ftintrne_w_d LA64 0000 00010001 10101 10010 fj:5 fd:5 +ftintrne_l_s LA64 0000 00010001 10101 11001 fj:5 fd:5 +ftintrne_l_d LA64 0000 00010001 10101 11010 fj:5 fd:5 +ftint_w_s LA64 0000 00010001 10110 00001 fj:5 fd:5 +ftint_w_d LA64 0000 00010001 10110 00010 fj:5 fd:5 +ftint_l_s LA64 0000 00010001 10110 01001 fj:5 fd:5 +ftint_l_d LA64 0000 00010001 10110 01010 fj:5 fd:5 +ffint_s_w LA64 0000 00010001 11010 00100 fj:5 fd:5 +ffint_s_l LA64 0000 00010001 11010 00110 fj:5 fd:5 +ffint_d_w LA64 0000 00010001 11010 01000 fj:5 fd:5 +ffint_d_l LA64 0000 00010001 11010 01010 fj:5 fd:5 +frint_s LA64 0000 00010001 11100 10001 fj:5 fd:5 +frint_d LA64 0000 00010001 11100 10010 fj:5 fd:5 + +# +# Floating point move instruction +# +fmov_s LA64 0000 00010001 01001 00101 fj:5 fd:5 +fmov_d LA64 0000 00010001 01001 00110 fj:5 fd:5 +fsel LA64 0000 11010000 00 ca:3 fk:5 fj:5 fd:5 +movgr2fr_w LA64 0000 00010001 01001 01001 rj:5 fd:5 \ + !constraints { $rj !=3D 2; } +movgr2fr_d LA64 0000 00010001 01001 01010 rj:5 fd:5 \ + !constraints { $rj !=3D 2; } +movgr2frh_w LA64 0000 00010001 01001 01011 rj:5 fd:5 \ + !constraints { $rj !=3D 2; } +movfr2gr_s LA64 0000 00010001 01001 01101 fj:5 rd:5 \ + !constraints { $rd !=3D 2; } +movfr2gr_d LA64 0000 00010001 01001 01110 fj:5 rd:5 \ + !constraints { $rd !=3D 2; } +movfrh2gr_s LA64 0000 00010001 01001 01111 fj:5 rd:5 \ + !constraints { $rd !=3D 2; } +movfr2cf LA64 0000 00010001 01001 10100 fj:5 00 cd:3 +movcf2fr LA64 0000 00010001 01001 10101 00 cj:3 fd:5 +movgr2cf LA64 0000 00010001 01001 10110 rj:5 00 cd:3 \ + !constraints { $rj !=3D 2; } +movcf2gr LA64 0000 00010001 01001 10111 00 cj:3 rd:5 \ + !constraints { $rd !=3D 2; } + +# +# Floating point load/store instruction +# +fld_s LA64 0010 101100 si12:12 rj:5 fd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D 2; } \ + !memory { reg_plus_imm($rj, sextract($si12, 12)); } +fst_s LA64 0010 101101 si12:12 rj:5 fd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D 2; } \ + !memory { reg_plus_imm($rj, sextract($si12, 12)); } +fld_d LA64 0010 101110 si12:12 rj:5 fd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D 2; } \ + !memory { reg_plus_imm($rj, sextract($si12, 12)); } +fst_d LA64 0010 101111 si12:12 rj:5 fd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D 2; } \ + !memory { reg_plus_imm($rj, sextract($si12, 12)); } +fldx_s LA64 0011 10000011 00000 rk:5 rj:5 fd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rk && $rk !=3D 2 && $rj !=3D 2;= } \ + !memory { reg_plus_reg($rj, $rk); } +fldx_d LA64 0011 10000011 01000 rk:5 rj:5 fd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rk && $rk !=3D 2 && $rj !=3D 2;= } \ + !memory { reg_plus_reg($rj, $rk); } +fstx_s LA64 0011 10000011 10000 rk:5 rj:5 fd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rk && $rk !=3D 2 && $rj !=3D 2;= } \ + !memory { reg_plus_reg($rj, $rk); } +fstx_d LA64 0011 10000011 11000 rk:5 rj:5 fd:5 \ + !constraints { $rj !=3D 0 && $rj !=3D $rk && $rk !=3D 2 && $rj !=3D 2;= } \ + !memory { reg_plus_reg($rj, $rk); } --=20 2.31.1 From nobody Tue Feb 10 06:29:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663400690488321.7430794931288; Sat, 17 Sep 2022 00:44:50 -0700 (PDT) Received: from localhost ([::1]:52364 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oZSVM-0007JB-86 for importer@patchew.org; Sat, 17 Sep 2022 03:44:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53840) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oZSU7-0004eZ-Be for qemu-devel@nongnu.org; Sat, 17 Sep 2022 03:43:31 -0400 Received: from mail.loongson.cn ([114.242.206.163]:55888 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oZSU3-0006BD-CE for qemu-devel@nongnu.org; Sat, 17 Sep 2022 03:43:31 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Cx72uVeiVjfgQcAA--.38083S7; Sat, 17 Sep 2022 15:43:20 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, peter.maydell@linaro.org, alex.bennee@linaro.org, maobibo@loongson.cn Subject: [RISU PATCH 5/5] loongarch: Add block 'safefloat' and nanbox_s() Date: Sat, 17 Sep 2022 15:43:17 +0800 Message-Id: <20220917074317.1410274-6-gaosong@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220917074317.1410274-1-gaosong@loongson.cn> References: <20220917074317.1410274-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8Cx72uVeiVjfgQcAA--.38083S7 X-Coremail-Antispam: 1UD129KBjvJXoW3KrW8KF17KF1kZF1UAF4rGrg_yoWkJr1kpr ZrtFWakr4xXr47Ar4vkr1Utay3Grn7Aa1UAryUtF12qr1UXr1kXryrZrW8trWkWr15Aryx Gr13tr10qr1UG3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663400691559100005 Content-Type: text/plain; charset="utf-8" Some LoongArch instructions don't care the high 32bit, so use nanbox_s() set the high 32bit 0xffffffff. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- loongarch64.risu | 119 +++++++++++++++++++++++++++-------------- risugen | 2 +- risugen_loongarch64.pm | 30 +++++++++++ 3 files changed, 110 insertions(+), 41 deletions(-) diff --git a/loongarch64.risu b/loongarch64.risu index d059811..d625a12 100644 --- a/loongarch64.risu +++ b/loongarch64.risu @@ -62,7 +62,7 @@ mulw_d_wu LA64 0000 00000001 11111 rk:5 rj:5 rd:5 \ !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } =20 #div.{w[u]/d[u]} rd,rj,rk -# the docement 2.2.13, rk, rj, need in 32bit [0x0 ~0x7FFFFFFF] +# div.w{u}, mod.w[u] rk, rj, need in [0x0 ~0x7FFFFFFF] # use function set_reg_w($reg) div_w LA64 0000 00000010 00000 rk:5 rj:5 rd:5 \ !constraints { $rk !=3D 2 && $rj !=3D 2 && $rd !=3D 2; } \ @@ -436,47 +436,68 @@ crcc_w_d_w LA64 0000 00000010 01111 rk:5 rj:5 rd:5 \ # # Floating point arithmetic operation instruction # -fadd_s LA64 0000 00010000 00001 fk:5 fj:5 fd:5 +fadd_s LA64 0000 00010000 00001 fk:5 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fadd_d LA64 0000 00010000 00010 fk:5 fj:5 fd:5 -fsub_s LA64 0000 00010000 00101 fk:5 fj:5 fd:5 +fsub_s LA64 0000 00010000 00101 fk:5 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fsub_d LA64 0000 00010000 00110 fk:5 fj:5 fd:5 -fmul_s LA64 0000 00010000 01001 fk:5 fj:5 fd:5 +fmul_s LA64 0000 00010000 01001 fk:5 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fmul_d LA64 0000 00010000 01010 fk:5 fj:5 fd:5 -fdiv_s LA64 0000 00010000 01101 fk:5 fj:5 fd:5 +fdiv_s LA64 0000 00010000 01101 fk:5 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fdiv_d LA64 0000 00010000 01110 fk:5 fj:5 fd:5 -fmadd_s LA64 0000 10000001 fa:5 fk:5 fj:5 fd:5 +fmadd_s LA64 0000 10000001 fa:5 fk:5 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fmadd_d LA64 0000 10000010 fa:5 fk:5 fj:5 fd:5 -fmsub_s LA64 0000 10000101 fa:5 fk:5 fj:5 fd:5 +fmsub_s LA64 0000 10000101 fa:5 fk:5 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fmsub_d LA64 0000 10000110 fa:5 fk:5 fj:5 fd:5 -fnmadd_s LA64 0000 10001001 fa:5 fk:5 fj:5 fd:5 +fnmadd_s LA64 0000 10001001 fa:5 fk:5 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fnmadd_d LA64 0000 10001010 fa:5 fk:5 fj:5 fd:5 -fnmsub_s LA64 0000 10001101 fa:5 fk:5 fj:5 fd:5 +fnmsub_s LA64 0000 10001101 fa:5 fk:5 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fnmsub_d LA64 0000 10001110 fa:5 fk:5 fj:5 fd:5 -fmax_s LA64 0000 00010000 10001 fk:5 fj:5 fd:5 +fmax_s LA64 0000 00010000 10001 fk:5 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fmax_d LA64 0000 00010000 10010 fk:5 fj:5 fd:5 -fmin_s LA64 0000 00010000 10101 fk:5 fj:5 fd:5 +fmin_s LA64 0000 00010000 10101 fk:5 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fmin_d LA64 0000 00010000 10110 fk:5 fj:5 fd:5 -fmaxa_s LA64 0000 00010000 11001 fk:5 fj:5 fd:5 +fmaxa_s LA64 0000 00010000 11001 fk:5 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fmaxa_d LA64 0000 00010000 11010 fk:5 fj:5 fd:5 -fmina_s LA64 0000 00010000 11101 fk:5 fj:5 fd:5 +fmina_s LA64 0000 00010000 11101 fk:5 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fmina_d LA64 0000 00010000 11110 fk:5 fj:5 fd:5 -fabs_s LA64 0000 00010001 01000 00001 fj:5 fd:5 +fabs_s LA64 0000 00010001 01000 00001 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fabs_d LA64 0000 00010001 01000 00010 fj:5 fd:5 -fneg_s LA64 0000 00010001 01000 00101 fj:5 fd:5 +fneg_s LA64 0000 00010001 01000 00101 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fneg_d LA64 0000 00010001 01000 00110 fj:5 fd:5 -fsqrt_s LA64 0000 00010001 01000 10001 fj:5 fd:5 +fsqrt_s LA64 0000 00010001 01000 10001 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fsqrt_d LA64 0000 00010001 01000 10010 fj:5 fd:5 -frecip_s LA64 0000 00010001 01000 10101 fj:5 fd:5 +frecip_s LA64 0000 00010001 01000 10101 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } frecip_d LA64 0000 00010001 01000 10110 fj:5 fd:5 -frsqrt_s LA64 0000 00010001 01000 11001 fj:5 fd:5 +frsqrt_s LA64 0000 00010001 01000 11001 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } frsqrt_d LA64 0000 00010001 01000 11010 fj:5 fd:5 -fscaleb_s LA64 0000 00010001 00001 fk:5 fj:5 fd:5 +fscaleb_s LA64 0000 00010001 00001 fk:5 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fscaleb_d LA64 0000 00010001 00010 fk:5 fj:5 fd:5 -flogb_s LA64 0000 00010001 01000 01001 fj:5 fd:5 +flogb_s LA64 0000 00010001 01000 01001 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } flogb_d LA64 0000 00010001 01000 01010 fj:5 fd:5 -fcopysign_s LA64 0000 00010001 00101 fk:5 fj:5 fd:5 +fcopysign_s LA64 0000 00010001 00101 fk:5 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fcopysign_d LA64 0000 00010001 00110 fk:5 fj:5 fd:5 -fclass_s LA64 0000 00010001 01000 01101 fj:5 fd:5 +fclass_s LA64 0000 00010001 01000 01101 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fclass_d LA64 0000 00010001 01000 01110 fj:5 fd:5 =20 # @@ -490,43 +511,59 @@ fcmp_cond_d LA64 0000 11000010 cond:5 fk:5 fj:5 00 cd= :3 \ # # Floating point conversion instruction # -fcvt_s_d LA64 0000 00010001 10010 00110 fj:5 fd:5 +fcvt_s_d LA64 0000 00010001 10010 00110 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fcvt_d_s LA64 0000 00010001 10010 01001 fj:5 fd:5 -ftintrm_w_s LA64 0000 00010001 10100 00001 fj:5 fd:5 -ftintrm_w_d LA64 0000 00010001 10100 00010 fj:5 fd:5 +ftintrm_w_s LA64 0000 00010001 10100 00001 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } +ftintrm_w_d LA64 0000 00010001 10100 00010 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } ftintrm_l_s LA64 0000 00010001 10100 01001 fj:5 fd:5 ftintrm_l_d LA64 0000 00010001 10100 01010 fj:5 fd:5 -ftintrp_w_s LA64 0000 00010001 10100 10001 fj:5 fd:5 -ftintrp_w_d LA64 0000 00010001 10100 10010 fj:5 fd:5 +ftintrp_w_s LA64 0000 00010001 10100 10001 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } +ftintrp_w_d LA64 0000 00010001 10100 10010 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } ftintrp_l_s LA64 0000 00010001 10100 11001 fj:5 fd:5 ftintrp_l_d LA64 0000 00010001 10100 11010 fj:5 fd:5 -ftintrz_w_s LA64 0000 00010001 10101 00001 fj:5 fd:5 -ftintrz_w_d LA64 0000 00010001 10101 00010 fj:5 fd:5 +ftintrz_w_s LA64 0000 00010001 10101 00001 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } +ftintrz_w_d LA64 0000 00010001 10101 00010 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } ftintrz_l_s LA64 0000 00010001 10101 01001 fj:5 fd:5 ftintrz_l_d LA64 0000 00010001 10101 01010 fj:5 fd:5 -ftintrne_w_s LA64 0000 00010001 10101 10001 fj:5 fd:5 -ftintrne_w_d LA64 0000 00010001 10101 10010 fj:5 fd:5 +ftintrne_w_s LA64 0000 00010001 10101 10001 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } +ftintrne_w_d LA64 0000 00010001 10101 10010 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } ftintrne_l_s LA64 0000 00010001 10101 11001 fj:5 fd:5 ftintrne_l_d LA64 0000 00010001 10101 11010 fj:5 fd:5 -ftint_w_s LA64 0000 00010001 10110 00001 fj:5 fd:5 -ftint_w_d LA64 0000 00010001 10110 00010 fj:5 fd:5 +ftint_w_s LA64 0000 00010001 10110 00001 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } +ftint_w_d LA64 0000 00010001 10110 00010 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } ftint_l_s LA64 0000 00010001 10110 01001 fj:5 fd:5 ftint_l_d LA64 0000 00010001 10110 01010 fj:5 fd:5 -ffint_s_w LA64 0000 00010001 11010 00100 fj:5 fd:5 -ffint_s_l LA64 0000 00010001 11010 00110 fj:5 fd:5 +ffint_s_w LA64 0000 00010001 11010 00100 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } +ffint_s_l LA64 0000 00010001 11010 00110 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } ffint_d_w LA64 0000 00010001 11010 01000 fj:5 fd:5 ffint_d_l LA64 0000 00010001 11010 01010 fj:5 fd:5 -frint_s LA64 0000 00010001 11100 10001 fj:5 fd:5 +frint_s LA64 0000 00010001 11100 10001 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } frint_d LA64 0000 00010001 11100 10010 fj:5 fd:5 =20 # # Floating point move instruction # -fmov_s LA64 0000 00010001 01001 00101 fj:5 fd:5 +fmov_s LA64 0000 00010001 01001 00101 fj:5 fd:5 \ + !safefloat { nanbox_s($fd); } fmov_d LA64 0000 00010001 01001 00110 fj:5 fd:5 fsel LA64 0000 11010000 00 ca:3 fk:5 fj:5 fd:5 movgr2fr_w LA64 0000 00010001 01001 01001 rj:5 fd:5 \ - !constraints { $rj !=3D 2; } + !constraints { $rj !=3D 2; } \ + !safefloat { nanbox_s($fd); } movgr2fr_d LA64 0000 00010001 01001 01010 rj:5 fd:5 \ !constraints { $rj !=3D 2; } movgr2frh_w LA64 0000 00010001 01001 01011 rj:5 fd:5 \ @@ -549,7 +586,8 @@ movcf2gr LA64 0000 00010001 01001 10111 00 cj:3 rd:5 \ # fld_s LA64 0010 101100 si12:12 rj:5 fd:5 \ !constraints { $rj !=3D 0 && $rj !=3D 2; } \ - !memory { reg_plus_imm($rj, sextract($si12, 12)); } + !memory { reg_plus_imm($rj, sextract($si12, 12)); } \ + !safefloat { nanbox_s($fd); } fst_s LA64 0010 101101 si12:12 rj:5 fd:5 \ !constraints { $rj !=3D 0 && $rj !=3D 2; } \ !memory { reg_plus_imm($rj, sextract($si12, 12)); } @@ -561,7 +599,8 @@ fst_d LA64 0010 101111 si12:12 rj:5 fd:5 \ !memory { reg_plus_imm($rj, sextract($si12, 12)); } fldx_s LA64 0011 10000011 00000 rk:5 rj:5 fd:5 \ !constraints { $rj !=3D 0 && $rj !=3D $rk && $rk !=3D 2 && $rj !=3D 2;= } \ - !memory { reg_plus_reg($rj, $rk); } + !memory { reg_plus_reg($rj, $rk); } \ + !safefloat { nanbox_s($fd); } fldx_d LA64 0011 10000011 01000 rk:5 rj:5 fd:5 \ !constraints { $rj !=3D 0 && $rj !=3D $rk && $rk !=3D 2 && $rj !=3D 2;= } \ !memory { reg_plus_reg($rj, $rk); } diff --git a/risugen b/risugen index e690b18..fa94a39 100755 --- a/risugen +++ b/risugen @@ -43,7 +43,7 @@ my @pattern_re =3D (); # include pattern my @not_pattern_re =3D (); # exclude pattern =20 # Valid block names (keys in blocks hash) -my %valid_blockname =3D ( constraints =3D> 1, memory =3D> 1 ); +my %valid_blockname =3D ( constraints =3D> 1, memory =3D> 1, safefloat =3D= >1 ); =20 sub parse_risu_directive($$@) { diff --git a/risugen_loongarch64.pm b/risugen_loongarch64.pm index 693fb71..8ab598b 100644 --- a/risugen_loongarch64.pm +++ b/risugen_loongarch64.pm @@ -66,6 +66,28 @@ sub set_reg_w($) return $reg; } =20 +sub write_orn_rrr($$$) +{ + my($rd, $rj, $rk)=3D@_; + # $rd =3D $rj | (~$rk) + insn32(0x160000 | $rk << 10 | $rj << 5 | $rd); +} + +sub nanbox_s($) +{ + my ($fpreg)=3D@_; + + # Set $fpreg register high 32bit ffffffff + # use r1 as a temp register + # r1 =3D r1 | ~(r0) + write_orn_rrr(1, 1, 0); + + # movgr2frh.w $fpreg ,$1 + insn32(0x114ac00 | 1 << 5 | $fpreg); + + return $fpreg; +} + sub align($) { my ($a) =3D @_; @@ -395,6 +417,7 @@ sub gen_one_insn($$) my $fixedbitmask =3D $rec->{fixedbitmask}; my $constraint =3D $rec->{blocks}{"constraints"}; my $memblock =3D $rec->{blocks}{"memory"}; + my $safefloat =3D $rec->{blocks}{"safefloat"}; =20 $insn &=3D ~$fixedbitmask; $insn |=3D $fixedbits; @@ -431,6 +454,13 @@ sub gen_one_insn($$) =20 insn32($insn); =20 + if (defined $safefloat) { + # Some result only care about low 32bit, + # so we use nanbox_s() make sure that high 32bit is 0xffffffff; + my $resultreg; + $resultreg =3D eval_with_fields($insnname, $insn, $rec, "safef= loat", $safefloat); + } + if (defined $memblock) { # Clean up following a memory access instruction: # we need to turn the (possibly written-back) basereg --=20 2.31.1