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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1663174476080100001 We currently have hacks across the hw/ to reference current_cpu to work out what the current accessing CPU is. This breaks in some cases including using gdbstub to access HW state. As we have MemTxAttrs to describe details about the access lets extend it to mention if this is a CPU access and which one it is. There are a number of places we need to fix up including: CPU helpers directly calling address_space_*() fns models in hw/ fishing the data out of current_cpu I'll start addressing some of these in following patches. Signed-off-by: Alex Benn=C3=A9e --- include/exec/memattrs.h | 4 +++- accel/tcg/cputlb.c | 22 ++++++++++++++++------ hw/core/cpu-sysemu.c | 17 +++++++++++++---- 3 files changed, 32 insertions(+), 11 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 9fb98bc1ef..3bccd5d291 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -43,7 +43,9 @@ typedef struct MemTxAttrs { * (see MEMTX_ACCESS_ERROR). */ unsigned int memory:1; - /* Requester ID (for MSI for example) */ + /* Requester is CPU (or as CPU, e.g. debug) */ + unsigned int requester_cpu:1; + /* Requester ID (for MSI for example) or cpu_index */ unsigned int requester_id:16; /* Invert endianness for this page */ unsigned int byte_swap:1; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 8fad2d9b83..68dc7dc646 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1340,8 +1340,13 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLB= Entry *iotlbentry, uint64_t val; bool locked =3D false; MemTxResult r; + MemTxAttrs attrs =3D iotlbentry->attrs; =20 - section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); + /* encode the accessing CPU */ + attrs.requester_cpu =3D 1; + attrs.requester_id =3D cpu->cpu_index; + + section =3D iotlb_to_section(cpu, iotlbentry->addr, attrs); mr =3D section->mr; mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc =3D retaddr; @@ -1353,14 +1358,14 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTL= BEntry *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_read(mr, mr_offset, &val, op, iotlbentry-= >attrs); + r =3D memory_region_dispatch_read(mr, mr_offset, &val, op, attrs); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - section->offset_within_region; =20 cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), access= _type, - mmu_idx, iotlbentry->attrs, r, retaddr); + mmu_idx, attrs, r, retaddr); } if (locked) { qemu_mutex_unlock_iothread(); @@ -1395,8 +1400,13 @@ static void io_writex(CPUArchState *env, CPUIOTLBEnt= ry *iotlbentry, MemoryRegion *mr; bool locked =3D false; MemTxResult r; + MemTxAttrs attrs =3D iotlbentry->attrs; + + /* encode the accessing CPU */ + attrs.requester_cpu =3D 1; + attrs.requester_id =3D cpu->cpu_index; =20 - section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); + section =3D iotlb_to_section(cpu, iotlbentry->addr, attrs); mr =3D section->mr; mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; if (!cpu->can_do_io) { @@ -1414,14 +1424,14 @@ static void io_writex(CPUArchState *env, CPUIOTLBEn= try *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_write(mr, mr_offset, val, op, iotlbentry-= >attrs); + r =3D memory_region_dispatch_write(mr, mr_offset, val, op, attrs); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - section->offset_within_region; =20 cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), - MMU_DATA_STORE, mmu_idx, iotlbentry->attrs,= r, + MMU_DATA_STORE, mmu_idx, attrs, r, retaddr); } if (locked) { diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index 00253f8929..bd7ae983ed 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -51,13 +51,22 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vad= dr addr, MemTxAttrs *attrs) { CPUClass *cc =3D CPU_GET_CLASS(cpu); + MemTxAttrs local =3D { }; + hwaddr res; =20 if (cc->sysemu_ops->get_phys_page_attrs_debug) { - return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs); + res =3D cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, &loca= l); + } else { + /* Fallback for CPUs which don't implement the _attrs_ hook */ + local =3D MEMTXATTRS_UNSPECIFIED; + res =3D cc->sysemu_ops->get_phys_page_debug(cpu, addr); } - /* Fallback for CPUs which don't implement the _attrs_ hook */ - *attrs =3D MEMTXATTRS_UNSPECIFIED; - return cc->sysemu_ops->get_phys_page_debug(cpu, addr); + + /* debug access is treated as though it came from the CPU */ + local.requester_cpu =3D 1; + local.requester_id =3D cpu->cpu_index; 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Wed, 14 Sep 2022 09:09:57 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Thomas Huth , Laurent Vivier , Paolo Bonzini Subject: [RFC PATCH 2/4] qtest: make read/write operation appear to be from CPU Date: Wed, 14 Sep 2022 17:09:53 +0100 Message-Id: <20220914160955.812151-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220914160955.812151-1-alex.bennee@linaro.org> References: <20220914160955.812151-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1663175707553100001 The point of qtest is to simulate how running code might interact with the system. However because it's not a real system we have places in the code which especially handle check qtest_enabled() before referencing current_cpu. Now we can encode these details in the MemTxAttrs lets do that so we can start removing them. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- softmmu/qtest.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/softmmu/qtest.c b/softmmu/qtest.c index f8acef2628..c086bd34b7 100644 --- a/softmmu/qtest.c +++ b/softmmu/qtest.c @@ -362,6 +362,13 @@ static void qtest_clock_warp(int64_t dest) qemu_clock_notify(QEMU_CLOCK_VIRTUAL); } =20 +/* + * QTest memory accesses are treated as though they come from the + * first (non-existent) CPU. We need to expose this via MemTxAttrs for + * those bits of HW which care which core is accessing them. + */ +#define MEMTXATTRS_QTEST ((MemTxAttrs) { .requester_cpu =3D 1 }) + static void qtest_process_command(CharBackend *chr, gchar **words) { const gchar *command; @@ -525,17 +532,17 @@ static void qtest_process_command(CharBackend *chr, g= char **words) } else if (words[0][5] =3D=3D 'w') { uint16_t data =3D value; tswap16s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIE= D, + address_space_write(first_cpu->as, addr, MEMTXATTRS_QTEST, &data, 2); } else if (words[0][5] =3D=3D 'l') { uint32_t data =3D value; tswap32s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIE= D, + address_space_write(first_cpu->as, addr, MEMTXATTRS_QTEST, &data, 4); } else if (words[0][5] =3D=3D 'q') { uint64_t data =3D value; tswap64s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIE= D, + address_space_write(first_cpu->as, addr, MEMTXATTRS_QTEST, &data, 8); } qtest_send_prefix(chr); @@ -554,21 +561,21 @@ static void qtest_process_command(CharBackend *chr, g= char **words) =20 if (words[0][4] =3D=3D 'b') { uint8_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_QTEST, &data, 1); value =3D data; } else if (words[0][4] =3D=3D 'w') { uint16_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_QTEST, &data, 2); value =3D tswap16(data); } else if (words[0][4] =3D=3D 'l') { uint32_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_QTEST, &data, 4); value =3D tswap32(data); } else if (words[0][4] =3D=3D 'q') { - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_QTEST, &value, 8); tswap64s(&value); } @@ -589,7 +596,7 @@ static void qtest_process_command(CharBackend *chr, gch= ar **words) g_assert(len); =20 data =3D g_malloc(len); - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, da= ta, + address_space_read(first_cpu->as, addr, MEMTXATTRS_QTEST, data, len); =20 enc =3D g_malloc(2 * len + 1); @@ -615,7 +622,7 @@ static void qtest_process_command(CharBackend *chr, gch= ar **words) g_assert(ret =3D=3D 0); =20 data =3D g_malloc(len); - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, da= ta, + address_space_read(first_cpu->as, addr, MEMTXATTRS_QTEST, data, len); b64_data =3D g_base64_encode(data, len); qtest_send_prefix(chr); @@ -650,7 +657,7 @@ static void qtest_process_command(CharBackend *chr, gch= ar **words) data[i] =3D 0; } } - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, d= ata, + address_space_write(first_cpu->as, addr, MEMTXATTRS_QTEST, data, len); g_free(data); =20 @@ -673,7 +680,7 @@ static void qtest_process_command(CharBackend *chr, gch= ar **words) if (len) { data =3D g_malloc(len); memset(data, pattern, len); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIE= D, + address_space_write(first_cpu->as, addr, MEMTXATTRS_QTEST, data, len); g_free(data); } @@ -707,7 +714,7 @@ static void qtest_process_command(CharBackend *chr, gch= ar **words) out_len =3D MIN(out_len, len); } =20 - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, d= ata, + address_space_write(first_cpu->as, addr, MEMTXATTRS_QTEST, data, len); =20 qtest_send_prefix(chr); --=20 2.34.1 From nobody Mon Feb 9 08:36:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1663174509; cv=none; d=zohomail.com; s=zohoarc; b=IllFQK7E2gFBvZR2BD6c0SIkIEVxvh4lgs1tnO+h2U+mxEmPVKllYYlRC1js7X7Igt5Ty0AM00XR6cC3vBcmPzYhikdHnB4SNuLLEbSe8HbkK4gouVGg6i15RFu6X94cZ07KwQMo5WVXNplalIa/rUJT9CDbhsI+99BcWAmLdbk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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Wed, 14 Sep 2022 09:09:57 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell Subject: [RFC PATCH 3/4] hw/intc/gic: use MxTxAttrs to divine accessing CPU Date: Wed, 14 Sep 2022 17:09:54 +0100 Message-Id: <20220914160955.812151-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220914160955.812151-1-alex.bennee@linaro.org> References: <20220914160955.812151-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1663174510229100001 Now that MxTxAttrs encodes a CPU we should use that to figure it out. This solves edge cases like accessing via gdbstub or qtest. Signed-off-by: Alex Benn=C3=A9e Resolves: https://gitlab.com/qemu-project/qemu/-/issues/124 Reviewed-by: Richard Henderson --- hw/intc/arm_gic.c | 39 ++++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 492b2421ab..7feedac735 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -56,17 +56,22 @@ static const uint8_t gic_id_gicv2[] =3D { 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; =20 -static inline int gic_get_current_cpu(GICState *s) +static inline int gic_get_current_cpu(GICState *s, MemTxAttrs attrs) { - if (!qtest_enabled() && s->num_cpu > 1) { - return current_cpu->cpu_index; - } - return 0; + /* + * Something other than a CPU accessing the GIC would be a bug as + * would a CPU index higher than the GICState expects to be + * handling + */ + g_assert(attrs.requester_cpu =3D=3D 1); + g_assert(attrs.requester_id < s->num_cpu); + + return attrs.requester_id; } =20 -static inline int gic_get_current_vcpu(GICState *s) +static inline int gic_get_current_vcpu(GICState *s, MemTxAttrs attrs) { - return gic_get_current_cpu(s) + GIC_NCPU; + return gic_get_current_cpu(s, attrs) + GIC_NCPU; } =20 /* Return true if this GIC config has interrupt groups, which is @@ -951,7 +956,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr off= set, MemTxAttrs attrs) int cm; int mask; =20 - cpu =3D gic_get_current_cpu(s); + cpu =3D gic_get_current_cpu(s, attrs); cm =3D 1 << cpu; if (offset < 0x100) { if (offset =3D=3D 0) { /* GICD_CTLR */ @@ -1182,7 +1187,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offs= et, int i; int cpu; =20 - cpu =3D gic_get_current_cpu(s); + cpu =3D gic_get_current_cpu(s, attrs); if (offset < 0x100) { if (offset =3D=3D 0) { if (s->security_extn && !attrs.secure) { @@ -1476,7 +1481,7 @@ static void gic_dist_writel(void *opaque, hwaddr offs= et, int mask; int target_cpu; =20 - cpu =3D gic_get_current_cpu(s); + cpu =3D gic_get_current_cpu(s, attrs); irq =3D value & 0xf; switch ((value >> 24) & 3) { case 0: @@ -1780,7 +1785,7 @@ static MemTxResult gic_thiscpu_read(void *opaque, hwa= ddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { GICState *s =3D (GICState *)opaque; - return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); + return gic_cpu_read(s, gic_get_current_cpu(s, attrs), addr, data, attr= s); } =20 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, @@ -1788,7 +1793,7 @@ static MemTxResult gic_thiscpu_write(void *opaque, hw= addr addr, MemTxAttrs attrs) { GICState *s =3D (GICState *)opaque; - return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); + return gic_cpu_write(s, gic_get_current_cpu(s, attrs), addr, value, at= trs); } =20 /* Wrappers to read/write the GIC CPU interface for a specific CPU. @@ -1818,7 +1823,7 @@ static MemTxResult gic_thisvcpu_read(void *opaque, hw= addr addr, uint64_t *data, { GICState *s =3D (GICState *)opaque; =20 - return gic_cpu_read(s, gic_get_current_vcpu(s), addr, data, attrs); + return gic_cpu_read(s, gic_get_current_vcpu(s, attrs), addr, data, att= rs); } =20 static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, @@ -1827,7 +1832,7 @@ static MemTxResult gic_thisvcpu_write(void *opaque, h= waddr addr, { GICState *s =3D (GICState *)opaque; =20 - return gic_cpu_write(s, gic_get_current_vcpu(s), addr, value, attrs); + return gic_cpu_write(s, gic_get_current_vcpu(s, attrs), addr, value, a= ttrs); } =20 static uint32_t gic_compute_eisr(GICState *s, int cpu, int lr_start) @@ -1860,7 +1865,7 @@ static uint32_t gic_compute_elrsr(GICState *s, int cp= u, int lr_start) =20 static void gic_vmcr_write(GICState *s, uint32_t value, MemTxAttrs attrs) { - int vcpu =3D gic_get_current_vcpu(s); + int vcpu =3D gic_get_current_vcpu(s, attrs); uint32_t ctlr; uint32_t abpr; uint32_t bpr; @@ -1995,7 +2000,7 @@ static MemTxResult gic_thiscpu_hyp_read(void *opaque,= hwaddr addr, uint64_t *dat { GICState *s =3D (GICState *)opaque; =20 - return gic_hyp_read(s, gic_get_current_cpu(s), addr, data, attrs); + return gic_hyp_read(s, gic_get_current_cpu(s, attrs), addr, data, attr= s); } =20 static MemTxResult gic_thiscpu_hyp_write(void *opaque, hwaddr addr, @@ -2004,7 +2009,7 @@ static MemTxResult gic_thiscpu_hyp_write(void *opaque= , hwaddr addr, { GICState *s =3D (GICState *)opaque; =20 - return gic_hyp_write(s, gic_get_current_cpu(s), addr, value, attrs); + return gic_hyp_write(s, gic_get_current_cpu(s, attrs), addr, value, at= trs); } =20 static MemTxResult gic_do_hyp_read(void *opaque, hwaddr addr, uint64_t *da= ta, --=20 2.34.1 From nobody Mon Feb 9 08:36:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1663174723; cv=none; d=zohomail.com; s=zohoarc; b=LB5zZl0HcvwrQqa5NAdq57MT+KAMj9tRoW5KGYMFo19unmKZV0bjdZTjvn06PEluJWkiG2Y5Qst4ZHFbdmtYNGVRjwhXWwmvOH3rn/5jpME6g57Mb5O0nUNFytTs7X30HBKFSTzm3cQsCY51JRpb6bC+rODkRrmmJnHqU5zeMxE= ARC-Message-Signature: i=1; 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Wed, 14 Sep 2022 09:09:59 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell Subject: [RFC PATCH 4/4] hw/timer: convert mptimer access to attrs to derive cpu index Date: Wed, 14 Sep 2022 17:09:55 +0100 Message-Id: <20220914160955.812151-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220914160955.812151-1-alex.bennee@linaro.org> References: <20220914160955.812151-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1663174725489100001 This removes the hacks to deal with empty current_cpu. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- hw/timer/arm_mptimer.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index cdfca3000b..a7fe6ddc0d 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -41,9 +41,10 @@ * which is used in both the ARM11MPCore and Cortex-A9MP. */ =20 -static inline int get_current_cpu(ARMMPTimerState *s) +static inline int get_current_cpu(ARMMPTimerState *s, MemTxAttrs attrs) { - int cpu_id =3D current_cpu ? current_cpu->cpu_index : 0; + int cpu_id =3D attrs.requester_id; + g_assert(attrs.requester_cpu =3D=3D 1); =20 if (cpu_id >=3D s->num_cpu) { hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n", @@ -178,25 +179,27 @@ static void timerblock_write(void *opaque, hwaddr add= r, /* Wrapper functions to implement the "read timer/watchdog for * the current CPU" memory regions. */ -static uint64_t arm_thistimer_read(void *opaque, hwaddr addr, - unsigned size) +static MemTxResult arm_thistimer_read(void *opaque, hwaddr addr, uint64_t = *data, + unsigned size, MemTxAttrs attrs) { ARMMPTimerState *s =3D (ARMMPTimerState *)opaque; - int id =3D get_current_cpu(s); - return timerblock_read(&s->timerblock[id], addr, size); + int id =3D get_current_cpu(s, attrs); + *data =3D timerblock_read(&s->timerblock[id], addr, size); + return MEMTX_OK; } =20 -static void arm_thistimer_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) +static MemTxResult arm_thistimer_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, MemTxAttrs = attrs) { ARMMPTimerState *s =3D (ARMMPTimerState *)opaque; - int id =3D get_current_cpu(s); + int id =3D get_current_cpu(s, attrs); timerblock_write(&s->timerblock[id], addr, value, size); + return MEMTX_OK; } =20 static const MemoryRegionOps arm_thistimer_ops =3D { - .read =3D arm_thistimer_read, - .write =3D arm_thistimer_write, + .read_with_attrs =3D arm_thistimer_read, + .write_with_attrs =3D arm_thistimer_write, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, --=20 2.34.1