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([89.101.193.68]) by smtp.gmail.com with ESMTPSA id b11-20020a05600c4e0b00b003b492753826sm5164972wmq.43.2022.09.13.08.50.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Sep 2022 08:50:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date; bh=zPgXvBKfJfKdVLVw1MwG7vyTC/gmDC+uf6dtarBonqk=; b=EVrQjH9jDMdGKX9O1t9EWc8QgvM7RB3VVDSRWN9fO45AbDo2+4Md1b1DpeTsPSlghZ CcmCIBXcErm8dhO/aaX9flANv+O4GOjpbdNOX5vZ8DM/ih+fiAkcHGiG5+Yy9I4YrmcH uVUVDvSkzcAafwQ0a3nDsP32SBMm9x+DoIJTL+nN5lJ/y4rVDlvcwuyuhd50axJvGazW kEK3+eYLwo0/wB4GGUPCFQVIxiHHVsEsWDZYSUE777YXhVOXiV9CPloUm2iuseHbC9vD HhZoZknZCog7pykj+N/qmyao/X/uOh45c7AhjkakPyUbYbe4RE3x08Cluuozgox8W2eB mwCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date; bh=zPgXvBKfJfKdVLVw1MwG7vyTC/gmDC+uf6dtarBonqk=; b=4b/aIkrcDowzC6s5Q+FYHo/FR3cfQkyoeCgdDMNPR0i+eFP6cKXkguZTFcBvA/5VRT id4uXclj5Tx+3gDN6nKSV7nuNeAcL5JgfmE7+FoMVO493C8wnT04CHeFNdjpelBXpn3+ +QAiMZQuIKPgakMZa9+u9DbZHDRubN0cj7Ier2AIqOvAF6MTcDLmxOu3DleJhOrl4lTs 51ipz1QdfOtMjXWlqZAt0I9U0ggQ8PzQc3OkjRsjLlmZ8cEpOdIKIOSnC3o0Tcg/GY/p lWOAEEv/n0tjZMtqgwBWB1IS+NCJKsb4LUBlily32TzFPSw6mkbXyHnNytzlAiRCdITu SdVg== X-Gm-Message-State: ACgBeo1X/ymLRHTRWsLyE5REMgnKx/TxaZqlWEDovsFlfYvtq05HsjXD +c21a3mOoBbjP3zC12J8IUbH27ff0yAcnbRu X-Google-Smtp-Source: AA6agR5LfYAUxsLYbXAuqbpC+AHvdwrdY9mv1n0w9SrNRadOA459QgC933mqzS2DRPpwvI8llmRRjQ== X-Received: by 2002:adf:d1cc:0:b0:22a:450c:6208 with SMTP id b12-20020adfd1cc000000b0022a450c6208mr11600820wrd.696.1663084218167; Tue, 13 Sep 2022 08:50:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Idan Horowitz Subject: [PATCH] target/arm: Do alignment check when translation disabled Date: Tue, 13 Sep 2022 16:49:56 +0100 Message-Id: <20220913154956.12731-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1663084413776100001 Content-Type: text/plain; charset="utf-8" If translation is disabled, the default memory type is Device, which requires alignment checking. Document, but defer, the more general case of per-page alignment checking. Reported-by: Idan Horowitz Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1204 Signed-off-by: Richard Henderson --- target/arm/helper.c | 38 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d7bc467a2a..79609443aa 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10713,6 +10713,39 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) return arm_mmu_idx_el(env, arm_current_el(env)); } =20 +/* + * Return true if memory alignment should be enforced. + */ +static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t = sctlr) +{ + /* Check the alignment enable bit. */ + if (sctlr & SCTLR_A) { + return true; + } + + /* + * If translation is disabled, then the default memory type + * may be Device(-nGnRnE) instead of Normal, which requires that + * alignment be enforced. + * + * TODO: The more general case is translation enabled, with a per-page + * check of the memory type as assigned via MAIR_ELx and the PTE. + * We could arrange for a bit in MemTxAttrs to enforce alignment + * via forced use of the softmmu slow path. Given that such pages + * are intended for MMIO, where the slow path is required anyhow, + * this should not result in extra overhead. + */ + if (sctlr & SCTLR_M) { + /* Translation enabled: memory type in PTE via MAIR_ELx. */ + return false; + } + if (el < 2 && (arm_hcr_el2_eff(env) & (HCR_DC | HCR_VM))) { + /* Stage 2 translation enabled: memory type in PTE. */ + return false; + } + return true; +} + static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, CPUARMTBFlags flags) @@ -10777,8 +10810,9 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState= *env, int fp_el, { CPUARMTBFlags flags =3D {}; int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); =20 - if (arm_sctlr(env, el) & SCTLR_A) { + if (aprofile_require_alignment(env, el, sctlr)) { DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); } =20 @@ -10871,7 +10905,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState= *env, int el, int fp_el, =20 sctlr =3D regime_sctlr(env, stage1); =20 - if (sctlr & SCTLR_A) { + if (aprofile_require_alignment(env, el, sctlr)) { DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); } =20 --=20 2.34.1