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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662539398957100003 Content-Type: text/plain; charset="utf-8" From: Anup Patel We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Reviewed-by: Alistair Francis Signed-off-by: Anup Patel Acked-by: dramforever Message-Id: <20220630061150.905174-2-apatel@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 5 + target/riscv/instmap.h | 45 +++++++ target/riscv/cpu_helper.c | 252 +++++++++++++++++++++++++++++++++++++- 3 files changed, 296 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5c7acc055a..ffb1a18873 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -285,6 +285,11 @@ struct CPUArchState { /* Signals whether the current exception occurred with two-stage addre= ss translation active. */ bool two_stage_lookup; + /* + * Signals whether the current exception occurred while doing two-stage + * address translation for the VS-stage page table walk. + */ + bool two_stage_indirect_lookup; =20 target_ulong scounteren; target_ulong mcounteren; diff --git a/target/riscv/instmap.h b/target/riscv/instmap.h index 40b6d2b64d..f877530576 100644 --- a/target/riscv/instmap.h +++ b/target/riscv/instmap.h @@ -184,6 +184,8 @@ enum { OPC_RISC_CSRRWI =3D OPC_RISC_SYSTEM | (0x5 << 12), OPC_RISC_CSRRSI =3D OPC_RISC_SYSTEM | (0x6 << 12), OPC_RISC_CSRRCI =3D OPC_RISC_SYSTEM | (0x7 << 12), + + OPC_RISC_HLVHSV =3D OPC_RISC_SYSTEM | (0x4 << 12), }; =20 #define MASK_OP_FP_LOAD(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) @@ -310,12 +312,20 @@ enum { | (extract32(inst, 12, 8) << 12) \ | (sextract64(inst, 31, 1) << 20)) =20 +#define GET_FUNCT3(inst) extract32(inst, 12, 3) +#define GET_FUNCT7(inst) extract32(inst, 25, 7) #define GET_RM(inst) extract32(inst, 12, 3) #define GET_RS3(inst) extract32(inst, 27, 5) #define GET_RS1(inst) extract32(inst, 15, 5) #define GET_RS2(inst) extract32(inst, 20, 5) #define GET_RD(inst) extract32(inst, 7, 5) #define GET_IMM(inst) sextract64(inst, 20, 12) +#define SET_RS1(inst, val) deposit32(inst, 15, 5, val) +#define SET_RS2(inst, val) deposit32(inst, 20, 5, val) +#define SET_RD(inst, val) deposit32(inst, 7, 5, val) +#define SET_I_IMM(inst, val) deposit32(inst, 20, 12, val) +#define SET_S_IMM(inst, val) \ + deposit32(deposit32(inst, 7, 5, val), 25, 7, (val) >> 5) =20 /* RVC decoding macros */ #define GET_C_IMM(inst) (extract32(inst, 2, 5) \ @@ -346,6 +356,8 @@ enum { | (extract32(inst, 5, 1) << 6)) #define GET_C_LD_IMM(inst) ((extract16(inst, 10, 3) << 3) \ | (extract16(inst, 5, 2) << 6)) +#define GET_C_SW_IMM(inst) GET_C_LW_IMM(inst) +#define GET_C_SD_IMM(inst) GET_C_LD_IMM(inst) #define GET_C_J_IMM(inst) ((extract32(inst, 3, 3) << 1) \ | (extract32(inst, 11, 1) << 4) \ | (extract32(inst, 2, 1) << 5) \ @@ -366,4 +378,37 @@ enum { #define GET_C_RS1S(inst) (8 + extract16(inst, 7, 3)) #define GET_C_RS2S(inst) (8 + extract16(inst, 2, 3)) =20 +#define GET_C_FUNC(inst) extract32(inst, 13, 3) +#define GET_C_OP(inst) extract32(inst, 0, 2) + +enum { + /* RVC Quadrants */ + OPC_RISC_C_OP_QUAD0 =3D 0x0, + OPC_RISC_C_OP_QUAD1 =3D 0x1, + OPC_RISC_C_OP_QUAD2 =3D 0x2 +}; + +enum { + /* RVC Quadrant 0 */ + OPC_RISC_C_FUNC_ADDI4SPN =3D 0x0, + OPC_RISC_C_FUNC_FLD_LQ =3D 0x1, + OPC_RISC_C_FUNC_LW =3D 0x2, + OPC_RISC_C_FUNC_FLW_LD =3D 0x3, + OPC_RISC_C_FUNC_FSD_SQ =3D 0x5, + OPC_RISC_C_FUNC_SW =3D 0x6, + OPC_RISC_C_FUNC_FSW_SD =3D 0x7 +}; + +enum { + /* RVC Quadrant 2 */ + OPC_RISC_C_FUNC_SLLI_SLLI64 =3D 0x0, + OPC_RISC_C_FUNC_FLDSP_LQSP =3D 0x1, + OPC_RISC_C_FUNC_LWSP =3D 0x2, + OPC_RISC_C_FUNC_FLWSP_LDSP =3D 0x3, + OPC_RISC_C_FUNC_JR_MV_EBREAK_JALR_ADD =3D 0x4, + OPC_RISC_C_FUNC_FSDSP_SQSP =3D 0x5, + OPC_RISC_C_FUNC_SWSP =3D 0x6, + OPC_RISC_C_FUNC_FSWSP_SDSP =3D 0x7 +}; + #endif diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 59b3680b1b..87daf7220f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -22,6 +22,7 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "exec/exec-all.h" +#include "instmap.h" #include "tcg/tcg-op.h" #include "trace.h" #include "semihosting/common-semi.h" @@ -1053,7 +1054,8 @@ restart: =20 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, MMUAccessType access_type, bool pmp_violat= ion, - bool first_stage, bool two_stage) + bool first_stage, bool two_stage, + bool two_stage_indirect) { CPUState *cs =3D env_cpu(env); int page_fault_exceptions, vm; @@ -1103,6 +1105,7 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, } env->badaddr =3D address; env->two_stage_lookup =3D two_stage; + env->two_stage_indirect_lookup =3D two_stage_indirect; } =20 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) @@ -1148,6 +1151,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hw= addr physaddr, env->badaddr =3D addr; env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); + env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); } =20 @@ -1173,6 +1177,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, env->badaddr =3D addr; env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); + env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); } =20 @@ -1188,6 +1193,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, bool pmp_violation =3D false; bool first_stage_error =3D true; bool two_stage_lookup =3D false; + bool two_stage_indirect_error =3D false; int ret =3D TRANSLATE_FAIL; int mode =3D mmu_idx; /* default TLB page size */ @@ -1225,6 +1231,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, */ if (ret =3D=3D TRANSLATE_G_STAGE_FAIL) { first_stage_error =3D false; + two_stage_indirect_error =3D true; access_type =3D MMU_DATA_LOAD; } =20 @@ -1308,12 +1315,218 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr addres= s, int size, raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error, riscv_cpu_virt_enabled(env) || - riscv_cpu_two_stage_lookup(mmu_idx)); + riscv_cpu_two_stage_lookup(mmu_idx), + two_stage_indirect_error); cpu_loop_exit_restore(cs, retaddr); } =20 return true; } + +static target_ulong riscv_transformed_insn(CPURISCVState *env, + target_ulong insn, + target_ulong taddr) +{ + target_ulong xinsn =3D 0; + target_ulong access_rs1 =3D 0, access_imm =3D 0, access_size =3D 0; + + /* + * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to + * be uncompressed. The Quadrant 1 of RVC instruction space need + * not be transformed because these instructions won't generate + * any load/store trap. + */ + + if ((insn & 0x3) !=3D 0x3) { + /* Transform 16bit instruction into 32bit instruction */ + switch (GET_C_OP(insn)) { + case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ + switch (GET_C_FUNC(insn)) { + case OPC_RISC_C_FUNC_FLD_LQ: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FLD (RV32/64) */ + xinsn =3D OPC_RISC_FLD; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_LD_IMM(insn); + access_size =3D 8; + } + break; + case OPC_RISC_C_FUNC_LW: /* C.LW */ + xinsn =3D OPC_RISC_LW; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_LW_IMM(insn); + access_size =3D 4; + break; + case OPC_RISC_C_FUNC_FLW_LD: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FLW (RV32) */ + xinsn =3D OPC_RISC_FLW; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_LW_IMM(insn); + access_size =3D 4; + } else { /* C.LD (RV64/RV128) */ + xinsn =3D OPC_RISC_LD; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_LD_IMM(insn); + access_size =3D 8; + } + break; + case OPC_RISC_C_FUNC_FSD_SQ: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FSD (RV32/64) */ + xinsn =3D OPC_RISC_FSD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_SD_IMM(insn); + access_size =3D 8; + } + break; + case OPC_RISC_C_FUNC_SW: /* C.SW */ + xinsn =3D OPC_RISC_SW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_SW_IMM(insn); + access_size =3D 4; + break; + case OPC_RISC_C_FUNC_FSW_SD: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FSW (RV32) */ + xinsn =3D OPC_RISC_FSW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_SW_IMM(insn); + access_size =3D 4; + } else { /* C.SD (RV64/RV128) */ + xinsn =3D OPC_RISC_SD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_SD_IMM(insn); + access_size =3D 8; + } + break; + default: + break; + } + break; + case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ + switch (GET_C_FUNC(insn)) { + case OPC_RISC_C_FUNC_FLDSP_LQSP: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FLDSP (RV32/64) */ + xinsn =3D OPC_RISC_FLD; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_LDSP_IMM(insn); + access_size =3D 8; + } + break; + case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ + xinsn =3D OPC_RISC_LW; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_LWSP_IMM(insn); + access_size =3D 4; + break; + case OPC_RISC_C_FUNC_FLWSP_LDSP: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FLWSP (RV32) */ + xinsn =3D OPC_RISC_FLW; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_LWSP_IMM(insn); + access_size =3D 4; + } else { /* C.LDSP (RV64/RV128) */ + xinsn =3D OPC_RISC_LD; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_LDSP_IMM(insn); + access_size =3D 8; + } + break; + case OPC_RISC_C_FUNC_FSDSP_SQSP: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FSDSP (RV32/64) */ + xinsn =3D OPC_RISC_FSD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_SDSP_IMM(insn); + access_size =3D 8; + } + break; + case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ + xinsn =3D OPC_RISC_SW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_SWSP_IMM(insn); + access_size =3D 4; + break; + case 7: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FSWSP (RV32) */ + xinsn =3D OPC_RISC_FSW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_SWSP_IMM(insn); + access_size =3D 4; + } else { /* C.SDSP (RV64/RV128) */ + xinsn =3D OPC_RISC_SD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_SDSP_IMM(insn); + access_size =3D 8; + } + break; + default: + break; + } + break; + default: + break; + } + + /* + * Clear Bit1 of transformed instruction to indicate that + * original insruction was a 16bit instruction + */ + xinsn &=3D ~((target_ulong)0x2); + } else { + /* Transform 32bit (or wider) instructions */ + switch (MASK_OP_MAJOR(insn)) { + case OPC_RISC_ATOMIC: + xinsn =3D insn; + access_rs1 =3D GET_RS1(insn); + access_size =3D 1 << GET_FUNCT3(insn); + break; + case OPC_RISC_LOAD: + case OPC_RISC_FP_LOAD: + xinsn =3D SET_I_IMM(insn, 0); + access_rs1 =3D GET_RS1(insn); + access_imm =3D GET_IMM(insn); + access_size =3D 1 << GET_FUNCT3(insn); + break; + case OPC_RISC_STORE: + case OPC_RISC_FP_STORE: + xinsn =3D SET_S_IMM(insn, 0); + access_rs1 =3D GET_RS1(insn); + access_imm =3D GET_STORE_IMM(insn); + access_size =3D 1 << GET_FUNCT3(insn); + break; + case OPC_RISC_SYSTEM: + if (MASK_OP_SYSTEM(insn) =3D=3D OPC_RISC_HLVHSV) { + xinsn =3D insn; + access_rs1 =3D GET_RS1(insn); + access_size =3D 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); + access_size =3D 1 << access_size; + } + break; + default: + break; + } + } + + if (access_size) { + xinsn =3D SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_i= mm)) & + (access_size - 1)); + } + + return xinsn; +} #endif /* !CONFIG_USER_ONLY */ =20 /* @@ -1338,6 +1551,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong cause =3D cs->exception_index & RISCV_EXCP_INT_MASK; uint64_t deleg =3D async ? env->mideleg : env->medeleg; target_ulong tval =3D 0; + target_ulong tinst =3D 0; target_ulong htval =3D 0; target_ulong mtval2 =3D 0; =20 @@ -1353,20 +1567,43 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { - case RISCV_EXCP_INST_GUEST_PAGE_FAULT: case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: - case RISCV_EXCP_INST_ADDR_MIS: - case RISCV_EXCP_INST_ACCESS_FAULT: case RISCV_EXCP_LOAD_ADDR_MIS: case RISCV_EXCP_STORE_AMO_ADDR_MIS: case RISCV_EXCP_LOAD_ACCESS_FAULT: case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: - case RISCV_EXCP_INST_PAGE_FAULT: case RISCV_EXCP_LOAD_PAGE_FAULT: case RISCV_EXCP_STORE_PAGE_FAULT: write_gva =3D env->two_stage_lookup; tval =3D env->badaddr; + if (env->two_stage_indirect_lookup) { + /* + * special pseudoinstruction for G-stage fault taken while + * doing VS-stage page table walk. + */ + tinst =3D (riscv_cpu_xlen(env) =3D=3D 32) ? 0x00002000 : 0= x00003000; + } else { + /* + * The "Addr. Offset" field in transformed instruction is + * non-zero only for misaligned access. + */ + tinst =3D riscv_transformed_insn(env, env->bins, tval); + } + break; + case RISCV_EXCP_INST_GUEST_PAGE_FAULT: + case RISCV_EXCP_INST_ADDR_MIS: + case RISCV_EXCP_INST_ACCESS_FAULT: + case RISCV_EXCP_INST_PAGE_FAULT: + write_gva =3D env->two_stage_lookup; + tval =3D env->badaddr; + if (env->two_stage_indirect_lookup) { + /* + * special pseudoinstruction for G-stage fault taken while + * doing VS-stage page table walk. + */ + tinst =3D (riscv_cpu_xlen(env) =3D=3D 32) ? 0x00002000 : 0= x00003000; + } break; case RISCV_EXCP_ILLEGAL_INST: case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: @@ -1446,6 +1683,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->sepc =3D env->pc; env->stval =3D tval; env->htval =3D htval; + env->htinst =3D tinst; env->pc =3D (env->stvec >> 2 << 2) + ((async && (env->stvec & 3) =3D=3D 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_S); @@ -1476,6 +1714,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mepc =3D env->pc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662538790397100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel We should disable extensions in riscv_cpu_realize() if minimum required priv spec version is not satisfied. This also ensures that machines with priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter extensions. Fixes: a775398be2e9 ("target/riscv: Add isa extenstion strings to the devic= e tree") Reviewed-by: Alistair Francis Signed-off-by: Anup Patel Signed-off-by: Rahul Pathak Message-Id: <20220630061150.905174-3-apatel@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 150 ++++++++++++++++++++++++++++----------------- 1 file changed, 94 insertions(+), 56 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac6f82ebd0..cab74faaca 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -43,9 +43,82 @@ static const char riscv_single_letter_exts[] =3D "IEMAFD= QCPVH"; =20 struct isa_ext_data { const char *name; - bool enabled; + bool multi_letter; + int min_version; + int ext_enable_offset; }; =20 +#define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ +{#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} + +/** + * Here are the ordering rules of extension naming defined by RISC-V + * specification : + * 1. All extensions should be separated from other multi-letter extensions + * by an underscore. + * 2. The first letter following the 'Z' conventionally indicates the most + * closely related alphabetical extension category, IMAFDQLCBKJTPVH. + * If multiple 'Z' extensions are named, they should be ordered first + * by category, then alphabetically within a category. + * 3. Standard supervisor-level extensions (starts with 'S') should be + * listed after standard unprivileged extensions. If multiple + * supervisor-level extensions are listed, they should be ordered + * alphabetically. + * 4. Non-standard extensions (starts with 'X') must be listed after all + * standard extensions. They must be separated from other multi-letter + * extensions by an underscore. + */ +static const struct isa_ext_data isa_edata_arr[] =3D { + ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), + ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), + ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), + ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), + ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), + ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), + ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), + ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), + ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), + ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), + ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), + ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), + ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), + ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), + ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), + ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), + ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), + ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), + ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), + ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), + ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), + ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), + ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), + ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), + ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), + ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), + ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), + ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), + ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), + ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), + ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), +}; + +static bool isa_ext_is_enabled(RISCVCPU *cpu, + const struct isa_ext_data *edata) +{ + bool *ext_enabled =3D (void *)&cpu->cfg + edata->ext_enable_offset; + + return *ext_enabled; +} + +static void isa_ext_update_enabled(RISCVCPU *cpu, + const struct isa_ext_data *edata, bool = en) +{ + bool *ext_enabled =3D (void *)&cpu->cfg + edata->ext_enable_offset; + + *ext_enabled =3D en; +} + const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -530,7 +603,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); CPUClass *cc =3D CPU_CLASS(mcc); - int priv_version =3D -1; + int i, priv_version =3D -1; Error *local_err =3D NULL; =20 cpu_exec_realizefn(cs, &local_err); @@ -558,6 +631,23 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) set_priv_version(env, priv_version); } =20 + /* Force disable extensions if priv spec version does not match */ + for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { + if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && + (env->priv_ver < isa_edata_arr[i].min_version)) { + isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); +#ifndef CONFIG_USER_ONLY + warn_report("disabling %s extension for hart 0x%lx because " + "privilege spec version does not match", + isa_edata_arr[i].name, (unsigned long)env->mhartid= ); +#else + warn_report("disabling %s extension because " + "privilege spec version does not match", + isa_edata_arr[i].name); +#endif + } + } + if (cpu->cfg.mmu) { riscv_set_feature(env, RISCV_FEATURE_MMU); } @@ -1044,67 +1134,15 @@ static void riscv_cpu_class_init(ObjectClass *c, vo= id *data) device_class_set_props(dc, riscv_cpu_properties); } =20 -#define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop} - static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_st= r_len) { char *old =3D *isa_str; char *new =3D *isa_str; int i; =20 - /** - * Here are the ordering rules of extension naming defined by RISC-V - * specification : - * 1. All extensions should be separated from other multi-letter exten= sions - * by an underscore. - * 2. The first letter following the 'Z' conventionally indicates the = most - * closely related alphabetical extension category, IMAFDQLCBKJTPVH. - * If multiple 'Z' extensions are named, they should be ordered fir= st - * by category, then alphabetically within a category. - * 3. Standard supervisor-level extensions (starts with 'S') should be - * listed after standard unprivileged extensions. If multiple - * supervisor-level extensions are listed, they should be ordered - * alphabetically. - * 4. Non-standard extensions (starts with 'X') must be listed after a= ll - * standard extensions. They must be separated from other multi-let= ter - * extensions by an underscore. - */ - struct isa_ext_data isa_edata_arr[] =3D { - ISA_EDATA_ENTRY(zicsr, ext_icsr), - ISA_EDATA_ENTRY(zifencei, ext_ifencei), - ISA_EDATA_ENTRY(zmmul, ext_zmmul), - ISA_EDATA_ENTRY(zfh, ext_zfh), - ISA_EDATA_ENTRY(zfhmin, ext_zfhmin), - ISA_EDATA_ENTRY(zfinx, ext_zfinx), - ISA_EDATA_ENTRY(zdinx, ext_zdinx), - ISA_EDATA_ENTRY(zba, ext_zba), - ISA_EDATA_ENTRY(zbb, ext_zbb), - ISA_EDATA_ENTRY(zbc, ext_zbc), - ISA_EDATA_ENTRY(zbkb, ext_zbkb), - ISA_EDATA_ENTRY(zbkc, ext_zbkc), - ISA_EDATA_ENTRY(zbkx, ext_zbkx), - ISA_EDATA_ENTRY(zbs, ext_zbs), - ISA_EDATA_ENTRY(zk, ext_zk), - ISA_EDATA_ENTRY(zkn, ext_zkn), - ISA_EDATA_ENTRY(zknd, ext_zknd), - ISA_EDATA_ENTRY(zkne, ext_zkne), - ISA_EDATA_ENTRY(zknh, ext_zknh), - ISA_EDATA_ENTRY(zkr, ext_zkr), - ISA_EDATA_ENTRY(zks, ext_zks), - ISA_EDATA_ENTRY(zksed, ext_zksed), - ISA_EDATA_ENTRY(zksh, ext_zksh), - ISA_EDATA_ENTRY(zkt, ext_zkt), - ISA_EDATA_ENTRY(zve32f, ext_zve32f), - ISA_EDATA_ENTRY(zve64f, ext_zve64f), - ISA_EDATA_ENTRY(zhinx, ext_zhinx), - ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin), - ISA_EDATA_ENTRY(svinval, ext_svinval), - ISA_EDATA_ENTRY(svnapot, ext_svnapot), - ISA_EDATA_ENTRY(svpbmt, ext_svpbmt), - }; - for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_edata_arr[i].enabled) { + if (isa_edata_arr[i].multi_letter && + isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { new =3D g_strconcat(old, "_", isa_edata_arr[i].name, NULL); g_free(old); old =3D new; --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662538703; cv=none; d=zohomail.com; s=zohoarc; b=jAZVSzJBfTaQd2JLCIw0ZoatufYF2CDgNEDyGgYWY5DuBVAW0ZnN0hw3/7wBb+LzhUIJV1Z4LpMQw9I11f+nZXWGe0erV3o+G1Hs6pQbtFjV6R362u2hQxD2ygH2JTcWyedW/Sjnd9jkQTt70p6fFdOe/h+8UIZ/r/AqaeuKKUw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662538703; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; 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X-IronPort-AV: E=Sophos;i="5.93,296,1654531200"; d="scan'208";a="210714940" IronPort-SDR: rcg83WKInhBhiD5rpPn5dXjGUMpKgti9MvxtrHIbtFtqPcfjvkDexq6lSCGYLXlxIGS+u6VGwZ Fvhf7K5Mc1v4RGUTFhzGSPNFkSF9H/blR1KnS1UvF+IaQ9OzXeUJK0U/LaS/4lBOt04pzjT51p 2x2Y0vBHAEZRjwjqPBLViySemGTGOpP83AfA0SIqqxj8IhlIbqjF3LPm4burEe/9bZ+GjVAWV1 /uoaTHadcO1i4sLnXmYCMRwxKFK1DaE2FC2AR9Gv2RlZEaAjS2bfdhveH77Cj8Zgf0Niv39Wfp 9wN9DkG/ZrSdzcKdIHhP8AVU IronPort-SDR: hbIEeeV2in9qPneBzwLo6VvrYqBH4WhFnaCQXn5YImsvje2rXlLmaA/YUUCGE92zxIqLGcZFV3 uk7nR7diVxgoI+yC+Pr4yYIF+eibtyMR3RtFl0oFuRaICulTAdEuwtlb53FJBifn8uJwAxQMec nfFOXZK7tSbLqXglNCR7XUIW2Bz6v9wfGGmRFyy8dHdKYMflYHRZTNZqJ/yboY6vhNq1MpbMye HaS5+1IKgMeGCVU4OIVN8fMfszocEC5H50DTWA4NYq0x69m4eSsoYOFweC4mVbsymSWSqsxW+D bfk= WDCIronportException: Internal To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , Weiwei Li , Richard Henderson , Alistair Francis Subject: [PULL 03/44] target/riscv: fix shifts shamt value for rv128c Date: Wed, 7 Sep 2022 10:03:12 +0200 Message-Id: <20220907080353.111926-4-alistair.francis@wdc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907080353.111926-1-alistair.francis@wdc.com> References: <20220907080353.111926-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662538705619100001 From: Fr=C3=A9d=C3=A9ric P=C3=A9trot For rv128c shifts, a shamt of 0 is a shamt of 64, while for rv32c/rv64c it stays 0 and is a hint instruction that does not change processor state. For rv128c right shifts, the 6-bit shamt is in addition sign extended to 7 bits. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Reviewed-by: Weiwei Li Reviewed-by: Richard Henderson Message-Id: <20220710110451.245567-1-frederic.petrot@univ-grenoble-alpes.fr> Signed-off-by: Alistair Francis --- target/riscv/insn16.decode | 7 ++++--- disas/riscv.c | 27 +++++++++++++++++++++------ target/riscv/translate.c | 20 ++++++++++++++++++-- 3 files changed, 43 insertions(+), 11 deletions(-) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 02c8f61b48..ccfe59f294 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -31,7 +31,8 @@ %imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=3Dex_shift_1 %imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=3Dex_shift_1 =20 -%shimm_6bit 12:1 2:5 !function=3Dex_rvc_shifti +%shlimm_6bit 12:1 2:5 !function=3Dex_rvc_shiftli +%shrimm_6bit 12:1 2:5 !function=3Dex_rvc_shiftri %uimm_6bit_lq 2:4 12:1 6:1 !function=3Dex_shift_4 %uimm_6bit_ld 2:3 12:1 5:2 !function=3Dex_shift_3 %uimm_6bit_lw 2:2 12:1 4:3 !function=3Dex_shift_2 @@ -82,9 +83,9 @@ @c_addi16sp ... . ..... ..... .. &i imm=3D%imm_addi16sp rs1=3D2 rd=3D2 =20 @c_shift ... . .. ... ..... .. \ - &shift rd=3D%rs1_3 rs1=3D%rs1_3 shamt=3D%shimm_6bit + &shift rd=3D%rs1_3 rs1=3D%rs1_3 shamt=3D%shrimm_6bit @c_shift2 ... . .. ... ..... .. \ - &shift rd=3D%rd rs1=3D%rd shamt=3D%shimm_6bit + &shift rd=3D%rd rs1=3D%rd shamt=3D%shlimm_6bit =20 @c_andi ... . .. ... ..... .. &i imm=3D%imm_ci rs1=3D%rs1_3 rd=3D%= rs1_3 =20 diff --git a/disas/riscv.c b/disas/riscv.c index 7af6afc8fa..489c2ae5e8 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -2402,10 +2402,25 @@ static int32_t operand_sbimm12(rv_inst inst) ((inst << 56) >> 63) << 11; } =20 -static uint32_t operand_cimmsh6(rv_inst inst) +static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa) { - return ((inst << 51) >> 63) << 5 | + int imm =3D ((inst << 51) >> 63) << 5 | (inst << 57) >> 59; + if (isa =3D=3D rv128) { + imm =3D imm ? imm : 64; + } + return imm; +} + +static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa) +{ + int imm =3D ((inst << 51) >> 63) << 5 | + (inst << 57) >> 59; + if (isa =3D=3D rv128) { + imm =3D imm | (imm & 32) << 1; + imm =3D imm ? imm : 64; + } + return imm; } =20 static int32_t operand_cimmi(rv_inst inst) @@ -2529,7 +2544,7 @@ static uint32_t operand_rnum(rv_inst inst) =20 /* decode operands */ =20 -static void decode_inst_operands(rv_decode *dec) +static void decode_inst_operands(rv_decode *dec, rv_isa isa) { rv_inst inst =3D dec->inst; dec->codec =3D opcode_data[dec->op].codec; @@ -2652,7 +2667,7 @@ static void decode_inst_operands(rv_decode *dec) case rv_codec_cb_sh6: dec->rd =3D dec->rs1 =3D operand_crs1rdq(inst) + 8; dec->rs2 =3D rv_ireg_zero; - dec->imm =3D operand_cimmsh6(inst); + dec->imm =3D operand_cimmshr6(inst, isa); break; case rv_codec_ci: dec->rd =3D dec->rs1 =3D operand_crs1rd(inst); @@ -2667,7 +2682,7 @@ static void decode_inst_operands(rv_decode *dec) case rv_codec_ci_sh6: dec->rd =3D dec->rs1 =3D operand_crs1rd(inst); dec->rs2 =3D rv_ireg_zero; - dec->imm =3D operand_cimmsh6(inst); + dec->imm =3D operand_cimmshl6(inst, isa); break; case rv_codec_ci_16sp: dec->rd =3D rv_ireg_sp; @@ -3193,7 +3208,7 @@ disasm_inst(char *buf, size_t buflen, rv_isa isa, uin= t64_t pc, rv_inst inst) dec.pc =3D pc; dec.inst =3D inst; decode_inst_opcode(&dec, isa); - decode_inst_operands(&dec); + decode_inst_operands(&dec, isa); decode_inst_decompress(&dec, isa); decode_inst_lift_pseudo(&dec); format_inst(buf, buflen, 16, &dec); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f8af6daa70..6eeb728462 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -705,10 +705,26 @@ static int ex_rvc_register(DisasContext *ctx, int reg) return 8 + reg; } =20 -static int ex_rvc_shifti(DisasContext *ctx, int imm) +static int ex_rvc_shiftli(DisasContext *ctx, int imm) { /* For RV128 a shamt of 0 means a shift by 64. */ - return imm ? imm : 64; + if (get_ol(ctx) =3D=3D MXL_RV128) { + imm =3D imm ? imm : 64; + } + return imm; +} + +static int ex_rvc_shiftri(DisasContext *ctx, int imm) +{ + /* + * For RV128 a shamt of 0 means a shift by 64, furthermore, for right + * shifts, the shamt is sign-extended. + */ + if (get_ol(ctx) =3D=3D MXL_RV128) { + imm =3D imm | (imm & 32) << 1; + imm =3D imm ? imm : 64; + } + return imm; } =20 /* Include the auto-generated decoder for 32 bit insn */ --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662538353364100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li - Zmmul is ratified and is now version 1.0 Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Message-Id: <20220710101546.3907-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cab74faaca..a3e4e2477f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1009,12 +1009,13 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), =20 + DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), + /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), =20 /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), - DEFINE_PROP_BOOL("x-zmmul", RISCVCPU, cfg.ext_zmmul, false), /* ePMP 0.9.3 */ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Donenfeld" , Alistair Francis , Bin Meng Subject: [PULL 05/44] hw/riscv: virt: pass random seed to fdt Date: Wed, 7 Sep 2022 10:03:14 +0200 Message-Id: <20220907080353.111926-6-alistair.francis@wdc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907080353.111926-1-alistair.francis@wdc.com> References: <20220907080353.111926-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662538432455100001 Content-Type: text/plain; charset="utf-8" From: "Jason A. Donenfeld" If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to initialize early. Set this using the usual guest random number generation function. This is confirmed to successfully initialize the RNG on Linux 5.19-rc2. Cc: Alistair Francis Signed-off-by: Jason A. Donenfeld Reviewed-by: Bin Meng Message-Id: <20220613115810.178210-1-Jason@zx2c4.com> Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index bc424dd2f5..f2ce5663a4 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qemu/error-report.h" +#include "qemu/guest-random.h" #include "qapi/error.h" #include "hw/boards.h" #include "hw/loader.h" @@ -998,6 +999,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapE= ntry *memmap, MachineState *mc =3D MACHINE(s); uint32_t phandle =3D 1, irq_mmio_phandle =3D 1, msi_pcie_phandle =3D 1; uint32_t irq_pcie_phandle =3D 1, irq_virtio_phandle =3D 1; + uint8_t rng_seed[32]; =20 if (mc->dtb) { mc->fdt =3D load_device_tree(mc->dtb, &s->fdt_size); @@ -1046,6 +1048,10 @@ update_bootargs: if (cmdline && *cmdline) { qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline); } + + /* Pass seed to RNG */ + qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); + qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_= seed)); } =20 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662539153; cv=none; d=zohomail.com; s=zohoarc; b=ifOmQouye/Oc+/IfuyaRj9YE/fMXBg2Zl/2ZvpeWNax8/70udt+lxOFWJi4yvkSq6cKDVOnZsEx1XpDfcIlpREeBQTQ/J9kuQba54Tqv+wlC7R99yzc7CZDwjAm3xaJdaXBKltv6oea3fEgBF18bFRu30LeaHxw3LO4f4yEya3w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662539153; 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Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662539155028100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li There are 3 suggested privilege mode combinations listed in section 1.2 of the riscv-privileged spec(draft-20220717): 1) M, 2) M, U 3) M, S, U Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Message-Id: <20220718130955.11899-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a3e4e2477f..b919ad9056 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -721,6 +721,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) return; } =20 + if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { + error_setg(errp, + "Setting S extension without U extension is illegal= "); + return; + } + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { error_setg(errp, "F extension requires Zicsr"); return; --=20 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envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662539756574100002 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Add check for "H depends on an I base integer ISA with 32 x registers" which is stated at the beginning of chapter 8 of the riscv-privileged spec(draft-20220717) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Message-Id: <20220718130955.11899-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b919ad9056..fb37ffac64 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -727,6 +727,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) return; } =20 + if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { + error_setg(errp, + "H depends on an I base integer ISA with 32 x regis= ters"); + return; + } + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { error_setg(errp, "F extension requires Zicsr"); return; --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted 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Francis , Andrew Jones Subject: [PULL 08/44] target/riscv: Fix checkpatch warning may triggered in csr_ops table Date: Wed, 7 Sep 2022 10:03:17 +0200 Message-Id: <20220907080353.111926-9-alistair.francis@wdc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907080353.111926-1-alistair.francis@wdc.com> References: <20220907080353.111926-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662539396941100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Fix the lines with over 80 characters Fix the lines which are obviously misalgined with other lines in the same group Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Message-Id: <20220718130955.11899-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 441 ++++++++++++++++++++++++--------------------- 1 file changed, 234 insertions(+), 207 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 235f2a011e..7d4b6ceced 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3461,20 +3461,20 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_FRM] =3D { "frm", fs, read_frm, write_frm }, [CSR_FCSR] =3D { "fcsr", fs, read_fcsr, write_fcsr }, /* Vector CSRs */ - [CSR_VSTART] =3D { "vstart", vs, read_vstart, write_vstart, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, - [CSR_VXSAT] =3D { "vxsat", vs, read_vxsat, write_vxsat, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, - [CSR_VXRM] =3D { "vxrm", vs, read_vxrm, write_vxrm, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, - [CSR_VCSR] =3D { "vcsr", vs, read_vcsr, write_vcsr, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, - [CSR_VL] =3D { "vl", vs, read_vl, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, - [CSR_VTYPE] =3D { "vtype", vs, read_vtype, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, - [CSR_VLENB] =3D { "vlenb", vs, read_vlenb, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_VSTART] =3D { "vstart", vs, read_vstart, write_vstart, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_VXSAT] =3D { "vxsat", vs, read_vxsat, write_vxsat, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_VXRM] =3D { "vxrm", vs, read_vxrm, write_vxrm, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_VCSR] =3D { "vcsr", vs, read_vcsr, write_vcsr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_VL] =3D { "vl", vs, read_vl, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_VTYPE] =3D { "vtype", vs, read_vtype, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_VLENB] =3D { "vlenb", vs, read_vlenb, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, /* User Timers and Counters */ [CSR_CYCLE] =3D { "cycle", ctr, read_hpmcounter }, [CSR_INSTRET] =3D { "instret", ctr, read_hpmcounter }, @@ -3493,10 +3493,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 #if !defined(CONFIG_USER_ONLY) /* Machine Timers and Counters */ - [CSR_MCYCLE] =3D { "mcycle", any, read_hpmcounter, write_mhpmc= ounter}, - [CSR_MINSTRET] =3D { "minstret", any, read_hpmcounter, write_mhpmc= ounter}, - [CSR_MCYCLEH] =3D { "mcycleh", any32, read_hpmcounterh, write_mhpm= counterh}, - [CSR_MINSTRETH] =3D { "minstreth", any32, read_hpmcounterh, write_mhpm= counterh}, + [CSR_MCYCLE] =3D { "mcycle", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MINSTRET] =3D { "minstret", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MCYCLEH] =3D { "mcycleh", any32, read_hpmcounterh, + write_mhpmcounterh }, + [CSR_MINSTRETH] =3D { "minstreth", any32, read_hpmcounterh, + write_mhpmcounterh }, =20 /* Machine Information Registers */ [CSR_MVENDORID] =3D { "mvendorid", any, read_mvendorid }, @@ -3505,23 +3509,25 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MHARTID] =3D { "mhartid", any, read_mhartid }, =20 [CSR_MCONFIGPTR] =3D { "mconfigptr", any, read_zero, - .min_priv_ver =3D PRIV_VERSION_1_1= 2_0 }, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, /* Machine Trap Setup */ - [CSR_MSTATUS] =3D { "mstatus", any, read_mstatus, write_m= status, NULL, - read_mstatus_i128 = }, - [CSR_MISA] =3D { "misa", any, read_misa, write_m= isa, NULL, - read_misa_i128 = }, - [CSR_MIDELEG] =3D { "mideleg", any, NULL, NULL, rmw_mid= eleg }, - [CSR_MEDELEG] =3D { "medeleg", any, read_medeleg, write_m= edeleg }, - [CSR_MIE] =3D { "mie", any, NULL, NULL, rmw_mie= }, - [CSR_MTVEC] =3D { "mtvec", any, read_mtvec, write_m= tvec }, - [CSR_MCOUNTEREN] =3D { "mcounteren", any, read_mcounteren, write_m= counteren }, - - [CSR_MSTATUSH] =3D { "mstatush", any32, read_mstatush, write_m= statush }, + [CSR_MSTATUS] =3D { "mstatus", any, read_mstatus, write_mstat= us, + NULL, read_mstatus_i128 = }, + [CSR_MISA] =3D { "misa", any, read_misa, write_misa, + NULL, read_misa_i128 = }, + [CSR_MIDELEG] =3D { "mideleg", any, NULL, NULL, rmw_mideleg= }, + [CSR_MEDELEG] =3D { "medeleg", any, read_medeleg, write_medel= eg }, + [CSR_MIE] =3D { "mie", any, NULL, NULL, rmw_mie = }, + [CSR_MTVEC] =3D { "mtvec", any, read_mtvec, write_mtvec= }, + [CSR_MCOUNTEREN] =3D { "mcounteren", any, read_mcounteren, + write_mcounteren = }, + + [CSR_MSTATUSH] =3D { "mstatush", any32, read_mstatush, + write_mstatush = }, =20 /* Machine Trap Handling */ - [CSR_MSCRATCH] =3D { "mscratch", any, read_mscratch, write_mscra= tch, NULL, - read_mscratch_i128, write_mscratc= h_i128 }, + [CSR_MSCRATCH] =3D { "mscratch", any, read_mscratch, write_mscratch, + NULL, read_mscratch_i128, write_mscratch_i128 }, [CSR_MEPC] =3D { "mepc", any, read_mepc, write_mepc }, [CSR_MCAUSE] =3D { "mcause", any, read_mcause, write_mcause }, [CSR_MTVAL] =3D { "mtval", any, read_mtval, write_mtval }, @@ -3532,12 +3538,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MIREG] =3D { "mireg", aia_any, NULL, NULL, rmw_xireg }, =20 /* Machine-Level Interrupts (AIA) */ - [CSR_MTOPEI] =3D { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, - [CSR_MTOPI] =3D { "mtopi", aia_any, read_mtopi }, + [CSR_MTOPEI] =3D { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, + [CSR_MTOPI] =3D { "mtopi", aia_any, read_mtopi }, =20 /* Virtual Interrupts for Supervisor Level (AIA) */ - [CSR_MVIEN] =3D { "mvien", aia_any, read_zero, write_ignore }, - [CSR_MVIP] =3D { "mvip", aia_any, read_zero, write_ignore }, + [CSR_MVIEN] =3D { "mvien", aia_any, read_zero, write_ignore }, + [CSR_MVIP] =3D { "mvip", aia_any, read_zero, write_ignore }, =20 /* Machine-Level High-Half CSRs (AIA) */ [CSR_MIDELEGH] =3D { "midelegh", aia_any32, NULL, NULL, rmw_midelegh }, @@ -3548,33 +3554,34 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 /* Execution environment configuration */ [CSR_MENVCFG] =3D { "menvcfg", any, read_menvcfg, write_menvcfg, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MENVCFGH] =3D { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_SENVCFG] =3D { "senvcfg", smode, read_senvcfg, write_senvcfg, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_HENVCFG] =3D { "henvcfg", hmode, read_henvcfg, write_henvcfg, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_HENVCFGH] =3D { "henvcfgh", hmode32, read_henvcfgh, write_henvcfg= h, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, =20 /* Supervisor Trap Setup */ - [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, NULL, - read_sstatus_i128 = }, - [CSR_SIE] =3D { "sie", smode, NULL, NULL, rmw_sie = }, - [CSR_STVEC] =3D { "stvec", smode, read_stvec, write_stv= ec }, - [CSR_SCOUNTEREN] =3D { "scounteren", smode, read_scounteren, write_sco= unteren }, + [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, + NULL, read_sstatus_i128 = }, + [CSR_SIE] =3D { "sie", smode, NULL, NULL, rmw_sie = }, + [CSR_STVEC] =3D { "stvec", smode, read_stvec, write_stv= ec }, + [CSR_SCOUNTEREN] =3D { "scounteren", smode, read_scounteren, + write_scounteren = }, =20 /* Supervisor Trap Handling */ - [CSR_SSCRATCH] =3D { "sscratch", smode, read_sscratch, write_sscratch,= NULL, - read_sscratch_i128, write_sscrat= ch_i128 }, + [CSR_SSCRATCH] =3D { "sscratch", smode, read_sscratch, write_sscratch, + NULL, read_sscratch_i128, write_sscratch_i128 }, [CSR_SEPC] =3D { "sepc", smode, read_sepc, write_sepc = }, [CSR_SCAUSE] =3D { "scause", smode, read_scause, write_scause = }, - [CSR_STVAL] =3D { "stval", smode, read_stval, write_stval }, + [CSR_STVAL] =3D { "stval", smode, read_stval, write_stval = }, [CSR_SIP] =3D { "sip", smode, NULL, NULL, rmw_sip = }, =20 /* Supervisor Protection and Translation */ - [CSR_SATP] =3D { "satp", smode, read_satp, write_satp = }, + [CSR_SATP] =3D { "satp", smode, read_satp, write_satp = }, =20 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ [CSR_SISELECT] =3D { "siselect", aia_smode, NULL, NULL, rmw_xisele= ct }, @@ -3588,87 +3595,100 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_SIEH] =3D { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, [CSR_SIPH] =3D { "siph", aia_smode32, NULL, NULL, rmw_siph }, =20 - [CSR_HSTATUS] =3D { "hstatus", hmode, read_hstatus, write_= hstatus, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HEDELEG] =3D { "hedeleg", hmode, read_hedeleg, write_= hedeleg, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HSTATUS] =3D { "hstatus", hmode, read_hstatus, write_hs= tatus, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HEDELEG] =3D { "hedeleg", hmode, read_hedeleg, write_he= deleg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_HIDELEG] =3D { "hideleg", hmode, NULL, NULL, rmw_hide= leg, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HVIP] =3D { "hvip", hmode, NULL, NULL, rmw_hv= ip, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HIP] =3D { "hip", hmode, NULL, NULL, rmw_hi= p, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HIE] =3D { "hie", hmode, NULL, NULL, rmw_h= ie, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HCOUNTEREN] =3D { "hcounteren", hmode, read_hcounteren, write= _hcounteren, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HGEIE] =3D { "hgeie", hmode, read_hgeie, writ= e_hgeie, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HTVAL] =3D { "htval", hmode, read_htval, write_= htval, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HTINST] =3D { "htinst", hmode, read_htinst, write_= htinst, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HVIP] =3D { "hvip", hmode, NULL, NULL, rmw_hvip, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HIP] =3D { "hip", hmode, NULL, NULL, rmw_hip, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HIE] =3D { "hie", hmode, NULL, NULL, rmw_hie, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HCOUNTEREN] =3D { "hcounteren", hmode, read_hcounteren, + write_hcounteren, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HGEIE] =3D { "hgeie", hmode, read_hgeie, write_hg= eie, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HTVAL] =3D { "htval", hmode, read_htval, write_ht= val, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HTINST] =3D { "htinst", hmode, read_htinst, write_ht= inst, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_HGEIP] =3D { "hgeip", hmode, read_hgeip, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HGATP] =3D { "hgatp", hmode, read_hgatp, write_= hgatp, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HTIMEDELTA] =3D { "htimedelta", hmode, read_htimedelta, write= _htimedelta, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HTIMEDELTAH] =3D { "htimedeltah", hmode32, read_htimedeltah, writ= e_htimedeltah, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - - [CSR_VSSTATUS] =3D { "vsstatus", hmode, read_vsstatus, write_= vsstatus, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_VSIP] =3D { "vsip", hmode, NULL, NULL, rmw_vs= ip, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_VSIE] =3D { "vsie", hmode, NULL, NULL, rmw_= vsie , - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_VSTVEC] =3D { "vstvec", hmode, read_vstvec, write_= vstvec, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_VSSCRATCH] =3D { "vsscratch", hmode, read_vsscratch, write_= vsscratch, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_VSEPC] =3D { "vsepc", hmode, read_vsepc, write_= vsepc, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_VSCAUSE] =3D { "vscause", hmode, read_vscause, write_= vscause, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_VSTVAL] =3D { "vstval", hmode, read_vstval, write_= vstval, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_VSATP] =3D { "vsatp", hmode, read_vsatp, write_= vsatp, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - - [CSR_MTVAL2] =3D { "mtval2", hmode, read_mtval2, write_= mtval2, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_MTINST] =3D { "mtinst", hmode, read_mtinst, write_= mtinst, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HGATP] =3D { "hgatp", hmode, read_hgatp, write_hg= atp, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HTIMEDELTA] =3D { "htimedelta", hmode, read_htimedelta, + write_htimedelta, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HTIMEDELTAH] =3D { "htimedeltah", hmode32, read_htimedeltah, + write_htimedeltah, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + + [CSR_VSSTATUS] =3D { "vsstatus", hmode, read_vsstatus, + write_vsstatus, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSIP] =3D { "vsip", hmode, NULL, NULL, rmw_vsi= p, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSIE] =3D { "vsie", hmode, NULL, NULL, rmw_vsi= e , + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSTVEC] =3D { "vstvec", hmode, read_vstvec, write_v= stvec, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSSCRATCH] =3D { "vsscratch", hmode, read_vsscratch, + write_vsscratch, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSEPC] =3D { "vsepc", hmode, read_vsepc, write_v= sepc, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSCAUSE] =3D { "vscause", hmode, read_vscause, write_v= scause, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSTVAL] =3D { "vstval", hmode, read_vstval, write_v= stval, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSATP] =3D { "vsatp", hmode, read_vsatp, write_v= satp, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + + [CSR_MTVAL2] =3D { "mtval2", hmode, read_mtval2, write_m= tval2, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MTINST] =3D { "mtinst", hmode, read_mtinst, write_m= tinst, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, =20 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) = */ [CSR_HVIEN] =3D { "hvien", aia_hmode, read_zero, write_ign= ore }, - [CSR_HVICTL] =3D { "hvictl", aia_hmode, read_hvictl, write_h= victl }, - [CSR_HVIPRIO1] =3D { "hviprio1", aia_hmode, read_hviprio1, wri= te_hviprio1 }, - [CSR_HVIPRIO2] =3D { "hviprio2", aia_hmode, read_hviprio2, wri= te_hviprio2 }, + [CSR_HVICTL] =3D { "hvictl", aia_hmode, read_hvictl, + write_hvictl = }, + [CSR_HVIPRIO1] =3D { "hviprio1", aia_hmode, read_hviprio1, + write_hviprio1 = }, + [CSR_HVIPRIO2] =3D { "hviprio2", aia_hmode, read_hviprio2, + write_hviprio2 = }, =20 /* * VS-Level Window to Indirectly Accessed Registers (H-extension with = AIA) */ - [CSR_VSISELECT] =3D { "vsiselect", aia_hmode, NULL, NULL, rmw= _xiselect }, - [CSR_VSIREG] =3D { "vsireg", aia_hmode, NULL, NULL, rmw= _xireg }, + [CSR_VSISELECT] =3D { "vsiselect", aia_hmode, NULL, NULL, + rmw_xiselect = }, + [CSR_VSIREG] =3D { "vsireg", aia_hmode, NULL, NULL, rmw_xire= g }, =20 /* VS-Level Interrupts (H-extension with AIA) */ [CSR_VSTOPEI] =3D { "vstopei", aia_hmode, NULL, NULL, rmw_xtop= ei }, [CSR_VSTOPI] =3D { "vstopi", aia_hmode, read_vstopi }, =20 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ - [CSR_HIDELEGH] =3D { "hidelegh", aia_hmode32, NULL, NULL, rmw_hi= delegh }, - [CSR_HVIENH] =3D { "hvienh", aia_hmode32, read_zero, write_i= gnore }, + [CSR_HIDELEGH] =3D { "hidelegh", aia_hmode32, NULL, NULL, + rmw_hidelegh = }, + [CSR_HVIENH] =3D { "hvienh", aia_hmode32, read_zero, + write_ignore = }, [CSR_HVIPH] =3D { "hviph", aia_hmode32, NULL, NULL, rmw_hv= iph }, - [CSR_HVIPRIO1H] =3D { "hviprio1h", aia_hmode32, read_hviprio1h, wr= ite_hviprio1h }, - [CSR_HVIPRIO2H] =3D { "hviprio2h", aia_hmode32, read_hviprio2h, wr= ite_hviprio2h }, + [CSR_HVIPRIO1H] =3D { "hviprio1h", aia_hmode32, read_hviprio1h, + write_hviprio1h = }, + [CSR_HVIPRIO2H] =3D { "hviprio2h", aia_hmode32, read_hviprio2h, + write_hviprio2h = }, [CSR_VSIEH] =3D { "vsieh", aia_hmode32, NULL, NULL, rmw_vs= ieh }, [CSR_VSIPH] =3D { "vsiph", aia_hmode32, NULL, NULL, rmw_vs= iph }, =20 /* Physical Memory Protection */ [CSR_MSECCFG] =3D { "mseccfg", epmp, read_mseccfg, write_mseccfg, - .min_priv_ver =3D PRIV_VERSION_1_11_0= }, + .min_priv_ver =3D PRIV_VERSION_1_11_0 }, [CSR_PMPCFG0] =3D { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG1] =3D { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG2] =3D { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, @@ -3697,17 +3717,23 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_TDATA3] =3D { "tdata3", debug, read_tdata, write_tdata }, =20 /* User Pointer Masking */ - [CSR_UMTE] =3D { "umte", pointer_masking, read_umte, write= _umte }, - [CSR_UPMMASK] =3D { "upmmask", pointer_masking, read_upmmask, write= _upmmask }, - [CSR_UPMBASE] =3D { "upmbase", pointer_masking, read_upmbase, write= _upmbase }, + [CSR_UMTE] =3D { "umte", pointer_masking, read_umte, write_u= mte }, + [CSR_UPMMASK] =3D { "upmmask", pointer_masking, read_upmmask, + write_upmmask = }, + [CSR_UPMBASE] =3D { "upmbase", pointer_masking, read_upmbase, + write_upmbase = }, /* Machine Pointer Masking */ - [CSR_MMTE] =3D { "mmte", pointer_masking, read_mmte, write= _mmte }, - [CSR_MPMMASK] =3D { "mpmmask", pointer_masking, read_mpmmask, write= _mpmmask }, - [CSR_MPMBASE] =3D { "mpmbase", pointer_masking, read_mpmbase, write= _mpmbase }, + [CSR_MMTE] =3D { "mmte", pointer_masking, read_mmte, write_m= mte }, + [CSR_MPMMASK] =3D { "mpmmask", pointer_masking, read_mpmmask, + write_mpmmask = }, + [CSR_MPMBASE] =3D { "mpmbase", pointer_masking, read_mpmbase, + write_mpmbase = }, /* Supervisor Pointer Masking */ - [CSR_SMTE] =3D { "smte", pointer_masking, read_smte, write= _smte }, - [CSR_SPMMASK] =3D { "spmmask", pointer_masking, read_spmmask, write= _spmmask }, - [CSR_SPMBASE] =3D { "spmbase", pointer_masking, read_spmbase, write= _spmbase }, + [CSR_SMTE] =3D { "smte", pointer_masking, read_smte, write_s= mte }, + [CSR_SPMMASK] =3D { "spmmask", pointer_masking, read_spmmask, + write_spmmask = }, + [CSR_SPMBASE] =3D { "spmbase", pointer_masking, read_spmbase, + write_spmbase = }, =20 /* Performance Counters */ [CSR_HPMCOUNTER3] =3D { "hpmcounter3", ctr, read_hpmcounter }, @@ -3741,125 +3767,126 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_HPMCOUNTER31] =3D { "hpmcounter31", ctr, read_hpmcounter }, =20 [CSR_MHPMCOUNTER3] =3D { "mhpmcounter3", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER4] =3D { "mhpmcounter4", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER5] =3D { "mhpmcounter5", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER6] =3D { "mhpmcounter6", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER7] =3D { "mhpmcounter7", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER8] =3D { "mhpmcounter8", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER9] =3D { "mhpmcounter9", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER10] =3D { "mhpmcounter10", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER11] =3D { "mhpmcounter11", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER12] =3D { "mhpmcounter12", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER13] =3D { "mhpmcounter13", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER14] =3D { "mhpmcounter14", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER15] =3D { "mhpmcounter15", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER16] =3D { "mhpmcounter16", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER17] =3D { "mhpmcounter17", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER18] =3D { "mhpmcounter18", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER19] =3D { "mhpmcounter19", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER20] =3D { "mhpmcounter20", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER21] =3D { "mhpmcounter21", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER22] =3D { "mhpmcounter22", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER23] =3D { "mhpmcounter23", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER24] =3D { "mhpmcounter24", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER25] =3D { "mhpmcounter25", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER26] =3D { "mhpmcounter26", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER27] =3D { "mhpmcounter27", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER28] =3D { "mhpmcounter28", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER29] =3D { "mhpmcounter29", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, =20 [CSR_MCOUNTINHIBIT] =3D { "mcountinhibit", any, read_mcountinhibit, - write_mcountinhibit, .min_priv_ver =3D PRIV_VERSION_1_11_0 = }, + write_mcountinhibit, + .min_priv_ver =3D PRIV_VERSION_1_11_0 }, =20 [CSR_MHPMEVENT3] =3D { "mhpmevent3", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT4] =3D { "mhpmevent4", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT5] =3D { "mhpmevent5", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT6] =3D { "mhpmevent6", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT7] =3D { "mhpmevent7", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT8] =3D { "mhpmevent8", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT9] =3D { "mhpmevent9", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT10] =3D { "mhpmevent10", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT11] =3D { "mhpmevent11", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT12] =3D { "mhpmevent12", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT13] =3D { "mhpmevent13", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT14] =3D { "mhpmevent14", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT15] =3D { "mhpmevent15", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT16] =3D { "mhpmevent16", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT17] =3D { "mhpmevent17", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT18] =3D { "mhpmevent18", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT19] =3D { "mhpmevent19", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT20] =3D { "mhpmevent20", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT21] =3D { "mhpmevent21", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT22] =3D { "mhpmevent22", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT23] =3D { "mhpmevent23", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT24] =3D { "mhpmevent24", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT25] =3D { "mhpmevent25", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT26] =3D { "mhpmevent26", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT27] =3D { "mhpmevent27", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT28] =3D { "mhpmevent28", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT29] =3D { "mhpmevent29", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT30] =3D { "mhpmevent30", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT31] =3D { "mhpmevent31", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, =20 [CSR_HPMCOUNTER3H] =3D { "hpmcounter3h", ctr32, read_hpmcounterh = }, [CSR_HPMCOUNTER4H] =3D { "hpmcounter4h", ctr32, read_hpmcounterh = }, @@ -3892,62 +3919,62 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_HPMCOUNTER31H] =3D { "hpmcounter31h", ctr32, read_hpmcounterh = }, =20 [CSR_MHPMCOUNTER3H] =3D { "mhpmcounter3h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER4H] =3D { "mhpmcounter4h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER5H] =3D { "mhpmcounter5h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER6H] =3D { "mhpmcounter6h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER7H] =3D { "mhpmcounter7h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER8H] =3D { "mhpmcounter8h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER9H] =3D { "mhpmcounter9h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER10H] =3D { "mhpmcounter10h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER11H] =3D { "mhpmcounter11h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER12H] =3D { "mhpmcounter12h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER13H] =3D { "mhpmcounter13h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER14H] =3D { "mhpmcounter14h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER15H] =3D { "mhpmcounter15h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER16H] =3D { "mhpmcounter16h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER17H] =3D { "mhpmcounter17h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER18H] =3D { "mhpmcounter18h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER19H] =3D { "mhpmcounter19h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER20H] =3D { "mhpmcounter20h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER21H] =3D { "mhpmcounter21h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER22H] =3D { "mhpmcounter22h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER23H] =3D { "mhpmcounter23h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER24H] =3D { "mhpmcounter24h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER25H] =3D { "mhpmcounter25h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER26H] =3D { "mhpmcounter26h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER27H] =3D { "mhpmcounter27h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER28H] =3D { "mhpmcounter28h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER29H] =3D { "mhpmcounter29h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER30H] =3D { "mhpmcounter30h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER31H] =3D { "mhpmcounter31h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, #endif /* !CONFIG_USER_ONLY */ }; --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662538361; cv=none; d=zohomail.com; s=zohoarc; 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X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907080353.111926-1-alistair.francis@wdc.com> References: <20220907080353.111926-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662538362499100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Add umode/umode32 predicate for mcounteren, menvcfg/menvcfgh Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Message-Id: <20220718130955.11899-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7d4b6ceced..5c69dc838c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -339,6 +339,24 @@ static RISCVException hmode32(CPURISCVState *env, int = csrno) =20 } =20 +static RISCVException umode(CPURISCVState *env, int csrno) +{ + if (riscv_has_ext(env, RVU)) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} + +static RISCVException umode32(CPURISCVState *env, int csrno) +{ + if (riscv_cpu_mxl(env) !=3D MXL_RV32) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return umode(env, csrno); +} + /* Checks if PointerMasking registers could be accessed */ static RISCVException pointer_masking(CPURISCVState *env, int csrno) { @@ -3519,7 +3537,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MEDELEG] =3D { "medeleg", any, read_medeleg, write_medel= eg }, [CSR_MIE] =3D { "mie", any, NULL, NULL, rmw_mie = }, [CSR_MTVEC] =3D { "mtvec", any, read_mtvec, write_mtvec= }, - [CSR_MCOUNTEREN] =3D { "mcounteren", any, read_mcounteren, + [CSR_MCOUNTEREN] =3D { "mcounteren", umode, read_mcounteren, write_mcounteren = }, =20 [CSR_MSTATUSH] =3D { "mstatush", any32, read_mstatush, @@ -3553,9 +3571,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MIPH] =3D { "miph", aia_any32, NULL, NULL, rmw_miph }, =20 /* Execution environment configuration */ - [CSR_MENVCFG] =3D { "menvcfg", any, read_menvcfg, write_menvcfg, + [CSR_MENVCFG] =3D { "menvcfg", umode, read_menvcfg, write_menvcfg, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MENVCFGH] =3D { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, + [CSR_MENVCFGH] =3D { "menvcfgh", umode32, read_menvcfgh, write_menvcfg= h, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_SENVCFG] =3D { "senvcfg", smode, read_senvcfg, write_senvcfg, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662538756; cv=none; d=zohomail.com; s=zohoarc; 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List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662538758335100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Add check for the implicit dependence between H and S Csrs only existed in RV32 will not trigger virtual instruction fault when not in RV32 based on section 8.6.1 of riscv-privileged spec (draft-20220717) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-Id: <20220718130955.11899-6-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 5 +++++ target/riscv/csr.c | 9 ++------- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fb37ffac64..117d308ae5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -733,6 +733,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) return; } =20 + if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { + error_setg(errp, "H extension implicitly requires S-mode"); + return; + } + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { error_setg(errp, "F extension requires Zicsr"); return; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5c69dc838c..cf15aa67b7 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -311,8 +311,7 @@ static int aia_smode32(CPURISCVState *env, int csrno) =20 static RISCVException hmode(CPURISCVState *env, int csrno) { - if (riscv_has_ext(env, RVS) && - riscv_has_ext(env, RVH)) { + if (riscv_has_ext(env, RVH)) { /* Hypervisor extension is supported */ if ((env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || env->priv =3D=3D PRV_M) { @@ -328,11 +327,7 @@ static RISCVException hmode(CPURISCVState *env, int cs= rno) static RISCVException hmode32(CPURISCVState *env, int csrno) { if (riscv_cpu_mxl(env) !=3D MXL_RV32) { - if (!riscv_cpu_virt_enabled(env)) { - return RISCV_EXCP_ILLEGAL_INST; - } else { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } + return RISCV_EXCP_ILLEGAL_INST; } =20 return hmode(env, csrno); --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662540173; cv=none; d=zohomail.com; s=zohoarc; b=lCAmsXmh/2je9uuSawXHKR/7DAbLLYDtDXVpKfEvXBfTRxKHf5L3eyj9lp3mqFZdcA2YlgVcCQyobEOFZ4587cBLxMI3odJA2GzdqQS1EpF7ZwMsBgBbKCq50ZUMH3T/tdjdD1VgPXjP7THyf5rNXtbaxwqlK7sm6nsMifoWhj8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662540173; 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quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662540173895100003 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Just add 1 to the effective privledge level when in HS mode, then reuse the check of 'effective_priv < csr_priv' in riscv_csrrw_check to replace the privilege level related check in hmode. Then, hmode will only check whether H extension is supported. When accessing Hypervior CSRs: 1) If accessing from M privilege level, the check of 'effective_priv< csr_priv' passes, returns hmode(...) which will return RISCV_EXCP_ILLEGAL_INST when H extension is not supported and return RISCV_EXCP_NONE otherwise. 2) If accessing from HS privilege level, effective_priv will add 1, the check passes and also returns hmode(...) too. 3) If accessing from VS/VU privilege level, the check fails, and returns RISCV_EXCP_VIRT_INSTRUCTION_FAULT 4) If accessing from U privilege level, the check fails, and returns RISCV_EXCP_ILLEGAL_INST Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Message-Id: <20220718130955.11899-7-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index cf15aa67b7..0fb042b2fd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -312,13 +312,7 @@ static int aia_smode32(CPURISCVState *env, int csrno) static RISCVException hmode(CPURISCVState *env, int csrno) { if (riscv_has_ext(env, RVH)) { - /* Hypervisor extension is supported */ - if ((env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || - env->priv =3D=3D PRV_M) { - return RISCV_EXCP_NONE; - } else { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } + return RISCV_EXCP_NONE; } =20 return RISCV_EXCP_ILLEGAL_INST; @@ -3279,13 +3273,11 @@ static inline RISCVException riscv_csrrw_check(CPUR= ISCVState *env, #if !defined(CONFIG_USER_ONLY) int csr_priv, effective_priv =3D env->priv; =20 - if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_S) { + if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_S && + !riscv_cpu_virt_enabled(env)) { /* - * We are in either HS or VS mode. - * Add 1 to the effective privledge level to allow us to access the - * Hypervisor CSRs. The `hmode` predicate will determine if access - * should be allowed(HS) or if a virtual instruction exception sho= uld be - * raised(VS). + * We are in HS mode. Add 1 to the effective privledge level to + * allow us to access the Hypervisor CSRs. */ effective_priv++; } --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662540023; cv=none; d=zohomail.com; s=zohoarc; b=kbhUNQ59S5MKkk9/ApwFamLr6tVl7tv3O7WJwD+oeHlVf1PaBXFFinHYezzF0qHGEEr+BL4K4d4kVg60hFeKXWplUe7hlCYz0fWm7AvJ12CMgaAG9tYdwHvQUPlmk/kpF2Y2eSWFPn4iU19UpXdGbPLr69MpTO14O/nSABRBQSQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662540023; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662540023932100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng Upgrade OpenSBI from v1.0 to v1.1 and the pre-built bios images. The v1.1 release includes the following commits: 5b99603 lib: utils/ipi: Fix size check in aclint_mswi_cold_init() 6dde435 lib: utils/sys: Extend HTIF library to allow custom base address 8257262 platform: sifive_fu740: do not use a global in da9063_reset/shutdown fb688d9 platform: sifive_fu740: fix reset when watchdog is running 5d025eb lib: fix pointer of type 'void *' used in arithmetic 632f593 lib: sbi: Map only the counters enabled in hardware 3b7c204 lib: sbi: Disable interrupt during config matching a26dc60 lib: sbi: Disable interrupt and inhibit counting in M-mode during i= nit 5d53b55 Makefile: fix build with binutils 2.38 6ad8917 lib: fix compilation when strings.h is included ce4c018 lib: utils/serial: Round UART8250 baud rate divisor to nearest inte= ger 01250d0 include: sbi: Add AIA related CSR defines 8f96070 lib: sbi: Detect AIA CSRs at boot-time 65b4c7c lib: sbi: Use AIA CSRs for local interrupts when available 222132f lib: sbi: Add sbi_trap_set_external_irqfn() API 5f56314 lib: utils/irqchip: Allow multiple FDT irqchip drivers 1050940 include: sbi: Introduce nascent_init() platform callback 55e79f8 lib: sbi: Enable mie.MEIE bit for IPIs based on external interrupts. 9f73669 lib: utils/irqchip: Add IMSIC library 811da5c lib: utils/irqchip: Add FDT based driver for IMSIC 7127aaa lib: utils: Disable appropriate IMSIC DT nodes in fdt_fixups() 9979265 lib: utils/irqchip: Add APLIC initialization library 3461219 lib: utils/irqchip: Add FDT based driver for APLIC 8e2ef4f lib: utils: Disable appropriate APLIC DT nodes in fdt_fixups() 3a69cc1 lib: sbi: fix typo in is_region_subset f2ccf2f lib: sbi: verbose sbi_domain_root_add_memregion f3f4604 lib: sbi: Add a simple external interrupt handling framework 4998a71 lib: utils: serial: Initial commit of xlnx-uartlite 2dfbd3c lib: pmp_set/pmp_get moved errors from runtime to compile time b6b7220 firmware: Fix code for accessing hart_count and stack_size d552fc8 lib: Add error messages via conditional compilation for the future 555bdb1 include: Use static asserts for SBI_PLATFORM_xxx_OFFSET defines 1b42d3a include: Use static asserts for SBI_SCRATCH_xxx_OFFSET defines 7924a0b include: Use static asserts for FW_DYNAMIC_INFO_xxx_OFFSET defines 722f80d include: Add defines for [m|h|s]envcfg CSRs 31fecad lib: sbi: Detect menvcfg CSR at boot time 47d6765 lib: sbi: Enable Zicbo[m|z] extensions in the menvcfg CSR 794986f lib: sbi: Enable Svpbmt extension in the menvcfg CSR 499601a lib: sbi: Add Smstateen extension defines d44568a lib: sbi: Detect Smstateen CSRs at boot-time 3383d6a lib: irqchip/imsic: configure mstateen 5c5cbb5 lib: utils/serial: support 'reg-offset' property c1e47d0 include: correct the definition of MSTATUS_VS 9cd95e1 lib: sbi/hart: preserve csr validation value 4035ae9 docs: pmu: Improve the PMU DT bindings d62f6da lib: sbi: Implement Sstc extension 474a9d4 lib: sbi: Fix mstatus_init() for RV32 when Sscofpmf is not available e576b3e include: sbi: Define SBI_PMU_HW_EVENT_MAX to 256 b0c9df5 lib: sbi: Fix mhpmeventh access for rv32 in absence of sscofpmf 1a754bb lib: sbi: Detect and print privileged spec version 5a6be99 lib: sbi: Remove 's' and 'u' from misa_string() output 5b8b377 lib: sbi: Update the name of ISA string printed at boot time d4b563c lib: sbi: Remove MCOUNTEREN and SCOUNTEREN hart features dbc3d8f lib: sbi: Remove MCOUNTINHIBT hart feature 97a17c2 lib: sbi: Remove MENVCFG hart feature a6ab94f lib: sbi: Fix AIA feature detection cad6c91 lib: sbi: Convert hart features into hart extensions be4903a lib: sbi: Detect hart features only once for each hart 994ace3 lib: sbi: Add sbi_hart_update_extension() function 023f0ad lib: sbi_platform: Add callback to populate HART extensions f726f2d Makefile: Allow generated C source to be anywhere in build directory 7fb474b Makefile: Add support for generating C array at compile time 73cf511 lib: utils/reset: Generate FDT reset driver list at compile-time 1e62705 lib: utils/serial: Generate FDT serial driver list at compile-time bfeb305 lib: utils/timer: Generate FDT timer driver list at compile-time 3a69d12 lib: utils/irqchip: Generate FDT irqchip driver list at compile-time 4ee0c57 lib: utils/ipi: Generate FDT ipi driver list at compile-time 998ed43 lib: utils/i2c: Generate FDT i2c adapter driver list at compile-time 4eacd82 lib: utils/gpio: Generate FDT gpio driver list at compile-time a3a3c60 platform: generic: Generate platform override module list at compil= e-time 9a7a677 platform: generic: Move Sifive platform overrides into own directory 851c14d lib: utils/irqchip: fix typo when checking for CPU node 90a9dd2 lib: utils/fdt: introduce fdt_node_is_enabled() 616da52 lib: utils: check if CPU node is enabled 575bb4e platform: generic: check if CPU node is enabled 1bc67db lib: utils/fdt: rename fdt_parse_max_hart_id f067bb8 lib: sbi: fix system_opcode_insn fab0379 lib: utils/fdt: Require match data to be const 295e5f3 lib: sbi_timer: Drop unnecessary get_platform_ticks wrapper ff65bfe lib: sbi_illegal_insn: Constify illegal_insn_table cb8271c lib: sbi_illegal_insn: Add emulation for fence.tso adc3388 lib: sbi_trap: Redirect exception based on hedeleg ce1d618 platform: generic: add overrides for vendor extensions b20ed9f lib: sbi_hsm: Call a device hook during hart resume 79e42eb lib: sbi_hsm: Assume a consistent resume address 2ea7799 lib: irqchip/plic: Constify plic_data pointers 8c362e7 lib: irqchip/plic: Factor out a context init function 415ecf2 lib: irqchip/plic: Add context save/restore helpers 2b79b69 lib: irqchip/plic: Add priority save/restore helpers 69be3df lib: utils/irqchip: Add FDT wrappers for PLIC save/restore functions 5e56758 lib: utils/irqchip: Add wrapper for T-HEAD PLIC delegation 9dc5ec5 platform: Add HSM implementation for Allwinner D1 551c70c include: sbi: Add mtinst/htinst psuedoinstructions 187127f lib: sbi: Fixup tinst for exceptions in sbi_misaligned_*() a07402a lib: sbi: Fix tval and tinst for sbi_get_insn() c653001 lib: utils: Remove CSRs that set/clear an IMSIC interrupt file bits 7738345 lib: utils/timer: Add a separate compatible for the D1 CLINT d76a196 lib: irqchip/plic: fix typo in plic_warm_irqchip_init 6f1fe98 lib: utils/timer: Remove Allwinner D1 CLINT compatibles c6fdbcf include: sbi: Change spec version to 1.0 3f66465 lib: pmu: allow to use the highest available counter 4489876 include: Bump-up version to 1.1 Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20220713090613.204046-1-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- .../opensbi-riscv32-generic-fw_dynamic.bin | Bin 108504 -> 117704 bytes .../opensbi-riscv64-generic-fw_dynamic.bin | Bin 105296 -> 115344 bytes roms/opensbi | 2 +- 3 files changed, 1 insertion(+), 1 deletion(-) diff --git a/pc-bios/opensbi-riscv32-generic-fw_dynamic.bin b/pc-bios/opens= bi-riscv32-generic-fw_dynamic.bin index dba8e8655f..81bab1adc9 100644 Binary files a/pc-bios/opensbi-riscv32-generic-fw_dynamic.bin and b/pc-bios= /opensbi-riscv32-generic-fw_dynamic.bin differ diff --git a/pc-bios/opensbi-riscv64-generic-fw_dynamic.bin b/pc-bios/opens= bi-riscv64-generic-fw_dynamic.bin index f223e56991..5eb0a74326 100644 Binary files a/pc-bios/opensbi-riscv64-generic-fw_dynamic.bin and b/pc-bios= /opensbi-riscv64-generic-fw_dynamic.bin differ diff --git a/roms/opensbi b/roms/opensbi index 48f91ee9c9..4489876e93 160000 --- a/roms/opensbi +++ b/roms/opensbi @@ -1 +1 @@ -Subproject commit 48f91ee9c960f048c4a7d1da4447d31e04931e38 +Subproject commit 4489876e933d8ba0d8bc6c64bae71e295d45faac --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: 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Message-Id: <20220907080353.111926-14-alistair.francis@wdc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907080353.111926-1-alistair.francis@wdc.com> References: <20220907080353.111926-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662539169188100001 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Fixes: 4302bef9e178 ("target/riscv: Calculate address according to XLEN") Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis Message-Id: <20220717101543.478533-2-space.monkey.delivers@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6eeb728462..76da8db8a7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -544,7 +544,7 @@ static TCGv get_address(DisasContext *ctx, int rs1, int= imm) =20 tcg_gen_addi_tl(addr, src1, imm); if (ctx->pm_mask_enabled) { - tcg_gen_and_tl(addr, addr, pm_mask); + tcg_gen_andc_tl(addr, addr, pm_mask); } else if (get_xl(ctx) =3D=3D MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662541002; cv=none; d=zohomail.com; s=zohoarc; b=glGEKMh710YODhJuVxE+p/hUbE/eXvz+i0fJHx/a8knJ4ysn4tTPDNBfygbiY0CS6fpp5VWJEuie6YaEBaqSicuddxGh5qxf5Lx/Js3lGqPEF9EVFLp6WP0/DxlE8y634/iHTgJVFXlLL4Aa3fsyoVH1lwt3WL6+VUHoykWOXJA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662541002; 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domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662541004277100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng Since commit fbf43c7dbf18 ("target/riscv: enable riscv kvm accel"), KVM accelerator is supported on RISC-V. Let's document it. Signed-off-by: Bin Meng Reviewed-by: Thomas Huth Reviewed-by: Alistair Francis Message-Id: <20220719082635.3741878-1-bin.meng@windriver.com> Signed-off-by: Alistair Francis --- docs/about/build-platforms.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/about/build-platforms.rst b/docs/about/build-platforms.rst index 26028756d0..a2fee53248 100644 --- a/docs/about/build-platforms.rst +++ b/docs/about/build-platforms.rst @@ -46,7 +46,7 @@ Those hosts are officially supported, with various accele= rators: * - PPC - kvm, tcg * - RISC-V - - tcg + - kvm, tcg * - s390x - kvm, tcg * - SPARC --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662540596047100001 Content-Type: text/plain; charset="utf-8" From: "Yueh-Ting (eop) Chen" According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elements' bits to all 1s". There are multiple possibility for agnostic elements according to v-spec. The main intent of this patch-set tries to add option that can distinguish between mask policies. Setting agnostic elements to all 1s allows QEMU to express this. This is the first commit regarding the optional mask agnostic behavior. Follow-up commits will add this optional behavior for all rvv instructions. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <165570784143.17634.35095816584573691-1@git.sr.ht> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ target/riscv/internals.h | 5 +++-- target/riscv/cpu_helper.c | 2 ++ target/riscv/translate.c | 2 ++ target/riscv/vector_helper.c | 8 ++++++++ target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ 6 files changed, 20 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ffb1a18873..561d7fa92c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -439,6 +439,7 @@ struct RISCVCPUConfig { bool ext_zve64f; bool ext_zmmul; bool rvv_ta_all_1s; + bool rvv_ma_all_1s; =20 uint32_t mvendorid; uint64_t marchid; @@ -596,6 +597,7 @@ FIELD(TB_FLAGS, XL, 20, 2) FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) FIELD(TB_FLAGS, VTA, 24, 1) +FIELD(TB_FLAGS, VMA, 25, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 193ce57a6d..5620fbffb6 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -26,8 +26,9 @@ FIELD(VDATA, VM, 0, 1) FIELD(VDATA, LMUL, 1, 3) FIELD(VDATA, VTA, 4, 1) FIELD(VDATA, VTA_ALL_1S, 5, 1) -FIELD(VDATA, NF, 6, 4) -FIELD(VDATA, WD, 6, 1) +FIELD(VDATA, VMA, 6, 1) +FIELD(VDATA, NF, 7, 4) +FIELD(VDATA, WD, 7, 1) =20 /* float point classify helpers */ target_ulong fclass_h(uint64_t frs1); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 87daf7220f..650574accf 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -68,6 +68,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); flags =3D FIELD_DP32(flags, TB_FLAGS, VTA, FIELD_EX64(env->vtype, VTYPE, VTA)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, + FIELD_EX64(env->vtype, VTYPE, VMA)); } else { flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 76da8db8a7..8925a44c6e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -95,6 +95,7 @@ typedef struct DisasContext { int8_t lmul; uint8_t sew; uint8_t vta; + uint8_t vma; bool cfg_vta_all_1s; target_ulong vstart; bool vl_eq_vlmax; @@ -1121,6 +1122,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->sew =3D FIELD_EX32(tb_flags, TB_FLAGS, SEW); ctx->lmul =3D sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); ctx->vta =3D FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_al= l_1s; + ctx->vma =3D FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_al= l_1s; ctx->cfg_vta_all_1s =3D cpu->cfg.rvv_ta_all_1s; ctx->vstart =3D env->vstart; ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a96fc49c71..de895050e0 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -127,6 +127,11 @@ static inline uint32_t vext_vta(uint32_t desc) return FIELD_EX32(simd_data(desc), VDATA, VTA); } =20 +static inline uint32_t vext_vma(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VMA); +} + static inline uint32_t vext_vta_all_1s(uint32_t desc) { return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S); @@ -812,10 +817,13 @@ static void do_vext_vv(void *vd, void *v0, void *vs1,= void *vs2, uint32_t vl =3D env->vl; uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); uint32_t i; =20 for (i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); continue; } fn(vd, vs1, vs2, i); diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 6c091824b6..5ec113f6fd 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1247,6 +1247,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3F= n *gvec_fn, data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8, @@ -1545,6 +1546,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr = *a, data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), @@ -1627,6 +1629,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr = *a, data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662540400; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662540402554100001 Content-Type: text/plain; charset="utf-8" From: "Yueh-Ting (eop) Chen" Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis Message-Id: <165570784143.17634.35095816584573691-2@git.sr.ht> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 35 +++++++++++++++++-------- target/riscv/insn_trans/trans_rvv.c.inc | 5 ++++ 2 files changed, 29 insertions(+), 11 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index de895050e0..e3810d2bc3 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -283,14 +283,18 @@ vext_ldst_stride(void *vd, void *v0, target_ulong bas= e, uint32_t esz =3D 1 << log2_esz; uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); =20 for (i =3D env->vstart; i < env->vl; i++, env->vstart++) { - if (!vm && !vext_elem_mask(v0, i)) { - continue; - } - k =3D 0; while (k < nf) { + if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, (i + k * max_elems) * esz, + (i + k * max_elems + 1) * esz); + k++; + continue; + } target_ulong addr =3D base + stride * i + (k << log2_esz); ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, = ra); k++; @@ -482,15 +486,19 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, uint32_t esz =3D 1 << log2_esz; uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); =20 /* load bytes from guest memory */ for (i =3D env->vstart; i < env->vl; i++, env->vstart++) { - if (!vm && !vext_elem_mask(v0, i)) { - continue; - } - k =3D 0; while (k < nf) { + if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, (i + k * max_elems) * esz, + (i + k * max_elems + 1) * esz); + k++; + continue; + } abi_ptr addr =3D get_index_addr(base, i, vs2) + (k << log2_esz= ); ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, = ra); k++; @@ -579,6 +587,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, uint32_t esz =3D 1 << log2_esz; uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); target_ulong addr, offset, remain; =20 /* probe every access*/ @@ -624,10 +633,14 @@ ProbeSuccess: } for (i =3D env->vstart; i < env->vl; i++) { k =3D 0; - if (!vm && !vext_elem_mask(v0, i)) { - continue; - } while (k < nf) { + if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, (i + k * max_elems) * esz, + (i + k * max_elems + 1) * esz); + k++; + continue; + } target_ulong addr =3D base + ((i * nf + k) << log2_esz); ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, = ra); k++; diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 5ec113f6fd..0627eda0c0 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -712,6 +712,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, ui= nt8_t eew) data =3D FIELD_DP32(data, VDATA, LMUL, emul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); } =20 @@ -777,6 +778,7 @@ static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a= , uint8_t eew) data =3D FIELD_DP32(data, VDATA, NF, 1); /* Mask destination register are always tail-agnostic */ data =3D FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); } =20 @@ -866,6 +868,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a,= uint8_t eew) data =3D FIELD_DP32(data, VDATA, LMUL, emul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } =20 @@ -996,6 +999,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, = uint8_t eew) data =3D FIELD_DP32(data, VDATA, LMUL, emul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } =20 @@ -1114,6 +1118,7 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, u= int8_t eew) data =3D FIELD_DP32(data, VDATA, LMUL, emul); data =3D FIELD_DP32(data, VDATA, NF, a->nf); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); return ldff_trans(a->rd, a->rs1, data, fn, s); } =20 --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662539225533100001 Content-Type: text/plain; charset="utf-8" From: "Yueh-Ting (eop) Chen" Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis Message-Id: <165570784143.17634.35095816584573691-3@git.sr.ht> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 3 +++ target/riscv/insn_trans/trans_rvv.c.inc | 2 ++ 2 files changed, 5 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index e3810d2bc3..6be3c4e739 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -899,10 +899,13 @@ static void do_vext_vx(void *vd, void *v0, target_lon= g s1, void *vs2, uint32_t vl =3D env->vl; uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); uint32_t i; =20 for (i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); continue; } fn(vd, s1, vs2, i); diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 0627eda0c0..07d86551a9 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1301,6 +1301,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, uint32_t vm, data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); =20 @@ -1468,6 +1469,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, ui= nt32_t vs2, uint32_t vm, data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); =20 --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662539473; cv=none; d=zohomail.com; s=zohoarc; b=clNrH9r0FKyJvd2GNxKMhtB8c/z2PJAgJGm/JwDna5FffjaJJ7/DrhEZZkmCL7tv4WsfA00KF81tOGEz+LhncCHZqE6TSxYgu6hyLx7VMsF6GBc/1RjEA/m3mm+4gKC+oxsNFfxS1Sh5CDYlbYCVhx0zgy8NwLhCN9GOM5gQsvo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662539473; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662539474638100001 Content-Type: text/plain; charset="utf-8" From: "Yueh-Ting (eop) Chen" Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis Message-Id: <165570784143.17634.35095816584573691-4@git.sr.ht> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 7 +++++++ target/riscv/insn_trans/trans_rvv.c.inc | 1 + 2 files changed, 8 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 6be3c4e739..d1daa764b7 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -1298,10 +1298,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t esz =3D sizeof(TS1); = \ uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); = \ uint32_t vta =3D vext_vta(desc); = \ + uint32_t vma =3D vext_vma(desc); = \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \ continue; \ } \ TS1 s1 =3D *((TS1 *)vs1 + HS1(i)); = \ @@ -1339,10 +1342,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong = s1, \ uint32_t total_elems =3D \ vext_get_total_elems(env, desc, esz); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * esz, \ + (i + 1) * esz); \ continue; \ } \ TS2 s2 =3D *((TS2 *)vs2 + HS2(i)); \ diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 07d86551a9..83b85bb851 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1901,6 +1901,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662538491; cv=none; d=zohomail.com; s=zohoarc; b=mweriDRcFq7qtlm2C4xlGATtTGehh5QXogZ6s9IQu969Z0n5LotOUqqsXy7LBpc70jptpU9UVG07KkHFjSQ6dH+KGPuRJ1vrn00CzWMGb4DQAXlJKE6KB9s+iyRikaJVST0jLM77AWvJZKZqAnX5aSYo1xMVX6xGV9KjZG2Q1JI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662538491; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662538492865100001 Content-Type: text/plain; charset="utf-8" From: "Yueh-Ting (eop) Chen" Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis Message-Id: <165570784143.17634.35095816584573691-5@git.sr.ht> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 10 ++++++++++ target/riscv/insn_trans/trans_rvv.c.inc | 1 + 2 files changed, 11 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index d1daa764b7..07ce671879 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -1404,12 +1404,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, vo= id *vs2, \ uint32_t vl =3D env->vl; \ uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + if (vma) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ continue; \ } \ vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \ @@ -1462,11 +1467,16 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong = s1, void *vs2, \ uint32_t vl =3D env->vl; \ uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + if (vma) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ continue; \ } \ vext_set_elem_mask(vd, i, \ diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 83b85bb851..e6aa5295a1 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1718,6 +1718,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ data =3D \ FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662539808; cv=none; d=zohomail.com; s=zohoarc; b=jmjsgCw0rNT/waRwjE4SZUZ737H8AhFhRPRAmkCWDKxovHRyo3hC8RBI+ZJnC1bMDpEDahb2qmoLOpUwqOV8rJt+Jgq9F8Lp400E8WwoYCqTPmUd+gm62PEu7W9t6YHLvhfrkW01jjiG6wG1iYFxzFmrr5LK6bPAq9isSmeiHDU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662539808; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662539810985100001 Content-Type: text/plain; charset="utf-8" From: "Yueh-Ting (eop) Chen" Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis Message-Id: <165570784143.17634.35095816584573691-6@git.sr.ht> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 07ce671879..597fa9c752 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -2129,10 +2129,12 @@ static inline void vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, uint32_t vl, uint32_t vm, int vxrm, - opivv2_rm_fn *fn) + opivv2_rm_fn *fn, uint32_t vma, uint32_t esz) { for (uint32_t i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); continue; } fn(vd, vs1, vs2, i, env, vxrm); @@ -2150,23 +2152,24 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *v= s2, uint32_t vl =3D env->vl; uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); =20 switch (env->vxrm) { case 0: /* rnu */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, 0, fn); + env, vl, vm, 0, fn, vma, esz); break; case 1: /* rne */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, 1, fn); + env, vl, vm, 1, fn, vma, esz); break; case 2: /* rdn */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, 2, fn); + env, vl, vm, 2, fn, vma, esz); break; default: /* rod */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, 3, fn); + env, vl, vm, 3, fn, vma, esz); break; } /* set tail elements to 1s */ @@ -2250,10 +2253,12 @@ static inline void vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2, CPURISCVState *env, uint32_t vl, uint32_t vm, int vxrm, - opivx2_rm_fn *fn) + opivx2_rm_fn *fn, uint32_t vma, uint32_t esz) { for (uint32_t i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); continue; } fn(vd, s1, vs2, i, env, vxrm); @@ -2271,23 +2276,24 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, vo= id *vs2, uint32_t vl =3D env->vl; uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); =20 switch (env->vxrm) { case 0: /* rnu */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, 0, fn); + env, vl, vm, 0, fn, vma, esz); break; case 1: /* rne */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, 1, fn); + env, vl, vm, 1, fn, vma, esz); break; case 2: /* rdn */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, 2, fn); + env, vl, vm, 2, fn, vma, esz); break; default: /* rod */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, 3, fn); + env, vl, vm, 3, fn, vma, esz); break; } /* set tail elements to 1s */ --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662541446562100001 Content-Type: text/plain; charset="utf-8" From: "Yueh-Ting (eop) Chen" Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis Message-Id: <165570784143.17634.35095816584573691-7@git.sr.ht> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 26 +++++++++++++++++++++++++ target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++++++++ 2 files changed, 38 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 597fa9c752..315742c6b8 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3051,10 +3051,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t total_elems =3D \ vext_get_total_elems(env, desc, ESZ); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * ESZ, \ + (i + 1) * ESZ); \ continue; \ } \ do_##NAME(vd, vs1, vs2, i, env); \ @@ -3090,10 +3094,14 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, = \ uint32_t total_elems =3D \ vext_get_total_elems(env, desc, ESZ); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * ESZ, \ + (i + 1) * ESZ); \ continue; \ } \ do_##NAME(vd, s1, vs2, i, env); \ @@ -3665,6 +3673,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ uint32_t total_elems =3D \ vext_get_total_elems(env, desc, ESZ); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ if (vl =3D=3D 0) { \ @@ -3672,6 +3681,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ } \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * ESZ, \ + (i + 1) * ESZ); \ continue; \ } \ do_##NAME(vd, vs2, i, env); \ @@ -4182,12 +4194,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, vo= id *vs2, \ uint32_t vl =3D env->vl; \ uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + if (vma) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ continue; \ } \ vext_set_elem_mask(vd, i, \ @@ -4215,11 +4232,16 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, = void *vs2, \ uint32_t vl =3D env->vl; \ uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + if (vma) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ continue; \ } \ vext_set_elem_mask(vd, i, \ @@ -4342,10 +4364,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ uint32_t total_elems =3D \ vext_get_total_elems(env, desc, ESZ); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * ESZ, \ + (i + 1) * ESZ); \ continue; \ } \ do_##NAME(vd, vs2, i); \ diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index e6aa5295a1..8ce3d28603 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2361,6 +2361,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ data =3D \ FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ @@ -2446,6 +2447,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, \ s->cfg_vta_all_1s); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ fns[s->sew - 1], s); \ } \ @@ -2485,6 +2487,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ @@ -2525,6 +2528,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ fns[s->sew - 1], s); \ } \ @@ -2562,6 +2566,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ @@ -2602,6 +2607,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ fns[s->sew - 1], s); \ } \ @@ -2686,6 +2692,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8, @@ -2790,6 +2797,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_= v_f *a) TCGv_i32 desc; uint32_t data =3D FIELD_DP32(0, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); static gen_helper_vmv_vx * const fns[3] =3D { gen_helper_vmv_v_x_h, gen_helper_vmv_v_x_w, @@ -2891,6 +2899,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ s->cfg_ptr->vlen / 8, \ @@ -2944,6 +2953,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ s->cfg_ptr->vlen / 8, \ @@ -3012,6 +3022,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ s->cfg_ptr->vlen / 8, \ @@ -3067,6 +3078,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ s->cfg_ptr->vlen / 8, \ --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-IronPort-AV: E=Sophos;i="5.93,296,1654531200"; d="scan'208";a="210715036" IronPort-SDR: V8e7ed/5iO9ha4dDdjB3q15jI6qrVtS4UvXu+QZl+IrmseDwt7zRww4IoUv+x3aq++WQS1OGYc B9NsQ3QN+8HR89O8fsE9nX2pHSWsrgNqTDRXyUhQnZgA/fstp64wl+JwBTaLdCrEmpvVPCHhFt Mul61+YXMRJ7CyrAQoIvyW4XhJ4XEMh4+ycUWuODO91uYbIFnFZnkSGd7dZARai+AesFJj1+75 Ijzopm/ItYbYChgukQM3mnqLwh7rh5ibJZYpJRQQ2eaSRDhVVN2J5IhlSmAlYOimziyQPgD9S3 BQ/0LNUbb0SwnHYFpYnzWlYv IronPort-SDR: ld8FR29VoLGgAr/wbaawebMO6AVgI6l4uhwMBwAcgggELqdp7rImcHyroWEQzKlWsdavOTcK6d 0u2qd5wmLSFz5TJJ1YA/OUReukHahCqXzL4IZZ5h6vCzxqUShCMIWPorOtDSsYFdm0rBiQ2JmP QqnoVzKeRD8IElgO6sk7NbdzbUqtzfwE+r4a7PlfZKqdHVjEmVYIOSZ6ldeTlTmthf1fchiOqm nBGdm9HPPsrbCdQn62fdJ7aK+/d6IbHopQJuAQtpq4Ti+zDePB7AXcdfEBSlakjfOANRhd4i0G rwU= WDCIronportException: Internal To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, "Yueh-Ting (eop) Chen" , Frank Chang , Weiwei Li , Alistair Francis Subject: [PULL 22/44] target/riscv: rvv: Add mask agnostic for vector mask instructions Date: Wed, 7 Sep 2022 10:03:31 +0200 Message-Id: <20220907080353.111926-23-alistair.francis@wdc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907080353.111926-1-alistair.francis@wdc.com> References: <20220907080353.111926-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662540145869100001 Content-Type: text/plain; charset="utf-8" From: "Yueh-Ting (eop) Chen" Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis Message-Id: <165570784143.17634.35095816584573691-8@git.sr.ht> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 11 +++++++++++ target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ 2 files changed, 14 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 315742c6b8..52518648bb 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4879,11 +4879,16 @@ static void vmsetm(void *vd, void *v0, void *vs2, C= PURISCVState *env, uint32_t vl =3D env->vl; uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; uint32_t vta_all_1s =3D vext_vta_all_1s(desc); + uint32_t vma =3D vext_vma(desc); int i; bool first_mask_bit =3D false; =20 for (i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + if (vma) { + vext_set_elem_mask(vd, i, 1); + } continue; } /* write a zero to all following active elements */ @@ -4944,11 +4949,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CP= URISCVState *env, \ uint32_t esz =3D sizeof(ETYPE); = \ uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); = \ uint32_t vta =3D vext_vta(desc); = \ + uint32_t vma =3D vext_vma(desc); = \ uint32_t sum =3D 0; = \ int i; \ \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \ continue; \ } \ *((ETYPE *)vd + H(i)) =3D sum; = \ @@ -4975,10 +4983,13 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState= *env, uint32_t desc) \ uint32_t esz =3D sizeof(ETYPE); = \ uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); = \ uint32_t vta =3D vext_vta(desc); = \ + uint32_t vma =3D vext_vma(desc); = \ int i; \ \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \ continue; \ } \ *((ETYPE *)vd + H(i)) =3D i; = \ diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 8ce3d28603..c1bd29329e 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3275,6 +3275,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D \ FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \ vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \ cpu_env, s->cfg_ptr->vlen / 8, \ @@ -3313,6 +3314,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_= m *a) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); static gen_helper_gvec_3_ptr * const fns[4] =3D { gen_helper_viota_m_b, gen_helper_viota_m_h, gen_helper_viota_m_w, gen_helper_viota_m_d, @@ -3343,6 +3345,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); static gen_helper_gvec_2_ptr * const fns[4] =3D { gen_helper_vid_v_b, gen_helper_vid_v_h, gen_helper_vid_v_w, gen_helper_vid_v_d, --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662540475747100001 Content-Type: text/plain; charset="utf-8" From: "Yueh-Ting (eop) Chen" Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis Message-Id: <165570784143.17634.35095816584573691-9@git.sr.ht> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 26 +++++++++++++++++++++++-- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 52518648bb..d224861c2c 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -5018,11 +5018,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong = s1, void *vs2, \ uint32_t esz =3D sizeof(ETYPE); = \ uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); = \ uint32_t vta =3D vext_vta(desc); = \ + uint32_t vma =3D vext_vma(desc); = \ target_ulong offset =3D s1, i_min, i; = \ \ i_min =3D MAX(env->vstart, offset); = \ for (i =3D i_min; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \ continue; \ } \ *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i - offset)); = \ @@ -5047,13 +5050,17 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong = s1, void *vs2, \ uint32_t esz =3D sizeof(ETYPE); = \ uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); = \ uint32_t vta =3D vext_vta(desc); = \ + uint32_t vma =3D vext_vma(desc); = \ target_ulong i_max, i; \ \ i_max =3D MAX(MIN(s1 < vlmax ? vlmax - s1 : 0, vl), env->vstart); = \ for (i =3D env->vstart; i < i_max; ++i) { = \ - if (vm || vext_elem_mask(v0, i)) { \ - *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i + s1)); = \ + if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \ + continue; \ } \ + *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i + s1)); = \ } \ \ for (i =3D i_max; i < vl; ++i) { = \ @@ -5083,10 +5090,13 @@ static void vslide1up_##BITWIDTH(void *vd, void *v0= , target_ulong s1, \ uint32_t esz =3D sizeof(ETYPE); = \ uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); = \ uint32_t vta =3D vext_vta(desc); = \ + uint32_t vma =3D vext_vma(desc); = \ uint32_t i; = \ = \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { = \ + /* set masked-off elements to 1s */ = \ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); = \ continue; = \ } = \ if (i =3D=3D 0) { = \ @@ -5128,10 +5138,13 @@ static void vslide1down_##BITWIDTH(void *vd, void *= v0, target_ulong s1, \ uint32_t esz =3D sizeof(ETYPE); = \ uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); = \ uint32_t vta =3D vext_vta(desc); = \ + uint32_t vma =3D vext_vma(desc); = \ uint32_t i; = \ = \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { = \ + /* set masked-off elements to 1s */ = \ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); = \ continue; = \ } = \ if (i =3D=3D vl - 1) { = \ @@ -5199,11 +5212,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, vo= id *vs2, \ uint32_t esz =3D sizeof(TS2); = \ uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); = \ uint32_t vta =3D vext_vta(desc); = \ + uint32_t vma =3D vext_vma(desc); = \ uint64_t index; \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \ continue; \ } \ index =3D *((TS1 *)vs1 + HS1(i)); = \ @@ -5239,11 +5255,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong = s1, void *vs2, \ uint32_t esz =3D sizeof(ETYPE); = \ uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); = \ uint32_t vta =3D vext_vta(desc); = \ + uint32_t vma =3D vext_vma(desc); = \ uint64_t index =3D s1; = \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \ continue; \ } \ if (index >=3D vlmax) { = \ @@ -5318,10 +5337,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \ continue; \ } \ *((ETYPE *)vd + HD(i)) =3D *((DTYPE *)vs2 + HS1(i)); \ diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index c1bd29329e..e58208f363 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3891,6 +3891,7 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, u= int8_t seq) data =3D FIELD_DP32(data, VDATA, VM, a->vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); =20 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662540853; cv=none; d=zohomail.com; s=zohoarc; b=g3rbC1gjQIK8WuBQf2vDPX2xr1wqiMttbvvxI2xODGgZi93HlwH/Yz93PxCZuH2wtaw3KtHoJPH40iEm+ggIa7wXxZ9oCuZbjVLjrF1OHOTf08b1gBQgxskvT8S4nNQ0nPly459BYcp+g11rbyd2S/F5WEVlM+SGnmH/+lfF6HI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662540853; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662540855434100001 Content-Type: text/plain; charset="utf-8" From: eopXD According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elements' bits to all 1s". There are multiple possibility for agnostic elements according to v-spec. The main intent of this patch-set tries to add option that can distinguish between mask policies. Setting agnostic elements to all 1s allows QEMU to express this. This commit adds option 'rvv_ma_all_1s' is added to enable the behavior, it is default as disabled. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <165570784143.17634.35095816584573691-10@git.sr.ht> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 117d308ae5..966e5f2dd7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1061,6 +1061,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, f= alse), =20 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), + DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662538906156100001 Content-Type: text/plain; charset="utf-8" From: Dao Lu Added support for RISC-V PAUSE instruction from Zihintpause extension, enabled by default. Tested-by: Heiko Stuebner Reviewed-by: Alistair Francis Signed-off-by: Dao Lu Message-Id: <20220725034728.2620750-2-daolu@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/insn32.decode | 7 ++++++- target/riscv/cpu.c | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++++ 4 files changed, 25 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 561d7fa92c..4be4b82a83 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -426,6 +426,7 @@ struct RISCVCPUConfig { bool ext_zkt; bool ext_ifencei; bool ext_icsr; + bool ext_zihintpause; bool ext_svinval; bool ext_svnapot; bool ext_svpbmt; diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4033565393..595fdcdad8 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -149,7 +149,12 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r sra 0100000 ..... ..... 101 ..... 0110011 @r or 0000000 ..... ..... 110 ..... 0110011 @r and 0000000 ..... ..... 111 ..... 0110011 @r -fence ---- pred:4 succ:4 ----- 000 ----- 0001111 + +{ + pause 0000 0001 0000 00000 000 00000 0001111 + fence ---- pred:4 succ:4 ----- 000 ----- 0001111 +} + fence_i ---- ---- ---- ----- 001 ----- 0001111 csrrw ............ ..... 001 ..... 1110011 @csr csrrs ............ ..... 010 ..... 1110011 @csr diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 966e5f2dd7..d4635c7df4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -73,6 +73,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), + ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintp= ause), ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), @@ -987,6 +988,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), + DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index ca8e3d1ea1..c49dbec0eb 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -792,6 +792,22 @@ static bool trans_srad(DisasContext *ctx, arg_srad *a) return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL); } =20 +static bool trans_pause(DisasContext *ctx, arg_pause *a) +{ + if (!ctx->cfg_ptr->ext_zihintpause) { + return false; + } + + /* + * PAUSE is a no-op in QEMU, + * end the TB and return to main loop + */ + gen_set_pc_imm(ctx, ctx->pc_succ_insn); + tcg_gen_exit_tb(NULL, 0); + ctx->base.is_jmp =3D DISAS_NORETURN; + + return true; +} =20 static bool trans_fence(DisasContext *ctx, arg_fence *a) { --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662539257; cv=none; d=zohomail.com; s=zohoarc; b=Wl062GUpsmxYyTPEv+WIxLjmBlmFJhwnA/MBdZ37RvnwIo7aGUJ7FzhXizPB5bMyZykwlbgtp1a2p6hj9eLbDTHPgHBcCeCVlLVF077VnkWPxvDuDjRyyfA7ytvseTJoReXUTcGWWQ7+Swm6BYw5TVStiQTldB/974K1WNJx7R4= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662539258121100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza The 'fdt' param is not being used in riscv_setup_rom_reset_vec(). Simplify the API by removing it. While we're at it, remove the redundant 'return' statement at the end of function. Cc: Palmer Dabbelt Cc: Alistair Francis Cc: Bin Meng Cc: Vijai Kumar K Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20220728181926.2123771-1-danielhb413@gmail.com> Signed-off-by: Alistair Francis --- include/hw/riscv/boot.h | 2 +- hw/riscv/boot.c | 4 +--- hw/riscv/microchip_pfsoc.c | 2 +- hw/riscv/shakti_c.c | 3 +-- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 2 +- 6 files changed, 6 insertions(+), 9 deletions(-) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index d2db29721a..a36f7618f5 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -51,7 +51,7 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RIS= CVHartArrayState *harts hwaddr saddr, hwaddr rom_base, hwaddr rom_size, uint64_t kernel_entry, - uint64_t fdt_load_addr, void *fdt); + uint64_t fdt_load_addr); void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, hwaddr rom_size, uint32_t reset_vec_size, diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 06b4fc5ac3..1ae7596873 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -286,7 +286,7 @@ void riscv_setup_rom_reset_vec(MachineState *machine, R= ISCVHartArrayState *harts hwaddr start_addr, hwaddr rom_base, hwaddr rom_size, uint64_t kernel_entry, - uint64_t fdt_load_addr, void *fdt) + uint64_t fdt_load_addr) { int i; uint32_t start_addr_hi32 =3D 0x00000000; @@ -326,8 +326,6 @@ void riscv_setup_rom_reset_vec(MachineState *machine, R= ISCVHartArrayState *harts rom_base, &address_space_memory); riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset= _vec), kernel_entry); - - return; } =20 void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 10a5d0e501..7313153606 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -583,7 +583,7 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_a= ddr, memmap[MICROCHIP_PFSOC_ENVM_DATA].base, memmap[MICROCHIP_PFSOC_ENVM_DATA].size, - kernel_entry, fdt_load_addr, machine->fd= t); + kernel_entry, fdt_load_addr); } } =20 diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index 90e2cf609f..e43cc9445c 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -66,8 +66,7 @@ static void shakti_c_machine_state_init(MachineState *mst= ate) riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus, shakti_c_memmap[SHAKTI_C_RAM].base, shakti_c_memmap[SHAKTI_C_ROM].base, - shakti_c_memmap[SHAKTI_C_ROM].size, 0, 0, - NULL); + shakti_c_memmap[SHAKTI_C_ROM].size, 0, 0); if (mstate->firmware) { riscv_load_firmware(mstate->firmware, shakti_c_memmap[SHAKTI_C_RAM].base, diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index e41b6aa9f0..5ba34543c8 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -308,7 +308,7 @@ static void spike_board_init(MachineState *machine) riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base, memmap[SPIKE_MROM].size, kernel_entry, - fdt_load_addr, s->fdt); + fdt_load_addr); =20 /* initialize HTIF using symbols found in load_kernel */ htif_mm_init(system_memory, mask_rom, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f2ce5663a4..c1e8e0fcaf 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1305,7 +1305,7 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, virt_memmap[VIRT_MROM].base, virt_memmap[VIRT_MROM].size, kernel_entry, - fdt_load_addr, machine->fdt); + fdt_load_addr); =20 /* * Only direct boot kernel is currently supported for KVM VM, --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662540942; cv=none; d=zohomail.com; s=zohoarc; b=gpMb/o5F9j/iphi9I8DY8oyfMUEVlVkxx7qH0ruF/Bzdm0BPpvoo5ep0msgSVfl0eeSh6TZ5Uy2lMWmgchXa17mn+LAR6A0Svw9nFeaoubhWl/qBCYv3BZZ+wmMTZAq6MsX9O48fuJ8gvaJxvNQj3d2OrXBZNpahHcDEuUGrJzQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662540942; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=h/mlMC5htKhJNweiE7uBQWYs3+KxBqXMK0/9UIAl3Rg=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662540943842100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Normally, riscv_csrrw_check is called when executing Zicsr instructions. And we can only do access control for existed CSRs. So the priority of CSR related check, from highest to lowest, should be as follows: 1) check whether Zicsr is supported: raise RISCV_EXCP_ILLEGAL_INST if not 2) check whether csr is existed: raise RISCV_EXCP_ILLEGAL_INST if not 3) do access control: raise RISCV_EXCP_ILLEGAL_INST or RISCV_EXCP_VIRT_ INSTRUCTION_FAULT if not allowed The predicates contain parts of function of both 2) and 3), So they need to be placed in the middle of riscv_csrrw_check Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Message-Id: <20220803123652.3700-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 44 +++++++++++++++++++++++++------------------- 1 file changed, 25 insertions(+), 19 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0fb042b2fd..d81f466c80 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3270,6 +3270,30 @@ static inline RISCVException riscv_csrrw_check(CPURI= SCVState *env, /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails = */ int read_only =3D get_field(csrno, 0xC00) =3D=3D 3; int csr_min_priv =3D csr_ops[csrno].min_priv_ver; + + /* ensure the CSR extension is enabled. */ + if (!cpu->cfg.ext_icsr) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (env->priv_ver < csr_min_priv) { + return RISCV_EXCP_ILLEGAL_INST; + } + + /* check predicate */ + if (!csr_ops[csrno].predicate) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (write_mask && read_only) { + return RISCV_EXCP_ILLEGAL_INST; + } + + RISCVException ret =3D csr_ops[csrno].predicate(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + #if !defined(CONFIG_USER_ONLY) int csr_priv, effective_priv =3D env->priv; =20 @@ -3290,25 +3314,7 @@ static inline RISCVException riscv_csrrw_check(CPURI= SCVState *env, return RISCV_EXCP_ILLEGAL_INST; } #endif - if (write_mask && read_only) { - return RISCV_EXCP_ILLEGAL_INST; - } - - /* ensure the CSR extension is enabled. */ - if (!cpu->cfg.ext_icsr) { - return RISCV_EXCP_ILLEGAL_INST; - } - - /* check predicate */ - if (!csr_ops[csrno].predicate) { - return RISCV_EXCP_ILLEGAL_INST; - } - - if (env->priv_ver < csr_min_priv) { - return RISCV_EXCP_ILLEGAL_INST; - } - - return csr_ops[csrno].predicate(env, csrno); + return RISCV_EXCP_NONE; } =20 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno, --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662541956; cv=none; d=zohomail.com; s=zohoarc; b=dxGLY1lRki2cHYDXJE4SAdJb/qrzmSPVtoVvTqAVMSfxaEwjYIO0Odc/Ax/vsxCnGjla9bnkyT3GmzjsN8z2AXqMdLNM3S6/vvqwjz5k/t80bW5imcrWD420QramkQVcQZvK9KNcH9jK+g87/wgyTYjPBWohzQF0pdRstQcqdEQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662541956; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; 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X-IronPort-AV: E=Sophos;i="5.93,296,1654531200"; d="scan'208";a="210715068" IronPort-SDR: IZ31FHc41Qb7Lz+gJ3Mn7yRS70TpEYTm8tqtANe69r4YtJJd4+9dPc+wkHxcIGxd73VV4XqJVF zYfBDa0dCesmyFz6JTrObb9W7d2/vb7AyA4LbbYM6OyhCRF+1BrcyCR8Arq2IFqHqfFbmtTad0 gs6kzpb2d2S7AZOr3CY4d40LgUXl9TW+FRpvZaQ2GVzH0OmIiRZ16bL7wyBajIll0I7wZeEI01 WStwIXMDr5ygi0EGku+FG27HWe2/7cjGkJ4rnKr1ZfYrUDZToV444UA6X5pj+0RToRFFhRB5Rh LTUm4GbfyRr1l31JiVcwMAmV IronPort-SDR: rmJ+5RY6hevajAzEy4CzUEk5L588rwPgV7t4K1eAWNhZnzJW3GtprFNRv/sb4PtopbJive1UfX qMf70SCCciBxfIMP13VjDjq73XfTgRt0F5I/7azRn+n4FdXprK8unf3wuNe6j+CTwB3Tn0yrUO 1V09duRwKQw+j9YITWlw4VUcqy1IAavyR2k45L8bcT5KyNW4VnrCxnPlDyKcSXpKug/pEpauTC 9XDgOdja2mblD8/Xbp+dm8sJ+zxczQ0lQyDl0UcX/jUtVSnUj0fJb7xYa0+jk3IMUKuY2AqK6S zwU= WDCIronportException: Internal To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Wilfred Mallawa , Alistair Francis Subject: [PULL 28/44] hw/riscv: opentitan: bump opentitan version Date: Wed, 7 Sep 2022 10:03:37 +0200 Message-Id: <20220907080353.111926-29-alistair.francis@wdc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907080353.111926-1-alistair.francis@wdc.com> References: <20220907080353.111926-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662541957968100003 Content-Type: text/plain; charset="utf-8" From: Wilfred Mallawa The following patch updates opentitan to match the new configuration, as per, lowRISC/opentitan@217a0168ba118503c166a9587819e3811eeb0c0c Note: with this patch we now skip the usage of the opentitan `boot_rom`. The Opentitan boot rom contains hw verification for devies which we are currently not supporting in qemu. As of now, the `boot_rom` has no major significance, however, would be good to support in the future. Tested by running utests from the latest tock [1] (that supports this version of OT). [1] https://github.com/tock/tock/pull/3056 Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis Message-Id: <20220812005229.358850-1-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis --- include/hw/riscv/opentitan.h | 11 ++++++----- hw/riscv/opentitan.c | 12 ++++++++---- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 68892cd8e5..26d960f288 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -74,6 +74,7 @@ enum { IBEX_DEV_TIMER, IBEX_DEV_SENSOR_CTRL, IBEX_DEV_OTP_CTRL, + IBEX_DEV_LC_CTRL, IBEX_DEV_PWRMGR, IBEX_DEV_RSTMGR, IBEX_DEV_CLKMGR, @@ -105,11 +106,11 @@ enum { IBEX_UART0_RX_BREAK_ERR_IRQ =3D 6, IBEX_UART0_RX_TIMEOUT_IRQ =3D 7, IBEX_UART0_RX_PARITY_ERR_IRQ =3D 8, - IBEX_TIMER_TIMEREXPIRED0_0 =3D 126, - IBEX_SPI_HOST0_ERR_IRQ =3D 150, - IBEX_SPI_HOST0_SPI_EVENT_IRQ =3D 151, - IBEX_SPI_HOST1_ERR_IRQ =3D 152, - IBEX_SPI_HOST1_SPI_EVENT_IRQ =3D 153, + IBEX_TIMER_TIMEREXPIRED0_0 =3D 127, + IBEX_SPI_HOST0_ERR_IRQ =3D 151, + IBEX_SPI_HOST0_SPI_EVENT_IRQ =3D 152, + IBEX_SPI_HOST1_ERR_IRQ =3D 153, + IBEX_SPI_HOST1_SPI_EVENT_IRQ =3D 154, }; =20 #endif diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 4495a2c039..af13dbe3b1 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -29,9 +29,9 @@ #include "sysemu/sysemu.h" =20 static const MemMapEntry ibex_memmap[] =3D { - [IBEX_DEV_ROM] =3D { 0x00008000, 16 * KiB }, - [IBEX_DEV_RAM] =3D { 0x10000000, 0x10000 }, - [IBEX_DEV_FLASH] =3D { 0x20000000, 0x80000 }, + [IBEX_DEV_ROM] =3D { 0x00008000, 0x8000 }, + [IBEX_DEV_RAM] =3D { 0x10000000, 0x20000 }, + [IBEX_DEV_FLASH] =3D { 0x20000000, 0x100000 }, [IBEX_DEV_UART] =3D { 0x40000000, 0x1000 }, [IBEX_DEV_GPIO] =3D { 0x40040000, 0x1000 }, [IBEX_DEV_SPI_DEVICE] =3D { 0x40050000, 0x1000 }, @@ -40,6 +40,7 @@ static const MemMapEntry ibex_memmap[] =3D { [IBEX_DEV_TIMER] =3D { 0x40100000, 0x1000 }, [IBEX_DEV_SENSOR_CTRL] =3D { 0x40110000, 0x1000 }, [IBEX_DEV_OTP_CTRL] =3D { 0x40130000, 0x4000 }, + [IBEX_DEV_LC_CTRL] =3D { 0x40140000, 0x1000 }, [IBEX_DEV_USBDEV] =3D { 0x40150000, 0x1000 }, [IBEX_DEV_SPI_HOST0] =3D { 0x40300000, 0x1000 }, [IBEX_DEV_SPI_HOST1] =3D { 0x40310000, 0x1000 }, @@ -141,7 +142,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_s= oc, Error **errp) &error_abort); object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, &error_abort); - object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_a= bort); + object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000490, + &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); =20 /* Boot ROM */ @@ -253,6 +255,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_s= oc, Error **errp) memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].si= ze); create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl", memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size); + create_unimplemented_device("riscv.lowrisc.ibex.lc_ctrl", + memmap[IBEX_DEV_LC_CTRL].base, memmap[IBEX_DEV_LC_CTRL].size); create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr", memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size); create_unimplemented_device("riscv.lowrisc.ibex.rstmgr", --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662542336015100003 Content-Type: text/plain; charset="utf-8" From: Conor Dooley Booting using "Direct Kernel Boot" for PolarFire SoC & skipping u-boot entirely is probably not advisable, but it does at least show signs of life. Recent Linux kernel versions make use of peripherals that are missing definitions in QEMU and lead to kernel panics. These issues almost certain rear their head for other methods of booting, but I was unable to figure out a suitable HSS version that is recent enough to support these peripherals & works with QEMU. With these peripherals added, booting a kernel with the following hangs hangs waiting for the system controller's hwrng, but the kernel no longer panics. With the Linux driver for hwrng disabled, it boots to console. qemu-system-riscv64 -M microchip-icicle-kit \ -m 2G -smp 5 \ -kernel $(vmlinux_bin) \ -dtb $(dtb)\ -initrd $(initramfs) \ -display none -serial null \ -serial stdio More peripherals are added than strictly required to fix the panics in the hopes of avoiding a replication of this problem in the future. Some of the peripherals which are in the device tree for recent kernels are implemented in the FPGA fabric. The eMMC/SD mux, which exists as an unimplemented device is replaced by a wider entry. This updated entry covers both the mux & the remainder of the FPGA fabric connected to the MSS using Fabric Interrconnect (FIC) 3. Link: https://github.com/polarfire-soc/icicle-kit-reference-design#fabric-m= emory-map Link: https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/Produ= ctDocuments/SupportingCollateral/V1_4_Register_Map.zip Signed-off-by: Conor Dooley Reviewed-by: Alistair Francis Message-Id: <20220813135127.2971754-1-mail@conchuod.ie> Signed-off-by: Alistair Francis --- include/hw/riscv/microchip_pfsoc.h | 14 ++++++- hw/riscv/microchip_pfsoc.c | 67 +++++++++++++++++++++++++++--- 2 files changed, 74 insertions(+), 7 deletions(-) diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchi= p_pfsoc.h index a0673f5f59..a757b240e0 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -88,8 +88,11 @@ enum { MICROCHIP_PFSOC_L2LIM, MICROCHIP_PFSOC_PLIC, MICROCHIP_PFSOC_MMUART0, + MICROCHIP_PFSOC_WDOG0, MICROCHIP_PFSOC_SYSREG, + MICROCHIP_PFSOC_AXISW, MICROCHIP_PFSOC_MPUCFG, + MICROCHIP_PFSOC_FMETER, MICROCHIP_PFSOC_DDR_SGMII_PHY, MICROCHIP_PFSOC_EMMC_SD, MICROCHIP_PFSOC_DDR_CFG, @@ -97,19 +100,28 @@ enum { MICROCHIP_PFSOC_MMUART2, MICROCHIP_PFSOC_MMUART3, MICROCHIP_PFSOC_MMUART4, + MICROCHIP_PFSOC_WDOG1, + MICROCHIP_PFSOC_WDOG2, + MICROCHIP_PFSOC_WDOG3, + MICROCHIP_PFSOC_WDOG4, MICROCHIP_PFSOC_SPI0, MICROCHIP_PFSOC_SPI1, + MICROCHIP_PFSOC_I2C0, MICROCHIP_PFSOC_I2C1, + MICROCHIP_PFSOC_CAN0, + MICROCHIP_PFSOC_CAN1, MICROCHIP_PFSOC_GEM0, MICROCHIP_PFSOC_GEM1, MICROCHIP_PFSOC_GPIO0, MICROCHIP_PFSOC_GPIO1, MICROCHIP_PFSOC_GPIO2, + MICROCHIP_PFSOC_RTC, MICROCHIP_PFSOC_ENVM_CFG, MICROCHIP_PFSOC_ENVM_DATA, + MICROCHIP_PFSOC_USB, MICROCHIP_PFSOC_QSPI_XIP, MICROCHIP_PFSOC_IOSCB, - MICROCHIP_PFSOC_EMMC_SD_MUX, + MICROCHIP_PFSOC_FABRIC_FIC3, MICROCHIP_PFSOC_DRAM_LO, MICROCHIP_PFSOC_DRAM_LO_ALIAS, MICROCHIP_PFSOC_DRAM_HI, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 7313153606..a821263d4f 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -100,8 +100,11 @@ static const MemMapEntry microchip_pfsoc_memmap[] =3D { [MICROCHIP_PFSOC_L2LIM] =3D { 0x8000000, 0x2000000 }, [MICROCHIP_PFSOC_PLIC] =3D { 0xc000000, 0x4000000 }, [MICROCHIP_PFSOC_MMUART0] =3D { 0x20000000, 0x1000 }, + [MICROCHIP_PFSOC_WDOG0] =3D { 0x20001000, 0x1000 }, [MICROCHIP_PFSOC_SYSREG] =3D { 0x20002000, 0x2000 }, + [MICROCHIP_PFSOC_AXISW] =3D { 0x20004000, 0x1000 }, [MICROCHIP_PFSOC_MPUCFG] =3D { 0x20005000, 0x1000 }, + [MICROCHIP_PFSOC_FMETER] =3D { 0x20006000, 0x1000 }, [MICROCHIP_PFSOC_DDR_SGMII_PHY] =3D { 0x20007000, 0x1000 }, [MICROCHIP_PFSOC_EMMC_SD] =3D { 0x20008000, 0x1000 }, [MICROCHIP_PFSOC_DDR_CFG] =3D { 0x20080000, 0x40000 }, @@ -109,19 +112,28 @@ static const MemMapEntry microchip_pfsoc_memmap[] =3D= { [MICROCHIP_PFSOC_MMUART2] =3D { 0x20102000, 0x1000 }, [MICROCHIP_PFSOC_MMUART3] =3D { 0x20104000, 0x1000 }, [MICROCHIP_PFSOC_MMUART4] =3D { 0x20106000, 0x1000 }, + [MICROCHIP_PFSOC_WDOG1] =3D { 0x20101000, 0x1000 }, + [MICROCHIP_PFSOC_WDOG2] =3D { 0x20103000, 0x1000 }, + [MICROCHIP_PFSOC_WDOG3] =3D { 0x20105000, 0x1000 }, + [MICROCHIP_PFSOC_WDOG4] =3D { 0x20106000, 0x1000 }, [MICROCHIP_PFSOC_SPI0] =3D { 0x20108000, 0x1000 }, [MICROCHIP_PFSOC_SPI1] =3D { 0x20109000, 0x1000 }, + [MICROCHIP_PFSOC_I2C0] =3D { 0x2010a000, 0x1000 }, [MICROCHIP_PFSOC_I2C1] =3D { 0x2010b000, 0x1000 }, + [MICROCHIP_PFSOC_CAN0] =3D { 0x2010c000, 0x1000 }, + [MICROCHIP_PFSOC_CAN1] =3D { 0x2010d000, 0x1000 }, [MICROCHIP_PFSOC_GEM0] =3D { 0x20110000, 0x2000 }, [MICROCHIP_PFSOC_GEM1] =3D { 0x20112000, 0x2000 }, [MICROCHIP_PFSOC_GPIO0] =3D { 0x20120000, 0x1000 }, [MICROCHIP_PFSOC_GPIO1] =3D { 0x20121000, 0x1000 }, [MICROCHIP_PFSOC_GPIO2] =3D { 0x20122000, 0x1000 }, + [MICROCHIP_PFSOC_RTC] =3D { 0x20124000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_CFG] =3D { 0x20200000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_DATA] =3D { 0x20220000, 0x20000 }, + [MICROCHIP_PFSOC_USB] =3D { 0x20201000, 0x1000 }, [MICROCHIP_PFSOC_QSPI_XIP] =3D { 0x21000000, 0x1000000 }, [MICROCHIP_PFSOC_IOSCB] =3D { 0x30000000, 0x10000000 }, - [MICROCHIP_PFSOC_EMMC_SD_MUX] =3D { 0x4f000000, 0x4 }, + [MICROCHIP_PFSOC_FABRIC_FIC3] =3D { 0x40000000, 0x20000000 }, [MICROCHIP_PFSOC_DRAM_LO] =3D { 0x80000000, 0x40000000 }, [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =3D { 0xc0000000, 0x40000000 }, [MICROCHIP_PFSOC_DRAM_HI] =3D { 0x1000000000, 0x0 }, @@ -292,11 +304,21 @@ static void microchip_pfsoc_soc_realize(DeviceState *= dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0, memmap[MICROCHIP_PFSOC_SYSREG].base); =20 + /* AXISW */ + create_unimplemented_device("microchip.pfsoc.axisw", + memmap[MICROCHIP_PFSOC_AXISW].base, + memmap[MICROCHIP_PFSOC_AXISW].size); + /* MPUCFG */ create_unimplemented_device("microchip.pfsoc.mpucfg", memmap[MICROCHIP_PFSOC_MPUCFG].base, memmap[MICROCHIP_PFSOC_MPUCFG].size); =20 + /* FMETER */ + create_unimplemented_device("microchip.pfsoc.fmeter", + memmap[MICROCHIP_PFSOC_FMETER].base, + memmap[MICROCHIP_PFSOC_FMETER].size); + /* DDR SGMII PHY */ sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp); sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0, @@ -336,6 +358,23 @@ static void microchip_pfsoc_soc_realize(DeviceState *d= ev, Error **errp) qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), serial_hd(4)); =20 + /* Watchdogs */ + create_unimplemented_device("microchip.pfsoc.watchdog0", + memmap[MICROCHIP_PFSOC_WDOG0].base, + memmap[MICROCHIP_PFSOC_WDOG0].size); + create_unimplemented_device("microchip.pfsoc.watchdog1", + memmap[MICROCHIP_PFSOC_WDOG1].base, + memmap[MICROCHIP_PFSOC_WDOG1].size); + create_unimplemented_device("microchip.pfsoc.watchdog2", + memmap[MICROCHIP_PFSOC_WDOG2].base, + memmap[MICROCHIP_PFSOC_WDOG2].size); + create_unimplemented_device("microchip.pfsoc.watchdog3", + memmap[MICROCHIP_PFSOC_WDOG3].base, + memmap[MICROCHIP_PFSOC_WDOG3].size); + create_unimplemented_device("microchip.pfsoc.watchdog4", + memmap[MICROCHIP_PFSOC_WDOG4].base, + memmap[MICROCHIP_PFSOC_WDOG4].size); + /* SPI */ create_unimplemented_device("microchip.pfsoc.spi0", memmap[MICROCHIP_PFSOC_SPI0].base, @@ -344,11 +383,27 @@ static void microchip_pfsoc_soc_realize(DeviceState *= dev, Error **errp) memmap[MICROCHIP_PFSOC_SPI1].base, memmap[MICROCHIP_PFSOC_SPI1].size); =20 - /* I2C1 */ + /* I2C */ + create_unimplemented_device("microchip.pfsoc.i2c0", + memmap[MICROCHIP_PFSOC_I2C0].base, + memmap[MICROCHIP_PFSOC_I2C0].size); create_unimplemented_device("microchip.pfsoc.i2c1", memmap[MICROCHIP_PFSOC_I2C1].base, memmap[MICROCHIP_PFSOC_I2C1].size); =20 + /* CAN */ + create_unimplemented_device("microchip.pfsoc.can0", + memmap[MICROCHIP_PFSOC_CAN0].base, + memmap[MICROCHIP_PFSOC_CAN0].size); + create_unimplemented_device("microchip.pfsoc.can1", + memmap[MICROCHIP_PFSOC_CAN1].base, + memmap[MICROCHIP_PFSOC_CAN1].size); + + /* USB */ + create_unimplemented_device("microchip.pfsoc.usb", + memmap[MICROCHIP_PFSOC_USB].base, + memmap[MICROCHIP_PFSOC_USB].size); + /* GEMs */ =20 nd =3D &nd_table[0]; @@ -402,10 +457,10 @@ static void microchip_pfsoc_soc_realize(DeviceState *= dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, memmap[MICROCHIP_PFSOC_IOSCB].base); =20 - /* eMMC/SD mux */ - create_unimplemented_device("microchip.pfsoc.emmc_sd_mux", - memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base, - memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size); + /* FPGA Fabric */ + create_unimplemented_device("microchip.pfsoc.fabricfic3", + memmap[MICROCHIP_PFSOC_FABRIC_FIC3].base, + memmap[MICROCHIP_PFSOC_FABRIC_FIC3].size); =20 /* QSPI Flash */ memory_region_init_rom(qspi_xip_mem, OBJECT(dev), --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662541191825100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra With .min_priv_version, additiona priv version check is uncessary for mcountinhibit read/write functions. Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-Id: <20220816232321.558250-7-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d81f466c80..4a7078f7d1 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1494,10 +1494,6 @@ static RISCVException write_mtvec(CPURISCVState *env= , int csrno, static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno, target_ulong *val) { - if (env->priv_ver < PRIV_VERSION_1_11_0) { - return RISCV_EXCP_ILLEGAL_INST; - } - *val =3D env->mcountinhibit; return RISCV_EXCP_NONE; } @@ -1508,10 +1504,6 @@ static RISCVException write_mcountinhibit(CPURISCVSt= ate *env, int csrno, int cidx; PMUCTRState *counter; =20 - if (env->priv_ver < PRIV_VERSION_1_11_0) { - return RISCV_EXCP_ILLEGAL_INST; - } - env->mcountinhibit =3D val; =20 /* Check if any other counter is also monitoring cycles/instructions */ --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662542866998100001 Content-Type: text/plain; charset="utf-8" From: Conor Dooley "uart" is not a node name that complies with the dt-schema. Change the node name to "serial" to ix warnings seen during dt-validate on a dtbdump of the virt machine such as: /stuff/qemu/qemu.dtb: uart@10000000: $nodename:0: 'uart@10000000' does not = match '^serial(@.*)?$' From schema: /stuff/linux/Documentation/devicetree/bindings/serial/= 8250.yaml Reported-by: Rob Herring Reviewed-by: Alistair Francis Signed-off-by: Conor Dooley Message-id: 20220810184612.157317-2-mail@conchuod.ie Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@ker= nel.org/ Fixes: 04331d0b56 ("RISC-V VirtIO Machine") Signed-off-by: Conor Dooley Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c1e8e0fcaf..9d36133b74 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -918,7 +918,7 @@ static void create_fdt_uart(RISCVVirtState *s, const Me= mMapEntry *memmap, char *name; MachineState *mc =3D MACHINE(s); =20 - name =3D g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].bas= e); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662539613774100001 Content-Type: text/plain; charset="utf-8" From: Conor Dooley When optional AIA PLIC support was added the to the virt machine, the address cells property was removed leading the issues with dt-validate on a dump from the virt machine: /stuff/qemu/qemu.dtb: plic@c000000: '#address-cells' is a required property From schema: /stuff/linux/Documentation/devicetree/bindings/interru= pt-controller/sifive,plic-1.0.0.yaml Add back the property to suppress the warning. Reported-by: Rob Herring Reviewed-by: Alistair Francis Signed-off-by: Conor Dooley Message-id: 20220810184612.157317-3-mail@conchuod.ie Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@ker= nel.org/ Fixes: e6faee6585 ("hw/riscv: virt: Add optional AIA APLIC support to virt = machine") Signed-off-by: Conor Dooley Signed-off-by: Alistair Francis --- include/hw/riscv/virt.h | 1 + hw/riscv/virt.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 984e55c77f..be4ab8fe7f 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -111,6 +111,7 @@ enum { =20 #define FDT_PCI_ADDR_CELLS 3 #define FDT_PCI_INT_CELLS 1 +#define FDT_PLIC_ADDR_CELLS 0 #define FDT_PLIC_INT_CELLS 1 #define FDT_APLIC_INT_CELLS 2 #define FDT_IMSIC_INT_CELLS 0 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 9d36133b74..f19758e1df 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -466,6 +466,8 @@ static void create_fdt_socket_plic(RISCVVirtState *s, qemu_fdt_add_subnode(mc->fdt, plic_name); qemu_fdt_setprop_cell(mc->fdt, plic_name, "#interrupt-cells", FDT_PLIC_INT_CELLS); + qemu_fdt_setprop_cell(mc->fdt, plic_name, + "#address-cells", FDT_PLIC_ADDR_CELLS); qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", (char **)&plic_compat, ARRAY_SIZE(plic_compat)); --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662541371; cv=none; d=zohomail.com; s=zohoarc; b=h1Pyfx2+Z02+NVGaJE6Y37TDOF01bNF1tpITjuScTB7wCKv3mTI5OErrparsTfRz9e8nas8+gMJmthYMIlXk3UIkstIMZmlb0Rj7+sB4QutAsh6ywCF14UvWM0wHalG34fCfoPdcxq3MSL68e90lrGuOUycOm3C8uidw53EXz54= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662541371; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662541372135100001 Content-Type: text/plain; charset="utf-8" From: Conor Dooley The reset and poweroff features of the syscon were originally added to top level, which is a valid path for a syscon subnode. Subsequently a reorganisation was carried out while implementing NUMA in which the subnodes were moved into the /soc node. As /soc is a "simple-bus", this path is invalid, and so dt-validate produces the following warnings: /stuff/qemu/qemu.dtb: soc: poweroff: {'value': [[21845]], 'offset': [[0]], = 'regmap': [[4]], 'compatible': ['syscon-poweroff']} should not be valid und= er {'type': 'object'} From schema: /home/conor/.local/lib/python3.9/site-packages/dtschem= a/schemas/simple-bus.yaml /stuff/qemu/qemu.dtb: soc: reboot: {'value': [[30583]], 'offset': [[0]], 'r= egmap': [[4]], 'compatible': ['syscon-reboot']} should not be valid under {= 'type': 'object'} From schema: /home/conor/.local/lib/python3.9/site-packages/dtschem= a/schemas/simple-bus.yaml Move the syscon subnodes back to the top level and silence the warnings. Reported-by: Rob Herring Signed-off-by: Conor Dooley Reviewed-by: Alistair Francis Message-id: 20220810184612.157317-4-mail@conchuod.ie Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@ker= nel.org/ Fixes: 18df0b4695 ("hw/riscv: virt: Allow creating multiple NUMA sockets") Signed-off-by: Conor Dooley Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f19758e1df..686341a0e2 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -897,7 +897,7 @@ static void create_fdt_reset(RISCVVirtState *s, const M= emMapEntry *memmap, test_phandle =3D qemu_fdt_get_phandle(mc->fdt, name); g_free(name); =20 - name =3D g_strdup_printf("/soc/reboot"); + name =3D g_strdup_printf("/reboot"); qemu_fdt_add_subnode(mc->fdt, name); qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"); qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); @@ -905,7 +905,7 @@ static void create_fdt_reset(RISCVVirtState *s, const M= emMapEntry *memmap, qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); g_free(name); =20 - name =3D g_strdup_printf("/soc/poweroff"); + name =3D g_strdup_printf("/poweroff"); qemu_fdt_add_subnode(mc->fdt, name); qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff"= ); qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662542156; cv=none; d=zohomail.com; s=zohoarc; b=BvNP/lOZd7tNnqh1LGGy4LwTQxCEGrrQoDxzbN+Zr4Kr5IH7N3c6Z3IlAY85cDrXtZo2dz6ap8UjNeuUrBLmvRhEf+9VLMn2kmouIZP2TQL+pU14u8y4CKMfhnX2FoHpEveC3OQhvOAHHqMyQ0/BBRRhkGJ6f9ao2YkqdHtTwLQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662542156; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662542156904100001 Content-Type: text/plain; charset="utf-8" From: Conor Dooley "platform" is not a valid name for a bus node in dt-schema, so warnings can be see in dt-validate on a dump of the riscv virt dtb: /stuff/qemu/qemu.dtb: platform@4000000: $nodename:0: 'platform@4000000' doe= s not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /home/conor/.local/lib/python3.9/site-packages/dtschem= a/schemas/simple-bus.yaml "platform-bus" is a valid name, so use that instead. CC: Rob Herring Fixes: 11d306b9df ("hw/arm/sysbus-fdt: helpers for platform bus nodes addit= ion") Reviewed-by: Alistair Francis Signed-off-by: Conor Dooley Message-id: 20220810184612.157317-5-mail@conchuod.ie Signed-off-by: Alistair Francis --- hw/core/sysbus-fdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/core/sysbus-fdt.c b/hw/core/sysbus-fdt.c index 19d22cbe73..edb0c49b19 100644 --- a/hw/core/sysbus-fdt.c +++ b/hw/core/sysbus-fdt.c @@ -539,7 +539,7 @@ void platform_bus_add_all_fdt_nodes(void *fdt, const ch= ar *intc, hwaddr addr, =20 assert(fdt); =20 - node =3D g_strdup_printf("/platform@%"PRIx64, addr); + node =3D g_strdup_printf("/platform-bus@%"PRIx64, addr); =20 /* Create a /platform node that we can put all devices into */ qemu_fdt_add_subnode(fdt, node); --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662541933744100001 Content-Type: text/plain; charset="utf-8" From: Rahul Pathak XVentanaCondOps is Ventana custom extension. Add its extension entry in the ISA Ext array Signed-off-by: Rahul Pathak Reviewed-by: Alistair Francis Message-id: 20220816045408.1231135-1-rpathak@ventanamicro.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d4635c7df4..e0d5941230 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -102,6 +102,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVe= ntanaCondOps), }; =20 static bool isa_ext_is_enabled(RISCVCPU *cpu, --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662541752614100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel The arch review of AIA spec is completed and we now have official extension names for AIA: Smaia (M-mode AIA CSRs) and Ssaia (S-mode AIA CSRs). Refer, section 1.6 of the latest AIA v0.3.1 stable specification at https://github.com/riscv/riscv-aia/releases/download/0.3.1-draft.32/riscv-i= nterrupts-032.pdf) Based on above, we update QEMU RISC-V to: 1) Have separate config options for Smaia and Ssaia extensions which replace RISCV_FEATURE_AIA in CPU features 2) Not generate AIA INTC compatible string in virt machine Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-id: 20220820042958.377018-1-apatel@ventanamicro.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 4 ++-- hw/intc/riscv_imsic.c | 4 +++- hw/riscv/virt.c | 13 ++----------- target/riscv/cpu.c | 9 ++++----- target/riscv/cpu_helper.c | 3 ++- target/riscv/csr.c | 24 ++++++++++++++++++------ 6 files changed, 31 insertions(+), 26 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4be4b82a83..081cd05544 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -85,7 +85,6 @@ enum { RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, RISCV_FEATURE_MISA, - RISCV_FEATURE_AIA, RISCV_FEATURE_DEBUG }; =20 @@ -439,6 +438,8 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; bool ext_zmmul; + bool ext_smaia; + bool ext_ssaia; bool rvv_ta_all_1s; bool rvv_ma_all_1s; =20 @@ -459,7 +460,6 @@ struct RISCVCPUConfig { bool mmu; bool pmp; bool epmp; - bool aia; bool debug; uint64_t resetvec; =20 diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index 8615e4cc1d..4d4d5b50ca 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -344,9 +344,11 @@ static void riscv_imsic_realize(DeviceState *dev, Erro= r **errp) =20 /* Force select AIA feature and setup CSR read-modify-write callback */ if (env) { - riscv_set_feature(env, RISCV_FEATURE_AIA); if (!imsic->mmode) { + rcpu->cfg.ext_ssaia =3D true; riscv_cpu_set_geilen(env, imsic->num_pages - 1); + } else { + rcpu->cfg.ext_smaia =3D true; } riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S, riscv_imsic_rmw, imsic); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 686341a0e2..ff8c0df5cd 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -260,17 +260,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, = int socket, qemu_fdt_add_subnode(mc->fdt, intc_name); qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", intc_phandles[cpu]); - if (riscv_feature(&s->soc[socket].harts[cpu].env, - RISCV_FEATURE_AIA)) { - static const char * const compat[2] =3D { - "riscv,cpu-intc-aia", "riscv,cpu-intc" - }; - qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible", - (char **)&compat, ARRAY_SIZE(compat)= ); - } else { - qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", - "riscv,cpu-intc"); - } + qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", + "riscv,cpu-intc"); qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL,= 0); qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e0d5941230..26d44df446 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -99,6 +99,8 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), + ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), @@ -666,10 +668,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) } } =20 - if (cpu->cfg.aia) { - riscv_set_feature(env, RISCV_FEATURE_AIA); - } - if (cpu->cfg.debug) { riscv_set_feature(env, RISCV_FEATURE_DEBUG); } @@ -1038,7 +1036,8 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), /* ePMP 0.9.3 */ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), - DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), + DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), + DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), =20 DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 650574accf..05c0c8d777 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -307,6 +307,7 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env, int extirq, unsigned int extirq_def_pr= io, uint64_t pending, uint8_t *iprio) { + RISCVCPU *cpu =3D env_archcpu(env); int irq, best_irq =3D RISCV_EXCP_NONE; unsigned int prio, best_prio =3D UINT_MAX; =20 @@ -315,7 +316,7 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env, } =20 irq =3D ctz64(pending); - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + if (!((extirq =3D=3D IRQ_M_EXT) ? cpu->cfg.ext_smaia : cpu->cfg.ext_ss= aia)) { return irq; } =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4a7078f7d1..3ddf309055 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -257,7 +257,9 @@ static RISCVException any32(CPURISCVState *env, int csr= no) =20 static int aia_any(CPURISCVState *env, int csrno) { - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_smaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -266,7 +268,9 @@ static int aia_any(CPURISCVState *env, int csrno) =20 static int aia_any32(CPURISCVState *env, int csrno) { - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_smaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -293,7 +297,9 @@ static int smode32(CPURISCVState *env, int csrno) =20 static int aia_smode(CPURISCVState *env, int csrno) { - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -302,7 +308,9 @@ static int aia_smode(CPURISCVState *env, int csrno) =20 static int aia_smode32(CPURISCVState *env, int csrno) { - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -358,7 +366,9 @@ static RISCVException pointer_masking(CPURISCVState *en= v, int csrno) =20 static int aia_hmode(CPURISCVState *env, int csrno) { - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -367,7 +377,9 @@ static int aia_hmode(CPURISCVState *env, int csrno) =20 static int aia_hmode32(CPURISCVState *env, int csrno) { - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662539937757100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra Historically, The mtime/mtimecmp has been part of the CPU because they are per hart entities. However, they actually belong to aclint which is a MMIO device. Move them to the ACLINT device. This also emulates the real hardware more closely. Reviewed-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Signed-off-by: Atish Patra Message-Id: <20220824221357.41070-2-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- include/hw/intc/riscv_aclint.h | 2 ++ include/hw/timer/ibex_timer.h | 2 ++ target/riscv/cpu.h | 2 -- hw/intc/riscv_aclint.c | 48 ++++++++++++++++++++++++---------- hw/timer/ibex_timer.c | 18 +++++-------- target/riscv/machine.c | 5 ++-- 6 files changed, 47 insertions(+), 30 deletions(-) diff --git a/include/hw/intc/riscv_aclint.h b/include/hw/intc/riscv_aclint.h index 26d4048687..693415eb6d 100644 --- a/include/hw/intc/riscv_aclint.h +++ b/include/hw/intc/riscv_aclint.h @@ -32,6 +32,8 @@ typedef struct RISCVAclintMTimerState { /*< private >*/ SysBusDevice parent_obj; uint64_t time_delta; + uint64_t *timecmp; + QEMUTimer **timers; =20 /*< public >*/ MemoryRegion mmio; diff --git a/include/hw/timer/ibex_timer.h b/include/hw/timer/ibex_timer.h index 1a0a28d5fa..41f5c82a92 100644 --- a/include/hw/timer/ibex_timer.h +++ b/include/hw/timer/ibex_timer.h @@ -33,6 +33,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(IbexTimerState, IBEX_TIMER) struct IbexTimerState { /* */ SysBusDevice parent_obj; + uint64_t mtimecmp; + QEMUTimer *mtimer; /* Internal timer for M-mode interrupt */ =20 /* */ MemoryRegion mmio; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 081cd05544..53335def23 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -307,7 +307,6 @@ struct CPUArchState { /* temporary htif regs */ uint64_t mfromhost; uint64_t mtohost; - uint64_t timecmp; =20 /* physical memory protection */ pmp_table_t pmp_state; @@ -362,7 +361,6 @@ struct CPUArchState { float_status fp_status; =20 /* Fields from here on are preserved across CPU reset. */ - QEMUTimer *timer; /* Internal timer */ =20 hwaddr kernel_addr; hwaddr fdt_addr; diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index e7942c4e5a..eee04643cb 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -32,6 +32,7 @@ #include "hw/intc/riscv_aclint.h" #include "qemu/timer.h" #include "hw/irq.h" +#include "migration/vmstate.h" =20 typedef struct riscv_aclint_mtimer_callback { RISCVAclintMTimerState *s; @@ -65,19 +66,22 @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAcli= ntMTimerState *mtimer, =20 uint64_t rtc_r =3D cpu_riscv_read_rtc(mtimer); =20 - cpu->env.timecmp =3D value; - if (cpu->env.timecmp <=3D rtc_r) { + /* Compute the relative hartid w.r.t the socket */ + hartid =3D hartid - mtimer->hartid_base; + + mtimer->timecmp[hartid] =3D value; + if (mtimer->timecmp[hartid] <=3D rtc_r) { /* * If we're setting an MTIMECMP value in the "past", * immediately raise the timer interrupt */ - qemu_irq_raise(mtimer->timer_irqs[hartid - mtimer->hartid_base]); + qemu_irq_raise(mtimer->timer_irqs[hartid]); return; } =20 /* otherwise, set up the future timer interrupt */ - qemu_irq_lower(mtimer->timer_irqs[hartid - mtimer->hartid_base]); - diff =3D cpu->env.timecmp - rtc_r; + qemu_irq_lower(mtimer->timer_irqs[hartid]); + diff =3D mtimer->timecmp[hartid] - rtc_r; /* back to ns (note args switched in muldiv64) */ uint64_t ns_diff =3D muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_f= req); =20 @@ -102,7 +106,7 @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAcli= ntMTimerState *mtimer, next =3D MIN(next, INT64_MAX); } =20 - timer_mod(cpu->env.timer, next); + timer_mod(mtimer->timers[hartid], next); } =20 /* @@ -133,11 +137,11 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque= , hwaddr addr, "aclint-mtimer: invalid hartid: %zu", hartid); } else if ((addr & 0x7) =3D=3D 0) { /* timecmp_lo for RV32/RV64 or timecmp for RV64 */ - uint64_t timecmp =3D env->timecmp; + uint64_t timecmp =3D mtimer->timecmp[hartid]; return (size =3D=3D 4) ? (timecmp & 0xFFFFFFFF) : timecmp; } else if ((addr & 0x7) =3D=3D 4) { /* timecmp_hi */ - uint64_t timecmp =3D env->timecmp; + uint64_t timecmp =3D mtimer->timecmp[hartid]; return (timecmp >> 32) & 0xFFFFFFFF; } else { qemu_log_mask(LOG_UNIMP, @@ -177,7 +181,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwa= ddr addr, } else if ((addr & 0x7) =3D=3D 0) { if (size =3D=3D 4) { /* timecmp_lo for RV32/RV64 */ - uint64_t timecmp_hi =3D env->timecmp >> 32; + uint64_t timecmp_hi =3D mtimer->timecmp[hartid] >> 32; riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), = hartid, timecmp_hi << 32 | (value & 0xFFFFFFFF)); } else { @@ -188,7 +192,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwa= ddr addr, } else if ((addr & 0x7) =3D=3D 4) { if (size =3D=3D 4) { /* timecmp_hi for RV32/RV64 */ - uint64_t timecmp_lo =3D env->timecmp; + uint64_t timecmp_lo =3D mtimer->timecmp[hartid]; riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), = hartid, value << 32 | (timecmp_lo & 0xFFFFFFFF)); } else { @@ -234,7 +238,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwa= ddr addr, } riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), mtimer->hartid_base + i, - env->timecmp); + mtimer->timecmp[i]); } return; } @@ -284,6 +288,8 @@ static void riscv_aclint_mtimer_realize(DeviceState *de= v, Error **errp) s->timer_irqs =3D g_new(qemu_irq, s->num_harts); qdev_init_gpio_out(dev, s->timer_irqs, s->num_harts); =20 + s->timers =3D g_new0(QEMUTimer *, s->num_harts); + s->timecmp =3D g_new0(uint64_t, s->num_harts); /* Claim timer interrupt bits */ for (i =3D 0; i < s->num_harts; i++) { RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(s->hartid_base + i)); @@ -310,6 +316,18 @@ static void riscv_aclint_mtimer_reset_enter(Object *ob= j, ResetType type) riscv_aclint_mtimer_write(mtimer, mtimer->time_base, 0, 8); } =20 +static const VMStateDescription vmstate_riscv_mtimer =3D { + .name =3D "riscv_mtimer", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_VARRAY_UINT32(timecmp, RISCVAclintMTimerState, + num_harts, 0, + vmstate_info_uint64, uint64_t), + VMSTATE_END_OF_LIST() + } +}; + static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -317,6 +335,7 @@ static void riscv_aclint_mtimer_class_init(ObjectClass = *klass, void *data) device_class_set_props(dc, riscv_aclint_mtimer_properties); ResettableClass *rc =3D RESETTABLE_CLASS(klass); rc->phases.enter =3D riscv_aclint_mtimer_reset_enter; + dc->vmsd =3D &vmstate_riscv_mtimer; } =20 static const TypeInfo riscv_aclint_mtimer_info =3D { @@ -336,6 +355,7 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hw= addr size, { int i; DeviceState *dev =3D qdev_new(TYPE_RISCV_ACLINT_MTIMER); + RISCVAclintMTimerState *s =3D RISCV_ACLINT_MTIMER(dev); =20 assert(num_harts <=3D RISCV_ACLINT_MAX_HARTS); assert(!(addr & 0x7)); @@ -366,11 +386,11 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, = hwaddr size, riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, dev); } =20 - cb->s =3D RISCV_ACLINT_MTIMER(dev); + cb->s =3D s; cb->num =3D i; - env->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + s->timers[i] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &riscv_aclint_mtimer_cb, cb); - env->timecmp =3D 0; + s->timecmp[i] =3D 0; =20 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(DEVICE(rvcpu), IRQ_M_TIMER)= ); diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c index 8c2ca364da..d8b8e4e1f6 100644 --- a/hw/timer/ibex_timer.c +++ b/hw/timer/ibex_timer.c @@ -60,8 +60,6 @@ static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) =20 static void ibex_timer_update_irqs(IbexTimerState *s) { - CPUState *cs =3D qemu_get_cpu(0); - RISCVCPU *cpu =3D RISCV_CPU(cs); uint64_t value =3D s->timer_compare_lower0 | ((uint64_t)s->timer_compare_upper0 << 32); uint64_t next, diff; @@ -73,9 +71,9 @@ static void ibex_timer_update_irqs(IbexTimerState *s) } =20 /* Update the CPUs mtimecmp */ - cpu->env.timecmp =3D value; + s->mtimecmp =3D value; =20 - if (cpu->env.timecmp <=3D now) { + if (s->mtimecmp <=3D now) { /* * If the mtimecmp was in the past raise the interrupt now. */ @@ -91,7 +89,7 @@ static void ibex_timer_update_irqs(IbexTimerState *s) qemu_irq_lower(s->m_timer_irq); qemu_set_irq(s->irq, false); =20 - diff =3D cpu->env.timecmp - now; + diff =3D s->mtimecmp - now; next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + muldiv64(diff, NANOSECONDS_PER_SECOND, @@ -99,9 +97,9 @@ static void ibex_timer_update_irqs(IbexTimerState *s) =20 if (next < qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { /* We overflowed the timer, just set it as large as we can */ - timer_mod(cpu->env.timer, 0x7FFFFFFFFFFFFFFF); + timer_mod(s->mtimer, 0x7FFFFFFFFFFFFFFF); } else { - timer_mod(cpu->env.timer, next); + timer_mod(s->mtimer, next); } } =20 @@ -120,11 +118,9 @@ static void ibex_timer_reset(DeviceState *dev) { IbexTimerState *s =3D IBEX_TIMER(dev); =20 - CPUState *cpu =3D qemu_get_cpu(0); - CPURISCVState *env =3D cpu->env_ptr; - env->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + s->mtimer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &ibex_timer_cb, s); - env->timecmp =3D 0; + s->mtimecmp =3D 0; =20 s->timer_ctrl =3D 0x00000000; s->timer_cfg0 =3D 0x00010000; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index dc182ca811..b508b042cb 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -307,8 +307,8 @@ static const VMStateDescription vmstate_pmu_ctr_state = =3D { =20 const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", - .version_id =3D 3, - .minimum_version_id =3D 3, + .version_id =3D 4, + .minimum_version_id =3D 4, .post_load =3D riscv_cpu_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), @@ -359,7 +359,6 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.mfromhost, RISCVCPU), VMSTATE_UINT64(env.mtohost, RISCVCPU), - VMSTATE_UINT64(env.timecmp, RISCVCPU), =20 VMSTATE_END_OF_LIST() }, --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662542301844100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra stimecmp allows the supervisor mode to update stimecmp CSR directly to program the next timer interrupt. This CSR is part of the Sstc extension which was ratified recently. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-Id: <20220824221357.41070-3-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 5 ++ target/riscv/cpu_bits.h | 4 ++ target/riscv/time_helper.h | 30 ++++++++++++ target/riscv/cpu.c | 9 ++++ target/riscv/csr.c | 86 +++++++++++++++++++++++++++++++++ target/riscv/machine.c | 1 + target/riscv/time_helper.c | 98 ++++++++++++++++++++++++++++++++++++++ target/riscv/meson.build | 3 +- 8 files changed, 235 insertions(+), 1 deletion(-) create mode 100644 target/riscv/time_helper.h create mode 100644 target/riscv/time_helper.c diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 53335def23..d2529b757a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -308,6 +308,9 @@ struct CPUArchState { uint64_t mfromhost; uint64_t mtohost; =20 + /* Sstc CSRs */ + uint64_t stimecmp; + /* physical memory protection */ pmp_table_t pmp_state; target_ulong mseccfg; @@ -361,6 +364,7 @@ struct CPUArchState { float_status fp_status; =20 /* Fields from here on are preserved across CPU reset. */ + QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ =20 hwaddr kernel_addr; hwaddr fdt_addr; @@ -424,6 +428,7 @@ struct RISCVCPUConfig { bool ext_ifencei; bool ext_icsr; bool ext_zihintpause; + bool ext_sstc; bool ext_svinval; bool ext_svnapot; bool ext_svpbmt; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 6be5a9e9f0..ac17cf1515 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -206,6 +206,10 @@ #define CSR_STVAL 0x143 #define CSR_SIP 0x144 =20 +/* Sstc supervisor CSRs */ +#define CSR_STIMECMP 0x14D +#define CSR_STIMECMPH 0x15D + /* Supervisor Protection and Translation */ #define CSR_SPTBR 0x180 #define CSR_SATP 0x180 diff --git a/target/riscv/time_helper.h b/target/riscv/time_helper.h new file mode 100644 index 0000000000..7b3cdcc350 --- /dev/null +++ b/target/riscv/time_helper.h @@ -0,0 +1,30 @@ +/* + * RISC-V timer header file. + * + * Copyright (c) 2022 Rivos Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef RISCV_TIME_HELPER_H +#define RISCV_TIME_HELPER_H + +#include "cpu.h" +#include "qemu/timer.h" + +void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer, + uint64_t timecmp, uint64_t delta, + uint32_t timer_irq); +void riscv_timer_init(RISCVCPU *cpu); + +#endif diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 26d44df446..8ab36e82e1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -23,6 +23,7 @@ #include "qemu/log.h" #include "cpu.h" #include "internals.h" +#include "time_helper.h" #include "exec/exec-all.h" #include "qapi/error.h" #include "qemu/error-report.h" @@ -101,6 +102,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), + ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), @@ -674,6 +676,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) =20 set_resetvec(env, cpu->cfg.resetvec); =20 +#ifndef CONFIG_USER_ONLY + if (cpu->cfg.ext_sstc) { + riscv_timer_init(cpu); + } +#endif /* CONFIG_USER_ONLY */ + /* Validate that MISA_MXL is set properly. */ switch (env->misa_mxl_max) { #ifdef TARGET_RISCV64 @@ -994,6 +1002,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), =20 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 3ddf309055..04b06a2389 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -22,6 +22,7 @@ #include "qemu/timer.h" #include "cpu.h" #include "pmu.h" +#include "time_helper.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" #include "sysemu/cpu-timers.h" @@ -815,6 +816,81 @@ static RISCVException read_timeh(CPURISCVState *env, i= nt csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException sstc(CPURISCVState *env, int csrno) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_sstc || !env->rdtime_fn) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (env->priv =3D=3D PRV_M) { + return RISCV_EXCP_NONE; + } + + /* + * No need of separate function for rv32 as menvcfg stores both menvcfg + * menvcfgh for RV32. + */ + if (!(get_field(env->mcounteren, COUNTEREN_TM) && + get_field(env->menvcfg, MENVCFG_STCE))) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return smode(env, csrno); +} + +static RISCVException sstc_32(CPURISCVState *env, int csrno) +{ + if (riscv_cpu_mxl(env) !=3D MXL_RV32) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return sstc(env, csrno); +} + +static RISCVException read_stimecmp(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->stimecmp; + return RISCV_EXCP_NONE; +} + +static RISCVException read_stimecmph(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->stimecmp >> 32; + return RISCV_EXCP_NONE; +} + +static RISCVException write_stimecmp(CPURISCVState *env, int csrno, + target_ulong val) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + env->stimecmp =3D deposit64(env->stimecmp, 0, 32, (uint64_t)val); + } else { + env->stimecmp =3D val; + } + + riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP= ); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_stimecmph(CPURISCVState *env, int csrno, + target_ulong val) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + env->stimecmp =3D deposit64(env->stimecmp, 32, 32, (uint64_t)val); + riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP= ); + + return RISCV_EXCP_NONE; +} + /* Machine constants */ =20 #define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP)) @@ -1723,6 +1799,12 @@ static RISCVException rmw_mip64(CPURISCVState *env, = int csrno, new_val |=3D env->external_seip * MIP_SEIP; } =20 + if (cpu->cfg.ext_sstc && (env->priv =3D=3D PRV_M) && + get_field(env->menvcfg, MENVCFG_STCE)) { + /* sstc extension forbids STIP & VSTIP to be writeable in mip */ + mask =3D mask & ~(MIP_STIP | MIP_VSTIP); + } + if (mask) { old_mip =3D riscv_cpu_update_mip(cpu, mask, (new_val & mask)); } else { @@ -3594,6 +3676,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_SCAUSE] =3D { "scause", smode, read_scause, write_scause = }, [CSR_STVAL] =3D { "stval", smode, read_stval, write_stval = }, [CSR_SIP] =3D { "sip", smode, NULL, NULL, rmw_sip = }, + [CSR_STIMECMP] =3D { "stimecmp", sstc, read_stimecmp, write_stimecmp, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_STIMECMPH] =3D { "stimecmph", sstc_32, read_stimecmph, write_stim= ecmph, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, =20 /* Supervisor Protection and Translation */ [CSR_SATP] =3D { "satp", smode, read_satp, write_satp = }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index b508b042cb..622fface48 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -359,6 +359,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.mfromhost, RISCVCPU), VMSTATE_UINT64(env.mtohost, RISCVCPU), + VMSTATE_UINT64(env.stimecmp, RISCVCPU), =20 VMSTATE_END_OF_LIST() }, diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c new file mode 100644 index 0000000000..f3fb5eac7b --- /dev/null +++ b/target/riscv/time_helper.c @@ -0,0 +1,98 @@ +/* + * RISC-V timer helper implementation. + * + * Copyright (c) 2022 Rivos Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "cpu_bits.h" +#include "time_helper.h" +#include "hw/intc/riscv_aclint.h" + +static void riscv_stimer_cb(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1)); +} + +/* + * Called when timecmp is written to update the QEMU timer or immediately + * trigger timer interrupt if mtimecmp <=3D current timer value. + */ +void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer, + uint64_t timecmp, uint64_t delta, + uint32_t timer_irq) +{ + uint64_t diff, ns_diff, next; + CPURISCVState *env =3D &cpu->env; + RISCVAclintMTimerState *mtimer =3D env->rdtime_fn_arg; + uint32_t timebase_freq =3D mtimer->timebase_freq; + uint64_t rtc_r =3D env->rdtime_fn(env->rdtime_fn_arg) + delta; + + if (timecmp <=3D rtc_r) { + /* + * If we're setting an stimecmp value in the "past", + * immediately raise the timer interrupt + */ + riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(1)); + return; + } + + /* Clear the [V]STIP bit in mip */ + riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); + + /* otherwise, set up the future timer interrupt */ + diff =3D timecmp - rtc_r; + /* back to ns (note args switched in muldiv64) */ + ns_diff =3D muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq); + + /* + * check if ns_diff overflowed and check if the addition would potenti= ally + * overflow + */ + if ((NANOSECONDS_PER_SECOND > timebase_freq && ns_diff < diff) || + ns_diff > INT64_MAX) { + next =3D INT64_MAX; + } else { + /* + * as it is very unlikely qemu_clock_get_ns will return a value + * greater than INT64_MAX, no additional check is needed for an + * unsigned integer overflow. + */ + next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns_diff; + /* + * if ns_diff is INT64_MAX next may still be outside the range + * of a signed integer. + */ + next =3D MIN(next, INT64_MAX); + } + + timer_mod(timer, next); +} + +void riscv_timer_init(RISCVCPU *cpu) +{ + CPURISCVState *env; + + if (!cpu) { + return; + } + + env =3D &cpu->env; + env->stimer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &riscv_stimer_cb, cpu= ); + env->stimecmp =3D 0; + +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 6b9435d69a..ba25164d74 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -29,7 +29,8 @@ riscv_softmmu_ss.add(files( 'debug.c', 'monitor.c', 'machine.c', - 'pmu.c' + 'pmu.c', + 'time_helper.c' )) =20 target_arch +=3D {'riscv': riscv_ss} --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662542843; cv=none; d=zohomail.com; s=zohoarc; b=bb+VGU0GDaJ2085HjeiG9G2qfwaQxuUxv9+Mgv2ZpXaHLGkMxNzpDbjJioDflogikIyP4hTpxz92Ogah3O7rv1Bb/Beo3cniv/bcjwikdS0MT28c9g3Gsgutw1ZGs96M1x9wB1D/eubWfOkuGGJnDnR7b2lQImvAbINA9RuobYo= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662542845065100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra vstimecmp CSR allows the guest OS or to program the next guest timer interrupt directly. Thus, hypervisor no longer need to inject the timer interrupt to the guest if vstimecmp is used. This was ratified as a part of the Sstc extension. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-Id: <20220824221357.41070-4-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 4 ++ target/riscv/cpu_bits.h | 4 ++ target/riscv/cpu_helper.c | 11 +++-- target/riscv/csr.c | 88 ++++++++++++++++++++++++++++++++++++-- target/riscv/machine.c | 1 + target/riscv/time_helper.c | 16 +++++++ 6 files changed, 118 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d2529b757a..d895a0af2c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -311,6 +311,8 @@ struct CPUArchState { /* Sstc CSRs */ uint64_t stimecmp; =20 + uint64_t vstimecmp; + /* physical memory protection */ pmp_table_t pmp_state; target_ulong mseccfg; @@ -365,6 +367,8 @@ struct CPUArchState { =20 /* Fields from here on are preserved across CPU reset. */ QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ + QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ + bool vstime_irq; =20 hwaddr kernel_addr; hwaddr fdt_addr; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index ac17cf1515..095dab19f5 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -257,6 +257,10 @@ #define CSR_VSIP 0x244 #define CSR_VSATP 0x280 =20 +/* Sstc virtual CSRs */ +#define CSR_VSTIMECMP 0x24D +#define CSR_VSTIMECMPH 0x25D + #define CSR_MTINST 0x34a #define CSR_MTVAL2 0x34b =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 05c0c8d777..719c5d5d02 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -346,8 +346,9 @@ uint64_t riscv_cpu_all_pending(CPURISCVState *env) { uint32_t gein =3D get_field(env->hstatus, HSTATUS_VGEIN); uint64_t vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; + uint64_t vstip =3D (env->vstime_irq) ? MIP_VSTIP : 0; =20 - return (env->mip | vsgein) & env->mie; + return (env->mip | vsgein | vstip) & env->mie; } =20 int riscv_cpu_mirq_pending(CPURISCVState *env) @@ -606,7 +607,7 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t m= ask, uint64_t value) { CPURISCVState *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); - uint64_t gein, vsgein =3D 0, old =3D env->mip; + uint64_t gein, vsgein =3D 0, vstip =3D 0, old =3D env->mip; bool locked =3D false; =20 if (riscv_cpu_virt_enabled(env)) { @@ -614,6 +615,10 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t = mask, uint64_t value) vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; } =20 + /* No need to update mip for VSTIP */ + mask =3D ((mask =3D=3D MIP_VSTIP) && env->vstime_irq) ? 0 : mask; + vstip =3D env->vstime_irq ? MIP_VSTIP : 0; + if (!qemu_mutex_iothread_locked()) { locked =3D true; qemu_mutex_lock_iothread(); @@ -621,7 +626,7 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t m= ask, uint64_t value) =20 env->mip =3D (env->mip & ~mask) | (value & mask); =20 - if (env->mip | vsgein) { + if (env->mip | vsgein | vstip) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 04b06a2389..1a35ac48cc 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -820,6 +820,7 @@ static RISCVException sstc(CPURISCVState *env, int csrn= o) { CPUState *cs =3D env_cpu(env); RISCVCPU *cpu =3D RISCV_CPU(cs); + bool hmode_check =3D false; =20 if (!cpu->cfg.ext_sstc || !env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; @@ -838,7 +839,18 @@ static RISCVException sstc(CPURISCVState *env, int csr= no) return RISCV_EXCP_ILLEGAL_INST; } =20 - return smode(env, csrno); + if (riscv_cpu_virt_enabled(env)) { + if (!(get_field(env->hcounteren, COUNTEREN_TM) & + get_field(env->henvcfg, HENVCFG_STCE))) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + } + + if ((csrno =3D=3D CSR_VSTIMECMP) || (csrno =3D=3D CSR_VSTIMECMPH)) { + hmode_check =3D true; + } + + return hmode_check ? hmode(env, csrno) : smode(env, csrno); } =20 static RISCVException sstc_32(CPURISCVState *env, int csrno) @@ -850,17 +862,72 @@ static RISCVException sstc_32(CPURISCVState *env, int= csrno) return sstc(env, csrno); } =20 +static RISCVException read_vstimecmp(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->vstimecmp; + + return RISCV_EXCP_NONE; +} + +static RISCVException read_vstimecmph(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->vstimecmp >> 32; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_vstimecmp(CPURISCVState *env, int csrno, + target_ulong val) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + env->vstimecmp =3D deposit64(env->vstimecmp, 0, 32, (uint64_t)val); + } else { + env->vstimecmp =3D val; + } + + riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + env->htimedelta, MIP_VSTIP); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_vstimecmph(CPURISCVState *env, int csrno, + target_ulong val) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + env->vstimecmp =3D deposit64(env->vstimecmp, 32, 32, (uint64_t)val); + riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + env->htimedelta, MIP_VSTIP); + + return RISCV_EXCP_NONE; +} + static RISCVException read_stimecmp(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->stimecmp; + if (riscv_cpu_virt_enabled(env)) { + *val =3D env->vstimecmp; + } else { + *val =3D env->stimecmp; + } + return RISCV_EXCP_NONE; } =20 static RISCVException read_stimecmph(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->stimecmp >> 32; + if (riscv_cpu_virt_enabled(env)) { + *val =3D env->vstimecmp >> 32; + } else { + *val =3D env->stimecmp >> 32; + } + return RISCV_EXCP_NONE; } =20 @@ -869,6 +936,10 @@ static RISCVException write_stimecmp(CPURISCVState *en= v, int csrno, { RISCVCPU *cpu =3D env_archcpu(env); =20 + if (riscv_cpu_virt_enabled(env)) { + return write_vstimecmp(env, csrno, val); + } + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { env->stimecmp =3D deposit64(env->stimecmp, 0, 32, (uint64_t)val); } else { @@ -885,6 +956,10 @@ static RISCVException write_stimecmph(CPURISCVState *e= nv, int csrno, { RISCVCPU *cpu =3D env_archcpu(env); =20 + if (riscv_cpu_virt_enabled(env)) { + return write_vstimecmph(env, csrno, val); + } + env->stimecmp =3D deposit64(env->stimecmp, 32, 32, (uint64_t)val); riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP= ); =20 @@ -1814,6 +1889,7 @@ static RISCVException rmw_mip64(CPURISCVState *env, i= nt csrno, if (csrno !=3D CSR_HVIP) { gin =3D get_field(env->hstatus, HSTATUS_VGEIN); old_mip |=3D (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP := 0; + old_mip |=3D env->vstime_irq ? MIP_VSTIP : 0; } =20 if (ret_val) { @@ -3680,6 +3756,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { .min_priv_ver =3D PRIV_VERSION_1_12_0 }, [CSR_STIMECMPH] =3D { "stimecmph", sstc_32, read_stimecmph, write_stim= ecmph, .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_VSTIMECMP] =3D { "vstimecmp", sstc, read_vstimecmp, + write_vstimecmp, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_VSTIMECMPH] =3D { "vstimecmph", sstc_32, read_vstimecmph, + write_vstimecmph, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, =20 /* Supervisor Protection and Translation */ [CSR_SATP] =3D { "satp", smode, read_satp, write_satp = }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 622fface48..4ba55705d1 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -92,6 +92,7 @@ static const VMStateDescription vmstate_hyper =3D { VMSTATE_UINTTL(env.hgeie, RISCVCPU), VMSTATE_UINTTL(env.hgeip, RISCVCPU), VMSTATE_UINT64(env.htimedelta, RISCVCPU), + VMSTATE_UINT64(env.vstimecmp, RISCVCPU), =20 VMSTATE_UINTTL(env.hvictl, RISCVCPU), VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64), diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index f3fb5eac7b..8cce667dfd 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -22,6 +22,14 @@ #include "time_helper.h" #include "hw/intc/riscv_aclint.h" =20 +static void riscv_vstimer_cb(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + CPURISCVState *env =3D &cpu->env; + env->vstime_irq =3D 1; + riscv_cpu_update_mip(cpu, MIP_VSTIP, BOOL_TO_MASK(1)); +} + static void riscv_stimer_cb(void *opaque) { RISCVCPU *cpu =3D opaque; @@ -47,10 +55,16 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer= *timer, * If we're setting an stimecmp value in the "past", * immediately raise the timer interrupt */ + if (timer_irq =3D=3D MIP_VSTIP) { + env->vstime_irq =3D 1; + } riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(1)); return; } =20 + if (timer_irq =3D=3D MIP_VSTIP) { + env->vstime_irq =3D 0; + } /* Clear the [V]STIP bit in mip */ riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); =20 @@ -95,4 +109,6 @@ void riscv_timer_init(RISCVCPU *cpu) env->stimer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &riscv_stimer_cb, cpu= ); env->stimecmp =3D 0; =20 + env->vstimer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &riscv_vstimer_cb, c= pu); + env->vstimecmp =3D 0; } --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-IronPort-AV: E=Sophos;i="5.93,296,1654531200"; d="scan'208";a="210715133" IronPort-SDR: g07FgQDO9rIGuads1av3NaelU2nQ+PVbtCYVtNp0ThLzgTW3A4mY2RbAGIWnXeLmXfsBBYtxJy DpcnpufIuCBZvSL4SC4HQQUWxv/LE1iczKLycCQJ/ZTu1NvRFwKIf6MIrKml6X3bLu2VQJ5/Ay OEt6MtGM7VoT8h7UcEok6eYiHVD2s3GCny/eQJUtNhFbkEuDVywI7UiTTrBS7e9V7lf/gH6ydS a0tanZCuvmr+CSHBPe4JtNRl4SH8+VPLFGAuRryrqM07aQJO2QxYr2Pgvga2ZoMB0sw27F2nYD UOOa7X/nX4gdxhsYOlWQuu7v IronPort-SDR: +nNNcvt0xWKbe0L5LQQ44PJ9YPZPik+t+ra2CQ7WcOlKXulb8/ien5z/eAZ2W3BnbnbS3zVOL5 8IaqnfFDuOxZ4Krh544BBQqIT2oDPL6i7z+5YPGtPoHOJaj5Nv/xYxP6VwwyDg0qjP+uO2RLys GrfqnAQ1SYFM2IifzAkwsX5Kl5Lsl5oPQEKTkYpryR2T+v9ISqr1Plks9q0y7aVTwSb6362hJb lUlCgGKBUKZqD1R498r1OJ4uwWDhtgmCoAy79VkyWSFLydbUz34hG1d6slL4T+2D+UamSDIvQB 4Tw= WDCIronportException: Internal To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Atish Patra , Heiko Stuebner , Alistair Francis , Atish Patra Subject: [PULL 40/44] target/riscv: Add sscofpmf extension support Date: Wed, 7 Sep 2022 10:03:49 +0200 Message-Id: <20220907080353.111926-41-alistair.francis@wdc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907080353.111926-1-alistair.francis@wdc.com> References: <20220907080353.111926-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662540277217100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Filtering) extension allows the perf to handle overflow interrupts and filtering support. This patch provides a framework for programmable counters to leverage the extension. As the extension doesn't have any provision for the overflow bit for fixed counters, the fixed events can also be monitoring using programmable counters. The underlying counters for cycle and instruction counters are always running. Thus, a separate timer device is programmed to handle the overflow. Tested-by: Heiko Stuebner Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra Message-Id: <20220824221701.41932-2-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 25 +++ target/riscv/cpu_bits.h | 55 ++++++ target/riscv/pmu.h | 7 + target/riscv/cpu.c | 12 ++ target/riscv/csr.c | 166 +++++++++++++++++- target/riscv/machine.c | 1 + target/riscv/pmu.c | 368 +++++++++++++++++++++++++++++++++++++++- 7 files changed, 623 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d895a0af2c..06751e1e3e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -136,6 +136,8 @@ typedef struct PMUCTRState { /* Snapshort value of a counter in RV32 */ target_ulong mhpmcounterh_prev; bool started; + /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigge= r */ + target_ulong irq_overflow_left; } PMUCTRState; =20 struct CPUArchState { @@ -301,6 +303,9 @@ struct CPUArchState { /* PMU event selector configured values. First three are unused*/ target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; =20 + /* PMU event selector configured values for RV32*/ + target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; + target_ulong sscratch; target_ulong mscratch; =20 @@ -447,6 +452,7 @@ struct RISCVCPUConfig { bool ext_zmmul; bool ext_smaia; bool ext_ssaia; + bool ext_sscofpmf; bool rvv_ta_all_1s; bool rvv_ma_all_1s; =20 @@ -493,6 +499,12 @@ struct ArchCPU { =20 /* Configuration Settings */ RISCVCPUConfig cfg; + + QEMUTimer *pmu_timer; + /* A bitmask of Available programmable counters */ + uint32_t pmu_avail_ctrs; + /* Mapping of events to counters */ + GHashTable *pmu_event_ctr_map; }; =20 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) @@ -753,6 +765,19 @@ enum { CSR_TABLE_SIZE =3D 0x1000 }; =20 +/** + * The event id are encoded based on the encoding specified in the + * SBI specification v0.3 + */ + +enum riscv_pmu_event_idx { + RISCV_PMU_EVENT_HW_CPU_CYCLES =3D 0x01, + RISCV_PMU_EVENT_HW_INSTRUCTIONS =3D 0x02, + RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS =3D 0x10019, + RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS =3D 0x1001B, + RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS =3D 0x10021, +}; + /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 095dab19f5..7be12cac2e 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -390,6 +390,37 @@ #define CSR_MHPMEVENT29 0x33d #define CSR_MHPMEVENT30 0x33e #define CSR_MHPMEVENT31 0x33f + +#define CSR_MHPMEVENT3H 0x723 +#define CSR_MHPMEVENT4H 0x724 +#define CSR_MHPMEVENT5H 0x725 +#define CSR_MHPMEVENT6H 0x726 +#define CSR_MHPMEVENT7H 0x727 +#define CSR_MHPMEVENT8H 0x728 +#define CSR_MHPMEVENT9H 0x729 +#define CSR_MHPMEVENT10H 0x72a +#define CSR_MHPMEVENT11H 0x72b +#define CSR_MHPMEVENT12H 0x72c +#define CSR_MHPMEVENT13H 0x72d +#define CSR_MHPMEVENT14H 0x72e +#define CSR_MHPMEVENT15H 0x72f +#define CSR_MHPMEVENT16H 0x730 +#define CSR_MHPMEVENT17H 0x731 +#define CSR_MHPMEVENT18H 0x732 +#define CSR_MHPMEVENT19H 0x733 +#define CSR_MHPMEVENT20H 0x734 +#define CSR_MHPMEVENT21H 0x735 +#define CSR_MHPMEVENT22H 0x736 +#define CSR_MHPMEVENT23H 0x737 +#define CSR_MHPMEVENT24H 0x738 +#define CSR_MHPMEVENT25H 0x739 +#define CSR_MHPMEVENT26H 0x73a +#define CSR_MHPMEVENT27H 0x73b +#define CSR_MHPMEVENT28H 0x73c +#define CSR_MHPMEVENT29H 0x73d +#define CSR_MHPMEVENT30H 0x73e +#define CSR_MHPMEVENT31H 0x73f + #define CSR_MHPMCOUNTER3H 0xb83 #define CSR_MHPMCOUNTER4H 0xb84 #define CSR_MHPMCOUNTER5H 0xb85 @@ -451,6 +482,7 @@ #define CSR_VSMTE 0x2c0 #define CSR_VSPMMASK 0x2c1 #define CSR_VSPMBASE 0x2c2 +#define CSR_SCOUNTOVF 0xda0 =20 /* Crypto Extension */ #define CSR_SEED 0x015 @@ -628,6 +660,7 @@ typedef enum RISCVException { #define IRQ_VS_EXT 10 #define IRQ_M_EXT 11 #define IRQ_S_GEXT 12 +#define IRQ_PMU_OVF 13 #define IRQ_LOCAL_MAX 16 #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) =20 @@ -645,11 +678,13 @@ typedef enum RISCVException { #define MIP_VSEIP (1 << IRQ_VS_EXT) #define MIP_MEIP (1 << IRQ_M_EXT) #define MIP_SGEIP (1 << IRQ_S_GEXT) +#define MIP_LCOFIP (1 << IRQ_PMU_OVF) =20 /* sip masks */ #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP #define SIP_SEIP MIP_SEIP +#define SIP_LCOFIP MIP_LCOFIP =20 /* MIE masks */ #define MIE_SEIE (1 << IRQ_S_EXT) @@ -803,4 +838,24 @@ typedef enum RISCVException { #define SEED_OPST_WAIT (0b01 << 30) #define SEED_OPST_ES16 (0b10 << 30) #define SEED_OPST_DEAD (0b11 << 30) +/* PMU related bits */ +#define MIE_LCOFIE (1 << IRQ_PMU_OVF) + +#define MHPMEVENT_BIT_OF BIT_ULL(63) +#define MHPMEVENTH_BIT_OF BIT(31) +#define MHPMEVENT_BIT_MINH BIT_ULL(62) +#define MHPMEVENTH_BIT_MINH BIT(30) +#define MHPMEVENT_BIT_SINH BIT_ULL(61) +#define MHPMEVENTH_BIT_SINH BIT(29) +#define MHPMEVENT_BIT_UINH BIT_ULL(60) +#define MHPMEVENTH_BIT_UINH BIT(28) +#define MHPMEVENT_BIT_VSINH BIT_ULL(59) +#define MHPMEVENTH_BIT_VSINH BIT(27) +#define MHPMEVENT_BIT_VUINH BIT_ULL(58) +#define MHPMEVENTH_BIT_VUINH BIT(26) + +#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000) +#define MHPMEVENT_IDX_MASK 0xFFFFF +#define MHPMEVENT_SSCOF_RESVD 16 + #endif diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 58a5bc3a40..036653627f 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -26,3 +26,10 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *e= nv, uint32_t target_ctr); bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr); +void riscv_pmu_timer_cb(void *priv); +int riscv_pmu_init(RISCVCPU *cpu, int num_counters); +int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, + uint32_t ctr_idx); +int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); +int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, + uint32_t ctr_idx); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8ab36e82e1..aee14a239a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -22,6 +22,7 @@ #include "qemu/ctype.h" #include "qemu/log.h" #include "cpu.h" +#include "pmu.h" #include "internals.h" #include "time_helper.h" #include "exec/exec-all.h" @@ -102,6 +103,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), + ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), @@ -889,6 +891,15 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) set_misa(env, env->misa_mxl, ext); } =20 +#ifndef CONFIG_USER_ONLY + if (cpu->cfg.pmu_num) { + if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpm= f) { + cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + riscv_pmu_timer_cb, cpu); + } + } +#endif + riscv_cpu_register_gdb_regs_for_features(cs); =20 qemu_init_vcpu(cs); @@ -993,6 +1004,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), + DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1a35ac48cc..888ddfc4dd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -75,7 +75,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) CPUState *cs =3D env_cpu(env); RISCVCPU *cpu =3D RISCV_CPU(cs); int ctr_index; - int base_csrno =3D CSR_HPMCOUNTER3; + int base_csrno =3D CSR_CYCLE; bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32 ? true : false; =20 if (rv32 && csrno >=3D CSR_CYCLEH) { @@ -84,11 +84,18 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } ctr_index =3D csrno - base_csrno; =20 - if (!cpu->cfg.pmu_num || ctr_index >=3D (cpu->cfg.pmu_num)) { + if ((csrno >=3D CSR_CYCLE && csrno <=3D CSR_INSTRET) || + (csrno >=3D CSR_CYCLEH && csrno <=3D CSR_INSTRETH)) { + goto skip_ext_pmu_check; + } + + if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & BIT(ctr_index)))) { /* No counter is enabled in PMU or the counter is out of range */ return RISCV_EXCP_ILLEGAL_INST; } =20 +skip_ext_pmu_check: + if (env->priv =3D=3D PRV_S) { switch (csrno) { case CSR_CYCLE: @@ -107,7 +114,6 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - ctr_index =3D csrno - CSR_CYCLE; if (!get_field(env->mcounteren, 1 << ctr_index)) { return RISCV_EXCP_ILLEGAL_INST; } @@ -131,7 +137,6 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - ctr_index =3D csrno - CSR_CYCLEH; if (!get_field(env->mcounteren, 1 << ctr_index)) { return RISCV_EXCP_ILLEGAL_INST; } @@ -161,7 +166,6 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - ctr_index =3D csrno - CSR_CYCLE; if (!get_field(env->hcounteren, 1 << ctr_index) && get_field(env->mcounteren, 1 << ctr_index)) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; @@ -189,7 +193,6 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - ctr_index =3D csrno - CSR_CYCLEH; if (!get_field(env->hcounteren, 1 << ctr_index) && get_field(env->mcounteren, 1 << ctr_index)) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; @@ -241,6 +244,18 @@ static RISCVException mctr32(CPURISCVState *env, int c= srno) return mctr(env, csrno); } =20 +static RISCVException sscofpmf(CPURISCVState *env, int csrno) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_sscofpmf) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return RISCV_EXCP_NONE; +} + static RISCVException any(CPURISCVState *env, int csrno) { return RISCV_EXCP_NONE; @@ -683,9 +698,39 @@ static int read_mhpmevent(CPURISCVState *env, int csrn= o, target_ulong *val) static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val) { int evt_index =3D csrno - CSR_MCOUNTINHIBIT; + uint64_t mhpmevt_val =3D val; =20 env->mhpmevent_val[evt_index] =3D val; =20 + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + mhpmevt_val =3D mhpmevt_val | + ((uint64_t)env->mhpmeventh_val[evt_index] << 32); + } + riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); + + return RISCV_EXCP_NONE; +} + +static int read_mhpmeventh(CPURISCVState *env, int csrno, target_ulong *va= l) +{ + int evt_index =3D csrno - CSR_MHPMEVENT3H + 3; + + *val =3D env->mhpmeventh_val[evt_index]; + + return RISCV_EXCP_NONE; +} + +static int write_mhpmeventh(CPURISCVState *env, int csrno, target_ulong va= l) +{ + int evt_index =3D csrno - CSR_MHPMEVENT3H + 3; + uint64_t mhpmevth_val =3D val; + uint64_t mhpmevt_val =3D env->mhpmevent_val[evt_index]; + + mhpmevt_val =3D mhpmevt_val | (mhpmevth_val << 32); + env->mhpmeventh_val[evt_index] =3D val; + + riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); + return RISCV_EXCP_NONE; } =20 @@ -693,12 +738,20 @@ static int write_mhpmcounter(CPURISCVState *env, int = csrno, target_ulong val) { int ctr_idx =3D csrno - CSR_MCYCLE; PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + uint64_t mhpmctr_val =3D val; =20 counter->mhpmcounter_val =3D val; if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { counter->mhpmcounter_prev =3D get_ticks(false); - } else { + if (ctr_idx > 2) { + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + mhpmctr_val =3D mhpmctr_val | + ((uint64_t)counter->mhpmcounterh_val << 32); + } + riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); + } + } else { /* Other counters can keep incrementing from the given value */ counter->mhpmcounter_prev =3D val; } @@ -710,11 +763,17 @@ static int write_mhpmcounterh(CPURISCVState *env, int= csrno, target_ulong val) { int ctr_idx =3D csrno - CSR_MCYCLEH; PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + uint64_t mhpmctr_val =3D counter->mhpmcounter_val; + uint64_t mhpmctrh_val =3D val; =20 counter->mhpmcounterh_val =3D val; + mhpmctr_val =3D mhpmctr_val | (mhpmctrh_val << 32); if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { counter->mhpmcounterh_prev =3D get_ticks(true); + if (ctr_idx > 2) { + riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); + } } else { counter->mhpmcounterh_prev =3D val; } @@ -790,6 +849,32 @@ static int read_hpmcounterh(CPURISCVState *env, int cs= rno, target_ulong *val) return riscv_pmu_read_ctr(env, val, true, ctr_index); } =20 +static int read_scountovf(CPURISCVState *env, int csrno, target_ulong *val) +{ + int mhpmevt_start =3D CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT; + int i; + *val =3D 0; + target_ulong *mhpm_evt_val; + uint64_t of_bit_mask; + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + mhpm_evt_val =3D env->mhpmeventh_val; + of_bit_mask =3D MHPMEVENTH_BIT_OF; + } else { + mhpm_evt_val =3D env->mhpmevent_val; + of_bit_mask =3D MHPMEVENT_BIT_OF; + } + + for (i =3D mhpmevt_start; i < RV_MAX_MHPMEVENTS; i++) { + if ((get_field(env->mcounteren, BIT(i))) && + (mhpm_evt_val[i] & of_bit_mask)) { + *val |=3D BIT(i); + } + } + + return RISCV_EXCP_NONE; +} + static RISCVException read_time(CPURISCVState *env, int csrno, target_ulong *val) { @@ -969,7 +1054,8 @@ static RISCVException write_stimecmph(CPURISCVState *e= nv, int csrno, /* Machine constants */ =20 #define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP)) -#define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP)) +#define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP | \ + MIP_LCOFIP)) #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) =20 @@ -1010,7 +1096,8 @@ static const target_ulong vs_delegable_excps =3D DELE= GABLE_EXCPS & static const target_ulong sstatus_v1_10_mask =3D SSTATUS_SIE | SSTATUS_SPI= E | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; -static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_= UEIP; +static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_= UEIP | + SIP_LCOFIP; static const target_ulong hip_writable_mask =3D MIP_VSSIP; static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | M= IP_VSEIP; static const target_ulong vsip_writable_mask =3D MIP_VSSIP; @@ -4071,6 +4158,65 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MHPMEVENT31] =3D { "mhpmevent31", any, read_mhpmevent, write_mhpmevent }, =20 + [CSR_MHPMEVENT3H] =3D { "mhpmevent3h", sscofpmf, read_mhpmevent= h, + write_mhpmeventh }, + [CSR_MHPMEVENT4H] =3D { "mhpmevent4h", sscofpmf, read_mhpmevent= h, + write_mhpmeventh }, + [CSR_MHPMEVENT5H] =3D { "mhpmevent5h", sscofpmf, read_mhpmevent= h, + write_mhpmeventh }, + [CSR_MHPMEVENT6H] =3D { "mhpmevent6h", sscofpmf, read_mhpmevent= h, + write_mhpmeventh }, + [CSR_MHPMEVENT7H] =3D { "mhpmevent7h", sscofpmf, read_mhpmevent= h, + write_mhpmeventh }, + [CSR_MHPMEVENT8H] =3D { "mhpmevent8h", sscofpmf, read_mhpmevent= h, + write_mhpmeventh }, + [CSR_MHPMEVENT9H] =3D { "mhpmevent9h", sscofpmf, read_mhpmevent= h, + write_mhpmeventh }, + [CSR_MHPMEVENT10H] =3D { "mhpmevent10h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT11H] =3D { "mhpmevent11h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT12H] =3D { "mhpmevent12h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT13H] =3D { "mhpmevent13h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT14H] =3D { "mhpmevent14h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT15H] =3D { "mhpmevent15h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT16H] =3D { "mhpmevent16h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT17H] =3D { "mhpmevent17h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT18H] =3D { "mhpmevent18h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT19H] =3D { "mhpmevent19h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT20H] =3D { "mhpmevent20h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT21H] =3D { "mhpmevent21h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT22H] =3D { "mhpmevent22h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT23H] =3D { "mhpmevent23h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT24H] =3D { "mhpmevent24h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT25H] =3D { "mhpmevent25h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT26H] =3D { "mhpmevent26h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT27H] =3D { "mhpmevent27h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT28H] =3D { "mhpmevent28h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT29H] =3D { "mhpmevent29h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT30H] =3D { "mhpmevent30h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_MHPMEVENT31H] =3D { "mhpmevent31h", sscofpmf, read_mhpmeven= th, + write_mhpmeventh }, + [CSR_HPMCOUNTER3H] =3D { "hpmcounter3h", ctr32, read_hpmcounterh = }, [CSR_HPMCOUNTER4H] =3D { "hpmcounter4h", ctr32, read_hpmcounterh = }, [CSR_HPMCOUNTER5H] =3D { "hpmcounter5h", ctr32, read_hpmcounterh = }, @@ -4159,5 +4305,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { write_mhpmcounterh }, [CSR_MHPMCOUNTER31H] =3D { "mhpmcounter31h", mctr32, read_hpmcounterh, write_mhpmcounterh }, + [CSR_SCOUNTOVF] =3D { "scountovf", sscofpmf, read_scountovf }, + #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 4ba55705d1..41098f6ad0 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -356,6 +356,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, = 0, vmstate_pmu_ctr_state, PMUCTRState), VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENT= S), + VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVEN= TS), VMSTATE_UINTTL(env.sscratch, RISCVCPU), VMSTATE_UINTTL(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.mfromhost, RISCVCPU), diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 000fe8da45..a5f504e53c 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -19,14 +19,378 @@ #include "qemu/osdep.h" #include "cpu.h" #include "pmu.h" +#include "sysemu/cpu-timers.h" + +#define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ +#define MAKE_32BIT_MASK(shift, length) \ + (((uint32_t)(~0UL) >> (32 - (length))) << (shift)) + +static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx) +{ + if (ctr_idx < 3 || ctr_idx >=3D RV_MAX_MHPMCOUNTERS || + !(cpu->pmu_avail_ctrs & BIT(ctr_idx))) { + return false; + } else { + return true; + } +} + +static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, uint32_t ctr_idx) +{ + CPURISCVState *env =3D &cpu->env; + + if (riscv_pmu_counter_valid(cpu, ctr_idx) && + !get_field(env->mcountinhibit, BIT(ctr_idx))) { + return true; + } else { + return false; + } +} + +static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx) +{ + CPURISCVState *env =3D &cpu->env; + target_ulong max_val =3D UINT32_MAX; + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + bool virt_on =3D riscv_cpu_virt_enabled(env); + + /* Privilege mode filtering */ + if ((env->priv =3D=3D PRV_M && + (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_MINH)) || + (env->priv =3D=3D PRV_S && virt_on && + (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VSINH)) || + (env->priv =3D=3D PRV_U && virt_on && + (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VUINH)) || + (env->priv =3D=3D PRV_S && !virt_on && + (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_SINH)) || + (env->priv =3D=3D PRV_U && !virt_on && + (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_UINH))) { + return 0; + } + + /* Handle the overflow scenario */ + if (counter->mhpmcounter_val =3D=3D max_val) { + if (counter->mhpmcounterh_val =3D=3D max_val) { + counter->mhpmcounter_val =3D 0; + counter->mhpmcounterh_val =3D 0; + /* Generate interrupt only if OF bit is clear */ + if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) { + env->mhpmeventh_val[ctr_idx] |=3D MHPMEVENTH_BIT_OF; + riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1)); + } + } else { + counter->mhpmcounterh_val++; + } + } else { + counter->mhpmcounter_val++; + } + + return 0; +} + +static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx) +{ + CPURISCVState *env =3D &cpu->env; + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + uint64_t max_val =3D UINT64_MAX; + bool virt_on =3D riscv_cpu_virt_enabled(env); + + /* Privilege mode filtering */ + if ((env->priv =3D=3D PRV_M && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) || + (env->priv =3D=3D PRV_S && virt_on && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VSINH)) || + (env->priv =3D=3D PRV_U && virt_on && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VUINH)) || + (env->priv =3D=3D PRV_S && !virt_on && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) || + (env->priv =3D=3D PRV_U && !virt_on && + (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) { + return 0; + } + + /* Handle the overflow scenario */ + if (counter->mhpmcounter_val =3D=3D max_val) { + counter->mhpmcounter_val =3D 0; + /* Generate interrupt only if OF bit is clear */ + if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) { + env->mhpmevent_val[ctr_idx] |=3D MHPMEVENT_BIT_OF; + riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1)); + } + } else { + counter->mhpmcounter_val++; + } + return 0; +} + +int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) +{ + uint32_t ctr_idx; + int ret; + CPURISCVState *env =3D &cpu->env; + gpointer value; + + if (!cpu->cfg.pmu_num) { + return 0; + } + value =3D g_hash_table_lookup(cpu->pmu_event_ctr_map, + GUINT_TO_POINTER(event_idx)); + if (!value) { + return -1; + } + + ctr_idx =3D GPOINTER_TO_UINT(value); + if (!riscv_pmu_counter_enabled(cpu, ctr_idx) || + get_field(env->mcountinhibit, BIT(ctr_idx))) { + return -1; + } + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + ret =3D riscv_pmu_incr_ctr_rv32(cpu, ctr_idx); + } else { + ret =3D riscv_pmu_incr_ctr_rv64(cpu, ctr_idx); + } + + return ret; +} =20 bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, uint32_t target_ctr) { - return (target_ctr =3D=3D 0) ? true : false; + RISCVCPU *cpu; + uint32_t event_idx; + uint32_t ctr_idx; + + /* Fixed instret counter */ + if (target_ctr =3D=3D 2) { + return true; + } + + cpu =3D RISCV_CPU(env_cpu(env)); + if (!cpu->pmu_event_ctr_map) { + return false; + } + + event_idx =3D RISCV_PMU_EVENT_HW_INSTRUCTIONS; + ctr_idx =3D GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_ma= p, + GUINT_TO_POINTER(event_idx))); + if (!ctr_idx) { + return false; + } + + return target_ctr =3D=3D ctr_idx ? true : false; } =20 bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr) { - return (target_ctr =3D=3D 2) ? true : false; + RISCVCPU *cpu; + uint32_t event_idx; + uint32_t ctr_idx; + + /* Fixed mcycle counter */ + if (target_ctr =3D=3D 0) { + return true; + } + + cpu =3D RISCV_CPU(env_cpu(env)); + if (!cpu->pmu_event_ctr_map) { + return false; + } + + event_idx =3D RISCV_PMU_EVENT_HW_CPU_CYCLES; + ctr_idx =3D GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_ma= p, + GUINT_TO_POINTER(event_idx))); + + /* Counter zero is not used for event_ctr_map */ + if (!ctr_idx) { + return false; + } + + return (target_ctr =3D=3D ctr_idx) ? true : false; +} + +static gboolean pmu_remove_event_map(gpointer key, gpointer value, + gpointer udata) +{ + return (GPOINTER_TO_UINT(value) =3D=3D GPOINTER_TO_UINT(udata)) ? true= : false; +} + +static int64_t pmu_icount_ticks_to_ns(int64_t value) +{ + int64_t ret =3D 0; + + if (icount_enabled()) { + ret =3D icount_to_ns(value); + } else { + ret =3D (NANOSECONDS_PER_SECOND / RISCV_TIMEBASE_FREQ) * value; + } + + return ret; +} + +int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, + uint32_t ctr_idx) +{ + uint32_t event_idx; + RISCVCPU *cpu =3D RISCV_CPU(env_cpu(env)); + + if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map)= { + return -1; + } + + /* + * Expected mhpmevent value is zero for reset case. Remove the current + * mapping. + */ + if (!value) { + g_hash_table_foreach_remove(cpu->pmu_event_ctr_map, + pmu_remove_event_map, + GUINT_TO_POINTER(ctr_idx)); + return 0; + } + + event_idx =3D value & MHPMEVENT_IDX_MASK; + if (g_hash_table_lookup(cpu->pmu_event_ctr_map, + GUINT_TO_POINTER(event_idx))) { + return 0; + } + + switch (event_idx) { + case RISCV_PMU_EVENT_HW_CPU_CYCLES: + case RISCV_PMU_EVENT_HW_INSTRUCTIONS: + case RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS: + case RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS: + case RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS: + break; + default: + /* We don't support any raw events right now */ + return -1; + } + g_hash_table_insert(cpu->pmu_event_ctr_map, GUINT_TO_POINTER(event_idx= ), + GUINT_TO_POINTER(ctr_idx)); + + return 0; +} + +static void pmu_timer_trigger_irq(RISCVCPU *cpu, + enum riscv_pmu_event_idx evt_idx) +{ + uint32_t ctr_idx; + CPURISCVState *env =3D &cpu->env; + PMUCTRState *counter; + target_ulong *mhpmevent_val; + uint64_t of_bit_mask; + int64_t irq_trigger_at; + + if (evt_idx !=3D RISCV_PMU_EVENT_HW_CPU_CYCLES && + evt_idx !=3D RISCV_PMU_EVENT_HW_INSTRUCTIONS) { + return; + } + + ctr_idx =3D GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_ma= p, + GUINT_TO_POINTER(evt_idx))); + if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) { + return; + } + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + mhpmevent_val =3D &env->mhpmeventh_val[ctr_idx]; + of_bit_mask =3D MHPMEVENTH_BIT_OF; + } else { + mhpmevent_val =3D &env->mhpmevent_val[ctr_idx]; + of_bit_mask =3D MHPMEVENT_BIT_OF; + } + + counter =3D &env->pmu_ctrs[ctr_idx]; + if (counter->irq_overflow_left > 0) { + irq_trigger_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + counter->irq_overflow_left; + timer_mod_anticipate_ns(cpu->pmu_timer, irq_trigger_at); + counter->irq_overflow_left =3D 0; + return; + } + + if (cpu->pmu_avail_ctrs & BIT(ctr_idx)) { + /* Generate interrupt only if OF bit is clear */ + if (!(*mhpmevent_val & of_bit_mask)) { + *mhpmevent_val |=3D of_bit_mask; + riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1)); + } + } +} + +/* Timer callback for instret and cycle counter overflow */ +void riscv_pmu_timer_cb(void *priv) +{ + RISCVCPU *cpu =3D priv; + + /* Timer event was triggered only for these events */ + pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_CPU_CYCLES); + pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_INSTRUCTIONS); +} + +int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr= _idx) +{ + uint64_t overflow_delta, overflow_at; + int64_t overflow_ns, overflow_left =3D 0; + RISCVCPU *cpu =3D RISCV_CPU(env_cpu(env)); + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + + if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscofpmf) { + return -1; + } + + if (value) { + overflow_delta =3D UINT64_MAX - value + 1; + } else { + overflow_delta =3D UINT64_MAX; + } + + /* + * QEMU supports only int64_t timers while RISC-V counters are uint64_= t. + * Compute the leftover and save it so that it can be reprogrammed aga= in + * when timer expires. + */ + if (overflow_delta > INT64_MAX) { + overflow_left =3D overflow_delta - INT64_MAX; + } + + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || + riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + overflow_ns =3D pmu_icount_ticks_to_ns((int64_t)overflow_delta); + overflow_left =3D pmu_icount_ticks_to_ns(overflow_left) ; + } else { + return -1; + } + overflow_at =3D (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + over= flow_ns; + + if (overflow_at > INT64_MAX) { + overflow_left +=3D overflow_at - INT64_MAX; + counter->irq_overflow_left =3D overflow_left; + overflow_at =3D INT64_MAX; + } + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + + return 0; +} + + +int riscv_pmu_init(RISCVCPU *cpu, int num_counters) +{ + if (num_counters > (RV_MAX_MHPMCOUNTERS - 3)) { + return -1; + } + + cpu->pmu_event_ctr_map =3D g_hash_table_new(g_direct_hash, g_direct_eq= ual); + if (!cpu->pmu_event_ctr_map) { + /* PMU support can not be enabled */ + qemu_log_mask(LOG_UNIMP, "PMU events can't be supported\n"); + cpu->cfg.pmu_num =3D 0; + return -1; + } + + /* Create a bitmask of available programmable counters */ + cpu->pmu_avail_ctrs =3D MAKE_32BIT_MASK(3, num_counters); + + return 0; } --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662543134; cv=none; d=zohomail.com; s=zohoarc; b=fBJmMux/P7SCdN9jN7YCwqSbyfDZHQav5dxk6hJ5BcoaO8PMKREAcieCYXfU5fGMtKqkENj9ECn05ivIBl75uXLJMezV6WIB0iUN4/zvfs6Xyg2Bnf6BF7omT4/hra9WTIXbso9MIATluLJ+0NsRv7VAlDJ55DHWLMwNgxyRiF0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662543134; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=eZ4C82s2C3GyEX0IfPgZovJndBkFDofVjQsrMifsWIY=; b=DwxOOkvVwyHk2rHmIKp5hd+BSOsJg6Yrp27M5QL/ZoCQziADpgOWO9UZm+4l5x+pXznBdTO9a4QZGJy2gVFxZbT0XHbcEgkRv06H+17Qt0QQf7ihjmuFUmBs3y+1U5sp+Hw/to4iEHoQb0Ik2f4ioSSatXFTw13sKmDeyvumpuM= ARC-Authentication-Results: i=1; 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X-IronPort-AV: E=Sophos;i="5.93,296,1654531200"; d="scan'208";a="210715136" IronPort-SDR: QK9MkGfGVwzGICgRg9DcU8jZxl+H3eJ9qLBtg8HNfCMD1Rr4p0vddLzpjgt+/5q4s6XSlFqBNp 6up0lZ1/tcJHNdVPZA8fWOnNbxucWPlIsMTcnSTTK4W6EBNDCr5Lf6r9Ek8CBCjubQMg85UjYg vuSS7qatUHy+1JWxb1I0c5w1OObrIQ7Pgy/U59RwxDn7Kofr88Z8/HIXQz/OIFXaa8tpJ2DG2R NEtPwCSKj+9wlvQ7icMppCsOFoG/qgA0uPshBFd1WPs2rAhmK5P+sGEbkyICanp/2LxTzRtZhR 38BlDlQH3BBu5BO3wqjqqFlP IronPort-SDR: xouAU+B6oHUkb1yGssmKy4of/upSMtLBnokLeTxptk0KgMBksAV7oH3t4IUP7+VP7CWnjlE4Qc dGwMMfRPv45kx2NWQxJaNSScJse5ACfPBrzbWHEYOzhTLOxQ5h1rv5jlXbmbP7C1MsVWYLvPAG qfBwqzMqDMRLkFUR2r8PaMdaBeNGCO5b48VcP1bMhkMFMacvt6j2snQW+FAO3mBSdcOywwa0WA 6z/zDjyjxWo37YEMxg9F8kKecyqW3vVRWEBs6TTCX7vpdTEC+5EgtPVzB6ebghcTHSJaPeL33v ZQ4= WDCIronportException: Internal To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Atish Patra , Bin Meng , Alistair Francis Subject: [PULL 41/44] target/riscv: Simplify counter predicate function Date: Wed, 7 Sep 2022 10:03:50 +0200 Message-Id: <20220907080353.111926-42-alistair.francis@wdc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907080353.111926-1-alistair.francis@wdc.com> References: <20220907080353.111926-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662543136217100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra All the hpmcounters and the fixed counters (CY, IR, TM) can be represented as a unified counter. Thus, the predicate function doesn't need handle each case separately. Simplify the predicate function so that we just handle things differently between RV32/RV64 and S/HS mode. Reviewed-by: Bin Meng Acked-by: Alistair Francis Signed-off-by: Atish Patra Message-Id: <20220824221701.41932-3-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 110 ++++----------------------------------------- 1 file changed, 9 insertions(+), 101 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 888ddfc4dd..2151e280a8 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -75,6 +75,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) CPUState *cs =3D env_cpu(env); RISCVCPU *cpu =3D RISCV_CPU(cs); int ctr_index; + target_ulong ctr_mask; int base_csrno =3D CSR_CYCLE; bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32 ? true : false; =20 @@ -83,122 +84,29 @@ static RISCVException ctr(CPURISCVState *env, int csrn= o) base_csrno +=3D 0x80; } ctr_index =3D csrno - base_csrno; + ctr_mask =3D BIT(ctr_index); =20 if ((csrno >=3D CSR_CYCLE && csrno <=3D CSR_INSTRET) || (csrno >=3D CSR_CYCLEH && csrno <=3D CSR_INSTRETH)) { goto skip_ext_pmu_check; } =20 - if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & BIT(ctr_index)))) { + if (!(cpu->pmu_avail_ctrs & ctr_mask)) { /* No counter is enabled in PMU or the counter is out of range */ return RISCV_EXCP_ILLEGAL_INST; } =20 skip_ext_pmu_check: =20 - if (env->priv =3D=3D PRV_S) { - switch (csrno) { - case CSR_CYCLE: - if (!get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_TIME: - if (!get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_INSTRET: - if (!get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - if (!get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - } - if (rv32) { - switch (csrno) { - case CSR_CYCLEH: - if (!get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_TIMEH: - if (!get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_INSTRETH: - if (!get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - if (!get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - } - } + if (((env->priv =3D=3D PRV_S) && (!get_field(env->mcounteren, ctr_mask= ))) || + ((env->priv =3D=3D PRV_U) && (!get_field(env->scounteren, ctr_mask= )))) { + return RISCV_EXCP_ILLEGAL_INST; } =20 if (riscv_cpu_virt_enabled(env)) { - switch (csrno) { - case CSR_CYCLE: - if (!get_field(env->hcounteren, COUNTEREN_CY) && - get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_TIME: - if (!get_field(env->hcounteren, COUNTEREN_TM) && - get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_INSTRET: - if (!get_field(env->hcounteren, COUNTEREN_IR) && - get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - if (!get_field(env->hcounteren, 1 << ctr_index) && - get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - } - if (rv32) { - switch (csrno) { - case CSR_CYCLEH: - if (!get_field(env->hcounteren, COUNTEREN_CY) && - get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_TIMEH: - if (!get_field(env->hcounteren, COUNTEREN_TM) && - get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_INSTRETH: - if (!get_field(env->hcounteren, COUNTEREN_IR) && - get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - if (!get_field(env->hcounteren, 1 << ctr_index) && - get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - } + if (!get_field(env->hcounteren, ctr_mask) && + get_field(env->mcounteren, ctr_mask)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 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X-IronPort-AV: E=Sophos;i="5.93,296,1654531200"; d="scan'208";a="210715138" IronPort-SDR: 7Q/zgOyyW45L6wHcl+sy1tS9B+sMWKQ6FPWsVji8f9yJ//aZDO8bsoK8XMpCO46xFZK8Hzni8R l7IPI2zPs/Oj0KdWUyEuCO3THn4tlpQl2WUuGw9MIbY31jC0TVIhOOvqLPMUkqZk4An82//d80 1KueaKbOZsVc2a7BfLU6vXfIzQWk4hHriZu3s4NowAtsVOozAWrU+2tvpAdufyUiP14FGownbj iw2Sl/mxe3m39moIfwgNCbKZHihwHre1hjo6LdOmqTpHyv7P62jaAHtu55II5pTGQDU7NTN452 L5nte2NX1ShKMShvOk/hm1OG IronPort-SDR: XsCVtEV93qwutHyKnFKASu0659zfYZ/k5T0r+yF8n++OhFAHcPOVS5yoaOoaBGddJ87DsysUr0 AsjZnnYAnJ4hvsQvFJluwKpMlnjLsJYN1dRUhew98AEJm5/XJU1FIu3RXHv5d8xlg0q0TjLMvw mqE2Y8GI9r0XyhEgofmi+nKHaNvrSgy6EGQvrlJly/6s6pSJHilEYo80agHGrhWfQ5AUWU21IO 8Dd/klY1reXhjJ6SdbSKLZ3BWZ790naL52RLZNYUI2fa2a1++hpdlAXjb+0+wdO7j4ntKO9fN0 ltk= WDCIronportException: Internal To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Atish Patra , Alistair Francis , Heiko Stuebner , Atish Patra Subject: [PULL 42/44] target/riscv: Add few cache related PMU events Date: Wed, 7 Sep 2022 10:03:51 +0200 Message-Id: <20220907080353.111926-43-alistair.francis@wdc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907080353.111926-1-alistair.francis@wdc.com> References: <20220907080353.111926-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662542764847100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Reviewed-by: Alistair Francis Tested-by: Heiko Stuebner Signed-off-by: Atish Patra Signed-off-by: Atish Patra Message-Id: <20220824221701.41932-4-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 719c5d5d02..67e4c0efd2 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -21,11 +21,13 @@ #include "qemu/log.h" #include "qemu/main-loop.h" #include "cpu.h" +#include "pmu.h" #include "exec/exec-all.h" #include "instmap.h" #include "tcg/tcg-op.h" #include "trace.h" #include "semihosting/common-semi.h" +#include "cpu_bits.h" =20 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { @@ -1189,6 +1191,28 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vad= dr addr, cpu_loop_exit_restore(cs, retaddr); } =20 + +static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) +{ + enum riscv_pmu_event_idx pmu_event_type; + + switch (access_type) { + case MMU_INST_FETCH: + pmu_event_type =3D RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; + break; + case MMU_DATA_LOAD: + pmu_event_type =3D RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; + break; + case MMU_DATA_STORE: + pmu_event_type =3D RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; + break; + default: + return; + } + + riscv_pmu_incr_ctr(cpu, pmu_event_type); +} + bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -1287,6 +1311,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, } } } else { + pmu_tlb_fill_incr_ctr(cpu, access_type); /* Single stage lookup */ ret =3D get_physical_address(env, &pa, &prot, address, NULL, access_type, mmu_idx, true, false, fals= e); --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662543515931100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra Qemu virt machine can support few cache events and cycle/instret counters. It also supports counter overflow for these events. Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine capabilities. There are some dummy nodes added for testing as well. Acked-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra Message-Id: <20220824221701.41932-5-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/pmu.h | 1 + hw/riscv/virt.c | 16 +++++++++++++ target/riscv/pmu.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 74 insertions(+) diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 036653627f..3004ce37b6 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -31,5 +31,6 @@ int riscv_pmu_init(RISCVCPU *cpu, int num_counters); int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); +void riscv_pmu_generate_fdt_node(void *fdt, int num_counters, char *pmu_na= me); int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index ff8c0df5cd..befa9d2c26 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -30,6 +30,7 @@ #include "hw/char/serial.h" #include "target/riscv/cpu.h" #include "hw/core/sysbus-fdt.h" +#include "target/riscv/pmu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" @@ -708,6 +709,20 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_phandles[socket] =3D aplic_s_phandle; } =20 +static void create_fdt_pmu(RISCVVirtState *s) +{ + char *pmu_name; + MachineState *mc =3D MACHINE(s); + RISCVCPU hart =3D s->soc[0].harts[0]; + + pmu_name =3D g_strdup_printf("/soc/pmu"); + qemu_fdt_add_subnode(mc->fdt, pmu_name); + qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu"); + riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name); + + g_free(pmu_name); +} + static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memma= p, bool is_32_bit, uint32_t *phandle, uint32_t *irq_mmio_phandle, @@ -1036,6 +1051,7 @@ static void create_fdt(RISCVVirtState *s, const MemMa= pEntry *memmap, =20 create_fdt_flash(s, memmap); create_fdt_fw_cfg(s, memmap); + create_fdt_pmu(s); =20 update_bootargs: if (cmdline && *cmdline) { diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index a5f504e53c..b8e56d2b7b 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -20,11 +20,68 @@ #include "cpu.h" #include "pmu.h" #include "sysemu/cpu-timers.h" +#include "sysemu/device_tree.h" =20 #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ #define MAKE_32BIT_MASK(shift, length) \ (((uint32_t)(~0UL) >> (32 - (length))) << (shift)) =20 +/* + * To keep it simple, any event can be mapped to any programmable counters= in + * QEMU. The generic cycle & instruction count events can also be monitored + * using programmable counters. In that case, mcycle & minstret must conti= nue + * to provide the correct value as well. Heterogeneous PMU per hart is not + * supported yet. Thus, number of counters are same across all harts. + */ +void riscv_pmu_generate_fdt_node(void *fdt, int num_ctrs, char *pmu_name) +{ + uint32_t fdt_event_ctr_map[20] =3D {}; + uint32_t cmask; + + /* All the programmable counters can map to any event */ + cmask =3D MAKE_32BIT_MASK(3, num_ctrs); + + /* + * The event encoding is specified in the SBI specification + * Event idx is a 20bits wide number encoded as follows: + * event_idx[19:16] =3D type + * event_idx[15:0] =3D code + * The code field in cache events are encoded as follows: + * event_idx.code[15:3] =3D cache_id + * event_idx.code[2:1] =3D op_id + * event_idx.code[0:0] =3D result_id + */ + + /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */ + fdt_event_ctr_map[0] =3D cpu_to_be32(0x00000001); + fdt_event_ctr_map[1] =3D cpu_to_be32(0x00000001); + fdt_event_ctr_map[2] =3D cpu_to_be32(cmask | 1 << 0); + + /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */ + fdt_event_ctr_map[3] =3D cpu_to_be32(0x00000002); + fdt_event_ctr_map[4] =3D cpu_to_be32(0x00000002); + fdt_event_ctr_map[5] =3D cpu_to_be32(cmask | 1 << 2); + + /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */ + fdt_event_ctr_map[6] =3D cpu_to_be32(0x00010019); + fdt_event_ctr_map[7] =3D cpu_to_be32(0x00010019); + fdt_event_ctr_map[8] =3D cpu_to_be32(cmask); + + /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */ + fdt_event_ctr_map[9] =3D cpu_to_be32(0x0001001B); + fdt_event_ctr_map[10] =3D cpu_to_be32(0x0001001B); + fdt_event_ctr_map[11] =3D cpu_to_be32(cmask); + + /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */ + fdt_event_ctr_map[12] =3D cpu_to_be32(0x00010021); + fdt_event_ctr_map[13] =3D cpu_to_be32(0x00010021); + fdt_event_ctr_map[14] =3D cpu_to_be32(cmask); + + /* This a OpenSBI specific DT property documented in OpenSBI docs */ + qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters", + fdt_event_ctr_map, sizeof(fdt_event_ctr_map)); +} + static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx) { if (ctr_idx < 3 || ctr_idx >=3D RV_MAX_MHPMCOUNTERS || --=20 2.37.2 From nobody Sun May 19 12:00:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-IronPort-AV: E=Sophos;i="5.93,296,1654531200"; d="scan'208";a="210715155" IronPort-SDR: pwlF14hjK5cIat958wj7B/pDuGX8K5BkCGRsYfimaB8Qi+mkQeL32pZVMBpvRlcH3w+Eh5z0ET vANxQXOcyNCoDRhMamgf1p2vKtkaHkDZatDUW+gjuzn3RxsyZQoOz7Qopijtedho5Gw+leOPNT UJGBNFMnvHdlJ5rTEA0had3EFvJ6HosWRCB00cCbw8emqX3EL4ndKANJWjpY3ppW0gy22CV6HC AeNkkmvqCa+oMXbbLJsuHGjTJpXBm6LXX9FYfi1CnA4N9aqRkeqUusklUlZwKnJqw0BB66fukT WEiaPmHXSyDUkJvmAuMLX0nu IronPort-SDR: Y0CgPmFu+NybHgbqPZdHWPkqEIa4bHXfbiJ8B/YJrFbHnTUD1Yhdce/y2p8lc26elzGWaLZbNc UaT6n+yunooUen9efj7ptASDhOVz3lxCoOUPI5o5Qi2NlB6q5Ds7tL8TdRyGb0ZDtU0hvfxPs7 V+DuN10qmON6E7CHTneREJvAzOjeri/E4aLoOg5HlGQNSIXX0PVILtPfGPj1Mq1u+ltkxy+KSu 02RypVka+JecEpZQhzrID//k8KZzqHGjOQZaf0R+qqMLEFKtJzQw/WkOk0YjWGESW55pwoNjY/ c9E= WDCIronportException: Internal To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Atish Patra , Weiwei Li , Alistair Francis Subject: [PULL 44/44] target/riscv: Update the privilege field for sscofpmf CSRs Date: Wed, 7 Sep 2022 10:03:53 +0200 Message-Id: <20220907080353.111926-45-alistair.francis@wdc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907080353.111926-1-alistair.francis@wdc.com> References: <20220907080353.111926-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis From: Alistair Francis via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1662543778278100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra The sscofpmf extension was ratified as a part of priv spec v1.12. Mark the csr_ops accordingly. Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-Id: <20220824221701.41932-6-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 90 ++++++++++++++++++++++++++++++---------------- 1 file changed, 60 insertions(+), 30 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 2151e280a8..b96db1b62b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -4067,63 +4067,92 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { write_mhpmevent }, =20 [CSR_MHPMEVENT3H] =3D { "mhpmevent3h", sscofpmf, read_mhpmevent= h, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT4H] =3D { "mhpmevent4h", sscofpmf, read_mhpmevent= h, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT5H] =3D { "mhpmevent5h", sscofpmf, read_mhpmevent= h, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT6H] =3D { "mhpmevent6h", sscofpmf, read_mhpmevent= h, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT7H] =3D { "mhpmevent7h", sscofpmf, read_mhpmevent= h, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT8H] =3D { "mhpmevent8h", sscofpmf, read_mhpmevent= h, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT9H] =3D { "mhpmevent9h", sscofpmf, read_mhpmevent= h, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT10H] =3D { "mhpmevent10h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT11H] =3D { "mhpmevent11h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT12H] =3D { "mhpmevent12h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT13H] =3D { "mhpmevent13h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT14H] =3D { "mhpmevent14h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT15H] =3D { "mhpmevent15h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT16H] =3D { "mhpmevent16h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT17H] =3D { "mhpmevent17h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT18H] =3D { "mhpmevent18h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT19H] =3D { "mhpmevent19h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT20H] =3D { "mhpmevent20h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT21H] =3D { "mhpmevent21h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT22H] =3D { "mhpmevent22h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT23H] =3D { "mhpmevent23h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT24H] =3D { "mhpmevent24h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT25H] =3D { "mhpmevent25h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT26H] =3D { "mhpmevent26h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT27H] =3D { "mhpmevent27h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT28H] =3D { "mhpmevent28h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT29H] =3D { "mhpmevent29h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT30H] =3D { "mhpmevent30h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MHPMEVENT31H] =3D { "mhpmevent31h", sscofpmf, read_mhpmeven= th, - write_mhpmeventh }, + write_mhpmeventh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, =20 [CSR_HPMCOUNTER3H] =3D { "hpmcounter3h", ctr32, read_hpmcounterh = }, [CSR_HPMCOUNTER4H] =3D { "hpmcounter4h", ctr32, read_hpmcounterh = }, @@ -4213,7 +4242,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { write_mhpmcounterh }, [CSR_MHPMCOUNTER31H] =3D { "mhpmcounter31h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_SCOUNTOVF] =3D { "scountovf", sscofpmf, read_scountovf }, + [CSR_SCOUNTOVF] =3D { "scountovf", sscofpmf, read_scountovf, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, =20 #endif /* !CONFIG_USER_ONLY */ }; --=20 2.37.2