From nobody Tue May 21 10:51:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662470151; cv=none; d=zohomail.com; s=zohoarc; b=njixYuYnEu5gMI/V33BMExSbQGRUL0MSvaFirv02zm5TYitdaQqigM4kUl5nlHJ36UQ6ShYmVxArVw3Y+gn6IGXGv/NeJxQc2l7x+KUX3Deem1h2c0aXkI1+MFTT3k4gythNvf4j3aCEkeLvOdqXZOVFSKnbAub/f7XSVLTp+70= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662470151; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aKbRoFYpyWQq6lG2nZ7OcTh1eDfc3FMAkgtdEXuGp5M=; b=MdJFeU5F8myomAhCxu8k9zTsA9pJZ1Dra6RPxPFahy6oxXhnqls6s/cAMMu3L8mhgGzNr3+shOESHPy1fGcS+wX73X8QrQ2PQmrvlChQEHU7WH5fy9o0XZ3JLCdIuV5WIk7a+oEL8WtzwaE3ZxyfwxxV64bQ/4KbYoyxYVeI/NQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1662470151395755.6082486740881; Tue, 6 Sep 2022 06:15:51 -0700 (PDT) Received: from localhost ([::1]:40652 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oVYQg-000475-74 for importer@patchew.org; Tue, 06 Sep 2022 09:15:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42646) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oVXbT-0005a7-IH for qemu-devel@nongnu.org; Tue, 06 Sep 2022 08:22:55 -0400 Received: from mail-ed1-x52e.google.com ([2a00:1450:4864:20::52e]:36842) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oVXbO-0003po-NV for qemu-devel@nongnu.org; Tue, 06 Sep 2022 08:22:54 -0400 Received: by mail-ed1-x52e.google.com with SMTP id e18so14910498edj.3 for ; Tue, 06 Sep 2022 05:22:50 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id d21-20020a170906305500b0073d6ab5bcaasm6479034ejd.212.2022.09.06.05.22.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 05:22:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=aKbRoFYpyWQq6lG2nZ7OcTh1eDfc3FMAkgtdEXuGp5M=; b=Nn35FHxtnu+IZkF+3zS+nlZgU7QFrj1cJ+97yeKNQPNPdKb/b22IwhEosXdWQ3o1n8 WtsX3e0eDpbrc9KJupcujUM92MJt+ZNTT61nk1gUashX4BU9ZghFJysc83OS/NOhP3AR m799085CmlfR5d0sv0TV/MrQQbmla/cy2q+Etr2cyHAmNPaR5G8W01m8i1GS9MC5uqba ieY4MGeOVK79tT8ECoMt6rd6yBqdwmkk9SzMGUpKhoRz3xcgTErQGluj3i/2/Rvw95AC BhUZXSbgOAyfrqXbzM63QvUI5SgkwT7fku6cIyNmhob36l+bZI+hxTPv1I0DkFC39NOa ueYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=aKbRoFYpyWQq6lG2nZ7OcTh1eDfc3FMAkgtdEXuGp5M=; b=v1vfiOMcC+L5bSARdyl+OjLewvQqoZM3Ly1oQ6M0TzhbvtFprUQhXBxFcCnEcWpr8X kv1pPPRRnr0GGjH74yZ0amgbVSsY1e3s9lJqc0qp1vAKFQ/Y3HAeDnwENpcFyQWaRh9R VsTU+muX75+7p4ZpT75IHmnH+zlEAhi4HBHEVwlSs1pRmImC1A3a7Mh8so3sFYRMuHXm q5YnwtcCotBt1T7S/oDf2uOWDCcbmswIrL7CmQRj8A/nk0rNQetClTuqWJrmwfAoUXyo 1tSLN6awKCSEuMj/QVAoNMUG9veZW6TJBh746+8OjQpI80NpIswH6iM5/wk1CTrdV2sM JknQ== X-Gm-Message-State: ACgBeo2QefFSfBqmz5KvJcN1dwOPDwGIEUW72qnVS+mdcD8j2RUe00t8 idVhSsWGbCzwptQKBj9R/wHMgg== X-Google-Smtp-Source: AA6agR4HjSrFaQX13TQm33z5sf/01d783XOxpRQU7HKfnb9NkGnbkgbgAgsKXx12g30/y0zCDdNl5w== X-Received: by 2002:a05:6402:50cb:b0:440:87d4:3ad2 with SMTP id h11-20020a05640250cb00b0044087d43ad2mr47322471edb.219.1662466968575; Tue, 06 Sep 2022 05:22:48 -0700 (PDT) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 01/11] riscv: Add privilege level to DisasContext Date: Tue, 6 Sep 2022 14:22:33 +0200 Message-Id: <20220906122243.1243354-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220906122243.1243354-1-christoph.muellner@vrull.eu> References: <20220906122243.1243354-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=christoph.muellner@vrull.eu; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1662470154344100001 From: Christoph M=C3=BCllner This allows privileged instructions to check the required privilege level in the translation without calling a helper. Signed-off-by: Christoph M=C3=BCllner Reviewed-by: LIU Zhiwei --- target/riscv/translate.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 63b04e8a94..fd241ff667 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -59,6 +59,9 @@ typedef struct DisasContext { /* pc_succ_insn points to the instruction following base.pc_next */ target_ulong pc_succ_insn; target_ulong priv_ver; +#ifndef CONFIG_USER_ONLY + target_ulong priv; +#endif RISCVMXL misa_mxl_max; RISCVMXL xl; uint32_t misa_ext; @@ -1079,6 +1082,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->mstatus_vs =3D tb_flags & TB_FLAGS_MSTATUS_VS; ctx->priv_ver =3D env->priv_ver; #if !defined(CONFIG_USER_ONLY) + ctx->priv =3D env->priv; if (riscv_has_ext(env, RVH)) { ctx->virt_enabled =3D riscv_cpu_virt_enabled(env); } else { --=20 2.37.2 From nobody Tue May 21 10:51:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662471695; cv=none; d=zohomail.com; s=zohoarc; b=mV7dE3TKc0S2W+DmYEt+WVNg298UDWuG0atoNqd1lu+bugSo9FtkhxECDpgSB4zR25+UnYLuJSImUXCyKS6O4HrnCtLtWngX5IOW9OmUQoWZtk7VEcpmJkGwdL8vrHsJWcKfqMe6JxF6sFrKdoYSFprI2SBPqOQ30agi5TCYZ0Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662471695; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Eu+amAVVQVyWILwD4hKAaZX2BvgEHifujr+Z2o9Bj7Q=; b=Eb2yBhUYO3Lr4Mn4vczEBgGsI7A6G5ZuXdmiY09PNsEhD84elJKHcQUFW3f3MxiskvdvImqNqHkO9luOKSf5FFY/uJ7Xk8f9SUu/SiGnugQkQ1pZ4vXGn3Gv25Y0StS+MQzHFqV2DtQ6dkCAmsSiGsXGDr8wHWGXaFeOJh/vBGw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166247169586445.07491447330756; Tue, 6 Sep 2022 06:41:35 -0700 (PDT) Received: from localhost ([::1]:56298 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oVYpa-0003sY-QD for importer@patchew.org; Tue, 06 Sep 2022 09:41:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59320) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oVXbX-0005cR-FD for qemu-devel@nongnu.org; Tue, 06 Sep 2022 08:23:04 -0400 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]:42594) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oVXbR-0003qN-7y for qemu-devel@nongnu.org; Tue, 06 Sep 2022 08:22:57 -0400 Received: by mail-ej1-x630.google.com with SMTP id dc5so2976660ejb.9 for ; Tue, 06 Sep 2022 05:22:51 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id d21-20020a170906305500b0073d6ab5bcaasm6479034ejd.212.2022.09.06.05.22.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 05:22:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=Eu+amAVVQVyWILwD4hKAaZX2BvgEHifujr+Z2o9Bj7Q=; b=cY3XT9/BMPmus5yNSmmyEHr2VuSdXMc8M/XqRT6trPWT4wniYwOLdg97HCjmO7H3IZ rn+QBy/JlfztLKCzVAGp0M8mXOoQcPtCFDWTCUGB3YBwgv6e5u7heuQH9VtqA7BA4nFB YRaMqce9XX5T0ntKrQskKgAFWmeXj0GycLBUOLBFKJ5UHU4YWidV6XO87Gd6clS/krJc ng5gnn8VciueQjc6COw1NFKI6mN6qlsyD8xPlMAPvADccIt7g+EdDPXQ4+lJ/ElHHXpH R6uuogm5CiH5EIOLDkreRUSh2nGQVBbE/Sh3z5lczfTIOevnxOa19TdrhreVFM55CCix zjxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=Eu+amAVVQVyWILwD4hKAaZX2BvgEHifujr+Z2o9Bj7Q=; b=l2Ylb05OPwxX3er7EwE86CqN16wTiZeJSa9SmO3nJPR4AeOBb1fXH8maOtSXMa7sPb jfDVoBEl2l8PK7mOa1j1vAEV11t3EXU+KCcdnQmIyRqKknb3wPqERujOGiSE9xnwwWYe Tm131OYlhWj1Csfe6aAollLFa72XULhY4zYn8NThDXJzmMt8OD2Rt9e4TZ8y0hXFhF5Q TtKB/6qYWFuzjMBvZUdsJhcN3wVY8vnaUZqaXaSVBzxkSE/f9L8IfevInWb4xKwgC/eX tb0DyHf3yAnZmNb79mf5nMPtUY4J2Rfyz+h6AUQtsK4iUD68zO27ecHm59+Hfl2TbVmz EcmQ== X-Gm-Message-State: ACgBeo3ySWVtmqgr06CmjFMAVXVjBpdkg2AYSHi1Dq55mlMINU91ywZA i0ipc7cvlWJrlprhP973iUUf7g== X-Google-Smtp-Source: AA6agR5vXctxHrPycrpv/F3rhzuE4y2jWpdlnR6sCae4365yHLB2fC0oYaekvD9/qMHlTnlXC4GAVQ== X-Received: by 2002:a17:907:c28:b0:73d:beb7:b9c2 with SMTP id ga40-20020a1709070c2800b0073dbeb7b9c2mr39094123ejc.336.1662466970288; Tue, 06 Sep 2022 05:22:50 -0700 (PDT) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 02/11] RISC-V: Adding T-Head CMO instructions Date: Tue, 6 Sep 2022 14:22:34 +0200 Message-Id: <20220906122243.1243354-3-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220906122243.1243354-1-christoph.muellner@vrull.eu> References: <20220906122243.1243354-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=christoph.muellner@vrull.eu; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1662471697170100001 From: Christoph M=C3=BCllner This patch adds support for the T-Head CMO instructions. To avoid interfering with standard extensions, decoder and translation are in its own T-Head specific files. Future patches should be able to easily add additional T-Head extesions. The implementation does not have much functionality (besides accepting the instructions and not qualifying them as illegal instructions if the hart executes in the required privilege level for the instruction), as QEMU does not model CPU caches and instructions don't have any exception behaviour (at least not documented). The documentation shows, that the instructions are gated by mxstatus.theadisaee and mxstatus.ucme. However, since these settings are not changed by the upstream Linux kernel, we simply enable the instructions in all modes. Signed-off-by: Christoph M=C3=BCllner Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 66 ++++++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 11 +++- target/riscv/xtheadcmo.decode | 43 ++++++++++++++ 6 files changed, 120 insertions(+), 3 deletions(-) create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc create mode 100644 target/riscv/xtheadcmo.decode diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac6f82ebd0..7718ab0478 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -920,6 +920,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), =20 /* Vendor-specific custom extensions */ + DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), =20 /* These are experimental so mark with 'x-' */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5c7acc055a..b7ab53b7b8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -440,6 +440,7 @@ struct RISCVCPUConfig { uint64_t mimpid; =20 /* Vendor-specific custom extensions */ + bool ext_xtheadcmo; bool ext_XVentanaCondOps; =20 uint8_t pmu_num; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc new file mode 100644 index 0000000000..1b1e21ab77 --- /dev/null +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -0,0 +1,66 @@ +/* + * RISC-V translation routines for the T-Head vendor extensions (xthead*). + * + * Copyright (c) 2022 VRULL GmbH. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#define REQUIRE_PRIV_MHSU(ctx) + +#ifndef CONFIG_USER_ONLY +#define REQUIRE_PRIV_MHS(ctx) \ +do { \ + if (!(ctx->priv =3D=3D PRV_M || \ + ctx->priv =3D=3D PRV_H || \ + ctx->priv =3D=3D PRV_S)) { \ + return false; \ + } \ +} while (0) +#else +#define REQUIRE_PRIV_MHS(ctx) \ + return false; +#endif + +#define NOP_PRIVCHECK(insn, privcheck) \ +static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn * a) \ +{ \ + (void) a; \ + privcheck(ctx); \ + return true; \ +} + +NOP_PRIVCHECK(th_dcache_call, REQUIRE_PRIV_MHS) +NOP_PRIVCHECK(th_dcache_ciall, REQUIRE_PRIV_MHS) +NOP_PRIVCHECK(th_dcache_iall, REQUIRE_PRIV_MHS) +NOP_PRIVCHECK(th_dcache_cpa, REQUIRE_PRIV_MHS) +NOP_PRIVCHECK(th_dcache_cipa, REQUIRE_PRIV_MHS) +NOP_PRIVCHECK(th_dcache_ipa, REQUIRE_PRIV_MHS) +NOP_PRIVCHECK(th_dcache_cva, REQUIRE_PRIV_MHSU) +NOP_PRIVCHECK(th_dcache_civa, REQUIRE_PRIV_MHSU) +NOP_PRIVCHECK(th_dcache_iva, REQUIRE_PRIV_MHSU) +NOP_PRIVCHECK(th_dcache_csw, REQUIRE_PRIV_MHS) +NOP_PRIVCHECK(th_dcache_cisw, REQUIRE_PRIV_MHS) +NOP_PRIVCHECK(th_dcache_isw, REQUIRE_PRIV_MHS) +NOP_PRIVCHECK(th_dcache_cpal1, REQUIRE_PRIV_MHS) +NOP_PRIVCHECK(th_dcache_cval1, REQUIRE_PRIV_MHS) + +NOP_PRIVCHECK(th_icache_iall, REQUIRE_PRIV_MHS) +NOP_PRIVCHECK(th_icache_ialls, REQUIRE_PRIV_MHS) +NOP_PRIVCHECK(th_icache_ipa, REQUIRE_PRIV_MHS) +NOP_PRIVCHECK(th_icache_iva, REQUIRE_PRIV_MHSU) + +NOP_PRIVCHECK(th_l2cache_call, REQUIRE_PRIV_MHS) +NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_PRIV_MHS) +NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_PRIV_MHS) + diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 6b9435d69a..1d149e05cd 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -2,6 +2,7 @@ gen =3D [ decodetree.process('insn16.decode', extra_args: ['--static-decode=3Ddeco= de_insn16', '--insnwidth=3D16']), decodetree.process('insn32.decode', extra_args: '--static-decode=3Ddecod= e_insn32'), + decodetree.process('xtheadcmo.decode', extra_args: '--static-decode=3Dde= code_xtheadcmo'), decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decod= e=3Ddecode_XVentanaCodeOps'), ] =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index fd241ff667..d16ae63850 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -132,7 +132,8 @@ static bool always_true_p(DisasContext *ctx __attribut= e__((__unused__))) return ctx->cfg_ptr->ext_ ## ext ; \ } =20 -MATERIALISE_EXT_PREDICATE(XVentanaCondOps); +MATERIALISE_EXT_PREDICATE(xtheadcmo) +MATERIALISE_EXT_PREDICATE(XVentanaCondOps) =20 #ifdef TARGET_RISCV32 #define get_xl(ctx) MXL_RV32 @@ -717,6 +718,10 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm) /* Include the auto-generated decoder for 32 bit insn */ #include "decode-insn32.c.inc" =20 +/* Include decoders for factored-out extensions */ +#include "decode-xtheadcmo.c.inc" +#include "decode-XVentanaCondOps.c.inc" + static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, void (*func)(TCGv, TCGv, target_long)) { @@ -1018,12 +1023,11 @@ static uint32_t opcode_at(DisasContextBase *dcbase,= target_ulong pc) #include "insn_trans/trans_rvk.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" +#include "insn_trans/trans_xthead.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" =20 /* Include the auto-generated decoder for 16 bit insn */ #include "decode-insn16.c.inc" -/* Include decoders for factored-out extensions */ -#include "decode-XVentanaCondOps.c.inc" =20 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opc= ode) { @@ -1036,6 +1040,7 @@ static void decode_opc(CPURISCVState *env, DisasConte= xt *ctx, uint16_t opcode) bool (*decode_func)(DisasContext *, uint32_t); } decoders[] =3D { { always_true_p, decode_insn32 }, + { has_xtheadcmo_p, decode_xtheadcmo }, { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, }; =20 diff --git a/target/riscv/xtheadcmo.decode b/target/riscv/xtheadcmo.decode new file mode 100644 index 0000000000..8ddf9b3997 --- /dev/null +++ b/target/riscv/xtheadcmo.decode @@ -0,0 +1,43 @@ +# +# RISC-V translation routines for the XTheadCmo extension +# +# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# The XTheadCmo extension provides instructions for cache management. +# +# It is documented in +# https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.= 0.0/xthead-2022-09-05-2.0.0.pdf + +# Fields: +%rs1 15:5 + +# Formats +@sfence_vm ....... ..... ..... ... ..... ....... %rs1 + +# *** CMO instructions +th_dcache_call 0000000 00001 00000 000 00000 0001011 +th_dcache_ciall 0000000 00011 00000 000 00000 0001011 +th_dcache_iall 0000000 00010 00000 000 00000 0001011 +th_dcache_cpa 0000001 01001 ..... 000 00000 0001011 @sfence_vm +th_dcache_cipa 0000001 01011 ..... 000 00000 0001011 @sfence_vm +th_dcache_ipa 0000001 01010 ..... 000 00000 0001011 @sfence_vm +th_dcache_cva 0000001 00101 ..... 000 00000 0001011 @sfence_vm +th_dcache_civa 0000001 00111 ..... 000 00000 0001011 @sfence_vm +th_dcache_iva 0000001 00110 ..... 000 00000 0001011 @sfence_vm +th_dcache_csw 0000001 00001 ..... 000 00000 0001011 @sfence_vm +th_dcache_cisw 0000001 00011 ..... 000 00000 0001011 @sfence_vm +th_dcache_isw 0000001 00010 ..... 000 00000 0001011 @sfence_vm +th_dcache_cpal1 0000001 01000 ..... 000 00000 0001011 @sfence_vm +th_dcache_cval1 0000001 00100 ..... 000 00000 0001011 @sfence_vm + +th_icache_iall 0000000 10000 00000 000 00000 0001011 +th_icache_ialls 0000000 10001 00000 000 00000 0001011 +th_icache_ipa 0000001 11000 ..... 000 00000 0001011 @sfence_vm +th_icache_iva 0000001 10000 ..... 000 00000 0001011 @sfence_vm + +th_l2cache_call 0000000 10101 00000 000 00000 0001011 +th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 +th_l2cache_iall 0000000 10110 00000 000 00000 0001011 + --=20 2.37.2 From nobody Tue May 21 10:51:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id d21-20020a170906305500b0073d6ab5bcaasm6479034ejd.212.2022.09.06.05.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 05:22:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=Q2A8+IgzZZwHIAVpxiQKqj6xI8wMhMdEYDyHApPPink=; b=Kzi9UAd30HHZrd1grTPc4KyjEoakABvnUDqxpHZxiTvIQU50gNjMTaih1EhQ0UDU/J PjXQ8QfvWJ/kJ3KGAIJy8gkYBXovEbDMlSu8YF9bPiTOBdGuM6iW0uICheajvG6f9Ita q0vv0/FZVJ9M5oDPrYir4Fgdufvl7A165Dlz0YDPdFIrSuejQxd/Ez1ETFSatNtkvhN+ mE2gPpfPFcJKEzypdseToSK9hYXfjtVR1ZtNGB65zYxrNZYLFP3jx5uisO3upjKsVbHo fTfvVjD/7pXOeCDYNTe6KTOMcipI2xXZ0r5M3IiGYVyK2W9PFcI7n9+yeaFZNR0/MUhW w5/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=Q2A8+IgzZZwHIAVpxiQKqj6xI8wMhMdEYDyHApPPink=; b=pYcLH8JizVDSjLwWGzsAt94kbou1/E5OLYZK3Vfx2Qpb4buZx2tLD5Oyhbd3Ve6YFj tHzK85UGK0Tjkr9KwNLJUfMZ/T4Yyd8viR8BZOb2ro90gYNLQfjbuJeLtEovu9UEj7Yi 8dGgpwG1k06wuT/ynIGcqBAD0xNEpBxckIPjRPnqex2LbgA+tNShX1FsH5tOo10D+zDV fRidC9/iWRIJ5gYLoUjeHZC/XyNraK20cd1A1TgAJF80qHZUZYeKJdwAdspGN6/NOFDP V5FmwKYpqcS/RHOvb2YwqtWD7kM1gyth3tpPKRXDh6uR9hqT2MDW8aK54H7tKdc1LaGl roGg== X-Gm-Message-State: ACgBeo22qcxQlyzBrB9/G6s6QDQ9r7CXTOz+W9doS/DCj1c6REvQ2AMb qv/W/0sP/e4Za2OUNp7bZI8a9A== X-Google-Smtp-Source: AA6agR47qxP/IwjtPFA5e/ISdOt9g+g26haHekCASCrc5gChBPvrNaD5lRme+cdxIV/BOZqBAgvydg== X-Received: by 2002:a05:6402:4517:b0:443:7fe1:2d60 with SMTP id ez23-20020a056402451700b004437fe12d60mr47627146edb.133.1662466971797; Tue, 06 Sep 2022 05:22:51 -0700 (PDT) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 03/11] RISC-V: Adding T-Head SYNC instructions Date: Tue, 6 Sep 2022 14:22:35 +0200 Message-Id: <20220906122243.1243354-4-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220906122243.1243354-1-christoph.muellner@vrull.eu> References: <20220906122243.1243354-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=christoph.muellner@vrull.eu; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1662470553829100003 From: Christoph M=C3=BCllner This patch adds support for the T-Head SYNC instructions. The patch uses the T-Head specific decoder and translation. The implementation does not have much functionality (besides accepting the instructions and not qualifying them as illegal instructions if the hart executes in the required privilege level for the instruction), as QEMU does not model CPU caches, or out-of-order execution. Further the instructions don't have any exception behaviour (at least not documented). Signed-off-by: Christoph M=C3=BCllner --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 6 ++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 3 +++ target/riscv/xtheadsync.decode | 25 ++++++++++++++++++++++ 6 files changed, 37 insertions(+) create mode 100644 target/riscv/xtheadsync.decode diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7718ab0478..a72722cfa6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -921,6 +921,7 @@ static Property riscv_cpu_extensions[] =3D { =20 /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), + DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), =20 /* These are experimental so mark with 'x-' */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b7ab53b7b8..4ae22cf529 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -441,6 +441,7 @@ struct RISCVCPUConfig { =20 /* Vendor-specific custom extensions */ bool ext_xtheadcmo; + bool ext_xtheadsync; bool ext_XVentanaCondOps; =20 uint8_t pmu_num; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index 1b1e21ab77..0a6719b2e2 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -64,3 +64,9 @@ NOP_PRIVCHECK(th_l2cache_call, REQUIRE_PRIV_MHS) NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_PRIV_MHS) NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_PRIV_MHS) =20 +NOP_PRIVCHECK(th_sfence_vmas, REQUIRE_PRIV_MHS) +NOP_PRIVCHECK(th_sync, REQUIRE_PRIV_MHSU) +NOP_PRIVCHECK(th_sync_i, REQUIRE_PRIV_MHSU) +NOP_PRIVCHECK(th_sync_is, REQUIRE_PRIV_MHSU) +NOP_PRIVCHECK(th_sync_s, REQUIRE_PRIV_MHSU) + diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 1d149e05cd..f201cc6997 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -3,6 +3,7 @@ gen =3D [ decodetree.process('insn16.decode', extra_args: ['--static-decode=3Ddeco= de_insn16', '--insnwidth=3D16']), decodetree.process('insn32.decode', extra_args: '--static-decode=3Ddecod= e_insn32'), decodetree.process('xtheadcmo.decode', extra_args: '--static-decode=3Dde= code_xtheadcmo'), + decodetree.process('xtheadsync.decode', extra_args: '--static-decode=3Dd= ecode_xtheadsync'), decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decod= e=3Ddecode_XVentanaCodeOps'), ] =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d16ae63850..a63cc3de46 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -133,6 +133,7 @@ static bool always_true_p(DisasContext *ctx __attribut= e__((__unused__))) } =20 MATERIALISE_EXT_PREDICATE(xtheadcmo) +MATERIALISE_EXT_PREDICATE(xtheadsync) MATERIALISE_EXT_PREDICATE(XVentanaCondOps) =20 #ifdef TARGET_RISCV32 @@ -720,6 +721,7 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm) =20 /* Include decoders for factored-out extensions */ #include "decode-xtheadcmo.c.inc" +#include "decode-xtheadsync.c.inc" #include "decode-XVentanaCondOps.c.inc" =20 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, @@ -1041,6 +1043,7 @@ static void decode_opc(CPURISCVState *env, DisasConte= xt *ctx, uint16_t opcode) } decoders[] =3D { { always_true_p, decode_insn32 }, { has_xtheadcmo_p, decode_xtheadcmo }, + { has_xtheadsync_p, decode_xtheadsync }, { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, }; =20 diff --git a/target/riscv/xtheadsync.decode b/target/riscv/xtheadsync.decode new file mode 100644 index 0000000000..d25735cce8 --- /dev/null +++ b/target/riscv/xtheadsync.decode @@ -0,0 +1,25 @@ +# +# RISC-V translation routines for the XTheadSync extension +# +# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# The XTheadSync extension provides instructions for multi-processor synch= ronization. +# +# It is documented in +# https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.= 0.0/xthead-2022-09-05-2.0.0.pdf + +# Fields: +%rs1 15:5 +%rs2 20:5 + +# Formats +@rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 + +# *** SYNC instructions +th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s +th_sync 0000000 11000 00000 000 00000 0001011 +th_sync_i 0000000 11010 00000 000 00000 0001011 +th_sync_is 0000000 11011 00000 000 00000 0001011 +th_sync_s 0000000 11001 00000 000 00000 0001011 --=20 2.37.2 From nobody Tue May 21 10:51:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id d21-20020a170906305500b0073d6ab5bcaasm6479034ejd.212.2022.09.06.05.22.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 05:22:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=dfnMqbplI81MlvFg/Jwud0Bz/JB0KG8jB7nKBm80dX0=; b=oYK2hkPhddto3Nv4vHoWLKwJALihsPwNRfDwL25Vf+c1buAPQXwYm5C8X31SMGvBQj Wy2zVkUGb5sI8vZ00ML7t7QQg5VLb2SBHHDAEPS03KE7bDR7IfgSschJWaJL7y2kjuWa jhPSE/YC+rTtYYVAp4JNpf0mSFWHZ9m8JvmywxO9WU7PORxzeYt8vQT2oUm4DqJg62On CtG3ia32l22rG13uhBdbYwvoAY2AZoQXEQ97nKI7ySBLj+UWuuyXA5n/nluglJIiGdsU WCuJOEmB5Ur8mw90J+vNIBsTcUNaIESZM6fxNyzkJ4jQ2RG4IZbNNP9c39+rgWRC1EF9 WwwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=dfnMqbplI81MlvFg/Jwud0Bz/JB0KG8jB7nKBm80dX0=; b=I3tZW7+M8A0Ol3WWuXQxgI2s8LOi+hHhmbFuLa6HziBIWFR0I9stzQIoahMYZq2GIA M6jQxHNMJEFSvBKpfvYZe+pSUtai+VFUcZFLaztmys3FIMlhy08JckHKkpj76agbZ8WN hq+QhjOB25TlKQy9TuKDW+7ILk6qnmwG8YrTjkFCYi5lw4DDOpf2v+Mz+/dnXP1xVPUj mxPsZ8Dfqs5iC4kLfWXLdefc3ONO74xSulEuqm0+GDHPPw2fY4YDRR4MgpvvL+HPfQJF wDQjSggUK/zS+yHbkjT/0pE0+BAri/JZ4IUQErGTsAqE6hi1zi7p0wQF8ZpVcewzva4U 0m4w== X-Gm-Message-State: ACgBeo0DTU5pX1b3cYxMR33gIJYTGYZ21FFTPDitbFaxpYATbn9s3P7g PBhm5sL2uHSgjU5qhy/JTVWKLQ== X-Google-Smtp-Source: AA6agR6GNG8Pfcn6DvTzY5TaE/04qMvYg7izWQtyjJImg8SdLWRlNNK+tOe6p+yPqYqa702LXDxmhw== X-Received: by 2002:a17:906:9bf4:b0:76f:73d2:be40 with SMTP id de52-20020a1709069bf400b0076f73d2be40mr1157779ejc.90.1662466973330; Tue, 06 Sep 2022 05:22:53 -0700 (PDT) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 04/11] RISC-V: Adding T-Head Bitmanip instructions Date: Tue, 6 Sep 2022 14:22:36 +0200 Message-Id: <20220906122243.1243354-5-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220906122243.1243354-1-christoph.muellner@vrull.eu> References: <20220906122243.1243354-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=christoph.muellner@vrull.eu; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1662471101330100001 From: Christoph M=C3=BCllner This patch adds support for the T-Head Bitmanip instructions. The patch uses the T-Head specific decoder and translation. As the instructions are similar to those of Zb*, we can reuse a lot of existing infrastructure code. Signed-off-by: Christoph M=C3=BCllner --- target/riscv/cpu.c | 3 + target/riscv/cpu.h | 3 + target/riscv/insn_trans/trans_xthead.c.inc | 124 +++++++++++++++++++++ target/riscv/meson.build | 3 + target/riscv/translate.c | 9 ++ target/riscv/xtheadba.decode | 46 ++++++++ target/riscv/xtheadbb.decode | 62 +++++++++++ target/riscv/xtheadbs.decode | 32 ++++++ 8 files changed, 282 insertions(+) create mode 100644 target/riscv/xtheadba.decode create mode 100644 target/riscv/xtheadbb.decode create mode 100644 target/riscv/xtheadbs.decode diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a72722cfa6..d129a6112a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -920,6 +920,9 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), =20 /* Vendor-specific custom extensions */ + DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), + DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), + DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4ae22cf529..9e2b3d6f56 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -440,6 +440,9 @@ struct RISCVCPUConfig { uint64_t mimpid; =20 /* Vendor-specific custom extensions */ + bool ext_xtheadba; + bool ext_xtheadbb; + bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index 0a6719b2e2..b2d523b905 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -70,3 +70,127 @@ NOP_PRIVCHECK(th_sync_i, REQUIRE_PRIV_MHSU) NOP_PRIVCHECK(th_sync_is, REQUIRE_PRIV_MHSU) NOP_PRIVCHECK(th_sync_s, REQUIRE_PRIV_MHSU) =20 +/* + * th.addsl is similar to sh[123]add (from Zba), but not an + * alternative encoding: while sh[123] applies the shift to rs1, + * th.addsl shifts rs2. + */ + +#define GEN_TH_ADDSL(SHAMT) \ +static void gen_th_addsl##SHAMT(TCGv ret, TCGv arg1, TCGv arg2) \ +{ \ + TCGv t =3D tcg_temp_new(); \ + tcg_gen_shli_tl(t, arg2, SHAMT); \ + tcg_gen_add_tl(ret, t, arg1); \ + tcg_temp_free(t); \ +} + +GEN_TH_ADDSL(1) +GEN_TH_ADDSL(2) +GEN_TH_ADDSL(3) + +#define GEN_TRANS_TH_ADDSL(SHAMT) \ +static bool trans_th_addsl##SHAMT(DisasContext *ctx, \ + arg_th_addsl##SHAMT * a) \ +{ \ + return gen_arith(ctx, a, EXT_NONE, gen_th_addsl##SHAMT, NULL); \ +} + +GEN_TRANS_TH_ADDSL(1) +GEN_TRANS_TH_ADDSL(2) +GEN_TRANS_TH_ADDSL(3) + + +/* th.srri is an alternate encoding for rori (from Zbb) */ +static bool trans_th_srri(DisasContext *ctx, arg_th_srri * a) +{ + return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl, NULL); +} + +/* th.srriw is an alternate encoding for roriw (from Zbb) */ +static bool trans_th_srriw(DisasContext *ctx, arg_th_srriw *a) +{ + ctx->ol =3D MXL_RV32; + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL); +} + +/* th.ext and th.extu perform signed/unsigned bitfield extraction */ +static bool gen_th_bfextract(DisasContext *ctx, arg_th_bfext *a, + void (*f)(TCGv, TCGv, unsigned int, unsigned = int)) +{ + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv source =3D get_gpr(ctx, a->rs1, EXT_ZERO); + + if (a->lsb <=3D a->msb) { + f(dest, source, a->lsb, a->msb - a->lsb + 1); + gen_set_gpr(ctx, a->rd, dest); + } + return true; +} + +static bool trans_th_ext(DisasContext *ctx, arg_th_ext *a) +{ + return gen_th_bfextract(ctx, a, tcg_gen_sextract_tl); +} + +static bool trans_th_extu(DisasContext *ctx, arg_th_extu *a) +{ + return gen_th_bfextract(ctx, a, tcg_gen_extract_tl); +} + +/* th.ff0: find first zero (clz on an inverted input) */ +static void gen_th_ff0(TCGv ret, TCGv arg1) +{ + TCGv t =3D tcg_temp_new(); + tcg_gen_not_tl(t, arg1); + gen_clz(ret, t); + tcg_temp_free(t); +} + +static bool trans_th_ff0(DisasContext *ctx, arg_th_ff0 *a) +{ + return gen_unary(ctx, a, EXT_NONE, gen_th_ff0); +} + +/* th.ff1 is an alternate encoding for clz (from Zbb) */ +static bool trans_th_ff1(DisasContext *ctx, arg_th_ff1 *a) +{ + return gen_unary(ctx, a, EXT_NONE, gen_clz); +} + +/* th.rev is an alternate encoding for the RV64 rev8 (from Zbb) */ +static bool trans_th_rev(DisasContext *ctx, arg_th_rev *a) +{ + return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl); +} + +/* th.revw is a sign-extended byte-swap of the lower word */ +static void gen_th_revw(TCGv ret, TCGv arg1) +{ + tcg_gen_bswap_tl(ret, arg1); + tcg_gen_sari_tl(ret, ret, 32); +} + +static bool trans_th_revw(DisasContext *ctx, arg_th_revw *a) +{ + return gen_unary(ctx, a, EXT_NONE, gen_th_revw); +} + +/* th.tstnbz is equivalent to an orc.b (from Zbb) with inverted result */ +static void gen_th_tstnbz(TCGv ret, TCGv source1) +{ + gen_orc_b(ret, source1); + tcg_gen_not_tl(ret, ret); +} + +static bool trans_th_tstnbz(DisasContext *ctx, arg_th_tstnbz *a) +{ + return gen_unary(ctx, a, EXT_ZERO, gen_th_tstnbz); +} + +/* th.tst is an alternate encoding for bexti (from Zbs) */ +static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a) +{ + return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext); +} + diff --git a/target/riscv/meson.build b/target/riscv/meson.build index f201cc6997..5ee37683cb 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -2,6 +2,9 @@ gen =3D [ decodetree.process('insn16.decode', extra_args: ['--static-decode=3Ddeco= de_insn16', '--insnwidth=3D16']), decodetree.process('insn32.decode', extra_args: '--static-decode=3Ddecod= e_insn32'), + decodetree.process('xtheadba.decode', extra_args: '--static-decode=3Ddec= ode_xtheadba'), + decodetree.process('xtheadbb.decode', extra_args: '--static-decode=3Ddec= ode_xtheadbb'), + decodetree.process('xtheadbs.decode', extra_args: '--static-decode=3Ddec= ode_xtheadbs'), decodetree.process('xtheadcmo.decode', extra_args: '--static-decode=3Dde= code_xtheadcmo'), decodetree.process('xtheadsync.decode', extra_args: '--static-decode=3Dd= ecode_xtheadsync'), decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decod= e=3Ddecode_XVentanaCodeOps'), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a63cc3de46..f662e403f8 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -132,6 +132,9 @@ static bool always_true_p(DisasContext *ctx __attribut= e__((__unused__))) return ctx->cfg_ptr->ext_ ## ext ; \ } =20 +MATERIALISE_EXT_PREDICATE(xtheadba) +MATERIALISE_EXT_PREDICATE(xtheadbb) +MATERIALISE_EXT_PREDICATE(xtheadbs) MATERIALISE_EXT_PREDICATE(xtheadcmo) MATERIALISE_EXT_PREDICATE(xtheadsync) MATERIALISE_EXT_PREDICATE(XVentanaCondOps) @@ -720,6 +723,9 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm) #include "decode-insn32.c.inc" =20 /* Include decoders for factored-out extensions */ +#include "decode-xtheadba.c.inc" +#include "decode-xtheadbb.c.inc" +#include "decode-xtheadbs.c.inc" #include "decode-xtheadcmo.c.inc" #include "decode-xtheadsync.c.inc" #include "decode-XVentanaCondOps.c.inc" @@ -1042,6 +1048,9 @@ static void decode_opc(CPURISCVState *env, DisasConte= xt *ctx, uint16_t opcode) bool (*decode_func)(DisasContext *, uint32_t); } decoders[] =3D { { always_true_p, decode_insn32 }, + { has_xtheadba_p, decode_xtheadba }, + { has_xtheadbb_p, decode_xtheadbb }, + { has_xtheadbs_p, decode_xtheadbs }, { has_xtheadcmo_p, decode_xtheadcmo }, { has_xtheadsync_p, decode_xtheadsync }, { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, diff --git a/target/riscv/xtheadba.decode b/target/riscv/xtheadba.decode new file mode 100644 index 0000000000..4e5e3f12f0 --- /dev/null +++ b/target/riscv/xtheadba.decode @@ -0,0 +1,46 @@ +# +# RISC-V instruction decode for the XTheadBa extension +# +# Copyright (c) 2022 Dr. Philipp Tomsich, philipp.tomsich@vrull.eu +# Christoph Muellner, christoph.muellner@vrull.eu +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# The XTheadBa extension provides instructions for address calculations, +# implementing the functional equivalent of a subset of Zba. +# +# It is documented in +# https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.= 0.0/xthead-2022-09-05-2.0.0.pdf +# +# The instruction contained in XTheadBb is: +# - th.addsl add rotate-right by immediate +# (similar to sh[123]add, but with rs1 and rs2 switched) +# This instruction reuses an existing instruction format. + +# Fields +%rs2 20:5 +%rs1 15:5 +%rd 7:5 + +# Argument sets +&r rd rs1 rs2 !extern + +# Formats: +@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd + +# *** Bitmanip addressing instructions +# Instead of defining a new encoding, we simply use the decoder to +# extract the imm[0:1] field and dispatch to separate translation +# functions (mirroring the `sh[123]add` instructions from Zba and +# the regular RVI `add` instruction. +# +# The only difference between sh[123]add and addsl is that the sohift +# is applied to rs1 (for addsl) instead of rs2 (for sh[123]add). +# +# Note that shift-by-0 is a valid operation according to the manual. +# This will be equivalent to a regular add. +add 0000000 ..... ..... 001 ..... 0001011 @r +th_addsl1 0000001 ..... ..... 001 ..... 0001011 @r +th_addsl2 0000010 ..... ..... 001 ..... 0001011 @r +th_addsl3 0000011 ..... ..... 001 ..... 0001011 @r + diff --git a/target/riscv/xtheadbb.decode b/target/riscv/xtheadbb.decode new file mode 100644 index 0000000000..2754a6444b --- /dev/null +++ b/target/riscv/xtheadbb.decode @@ -0,0 +1,62 @@ +# +# RISC-V instruction decode for the XTheadBb extension +# +# Copyright (c) 2022 Dr. Philipp Tomsich, philipp.tomsich@vrull.eu +# Christoph Muellner, christoph.muellner@vrull.eu +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# The XTheadBb extension provides basic bit-manipulation instructions, +# implementing the functional equivalent of a subset of Zbb. +# +# It is documented in +# https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.= 0.0/xthead-2022-09-05-2.0.0.pdf +# +# The instructions contained in XTheadBb are: +# - th.srri rotate-right by immediate (matches rori) +# - th.srriw rotate-right by immediate, w-form (matches roriw) +# - th.rev byte-reverse register (matches RV64-form of rev8) +# - th.revw byte-reverse low word, sign-extend result (no equivalent) +# - th.ext signed bitfield-extract (no equivalent) +# - th.extu unsigned bitfield-extract (no equivalent) +# - th.ff0 find-first zero (equivalent to clz on the inverted opera= nd) +# - th.ff1 find-first one (matches clz) +# - th.tstnbz test for zero-bytes (equivalent to the inverted result o= f orc.b) +# - th.tst test for bit (equivalent to bexti) +# +# These instructions generally reuse existing instruction formats. +# Only the th.ext and th.ext introduce a new, vendor-defined instruction f= ormat. + +# Fields +%rs2 20:5 +%rs1 15:5 +%rd 7:5 +%sh5 20:5 +%sh6 20:6 + +# Argument sets +&r2 rd rs1 !extern +&shift shamt rs1 rd !extern +&th_bfext msb lsb rs1 rd + +# Formats: +@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd +@th_bfext msb:6 lsb:6 ..... ... ..... ....... &th_bfext %rs1 %rd + +# Formats 64: +@sh5 ....... ..... ..... ... ..... ....... &shift shamt=3D%sh5 = %rs1 %rd + +# Formats 128: +@sh6 ...... ...... ..... ... ..... ....... &shift shamt=3D%sh6 %rs= 1 %rd + +# *** Bitmanip instructions +th_ext ...... ...... ..... 010 ..... 0001011 @th_bfext +th_extu ...... ...... ..... 011 ..... 0001011 @th_bfext +th_ff0 1000010 00000 ..... 001 ..... 0001011 @r2 +th_ff1 1000011 00000 ..... 001 ..... 0001011 @r2 +th_srri 000100 ...... ..... 001 ..... 0001011 @sh6 +th_srriw 0001010 ..... ..... 001 ..... 0001011 @sh5 +th_rev 1000001 00000 ..... 001 ..... 0001011 @r2 +th_revw 1001000 00000 ..... 001 ..... 0001011 @r2 +th_tstnbz 1000000 00000 ..... 001 ..... 0001011 @r2 + diff --git a/target/riscv/xtheadbs.decode b/target/riscv/xtheadbs.decode new file mode 100644 index 0000000000..7aa345b207 --- /dev/null +++ b/target/riscv/xtheadbs.decode @@ -0,0 +1,32 @@ +# +# RISC-V instruction decode for the XTheadBb extension +# +# Copyright (c) 2022 Dr. Philipp Tomsich, philipp.tomsich@vrull.eu +# Christoph Muellner, christoph.muellner@vrull.eu +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# XTheadBs provides basic bit-manipulation instructions, +# implementing the functional equivalent of a subset of Zbs. +# +# It is documented in +# https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.= 0.0/xthead-2022-09-05-2.0.0.pdf +# +# The instruction contained in XTheadBb is: +# - th.tst test if bit is set (matches bexti) +# +# The instruction reuses an existing instruction format. + +# Fields +%rs1 15:5 +%rd 7:5 +%sh6 20:6 + +# Argument sets +&shift shamt rs1 rd !extern + +# Formats 128: +@sh6 ...... ...... ..... ... ..... ....... &shift shamt=3D%sh6 %rs= 1 %rd + +# *** Bitmanip single-bit instructions +th_tst 100010 ...... ..... 001 ..... 0001011 @sh6 --=20 2.37.2 From nobody Tue May 21 10:51:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662472060; cv=none; d=zohomail.com; s=zohoarc; b=oIld5dYWwZV4Lt800lxi7DpbgODWXA0HJcLSgB3AaMY3VEOEcs02SsEALlkjldf3xIQgtXTTy8oWIJ79ZdJsb2/p9bGL2IzhCyIDecSOlIk44FEk4nlbnMkNqnv5X/JQnMwtTnF4uVsT/NE4a8alclLMPYvAhHjhK1qSX4304Nw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662472060; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aOh7zsauraP9R+VJcwE2IKulzqyQTi8hmp+P1Bbj1v8=; b=cn+0cKOTMPTL+8mIUW6IV1IwxsL6fNoZqSGqhEPdd+DqbxsZPqGM7FY8Ubk5r62fuAW+YebEgcXsvO/dbZigQm32Cl4kAsIu4RSbWMSlujXRbxjUD1JAsraBzxrl8trhlGVHqWgwuR8JT2l5rIBRcsMLUJndoAsFY5DpPXnGj9k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1662472060509110.05738468772188; Tue, 6 Sep 2022 06:47:40 -0700 (PDT) Received: from localhost ([::1]:54514 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oVYvS-00021b-Ud for importer@patchew.org; Tue, 06 Sep 2022 09:47:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42296) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oVXbh-0005gD-QZ for qemu-devel@nongnu.org; Tue, 06 Sep 2022 08:23:11 -0400 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]:38806) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oVXbV-0003rT-3D for qemu-devel@nongnu.org; Tue, 06 Sep 2022 08:23:04 -0400 Received: by mail-ej1-x631.google.com with SMTP id u9so22823849ejy.5 for ; Tue, 06 Sep 2022 05:22:56 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id d21-20020a170906305500b0073d6ab5bcaasm6479034ejd.212.2022.09.06.05.22.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 05:22:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=aOh7zsauraP9R+VJcwE2IKulzqyQTi8hmp+P1Bbj1v8=; b=X8Bhk+zGm0SurfMSG/2whlaE+11OEG8+E39qPS4Wg4/F8nUgNaZInDb8uJzjwSEklR 6/YeVn8KXXsLr1m3/Hzt7ijS7ZcCC3U69pWecCRtEPmAEh+YbbNgsnIYKDR0PliEpL5Y An5dlVbw5d+QbyW2hAllcDbw/YrRbsT5G2KyLGk8FlQNO/22MXSS+4h0bA6PCidqtAgd Lm6+Y0lJ7IwLcDPWavaBPwPqIR1pLLIjZ/57uXz226MKK6eO5CW01K+Te+MAfVqOZT8T rWxzrW03Nbn8cIv/b7EPumigrVFPcngh2okh0FuNPWWh67gZNYRxBRBprZN/bshE338r By3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=aOh7zsauraP9R+VJcwE2IKulzqyQTi8hmp+P1Bbj1v8=; b=L0FJ/iJLcHKS6Qhlb4qGchlGTGw8bynDCgH2IXcdQvLcfpkpEulS3Ron6PnX02EEYw ltiU8JiHhCzsNC6EpiWnMPFhJC5/ZC8dRP2To31N+13gIZJmevIzK9hCiM5p8ssMzPPw hVplYas4Ci6K3x+4EUKn+qI0M9a34RUWtWlpaarc918MFRaxh8leUNstl0mcSkTUomSJ EVFJd/BCe0gQEFEh4O0jxpgPiiGwTJmFOxHdp3TUUdCo/0Ib4lCRvFy/JLvFXFF7TsB9 EV31txlmM2CfzLYXDrzaG782EFPeoqvNYNB1ins4G3l4IfcryJbH5e2z3TgNLzuQUJBA bntw== X-Gm-Message-State: ACgBeo3xuu8iaZswEZO505WPRkbS6nk9MWtvKIbYGm41BZ1Z+ppU4KkS Gw9xVPNVX6HubuViLmxQ4GrtZw== X-Google-Smtp-Source: AA6agR4x6aHQtS3I+QxXgWppTmliap7/p0eVHDqcGs694rgyLrAfOZkhvKly3SpsF79ZmOff4RQKaA== X-Received: by 2002:a17:906:9c82:b0:6e1:1d6c:914c with SMTP id fj2-20020a1709069c8200b006e11d6c914cmr1616044ejc.769.1662466974878; Tue, 06 Sep 2022 05:22:54 -0700 (PDT) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 05/11] RISC-V: Adding T-Head CondMov instructions Date: Tue, 6 Sep 2022 14:22:37 +0200 Message-Id: <20220906122243.1243354-6-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220906122243.1243354-1-christoph.muellner@vrull.eu> References: <20220906122243.1243354-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=christoph.muellner@vrull.eu; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1662472062422100001 From: Christoph M=C3=BCllner This patch adds support for the T-Head CondMov instructions. The patch uses the T-Head specific decoder and translation. Signed-off-by: Christoph M=C3=BCllner --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 23 +++++++++++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 3 ++ target/riscv/xtheadcondmov.decode | 33 ++++++++++++++++++++++ 6 files changed, 62 insertions(+) create mode 100644 target/riscv/xtheadcondmov.decode diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d129a6112a..b7d6dbd28e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -924,6 +924,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), + DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, fal= se), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9e2b3d6f56..0b58b38335 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -444,6 +444,7 @@ struct RISCVCPUConfig { bool ext_xtheadbb; bool ext_xtheadbs; bool ext_xtheadcmo; + bool ext_xtheadcondmov; bool ext_xtheadsync; bool ext_XVentanaCondOps; =20 diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index b2d523b905..da3a538400 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -194,3 +194,26 @@ static bool trans_th_tst(DisasContext *ctx, arg_th_tst= *a) return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext); } =20 +static bool gen_th_condmove(DisasContext *ctx, arg_r *a, TCGCond cond) +{ + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); + + tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, dest); + + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +/* th.mveqz: "if (rs2 =3D=3D 0) rd =3D rs1;" */ +static bool trans_th_mveqz(DisasContext *ctx, arg_th_mveqz *a) +{ + return gen_th_condmove(ctx, a, TCG_COND_EQ); +} + +/* th.mvnez: "if (rs2 !=3D 0) rd =3D rs1;" */ +static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a) +{ + return gen_th_condmove(ctx, a, TCG_COND_NE); +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 5ee37683cb..496ae37f26 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -6,6 +6,7 @@ gen =3D [ decodetree.process('xtheadbb.decode', extra_args: '--static-decode=3Ddec= ode_xtheadbb'), decodetree.process('xtheadbs.decode', extra_args: '--static-decode=3Ddec= ode_xtheadbs'), decodetree.process('xtheadcmo.decode', extra_args: '--static-decode=3Dde= code_xtheadcmo'), + decodetree.process('xtheadcondmov.decode', extra_args: '--static-decode= =3Ddecode_xtheadcondmov'), decodetree.process('xtheadsync.decode', extra_args: '--static-decode=3Dd= ecode_xtheadsync'), decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decod= e=3Ddecode_XVentanaCodeOps'), ] diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f662e403f8..986243df99 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -136,6 +136,7 @@ MATERIALISE_EXT_PREDICATE(xtheadba) MATERIALISE_EXT_PREDICATE(xtheadbb) MATERIALISE_EXT_PREDICATE(xtheadbs) MATERIALISE_EXT_PREDICATE(xtheadcmo) +MATERIALISE_EXT_PREDICATE(xtheadcondmov); MATERIALISE_EXT_PREDICATE(xtheadsync) MATERIALISE_EXT_PREDICATE(XVentanaCondOps) =20 @@ -727,6 +728,7 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm) #include "decode-xtheadbb.c.inc" #include "decode-xtheadbs.c.inc" #include "decode-xtheadcmo.c.inc" +#include "decode-xtheadcondmov.c.inc" #include "decode-xtheadsync.c.inc" #include "decode-XVentanaCondOps.c.inc" =20 @@ -1052,6 +1054,7 @@ static void decode_opc(CPURISCVState *env, DisasConte= xt *ctx, uint16_t opcode) { has_xtheadbb_p, decode_xtheadbb }, { has_xtheadbs_p, decode_xtheadbs }, { has_xtheadcmo_p, decode_xtheadcmo }, + { has_xtheadcondmov_p, decode_xtheadcondmov }, { has_xtheadsync_p, decode_xtheadsync }, { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, }; diff --git a/target/riscv/xtheadcondmov.decode b/target/riscv/xtheadcondmov= .decode new file mode 100644 index 0000000000..00f9ca96c6 --- /dev/null +++ b/target/riscv/xtheadcondmov.decode @@ -0,0 +1,33 @@ +# +# RISC-V instruction decode for the XTheadCondMov extension +# +# Copyright (c) 2022 Dr. Philipp Tomsich, philipp.tomsich@vrull.eu +# Christoph Muellner, christoph.muellner@vrull.eu +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# The XTheadCondMov extension provides conditional move instructions. +# +# It is documented in +# https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.= 0.0/xthead-2022-09-05-2.0.0.pdf +# +# The instructions contained in XTheadCondMov are: +# - th.mveqz move to register, if condition is zero +# - th.mvnez move to register, if condition is non-zero +# +# These instructions reuse existing instruction formats. + +# Fields +%rs2 20:5 +%rs1 15:5 +%rd 7:5 + +# Argument sets +&r rd rs1 rs2 !extern + +# Formats: +@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd + +# T-Head conditional move instructions +th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r +th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r --=20 2.37.2 From nobody Tue May 21 10:51:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id d21-20020a170906305500b0073d6ab5bcaasm6479034ejd.212.2022.09.06.05.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 05:22:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=BkvWtveihlbHGzWrmOD3R7Q8EqBt46lT5/dQA1FAtlQ=; b=itrGn3CHAnOwnM0CrvxqPlJeWTHLwXPDrIfPgTXOImeSEFUH+BVVLAFktd8RtMIPpP Uawty9rJLz1YS5DaxBjka9aBpqtM47YW2w37aDuBQERr4+EOastPMj57V5oXjAOVgK9G mdE3gx9XPW1rzGXW9rnjP0LjZOt4Q8VnKQ344SXFBWgMKlwcSfBPDj2fTGzY3XWRa67V qn05eG18I4aPnMD2qBRhZOe+Ta/KQZt7WjmrWXwAC5kOnJrPnBGlPfySzQVtCc/1xXCU TeDRg6LNA0Fb+H7HB4LBDgPFExejcHw2aQMXwQng8Qq6pA3maG0qMRgcAcAeBPfC48eA ukNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=BkvWtveihlbHGzWrmOD3R7Q8EqBt46lT5/dQA1FAtlQ=; b=Jry7CC0NTe5iW0iG4nPvIskdGKEJbFEqOin2hguiyP6snxev5x3vMF4UJUz/DXjoki A77Q9Dj4W3xvYBgYyoEJiba0StAc0cbiJ7SUAcwEpP01/hr09bVsdXB854Ej8dUf8smj sID0Uv0cpJQCW5ZwCRqVeVUJEl9C4dDHn+cCPCvR1X340gCmrW8gULeATxefSQzrW2Tl heyGkpLK3wWpgTMXBllBMUo9kKLewVSfgCP/mti32wqN0rn2tpyKVfpEFDQroK6pCGHi xuQcYQ1PXDawPq+DXrwEQ8oUTaS0XApnj0ghHPtw6JNQ22Z1qKXKxA5gkWAy86tv680V Pw+Q== X-Gm-Message-State: ACgBeo3VQrJy0+p1tY71I3X87Ac7yF3tPEkmyjC0lVAgYgS5P43CK3tA CwBw2bZ624OjmxuhUVWAcAUuOA== X-Google-Smtp-Source: AA6agR4aSNfrI5CsoMZsK3LfAJd8nnfTfw8NV/RzXMbrY6coaX4wK25UayHNUC/cHa0T+6HZTs6RRQ== X-Received: by 2002:a17:906:eecb:b0:73c:5bcb:8eb3 with SMTP id wu11-20020a170906eecb00b0073c5bcb8eb3mr39295434ejb.284.1662466976299; Tue, 06 Sep 2022 05:22:56 -0700 (PDT) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 06/11] RISC-V: Adding T-Head multiply-accumulate instructions Date: Tue, 6 Sep 2022 14:22:38 +0200 Message-Id: <20220906122243.1243354-7-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220906122243.1243354-1-christoph.muellner@vrull.eu> References: <20220906122243.1243354-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=christoph.muellner@vrull.eu; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1662470893393100001 From: Christoph M=C3=BCllner This patch adds support for the T-Head MAC instructions. The patch uses the T-Head specific decoder and translation. Signed-off-by: Christoph M=C3=BCllner --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 67 ++++++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 3 + target/riscv/xtheadmac.decode | 30 ++++++++++ 6 files changed, 103 insertions(+) create mode 100644 target/riscv/xtheadmac.decode diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b7d6dbd28e..e2d74fa701 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -925,6 +925,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, fal= se), + DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0b58b38335..d0dc4ab031 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -445,6 +445,7 @@ struct RISCVCPUConfig { bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadcondmov; + bool ext_xtheadmac; bool ext_xtheadsync; bool ext_XVentanaCondOps; =20 diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index da3a538400..fc8307b113 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -217,3 +217,70 @@ static bool trans_th_mvnez(DisasContext *ctx, arg_th_m= veqz *a) { return gen_th_condmove(ctx, a, TCG_COND_NE); } + +static bool gen_th_mac(DisasContext *ctx, arg_r *a, + void (*accumulate_func)(TCGv, TCGv, TCGv), + void (*extend_operand_func)(TCGv, TCGv)) +{ + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv src0 =3D get_gpr(ctx, a->rd, EXT_NONE); + TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGv tmp =3D tcg_temp_new(); + + if (extend_operand_func) { + TCGv tmp2 =3D tcg_temp_new(); + extend_operand_func(tmp, src1); + extend_operand_func(tmp2, src2); + tcg_gen_mul_tl(tmp, tmp, tmp2); + tcg_temp_free(tmp2); + } else { + tcg_gen_mul_tl(tmp, src1, src2); + } + + accumulate_func(dest, src0, tmp); + gen_set_gpr(ctx, a->rd, dest); + tcg_temp_free(tmp); + + return true; +} + +/* th.mula: "rd =3D rd + rs1 * rs2" */ +static bool trans_th_mula(DisasContext *ctx, arg_th_mula *a) +{ + return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL); +} + +/* th.mulah: "rd =3D sext.w(rd + sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */ +static bool trans_th_mulah(DisasContext *ctx, arg_th_mulah *a) +{ + ctx->ol =3D MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_add_tl, tcg_gen_ext16s_tl); +} + +/* th.mulaw: "rd =3D sext.w(rd + rs1 * rs2)" */ +static bool trans_th_mulaw(DisasContext *ctx, arg_th_mulaw *a) +{ + ctx->ol =3D MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL); +} + +/* th.muls: "rd =3D rd - rs1 * rs2" */ +static bool trans_th_muls(DisasContext *ctx, arg_th_muls *a) +{ + return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); +} + +/* th.mulsh: "rd =3D sext.w(rd - sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */ +static bool trans_th_mulsh(DisasContext *ctx, arg_th_mulsh *a) +{ + ctx->ol =3D MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_sub_tl, tcg_gen_ext16s_tl); +} + +/* th.mulsw: "rd =3D sext.w(rd - rs1 * rs2)" */ +static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a) +{ + ctx->ol =3D MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 496ae37f26..55c019e55b 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -7,6 +7,7 @@ gen =3D [ decodetree.process('xtheadbs.decode', extra_args: '--static-decode=3Ddec= ode_xtheadbs'), decodetree.process('xtheadcmo.decode', extra_args: '--static-decode=3Dde= code_xtheadcmo'), decodetree.process('xtheadcondmov.decode', extra_args: '--static-decode= =3Ddecode_xtheadcondmov'), + decodetree.process('xtheadmac.decode', extra_args: '--static-decode=3Dde= code_xtheadmac'), decodetree.process('xtheadsync.decode', extra_args: '--static-decode=3Dd= ecode_xtheadsync'), decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decod= e=3Ddecode_XVentanaCodeOps'), ] diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 986243df99..56cc89ce4a 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -137,6 +137,7 @@ MATERIALISE_EXT_PREDICATE(xtheadbb) MATERIALISE_EXT_PREDICATE(xtheadbs) MATERIALISE_EXT_PREDICATE(xtheadcmo) MATERIALISE_EXT_PREDICATE(xtheadcondmov); +MATERIALISE_EXT_PREDICATE(xtheadmac); MATERIALISE_EXT_PREDICATE(xtheadsync) MATERIALISE_EXT_PREDICATE(XVentanaCondOps) =20 @@ -729,6 +730,7 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm) #include "decode-xtheadbs.c.inc" #include "decode-xtheadcmo.c.inc" #include "decode-xtheadcondmov.c.inc" +#include "decode-xtheadmac.c.inc" #include "decode-xtheadsync.c.inc" #include "decode-XVentanaCondOps.c.inc" =20 @@ -1055,6 +1057,7 @@ static void decode_opc(CPURISCVState *env, DisasConte= xt *ctx, uint16_t opcode) { has_xtheadbs_p, decode_xtheadbs }, { has_xtheadcmo_p, decode_xtheadcmo }, { has_xtheadcondmov_p, decode_xtheadcondmov }, + { has_xtheadmac_p, decode_xtheadmac }, { has_xtheadsync_p, decode_xtheadsync }, { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, }; diff --git a/target/riscv/xtheadmac.decode b/target/riscv/xtheadmac.decode new file mode 100644 index 0000000000..dda1f82334 --- /dev/null +++ b/target/riscv/xtheadmac.decode @@ -0,0 +1,30 @@ +# +# RISC-V instruction decode for the XTheadMac extension +# +# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# The XTheadMac extension provides multiply-accumulate instructions. +# +# It is documented in +# https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.= 0.0/xthead-2022-09-05-2.0.0.pdf + +# Fields +%rs2 20:5 +%rs1 15:5 +%rd 7:5 + +# Argument sets +&r rd rs1 rs2 !extern + +# Formats: +@r ..... .. ..... ..... ... ..... ....... &r %rs2 %rs1 %rd + +# T-Head conditional move instructions +th_mula 00100 00 ..... ..... 001 ..... 0001011 @r +th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r +th_mulaw 00100 10 ..... ..... 001 ..... 0001011 @r +th_muls 00100 01 ..... ..... 001 ..... 0001011 @r +th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r +th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r --=20 2.37.2 From nobody Tue May 21 10:51:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id d21-20020a170906305500b0073d6ab5bcaasm6479034ejd.212.2022.09.06.05.22.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 05:22:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=Le20JxDRtr5XtbLRfBRfEaLtfPuVmzxK2ChfnUtZSkQ=; b=PIc34vxWqWl7lveqj3YcQCT0GoH9aAwfJt/EtjHxVgp885tfxV4D1CkGz5XGii0r1x d2ZnwP0PXu9NzbwuTfjBSHLBayNNJPgf5alFLRBlUUUGuhaZmCTBuMW4wh/0GjkSXQOv lGK4QvF4D6YyDHYu/2d2CsBdM33AvrWIEd+f0AnfxgaJbyti7OAPE8tKCH/V4WZ5f5Vx s2riPSzojfGuXqVDi0IqqBHMY85Z3inLx4S4Xrw2QzDMeie0aYGd2RFBuQzroDsm1C2G TdC4U1SYsiMnhi7qar3zJ2tT7TDAUjVax4yAjLDkqurONRymLn42YWZu340adrLSph7g 3ILA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=Le20JxDRtr5XtbLRfBRfEaLtfPuVmzxK2ChfnUtZSkQ=; b=PDFaQ3eoMMxmRUe2D60oqSILoptLMj1B2/ywGzI0SOgt6HsytNPZi5Lz5qP1lqi8+I DYtisTCby1ZVF92XmypIGfbgA26/X/lwSjRUgNEf7B/+dI6Y5MuyWIq5OMw1hm/R6RP2 xjk1pjFFnuHgk8+XHOpk9PiaQP1cewliGbrMGMyZ/R6epaVxz8ReDb5YkwaMs3UvjNsW T0jdxpszc6N+OQVQUNXOax3O7A6mFJCbaQAtHvr1/BdcGtR46L9WA0vK4LxuLUfWsMcB fRm3DpLiEP1MPYQHA5gnppS7WQnKezt9eystvAQhcS6rVHaISTAQvkynowuRXBVATXWZ SBTQ== X-Gm-Message-State: ACgBeo2zZ3oaRoL8/cAZhl/X5VXIBPTuzOzdIjRsV/LmsKdnjIe2aoN2 Isl31dN61Hsi2RGwWMefnl0mcw== X-Google-Smtp-Source: AA6agR5sefmC3Ac4uUfEmzw3Uz7C8GY6aELHniAgnW0VxGOABA/rkzUg3Lp845eTNQSCztbU4c9YdA== X-Received: by 2002:aa7:cc05:0:b0:447:8654:7fa9 with SMTP id q5-20020aa7cc05000000b0044786547fa9mr46752376edt.298.1662466977647; Tue, 06 Sep 2022 05:22:57 -0700 (PDT) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 07/11] RISC-V: Adding T-Head XMAE support Date: Tue, 6 Sep 2022 14:22:39 +0200 Message-Id: <20220906122243.1243354-8-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220906122243.1243354-1-christoph.muellner@vrull.eu> References: <20220906122243.1243354-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=christoph.muellner@vrull.eu; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1662468333298100001 From: Christoph M=C3=BCllner This patch adds support for the T-Head specific extended memory attributes. Similar like Svpbmt, this support does not have much effect as most behaviour is not modelled in QEMU. We also don't set any EDATA information, because XMAE discovery is done using the vendor ID in the Linux kernel. Signed-off-by: Christoph M=C3=BCllner --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 6 ++++-- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e2d74fa701..990a1f57af 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -927,6 +927,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, fal= se), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), + DEFINE_PROP_BOOL("xtheadxmae", RISCVCPU, cfg.ext_xtheadxmae, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), =20 /* These are experimental so mark with 'x-' */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d0dc4ab031..1982d9293f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -447,6 +447,7 @@ struct RISCVCPUConfig { bool ext_xtheadcondmov; bool ext_xtheadmac; bool ext_xtheadsync; + bool ext_xtheadxmae; bool ext_XVentanaCondOps; =20 uint8_t pmu_num; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 59b3680b1b..d7941e64e1 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -927,7 +927,8 @@ restart: =20 if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { ppn =3D pte >> PTE_PPN_SHIFT; - } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) { + } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot || + cpu->cfg.ext_xtheadxmae) { ppn =3D (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; } else { ppn =3D pte >> PTE_PPN_SHIFT; @@ -939,7 +940,8 @@ restart: if (!(pte & PTE_V)) { /* Invalid PTE */ return TRANSLATE_FAIL; - } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) { + } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT) && + !cpu->cfg.ext_xtheadxmae) { return TRANSLATE_FAIL; } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { /* Inner PTE, continue walking */ --=20 2.37.2 From nobody Tue May 21 10:51:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1662471451; cv=none; d=zohomail.com; s=zohoarc; b=acgNgfCVLYdK/Mu9g2c1iwZQkJc09Pb6uNxArjbdrToZ6Nbty3VcuEjFg6Z8//Y6CceRSkuKlJ+eymdxpUUjpqtYIP+BziZGUbJ+q4jGrdkZOZAGqr8b18jRkkt2GpLdFe33oMEs/0fcmFqUkqbTQhYDS2LRUieqv2QrFAbWsPQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662471451; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HzcnmBZhlnyxyz+B0S5H5mHBZlHKlSltS0mBvmvwa5I=; b=g39G6S6akoT67uSDfFVypj8OCOdqZDcRfLnqoIHCziIHEPU1KaxYjx3MW6hOrugzxYLI/VUeFI5ceKjAqWaDR6urZEIpcLsM0OC90QTkhFMHqRFx6dGyRGu+SObtL1iAz0FRGFkXEY7KCfgcKagXJiarpDGVYaftaAphWWBNiFU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1662471451207630.1564385557875; Tue, 6 Sep 2022 06:37:31 -0700 (PDT) Received: from localhost ([::1]:46416 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oVYle-0004wC-2e for importer@patchew.org; Tue, 06 Sep 2022 09:37:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36876) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oVXbz-0005mB-5Q for qemu-devel@nongnu.org; Tue, 06 Sep 2022 08:23:29 -0400 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]:45932) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oVXba-0003tx-KO for qemu-devel@nongnu.org; Tue, 06 Sep 2022 08:23:26 -0400 Received: by mail-ej1-x631.google.com with SMTP id lx1so22769057ejb.12 for ; Tue, 06 Sep 2022 05:22:59 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id d21-20020a170906305500b0073d6ab5bcaasm6479034ejd.212.2022.09.06.05.22.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 05:22:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=HzcnmBZhlnyxyz+B0S5H5mHBZlHKlSltS0mBvmvwa5I=; b=qznkQ0PYEEXkpUnYral+U0lnkTVZcSxzx4iowY5pUJHacnWjzhnZHy7N6YMK4YCHML emz49Ef5DRdI0KMYqNXBrm9WYDhQeP6fOlZEUfcSeRpV1g79Y8yCCTeXl/6pmpZ2CKm2 ZO4LXV4HFnR2d2JAObJteZ1xVthwOEe5irzcYJl9lEbKNGrFEDDFArssyqIcLciHtC9I zWtsr+0DwK3PKdxjr3FOJ2dxRuiFeNcjSxOj4gQ5nNBZnEskACuYXQl30GOF9n9wxG4/ vfQUZM5lJbShjW7uYVCcDmRBhmjCvZAwGzGgS40Nelr24w6YFSiEAobzf0kySmQYEYCP 6JeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=HzcnmBZhlnyxyz+B0S5H5mHBZlHKlSltS0mBvmvwa5I=; b=EFdFbI5Y4cAy5qdla4WG2TJOcV3Gcih9O98N+CBEZ5Jex0DgtbLhvt1CH58OaAnIsh gVOWbKGeO5oNuUddwR5seKfIqHhxrXXHD1W54QTkrK9Ho+jMjoxmiIb+0UjbDNXOkP9/ uvUrZRVcAnqImIg3chwNizsll0sAispIfn8l5ll21BXyq1rZyi/zIw8Xz+TzkZYNpuqS /Ono/wi41xjjp5tX7MlXNdT9HfdYZtEYD9G1DVD8llF9rtVbG2u2kPQZEGqEYfhwDoCo 6oBb1kTKU+p/j9RBGPWrNWZzfoV23+b3hMEnPU88ZQBRG0f0OKrlRkXt8Jz2JSTh7eYR K9gA== X-Gm-Message-State: ACgBeo37hMCRMjT9te90gW4BPpvxzgajOWoUznyGP0SUZHCMyKFPS42s ETT5f27x4x35DBJ3gKlDDZxuAg== X-Google-Smtp-Source: AA6agR6M+Z1LArubZmJGKr8ZrnkDmYmoV9cnyFoks1aUBAeDfTcSlyXel8XD+B1GwrC/CxRKE0C/mA== X-Received: by 2002:a17:906:db05:b0:741:5730:270e with SMTP id xj5-20020a170906db0500b007415730270emr30999693ejb.609.1662466979098; Tue, 06 Sep 2022 05:22:59 -0700 (PDT) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 08/11] RISC-V: Adding T-Head MemPair extension Date: Tue, 6 Sep 2022 14:22:40 +0200 Message-Id: <20220906122243.1243354-9-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220906122243.1243354-1-christoph.muellner@vrull.eu> References: <20220906122243.1243354-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=christoph.muellner@vrull.eu; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1662471451805100001 From: Christoph M=C3=BCllner This patch adds support for the T-Head MemPair instructions. The patch uses the T-Head specific decoder and translation. Signed-off-by: Christoph M=C3=BCllner --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 90 ++++++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 3 + target/riscv/xtheadmempair.decode | 29 +++++++ 6 files changed, 125 insertions(+) create mode 100644 target/riscv/xtheadmempair.decode diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 990a1f57af..9370722ffa 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -926,6 +926,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, fal= se), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), + DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, fal= se), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xtheadxmae", RISCVCPU, cfg.ext_xtheadxmae, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1982d9293f..6cc2d19075 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -446,6 +446,7 @@ struct RISCVCPUConfig { bool ext_xtheadcmo; bool ext_xtheadcondmov; bool ext_xtheadmac; + bool ext_xtheadmempair; bool ext_xtheadsync; bool ext_xtheadxmae; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index fc8307b113..a2bae249fb 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -284,3 +284,93 @@ static bool trans_th_mulsw(DisasContext *ctx, arg_th_m= ulsw *a) ctx->ol =3D MXL_RV32; return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); } + +static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop, + int shamt) +{ + TCGv rd1 =3D dest_gpr(ctx, a->rd1); + TCGv rd2 =3D dest_gpr(ctx, a->rd2); + TCGv rs =3D get_gpr(ctx, a->rs, EXT_NONE); + TCGv addr1 =3D tcg_temp_new(); + TCGv addr2 =3D tcg_temp_new(); + + tcg_gen_movi_tl(addr1, a->sh2); + tcg_gen_shli_tl(addr1, addr1, shamt); + tcg_gen_add_tl(addr1, rs, addr1); + if ((memop & MO_SIZE) =3D=3D MO_64) { + tcg_gen_addi_tl(addr2, addr1, 8); + } else { + tcg_gen_addi_tl(addr2, addr1, 4); + } + + if (get_xl(ctx) =3D=3D MXL_RV32) { + tcg_gen_ext32u_tl(addr1, addr1); + tcg_gen_ext32u_tl(addr2, addr2); + } + + tcg_gen_qemu_ld_tl(rd1, addr1, ctx->mem_idx, memop); + tcg_gen_qemu_ld_tl(rd2, addr2, ctx->mem_idx, memop); + gen_set_gpr(ctx, a->rd1, rd1); + gen_set_gpr(ctx, a->rd2, rd2); + + tcg_temp_free(addr1); + tcg_temp_free(addr2); + return true; +} + +static bool trans_th_ldd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_64BIT(ctx); + return gen_loadpair_tl(ctx, a, MO_TESQ, 4); +} + +static bool trans_th_lwd(DisasContext *ctx, arg_th_pair *a) +{ + return gen_loadpair_tl(ctx, a, MO_TESL, 3); +} + +static bool trans_th_lwud(DisasContext *ctx, arg_th_pair *a) +{ + return gen_loadpair_tl(ctx, a, MO_TEUL, 3); +} + +static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memo= p, + int shamt) +{ + TCGv data1 =3D get_gpr(ctx, a->rd1, EXT_NONE); + TCGv data2 =3D get_gpr(ctx, a->rd2, EXT_NONE); + TCGv rs =3D get_gpr(ctx, a->rs, EXT_NONE); + TCGv addr1 =3D tcg_temp_new(); + TCGv addr2 =3D tcg_temp_new(); + + tcg_gen_movi_tl(addr1, a->sh2); + tcg_gen_shli_tl(addr1, addr1, shamt); + tcg_gen_add_tl(addr1, rs, addr1); + if ((memop & MO_SIZE) =3D=3D MO_64) { + tcg_gen_addi_tl(addr2, addr1, 8); + } else { + tcg_gen_addi_tl(addr2, addr1, 4); + } + + if (get_xl(ctx) =3D=3D MXL_RV32) { + tcg_gen_ext32u_tl(addr1, addr1); + tcg_gen_ext32u_tl(addr2, addr2); + } + + tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop); + tcg_gen_qemu_st_tl(data2, addr2, ctx->mem_idx, memop); + + tcg_temp_free(addr1); + tcg_temp_free(addr2); + return true; +} + +static bool trans_th_sdd(DisasContext *ctx, arg_th_pair *a) +{ + return gen_storepair_tl(ctx, a, MO_TESQ, 4); +} + +static bool trans_th_swd(DisasContext *ctx, arg_th_pair *a) +{ + return gen_storepair_tl(ctx, a, MO_TESL, 3); +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 55c019e55b..998f0ba336 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -8,6 +8,7 @@ gen =3D [ decodetree.process('xtheadcmo.decode', extra_args: '--static-decode=3Dde= code_xtheadcmo'), decodetree.process('xtheadcondmov.decode', extra_args: '--static-decode= =3Ddecode_xtheadcondmov'), decodetree.process('xtheadmac.decode', extra_args: '--static-decode=3Dde= code_xtheadmac'), + decodetree.process('xtheadmempair.decode', extra_args: '--static-decode= =3Ddecode_xtheadmempair'), decodetree.process('xtheadsync.decode', extra_args: '--static-decode=3Dd= ecode_xtheadsync'), decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decod= e=3Ddecode_XVentanaCodeOps'), ] diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 56cc89ce4a..308de419cb 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -138,6 +138,7 @@ MATERIALISE_EXT_PREDICATE(xtheadbs) MATERIALISE_EXT_PREDICATE(xtheadcmo) MATERIALISE_EXT_PREDICATE(xtheadcondmov); MATERIALISE_EXT_PREDICATE(xtheadmac); +MATERIALISE_EXT_PREDICATE(xtheadmempair); MATERIALISE_EXT_PREDICATE(xtheadsync) MATERIALISE_EXT_PREDICATE(XVentanaCondOps) =20 @@ -731,6 +732,7 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm) #include "decode-xtheadcmo.c.inc" #include "decode-xtheadcondmov.c.inc" #include "decode-xtheadmac.c.inc" +#include "decode-xtheadmempair.c.inc" #include "decode-xtheadsync.c.inc" #include "decode-XVentanaCondOps.c.inc" =20 @@ -1058,6 +1060,7 @@ static void decode_opc(CPURISCVState *env, DisasConte= xt *ctx, uint16_t opcode) { has_xtheadcmo_p, decode_xtheadcmo }, { has_xtheadcondmov_p, decode_xtheadcondmov }, { has_xtheadmac_p, decode_xtheadmac }, + { has_xtheadmempair_p, decode_xtheadmempair }, { has_xtheadsync_p, decode_xtheadsync }, { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, }; diff --git a/target/riscv/xtheadmempair.decode b/target/riscv/xtheadmempair= .decode new file mode 100644 index 0000000000..135dc10a59 --- /dev/null +++ b/target/riscv/xtheadmempair.decode @@ -0,0 +1,29 @@ +# +# RISC-V instruction decode for the XTheadMemPair extension +# +# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu +# +# SPDX-License-Identifier: LGPL-2.1-or-later + +# The XTheadMemPair extension provides two-GP-register operations. +# +# It is documented in +# https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.= 0.0/xthead-2022-09-05-2.0.0.pdf + +# Fields +%sh2 25:2 +%rd2 20:5 +%rs 15:5 +%rd1 7:5 + +# Argument sets +&th_pair rd1 rs rd2 sh2 + +# Formats: +@th_pair ..... .. ..... ..... ... ..... ....... &th_pair %rd1 %rs %rd2= %sh2 + +th_ldd 11111 .. ..... ..... 100 ..... 0001011 @th_pair +th_lwd 11100 .. ..... ..... 100 ..... 0001011 @th_pair +th_lwud 11110 .. ..... ..... 100 ..... 0001011 @th_pair +th_sdd 11111 .. ..... ..... 101 ..... 0001011 @th_pair +th_swd 11100 .. ..... ..... 101 ..... 0001011 @th_pair --=20 2.37.2 From nobody Tue May 21 10:51:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id d21-20020a170906305500b0073d6ab5bcaasm6479034ejd.212.2022.09.06.05.22.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 05:23:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=TdwaakR6p7hs8L+dX1B2H65CkrYYEFnR0eH2jeUCe3U=; b=DWxJDju0W8mFtTmmHH2skWFIS4BV+GtW09T8ueOEZalt7HA/TAiO+xx4hV2d6tfHR0 /xi23p2McQKweUz5tXhNpxnImClkwOAWGFQ+01J+AvuMIWrOL/i7eGhezpaXgieW0xyR CFduqiTnStXfbsYeRqu9m4JsocpPo3LMRiluompBmLDJxjQJ//AjU3mKDmxo1pdPrZ0p 1qsPkT1zBVKk12qsWolTDXDPs4hmAqUFKJr6YQnoB5zpspVK0Kq44avMb9LRDLuzHFo9 73xxXYkPxVDLKjPEr3p21HHzwqpUzXZxXW4eC5o3WPG7uU1i718xEykBhKMXzMYQETS7 HpWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=TdwaakR6p7hs8L+dX1B2H65CkrYYEFnR0eH2jeUCe3U=; b=CjXKZaaMB7TESxkP/gSvi3OQAc6M2mqZOksi6ql1Qd+/RfUR+ICGWGnbc1qNFUtAFT G8SLJVEqraeZn1b1qhOTSpxcljWTLHKXWxhpeKLbpzRtGc1pnOVhTEATk4HTR2xZ3Mnb k8NdpLbMu1KcZD7Mc8cECF9JQoVffdS0ha0kMhkwQwPXTdQ5MPlq5XvGMqFXrtmedIH6 HD93gf+nfanFGGCHE26rjl57oIm8Q2NMN011vc6bObvVWeJzjksxHocmeOQFiOI0oN4C EVe+wP2SWw/EqTT7wfMgiml2+5dCcwf0NMflHYtqPOOSCdogKMQCwJ44VMRtXfJJ7ndU ijhA== X-Gm-Message-State: ACgBeo3t+N+kFLblL/kinVfZk25DnemdlgjRIlYwHtKjM7an37x+aEcM +urjfWPgXX3gc+B9mRoXSv/XrQ== X-Google-Smtp-Source: AA6agR4nLJfpE9ql16tHOKxWcEf5+vWxzBy9ngspSI0+RnbeWO1tBFukTQsLPoFLL5UDanZP0DH5gw== X-Received: by 2002:a17:906:4fd2:b0:742:133b:3522 with SMTP id i18-20020a1709064fd200b00742133b3522mr26106485ejw.21.1662466980544; Tue, 06 Sep 2022 05:23:00 -0700 (PDT) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 09/11] RISC-V: Adding T-Head MemIdx extension Date: Tue, 6 Sep 2022 14:22:41 +0200 Message-Id: <20220906122243.1243354-10-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220906122243.1243354-1-christoph.muellner@vrull.eu> References: <20220906122243.1243354-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=christoph.muellner@vrull.eu; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1662471135580100003 From: Christoph M=C3=BCllner This patch adds support for the T-Head MemIdx instructions. The patch uses the T-Head specific decoder and translation. Signed-off-by: Christoph M=C3=BCllner --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 377 +++++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 3 + target/riscv/xtheadmemidx.decode | 73 ++++ 6 files changed, 456 insertions(+) create mode 100644 target/riscv/xtheadmemidx.decode diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9370722ffa..0af9cc7bec 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -926,6 +926,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, fal= se), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), + DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false= ), DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, fal= se), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xtheadxmae", RISCVCPU, cfg.ext_xtheadxmae, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6cc2d19075..590a597f39 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -446,6 +446,7 @@ struct RISCVCPUConfig { bool ext_xtheadcmo; bool ext_xtheadcondmov; bool ext_xtheadmac; + bool ext_xtheadmemidx; bool ext_xtheadmempair; bool ext_xtheadsync; bool ext_xtheadxmae; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index a2bae249fb..95c6b10d77 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -374,3 +374,380 @@ static bool trans_th_swd(DisasContext *ctx, arg_th_pa= ir *a) { return gen_storepair_tl(ctx, a, MO_TESL, 3); } + +/* + * Load with memop from indexed address and add sext(imm5 << imm2) to rs1. + * If !preinc, then the address is rs1. + * If preinc, then the address is rs1 + (sext(imm5) << imm2). + */ +static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop, + bool preinc) +{ + TCGv rd =3D dest_gpr(ctx, a->rd); + TCGv base =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv addr =3D tcg_temp_new(); + TCGv offs =3D tcg_temp_new(); + + tcg_gen_movi_tl(offs, a->imm5); + tcg_gen_sextract_tl(offs, offs, 0, 5); + tcg_gen_shli_tl(offs, offs, a->imm2); + + if (preinc) { + tcg_gen_add_tl(addr, base, offs); + if (get_xl(ctx) =3D=3D MXL_RV32) { + tcg_gen_ext32u_tl(addr, addr); + } + } else { + tcg_gen_mov_tl(addr, base); + } + + tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); + + if (!preinc) { + tcg_gen_add_tl(addr, base, offs); + if (get_xl(ctx) =3D=3D MXL_RV32) { + tcg_gen_ext32u_tl(addr, addr); + } + } + + gen_set_gpr(ctx, a->rd, rd); + gen_set_gpr(ctx, a->rs1, addr); + + tcg_temp_free(addr); + tcg_temp_free(offs); + return true; +} + +/* + * Store with memop to indexed address and add sext(imm5 << imm2) to rs1. + * If !preinc, then the address is rs1. + * If preinc, then the address is rs1 + (sext(imm5) << imm2). + */ +static bool gen_store_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop, + bool preinc) +{ + TCGv data =3D get_gpr(ctx, a->rd, EXT_NONE); + TCGv base =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv addr =3D tcg_temp_new(); + TCGv offs =3D tcg_temp_new(); + + tcg_gen_movi_tl(offs, a->imm5); + tcg_gen_sextract_tl(offs, offs, 0, 5); + tcg_gen_shli_tl(offs, offs, a->imm2); + + if (preinc) { + tcg_gen_add_tl(addr, base, offs); + if (get_xl(ctx) =3D=3D MXL_RV32) { + tcg_gen_ext32u_tl(addr, addr); + } + } else { + tcg_gen_mov_tl(addr, base); + } + + tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); + + if (!preinc) { + tcg_gen_add_tl(addr, base, offs); + if (get_xl(ctx) =3D=3D MXL_RV32) { + tcg_gen_ext32u_tl(addr, addr); + } + } + + gen_set_gpr(ctx, a->rs1, addr); + + tcg_temp_free(addr); + tcg_temp_free(offs); + return true; +} + +static bool trans_th_ldia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TESQ, false); +} + +static bool trans_th_ldib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TESQ, true); +} + +static bool trans_th_lwia(DisasContext *ctx, arg_th_meminc *a) +{ + return gen_load_inc(ctx, a, MO_TESL, false); +} + +static bool trans_th_lwib(DisasContext *ctx, arg_th_meminc *a) +{ + return gen_load_inc(ctx, a, MO_TESL, true); +} + +static bool trans_th_lwuia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TEUL, false); +} + +static bool trans_th_lwuib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TEUL, true); +} + +static bool trans_th_lhia(DisasContext *ctx, arg_th_meminc *a) +{ + return gen_load_inc(ctx, a, MO_TESW, false); +} + +static bool trans_th_lhib(DisasContext *ctx, arg_th_meminc *a) +{ + return gen_load_inc(ctx, a, MO_TESW, true); +} + +static bool trans_th_lhuia(DisasContext *ctx, arg_th_meminc *a) +{ + return gen_load_inc(ctx, a, MO_TEUW, false); +} + +static bool trans_th_lhuib(DisasContext *ctx, arg_th_meminc *a) +{ + return gen_load_inc(ctx, a, MO_TEUW, true); +} + +static bool trans_th_lbia(DisasContext *ctx, arg_th_meminc *a) +{ + return gen_load_inc(ctx, a, MO_SB, false); +} + +static bool trans_th_lbib(DisasContext *ctx, arg_th_meminc *a) +{ + return gen_load_inc(ctx, a, MO_SB, true); +} + +static bool trans_th_lbuia(DisasContext *ctx, arg_th_meminc *a) +{ + return gen_load_inc(ctx, a, MO_UB, false); +} + +static bool trans_th_lbuib(DisasContext *ctx, arg_th_meminc *a) +{ + return gen_load_inc(ctx, a, MO_UB, true); +} + +static bool trans_th_sdia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_64BIT(ctx); + return gen_store_inc(ctx, a, MO_TESQ, false); +} + +static bool trans_th_sdib(DisasContext *ctx, arg_th_meminc *a) +{ + return gen_store_inc(ctx, a, MO_TESQ, true); +} + +static bool trans_th_swia(DisasContext *ctx, arg_th_meminc *a) +{ + return gen_store_inc(ctx, a, MO_TESL, false); +} + +static bool trans_th_swib(DisasContext *ctx, arg_th_meminc *a) +{ + return gen_store_inc(ctx, a, MO_TESL, true); +} + +static bool trans_th_shia(DisasContext *ctx, arg_th_meminc *a) +{ + return gen_store_inc(ctx, a, MO_TESW, false); +} + +static bool trans_th_shib(DisasContext *ctx, arg_th_meminc *a) +{ + return gen_store_inc(ctx, a, MO_TESW, true); +} + +static bool trans_th_sbia(DisasContext *ctx, arg_th_meminc *a) +{ + return gen_store_inc(ctx, a, MO_SB, false); +} + +static bool trans_th_sbib(DisasContext *ctx, arg_th_meminc *a) +{ + return gen_store_inc(ctx, a, MO_SB, true); +} + +/* + * Load with memop from indexed address. + * If !zero_extend_offset, then address is rs1 + (rs2 << imm2). + * If zero_extend_offset, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_load_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop, + bool zero_extend_offset) +{ + TCGv rd =3D dest_gpr(ctx, a->rd); + TCGv base =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv offs =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGv addr =3D tcg_temp_new(); + + if (zero_extend_offset) { + tcg_gen_extract_tl(addr, offs, 0, 32); + } else { + tcg_gen_mov_tl(addr, offs); + } + tcg_gen_shli_tl(addr, addr, a->imm2); + tcg_gen_add_tl(addr, base, addr); + + if (get_xl(ctx) =3D=3D MXL_RV32) { + tcg_gen_ext32u_tl(addr, addr); + } + + tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); + gen_set_gpr(ctx, a->rd, rd); + + tcg_temp_free(addr); + return true; +} + +/* + * Store with memop to indexed address. + * If !zero_extend_offset, then address is rs1 + (rs2 << imm2). + * If zero_extend_offset, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_store_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop, + bool zero_extend_offset) +{ + TCGv data =3D get_gpr(ctx, a->rd, EXT_NONE); + TCGv base =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv offs =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGv addr =3D tcg_temp_new(); + + if (zero_extend_offset) { + tcg_gen_extract_tl(addr, offs, 0, 32); + } else { + tcg_gen_mov_tl(addr, offs); + } + tcg_gen_shli_tl(addr, addr, a->imm2); + tcg_gen_add_tl(addr, base, addr); + + if (get_xl(ctx) =3D=3D MXL_RV32) { + tcg_gen_ext32u_tl(addr, addr); + } + + tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); + + tcg_temp_free(addr); + return true; +} + +static bool trans_th_lrd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TESQ, false); +} + +static bool trans_th_lrw(DisasContext *ctx, arg_th_memidx *a) +{ + return gen_load_idx(ctx, a, MO_TESL, false); +} + +static bool trans_th_lrwu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TEUL, false); +} + +static bool trans_th_lrh(DisasContext *ctx, arg_th_memidx *a) +{ + return gen_load_idx(ctx, a, MO_TESW, false); +} + +static bool trans_th_lrhu(DisasContext *ctx, arg_th_memidx *a) +{ + return gen_load_idx(ctx, a, MO_TEUW, false); +} + +static bool trans_th_lrb(DisasContext *ctx, arg_th_memidx *a) +{ + return gen_load_idx(ctx, a, MO_SB, false); +} + +static bool trans_th_lrbu(DisasContext *ctx, arg_th_memidx *a) +{ + return gen_load_idx(ctx, a, MO_UB, false); +} + +static bool trans_th_srd(DisasContext *ctx, arg_th_memidx *a) +{ + return gen_store_idx(ctx, a, MO_TESQ, false); +} + +static bool trans_th_srw(DisasContext *ctx, arg_th_memidx *a) +{ + return gen_store_idx(ctx, a, MO_TESL, false); +} + +static bool trans_th_srh(DisasContext *ctx, arg_th_memidx *a) +{ + return gen_store_idx(ctx, a, MO_TESW, false); +} + +static bool trans_th_srb(DisasContext *ctx, arg_th_memidx *a) +{ + return gen_store_idx(ctx, a, MO_SB, false); +} +static bool trans_th_lurd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TESQ, true); +} + +static bool trans_th_lurw(DisasContext *ctx, arg_th_memidx *a) +{ + return gen_load_idx(ctx, a, MO_TESL, true); +} + +static bool trans_th_lurwu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TEUL, true); +} + +static bool trans_th_lurh(DisasContext *ctx, arg_th_memidx *a) +{ + return gen_load_idx(ctx, a, MO_TESW, true); +} + +static bool trans_th_lurhu(DisasContext *ctx, arg_th_memidx *a) +{ + return gen_load_idx(ctx, a, MO_TEUW, true); +} + +static bool trans_th_lurb(DisasContext *ctx, arg_th_memidx *a) +{ + return gen_load_idx(ctx, a, MO_SB, true); +} + +static bool trans_th_lurbu(DisasContext *ctx, arg_th_memidx *a) +{ + return gen_load_idx(ctx, a, MO_UB, true); +} + +static bool trans_th_surd(DisasContext *ctx, arg_th_memidx *a) +{ + return gen_store_idx(ctx, a, MO_TESQ, true); +} + +static bool trans_th_surw(DisasContext *ctx, arg_th_memidx *a) +{ + return gen_store_idx(ctx, a, MO_TESL, true); +} + +static bool trans_th_surh(DisasContext *ctx, arg_th_memidx *a) +{ + return gen_store_idx(ctx, a, MO_TESW, true); +} + +static bool trans_th_surb(DisasContext *ctx, arg_th_memidx *a) +{ + return gen_store_idx(ctx, a, MO_SB, true); +} + diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 998f0ba336..30bb4c5bab 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -8,6 +8,7 @@ gen =3D [ decodetree.process('xtheadcmo.decode', extra_args: '--static-decode=3Dde= code_xtheadcmo'), decodetree.process('xtheadcondmov.decode', extra_args: '--static-decode= =3Ddecode_xtheadcondmov'), decodetree.process('xtheadmac.decode', extra_args: '--static-decode=3Dde= code_xtheadmac'), + decodetree.process('xtheadmemidx.decode', extra_args: '--static-decode= =3Ddecode_xtheadmemidx'), decodetree.process('xtheadmempair.decode', extra_args: '--static-decode= =3Ddecode_xtheadmempair'), decodetree.process('xtheadsync.decode', extra_args: '--static-decode=3Dd= ecode_xtheadsync'), decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decod= e=3Ddecode_XVentanaCodeOps'), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 308de419cb..1cb0d885b8 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -138,6 +138,7 @@ MATERIALISE_EXT_PREDICATE(xtheadbs) MATERIALISE_EXT_PREDICATE(xtheadcmo) MATERIALISE_EXT_PREDICATE(xtheadcondmov); MATERIALISE_EXT_PREDICATE(xtheadmac); +MATERIALISE_EXT_PREDICATE(xtheadmemidx); MATERIALISE_EXT_PREDICATE(xtheadmempair); MATERIALISE_EXT_PREDICATE(xtheadsync) MATERIALISE_EXT_PREDICATE(XVentanaCondOps) @@ -732,6 +733,7 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm) #include "decode-xtheadcmo.c.inc" #include "decode-xtheadcondmov.c.inc" #include "decode-xtheadmac.c.inc" +#include "decode-xtheadmemidx.c.inc" #include "decode-xtheadmempair.c.inc" #include "decode-xtheadsync.c.inc" #include "decode-XVentanaCondOps.c.inc" @@ -1060,6 +1062,7 @@ static void decode_opc(CPURISCVState *env, DisasConte= xt *ctx, uint16_t opcode) { has_xtheadcmo_p, decode_xtheadcmo }, { has_xtheadcondmov_p, decode_xtheadcondmov }, { has_xtheadmac_p, decode_xtheadmac }, + { has_xtheadmemidx_p, decode_xtheadmemidx }, { has_xtheadmempair_p, decode_xtheadmempair }, { has_xtheadsync_p, decode_xtheadsync }, { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, diff --git a/target/riscv/xtheadmemidx.decode b/target/riscv/xtheadmemidx.d= ecode new file mode 100644 index 0000000000..d2e0f2af6f --- /dev/null +++ b/target/riscv/xtheadmemidx.decode @@ -0,0 +1,73 @@ +# +# RISC-V instruction decode for the XTheadMemIdx extension +# +# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# The XTheadMemIdx extension provides GPR memory operations. +# +# It is documented in +# https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.= 0.0/xthead-2022-09-05-2.0.0.pdf + +# Fields +%imm2 25:2 +%imm5 20:5 +%rs2 20:5 +%rs1 15:5 +%rd 7:5 + +# Argument sets +&th_meminc rd rs1 imm5 imm2 +&th_memidx rd rs1 rs2 imm2 + +# Formats: +@th_meminc ..... .. ..... ..... ... ..... ....... &th_meminc %rd %rs1 %i= mm5 %imm2 +@th_memidx ..... .. ..... ..... ... ..... ....... &th_memidx %rd %rs1 %r= s2 %imm2 + +th_ldia 01111 .. ..... ..... 100 ..... 0001011 @th_meminc +th_ldib 01101 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwia 01011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwib 01001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwuia 11011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwuib 11001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhia 00111 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhib 00101 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhuia 10111 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhuib 10101 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbia 00011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbib 00001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbuia 10011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbuib 10001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_sdia 01111 .. ..... ..... 101 ..... 0001011 @th_meminc +th_sdib 01101 .. ..... ..... 101 ..... 0001011 @th_meminc +th_swia 01011 .. ..... ..... 101 ..... 0001011 @th_meminc +th_swib 01001 .. ..... ..... 101 ..... 0001011 @th_meminc +th_shia 00111 .. ..... ..... 101 ..... 0001011 @th_meminc +th_shib 00101 .. ..... ..... 101 ..... 0001011 @th_meminc +th_sbia 00011 .. ..... ..... 101 ..... 0001011 @th_meminc +th_sbib 00001 .. ..... ..... 101 ..... 0001011 @th_meminc + +th_lrd 01100 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrw 01000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrwu 11000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrh 00100 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrhu 10100 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrb 00000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrbu 10000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_srd 01100 .. ..... ..... 101 ..... 0001011 @th_memidx +th_srw 01000 .. ..... ..... 101 ..... 0001011 @th_memidx +th_srh 00100 .. ..... ..... 101 ..... 0001011 @th_memidx +th_srb 00000 .. ..... ..... 101 ..... 0001011 @th_memidx + +th_lurd 01110 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurw 01010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurwu 11010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurh 00110 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurhu 10110 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurb 00010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurbu 10010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_surd 01110 .. ..... ..... 101 ..... 0001011 @th_memidx +th_surw 01010 .. ..... ..... 101 ..... 0001011 @th_memidx +th_surh 00110 .. ..... ..... 101 ..... 0001011 @th_memidx +th_surb 00010 .. ..... ..... 101 ..... 0001011 @th_memidx --=20 2.37.2 From nobody Tue May 21 10:51:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id d21-20020a170906305500b0073d6ab5bcaasm6479034ejd.212.2022.09.06.05.23.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 05:23:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=Yxbn8wlTHy7WglFSTrfT8DPtvWoSWM35aNvlLv9OrwI=; b=cMwc7DleCp1rKbjpPNfYfreGHZ6R1S65VSSYFEPzkBENf2QK2soXnOvc087rispmxa rfWuwyDEL+dXkujjIN0VhdM2YWaOd+xxLLKNrhgvCnUBo8obJOE6aWO+y+2AHCpV0Yy1 CjdzA7T7iCthdRY9uU7KxpB0x1tp1iV2a2kX/jF/b0kud9ABKtLB6kRPjWLKEf0BZwP3 IZ5mDo3fPT7SfogNkrEKLk3pxJOrapldF7p49R2aM+05o9Erkibdokti74sHaOui/yxd pA6zACMk+0UdXfvKe5j03KWcKPeq2MxStyPDc3oKsWO98yLPA/VrgMjIP+IY5uNmHu7b 7ntg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=Yxbn8wlTHy7WglFSTrfT8DPtvWoSWM35aNvlLv9OrwI=; b=ov3LrSg/wSdp6epLT7Ze9++Gl/S16W8Jstb3KHA6yM/LpDpEod4oWJ1F3iHrEovN+V 2GD1E9I7ZhnQTetPXDYL1WTehyu63noKPqJQcQX3Ng1ilAElHPuihbMFA7B3SU7f5VEG fWDttG59pn56s4a9NPb2h+QnVK7CJtM/Wl7psv1psNA0mL2HNa52Zx3RZkL9buoLnODK SsfJU0+GxCB+EAqMhMbu6EH4B7A1KlmC857Itbxz66tR/D1V6pAkHBATFta5Z2RWjcqm kjzOkHa9ZnnBlqKXFw/6xAbMz/TieYoLsV0mQMlYAT8R5b2bLHGstb66DWtDqUelt87n NZCA== X-Gm-Message-State: ACgBeo1+i3KZ/y3Equp/VrWzB17PobH3n2TEZPLRCi/r9wuFshrLKaM6 rsZFATSiq775YzeQ0bGpwBNUdQ== X-Google-Smtp-Source: AA6agR6Z0J1ZC6tGBDR0oClHYFURkIKD4ZWZB69yVcoxPbpycFEGmjJz1IcNz7B9X0JnupW+ogPX+Q== X-Received: by 2002:a05:6402:493:b0:445:b5f0:7a0f with SMTP id k19-20020a056402049300b00445b5f07a0fmr46914092edv.120.1662466982099; Tue, 06 Sep 2022 05:23:02 -0700 (PDT) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 10/11] RISC-V: Adding T-Head FMemIdx extension Date: Tue, 6 Sep 2022 14:22:42 +0200 Message-Id: <20220906122243.1243354-11-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220906122243.1243354-1-christoph.muellner@vrull.eu> References: <20220906122243.1243354-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=christoph.muellner@vrull.eu; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1662472343081100001 From: Christoph M=C3=BCllner This patch adds support for the T-Head FMemIdx instructions. The patch uses the T-Head specific decoder and translation. Signed-off-by: Christoph M=C3=BCllner --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 121 +++++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 3 + target/riscv/xtheadfmemidx.decode | 34 ++++++ 6 files changed, 161 insertions(+) create mode 100644 target/riscv/xtheadfmemidx.decode diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0af9cc7bec..01d85f0f96 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -925,6 +925,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, fal= se), + DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, fal= se), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false= ), DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, fal= se), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 590a597f39..8b02f530a6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -445,6 +445,7 @@ struct RISCVCPUConfig { bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadcondmov; + bool ext_xtheadfmemidx; bool ext_xtheadmac; bool ext_xtheadmemidx; bool ext_xtheadmempair; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index 95c6b10d77..1a91371318 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -751,3 +751,124 @@ static bool trans_th_surb(DisasContext *ctx, arg_th_m= emidx *a) return gen_store_idx(ctx, a, MO_SB, true); } =20 +/* + * Load 64-bit float from indexed address. + * If !zero_extend_offset, then address is rs1 + (rs2 << imm2). + * If zero_extend_offset, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_fload_idx(DisasContext *ctx, arg_th_fmemidx *a, MemOp memo= p, + bool zero_extend_offset) +{ + TCGv_i64 rd =3D cpu_fpr[a->rd]; + TCGv base =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv offs =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGv addr =3D tcg_temp_new(); + + if (zero_extend_offset) { + tcg_gen_extract_tl(addr, offs, 0, 32); + } else { + tcg_gen_mov_tl(addr, offs); + } + tcg_gen_shli_tl(addr, addr, a->imm2); + tcg_gen_add_tl(addr, base, addr); + + if (get_xl(ctx) =3D=3D MXL_RV32) { + tcg_gen_ext32u_tl(addr, addr); + } + + tcg_gen_qemu_ld_i64(rd, addr, ctx->mem_idx, memop); + if ((memop & MO_SIZE) =3D=3D MO_32) { + gen_nanbox_s(rd, rd); + } + + mark_fs_dirty(ctx); + tcg_temp_free(addr); + return true; +} + +/* + * Store 64-bit float to indexed address. + * If !zero_extend_offset, then address is rs1 + (rs2 << imm2). + * If zero_extend_offset, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_fstore_idx(DisasContext *ctx, arg_th_fmemidx *a, MemOp mem= op, + bool zero_extend_offset) +{ + TCGv_i64 rd =3D cpu_fpr[a->rd]; + TCGv base =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv offs =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGv addr =3D tcg_temp_new(); + + if (zero_extend_offset) { + tcg_gen_extract_tl(addr, offs, 0, 32); + } else { + tcg_gen_mov_tl(addr, offs); + } + tcg_gen_shli_tl(addr, addr, a->imm2); + tcg_gen_add_tl(addr, base, addr); + + if (get_xl(ctx) =3D=3D MXL_RV32) { + tcg_gen_ext32u_tl(addr, addr); + } + + tcg_gen_qemu_st_i64(rd, addr, ctx->mem_idx, memop); + + tcg_temp_free(addr); + return true; +} + +static bool trans_th_flrd(DisasContext *ctx, arg_th_fmemidx *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fload_idx(ctx, a, MO_TEUQ, false); +} + +static bool trans_th_flrw(DisasContext *ctx, arg_th_fmemidx *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fload_idx(ctx, a, MO_TEUL, false); +} + +static bool trans_th_flurd(DisasContext *ctx, arg_th_fmemidx *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fload_idx(ctx, a, MO_TEUQ, true); +} + +static bool trans_th_flurw(DisasContext *ctx, arg_th_fmemidx *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fload_idx(ctx, a, MO_TEUL, true); +} + +static bool trans_th_fsrd(DisasContext *ctx, arg_th_fmemidx *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fstore_idx(ctx, a, MO_TEUQ, false); +} + +static bool trans_th_fsrw(DisasContext *ctx, arg_th_fmemidx *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fstore_idx(ctx, a, MO_TEUL, false); +} + +static bool trans_th_fsurd(DisasContext *ctx, arg_th_fmemidx *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fstore_idx(ctx, a, MO_TEUQ, true); +} + +static bool trans_th_fsurw(DisasContext *ctx, arg_th_fmemidx *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fstore_idx(ctx, a, MO_TEUL, true); +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 30bb4c5bab..81175b67ce 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -7,6 +7,7 @@ gen =3D [ decodetree.process('xtheadbs.decode', extra_args: '--static-decode=3Ddec= ode_xtheadbs'), decodetree.process('xtheadcmo.decode', extra_args: '--static-decode=3Dde= code_xtheadcmo'), decodetree.process('xtheadcondmov.decode', extra_args: '--static-decode= =3Ddecode_xtheadcondmov'), + decodetree.process('xtheadfmemidx.decode', extra_args: '--static-decode= =3Ddecode_xtheadfmemidx'), decodetree.process('xtheadmac.decode', extra_args: '--static-decode=3Dde= code_xtheadmac'), decodetree.process('xtheadmemidx.decode', extra_args: '--static-decode= =3Ddecode_xtheadmemidx'), decodetree.process('xtheadmempair.decode', extra_args: '--static-decode= =3Ddecode_xtheadmempair'), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1cb0d885b8..915ac11d3b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -137,6 +137,7 @@ MATERIALISE_EXT_PREDICATE(xtheadbb) MATERIALISE_EXT_PREDICATE(xtheadbs) MATERIALISE_EXT_PREDICATE(xtheadcmo) MATERIALISE_EXT_PREDICATE(xtheadcondmov); +MATERIALISE_EXT_PREDICATE(xtheadfmemidx); MATERIALISE_EXT_PREDICATE(xtheadmac); MATERIALISE_EXT_PREDICATE(xtheadmemidx); MATERIALISE_EXT_PREDICATE(xtheadmempair); @@ -732,6 +733,7 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm) #include "decode-xtheadbs.c.inc" #include "decode-xtheadcmo.c.inc" #include "decode-xtheadcondmov.c.inc" +#include "decode-xtheadfmemidx.c.inc" #include "decode-xtheadmac.c.inc" #include "decode-xtheadmemidx.c.inc" #include "decode-xtheadmempair.c.inc" @@ -1061,6 +1063,7 @@ static void decode_opc(CPURISCVState *env, DisasConte= xt *ctx, uint16_t opcode) { has_xtheadbs_p, decode_xtheadbs }, { has_xtheadcmo_p, decode_xtheadcmo }, { has_xtheadcondmov_p, decode_xtheadcondmov }, + { has_xtheadfmemidx_p, decode_xtheadfmemidx }, { has_xtheadmac_p, decode_xtheadmac }, { has_xtheadmemidx_p, decode_xtheadmemidx }, { has_xtheadmempair_p, decode_xtheadmempair }, diff --git a/target/riscv/xtheadfmemidx.decode b/target/riscv/xtheadfmemidx= .decode new file mode 100644 index 0000000000..43e0f80df8 --- /dev/null +++ b/target/riscv/xtheadfmemidx.decode @@ -0,0 +1,34 @@ +# +# RISC-V instruction decode for the XTheadMemIdx extension +# +# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# The XTheadFMemIdx extension provides floating-point memory operations. +# +# It is documented in +# https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.= 0.0/xthead-2022-09-05-2.0.0.pdf + +# Fields +%imm2 25:2 +%rs2 20:5 +%rs1 15:5 +%rd 7:5 + +# Argument sets +&th_fmemidx rd rs1 rs2 imm2 + +# Formats +@th_fmemidx ..... .. ..... ..... ... ..... ....... &th_fmemidx %rd %rs1 %r= s2 %imm2 + +# Instructions +th_flrd 01100 .. ..... ..... 110 ..... 0001011 @th_fmemidx +th_flrw 01000 .. ..... ..... 110 ..... 0001011 @th_fmemidx +th_flurd 01110 .. ..... ..... 110 ..... 0001011 @th_fmemidx +th_flurw 01010 .. ..... ..... 110 ..... 0001011 @th_fmemidx + +th_fsrd 01100 .. ..... ..... 111 ..... 0001011 @th_fmemidx +th_fsrw 01000 .. ..... ..... 111 ..... 0001011 @th_fmemidx +th_fsurd 01110 .. ..... ..... 111 ..... 0001011 @th_fmemidx +th_fsurw 01010 .. ..... ..... 111 ..... 0001011 @th_fmemidx --=20 2.37.2 From nobody Tue May 21 10:51:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id d21-20020a170906305500b0073d6ab5bcaasm6479034ejd.212.2022.09.06.05.23.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 05:23:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=MSeHrtZy6/z9aLfg15MifS4M5qZYg4KlFPrRIZ3XZf0=; b=MIoQYfvSWNdemt6ycKWCb67ELSovsbkwArvYG4tXkGuGSxoqJRYws3p5Rb33fG4RJ9 gaN2MuaUix/YhgkGEPHjAYgiCH8vvL1L5rpDOQWOkwuZx7oc/51bgRAGylF/BZHM9R8U /0uVPgYW7D85IlRhRNLGjGAos5TNtZ26tUxb/9ieAZJi9JQwInjv14Wd0zOUWHP6TVpr SrZdYKgsRUB0rPGTnMzuwfsMJFYNwgcLCU9x/36ajpk3UsZZDSN8j4wmdSOXyVP9jFmL tdAs15pOlpGqE6TnoXh/c9aleVETXuANhs7yZ9kVTP5eeRfw8eU5BGlv+8Z9eJNfdKAp scZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=MSeHrtZy6/z9aLfg15MifS4M5qZYg4KlFPrRIZ3XZf0=; b=1uNX29XuPqJJT5/sKTXIdwvMih7jefYKdxn7eG775TolxqqYCMbfHF0gLwreh4qYon d60YHkFphCuOAFgz64IXxAtCsZ2YAwOlHf2CGg+tUG95FJp15ECLBbxl2+BShbaFbuM+ aZsaSgI2eaKuWPcsI6RMyoRt5aqmJ9W1hTZoUmQSNNGNj3zvIfGtGC8+mM6j+qrzlNA9 k64DzaxofYAH4uqTX8SvokBHm9PbU2RV0jgeHqVPIaoGvvMTiD+ljxmJklz1xNHiFGsi pqWT05pJkkcmESAPgMNaGpKIzrqyIITAgg0wegbUwwWBREAWmiKIb+S5vrSVwaJTkqs6 Ebtg== X-Gm-Message-State: ACgBeo1VgZmzcs3rx5HgQrErfdcHWoJXzrpAOJOfdSXoKqpTtJg4aRVh 6UmmRJ5NTiYDlgcvZ8u+oHBgLA== X-Google-Smtp-Source: AA6agR6ijj5IvZhfKoNvwLqOIwMB88lXmtKHmmrran4FNtmzOVXKRc2x/1u0jChrqNWsDrPPMCywEw== X-Received: by 2002:a17:907:2701:b0:741:51eb:2338 with SMTP id w1-20020a170907270100b0074151eb2338mr32582029ejk.501.1662466983588; Tue, 06 Sep 2022 05:23:03 -0700 (PDT) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 11/11] RISC-V: Add initial support for T-Head C906 and C910 CPUs Date: Tue, 6 Sep 2022 14:22:43 +0200 Message-Id: <20220906122243.1243354-12-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220906122243.1243354-1-christoph.muellner@vrull.eu> References: <20220906122243.1243354-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=christoph.muellner@vrull.eu; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1662468859872100001 From: Christoph M=C3=BCllner This patch adds the following T-Head CPUs to the list of known CPUs: * C906 * C910 Selecting those CPUs will automatically enable the available ISA extensions of the CPUs (incl. vendor extensions). Signed-off-by: Christoph M=C3=BCllner --- target/riscv/cpu.c | 32 ++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 3 +++ target/riscv/cpu_vendorid.h | 6 ++++++ 3 files changed, 41 insertions(+) create mode 100644 target/riscv/cpu_vendorid.h diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 01d85f0f96..1db440e21f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -194,6 +194,36 @@ static void rv64_sifive_e_cpu_init(Object *obj) cpu->cfg.mmu =3D false; } =20 +static void rv64_thead_c906_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_priv_version(env, PRIV_VERSION_1_10_0); + + cpu->cfg.ext_g =3D true; + cpu->cfg.ext_c =3D true; + cpu->cfg.ext_u =3D true; + cpu->cfg.ext_s =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.ext_zfh =3D true; + cpu->cfg.mmu =3D true; + cpu->cfg.ext_xtheadba =3D true; + cpu->cfg.ext_xtheadbb =3D true; + cpu->cfg.ext_xtheadbs =3D true; + cpu->cfg.ext_xtheadcmo =3D true; + cpu->cfg.ext_xtheadcondmov =3D true; + cpu->cfg.ext_xtheadfmemidx =3D true; + cpu->cfg.ext_xtheadmac =3D true; + cpu->cfg.ext_xtheadmemidx =3D true; + cpu->cfg.ext_xtheadmempair =3D true; + cpu->cfg.ext_xtheadsync =3D true; + cpu->cfg.ext_xtheadxmae =3D true; + + cpu->cfg.mvendorid =3D THEAD_VENDOR_ID; +} + static void rv128_base_cpu_init(Object *obj) { if (qemu_tcg_mttcg_enabled()) { @@ -1205,6 +1235,8 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C910, rv64_thead_c906_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8b02f530a6..74b291b4e4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -27,6 +27,7 @@ #include "qom/object.h" #include "qemu/int128.h" #include "cpu_bits.h" +#include "cpu_vendorid.h" =20 #define TCG_GUEST_DEFAULT_MO 0 =20 @@ -53,6 +54,8 @@ #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") +#define TYPE_RISCV_CPU_THEAD_C910 RISCV_CPU_TYPE_NAME("thead-c910") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") =20 #if defined(TARGET_RISCV32) diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h new file mode 100644 index 0000000000..a5aa249bc9 --- /dev/null +++ b/target/riscv/cpu_vendorid.h @@ -0,0 +1,6 @@ +#ifndef TARGET_RISCV_CPU_VENDORID_H +#define TARGET_RISCV_CPU_VENDORID_H + +#define THEAD_VENDOR_ID 0x5b7 + +#endif /* TARGET_RISCV_CPU_VENDORID_H */ --=20 2.37.2