From nobody Tue Feb 10 09:59:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1662464557; cv=none; d=zohomail.com; s=zohoarc; b=CRv1KFl5pn3M0zbZvEOpINiaag23YC1J1XFmnnsOr4GrD5Re12dJDzh84bFK4W8cuVD5aAPTrLcqmlJWddVNuZ7snLbr+XmjfaYeANvTZ8MLi1t3CdIsLXj50Pu8Orp1Tnzq2JJnlgbxGQUEoMwIc0aq5tD3GHVXxiYNAGkcHdU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662464557; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HUlJz3BTam22498ATvxGRZB5iusPGsSAquDVzoUZi34=; b=fh3mxQZf6iECi7kc18G5XE8um571LiKV9nGMtv+yKP1jfdz08X1RkxjaDc5zByq+oRNTcNqDwAR2CB0E2rQaccZVPcQAj5Ho94MSxe3uiBcv+pHOM2Ug2W/59uDuCnz89dnAQ6HxlbVldaHpGRBDLGslJHX0eNS9ELy2Ves0LIY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1662464557716390.54388019267606; Tue, 6 Sep 2022 04:42:37 -0700 (PDT) Received: from localhost ([::1]:36856 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oVWyS-0000nA-9K for importer@patchew.org; Tue, 06 Sep 2022 07:42:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51162) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oVVf9-0003y8-5d for qemu-devel@nongnu.org; Tue, 06 Sep 2022 06:18:35 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:33499) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oVVes-0005JP-JE for qemu-devel@nongnu.org; Tue, 06 Sep 2022 06:18:33 -0400 Received: by mail-wr1-x432.google.com with SMTP id k9so14727759wri.0 for ; Tue, 06 Sep 2022 03:18:18 -0700 (PDT) Received: from localhost.localdomain ([2a02:8084:a5c0:5a80:ba98:3a71:8524:e0b1]) by smtp.gmail.com with ESMTPSA id y16-20020a05600c365000b003a62bc1735asm14094361wmq.9.2022.09.06.03.18.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 03:18:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=HUlJz3BTam22498ATvxGRZB5iusPGsSAquDVzoUZi34=; b=iEOFWZx42nsBo4IWCutwHhgzFgn/s6TtixcIWbjLzyQ0XnYUVUmrHEYn+C7Bevt0ci OtBFGuCg9ylDadpxg2G1nKjaVas/ARTjg3x1Zkfsl53u9T42lEK/jzaxzNe/PZkoWqAM zQFp93A6Xpk2cAD3wmX6YvAkrh6UTffifd/ZZilciMeBo3s/afTBolBULiufOAYQzS7j sosHv6DD3C6pJhSkYNN+Tt174PuhKLmIWxppoGMSq9xxW+RGzMFjTb0ZtTL8gZdwQCLO xr8ZB+S+FFNaDv1vzPzbgUPb1LXd5Q0+FYPEQIrf8vqJSGpCzIvwwg6Dv9lEBx3H5dY8 mvow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=HUlJz3BTam22498ATvxGRZB5iusPGsSAquDVzoUZi34=; b=Uh8lqwrqTjk67w9J7cKCJAb0Yr4FGGLTM/pX3lLfLIK0faSscjsTonAs78pcTmRIuU GIGwo+nbTPGmk0t57WlQ5QhWM+QSlC1kzsw4z1YhJBxGX7CCMzg0DYCNg4jUk2m8TtVf hxogA9mTOLiplo0O0sK1+GDQ8DGniqpLT7fZxbVt96Ws99bS/sxAJ/7Oh+Hf7nyEtDVj broi7FH/R2DcrvVAxpoZ4ZsDxCdNzAwrSihlnnOSvM+tZ0a3D+bAh2zPhMSSTtcDBX9X 1Utqm8iBxX/sF0Y4oPUpOEpJmfBKUdUjtI6vwNFJ1b4/L4YNEoIun3XXmsWgMRW7N+eI 6LNw== X-Gm-Message-State: ACgBeo0bIXNOiXEEkAtAMO7f38MciqvYL83lXoC95OuDLFyqZTYAXk2A hYywVfYym2H8bhVfQNVBS5IyNGQo1mUm5x9I X-Google-Smtp-Source: AA6agR4I8wr6S1qJ80lreprJ0i1/jL0ZSPqvY/hSpMqygEYcZHr6wZQpIyN+evwzgMMQZ/rm6MZKGQ== X-Received: by 2002:a5d:60ca:0:b0:228:d77e:4b25 with SMTP id x10-20020a5d60ca000000b00228d77e4b25mr1751209wrt.139.1662459496433; Tue, 06 Sep 2022 03:18:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH v1 26/26] target/s390x: Enable TARGET_TB_PCREL Date: Tue, 6 Sep 2022 11:17:47 +0100 Message-Id: <20220906101747.344559-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220906101747.344559-1-richard.henderson@linaro.org> References: <20220906101747.344559-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1662464559042100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/s390x/cpu-param.h | 1 + target/s390x/cpu.c | 14 ++++-- target/s390x/tcg/translate.c | 88 +++++++++++++++++++++++------------- 3 files changed, 66 insertions(+), 37 deletions(-) diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index bf951a002e..467ecade8c 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -13,5 +13,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 #define NB_MMU_MODES 4 +#define TARGET_TB_PCREL 1 =20 #endif diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index c31bb2351f..6721bf937c 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -35,6 +35,7 @@ #include "fpu/softfloat-helpers.h" #include "disas/capstone.h" #include "sysemu/tcg.h" +#include "exec/exec-all.h" =20 #define CR0_RESET 0xE0UL #define CR14_RESET 0xC2000000UL; @@ -81,11 +82,14 @@ uint64_t s390_cpu_get_psw_mask(CPUS390XState *env) return r; } =20 -static void s390_cpu_set_pc(CPUState *cs, vaddr value) +static void s390_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { - S390CPU *cpu =3D S390_CPU(cs); - - cpu->env.psw.addr =3D value; + /* The program counter is always up to date with TARGET_TB_PCREL. */ + if (!TARGET_TB_PCREL) { + S390CPU *cpu =3D S390_CPU(cs); + cpu->env.psw.addr =3D tb_pc(tb); + } } =20 static bool s390_cpu_has_work(CPUState *cs) @@ -265,6 +269,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 static const struct TCGCPUOps s390_tcg_ops =3D { .initialize =3D s390x_translate_init, + .synchronize_from_tb =3D s390_cpu_synchronize_from_tb, =20 #ifdef CONFIG_USER_ONLY .record_sigsegv =3D s390_cpu_record_sigsegv, @@ -296,7 +301,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->class_by_name =3D s390_cpu_class_by_name, cc->has_work =3D s390_cpu_has_work; cc->dump_state =3D s390_cpu_dump_state; - cc->set_pc =3D s390_cpu_set_pc; cc->gdb_read_register =3D s390_cpu_gdb_read_register; cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index b27e34f712..c33dcc115d 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -139,6 +139,7 @@ struct DisasContext { DisasContextBase base; const DisasInsn *insn; TCGOp *insn_start; + target_ulong pc_save; DisasFields fields; uint64_t ex_value; uint32_t ilen; @@ -163,29 +164,6 @@ static uint64_t inline_branch_hit[CC_OP_MAX]; static uint64_t inline_branch_miss[CC_OP_MAX]; #endif =20 -static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) -{ - tcg_gen_movi_i64(dest, s->base.pc_next + disp); -} - -static void pc_to_link_info(TCGv_i64 out, DisasContext *s) -{ - TCGv_i64 tmp; - - if (s->base.tb->flags & FLAG_MASK_64) { - gen_psw_addr_disp(s, out, s->ilen); - return; - } - - tmp =3D tcg_temp_new_i64(); - gen_psw_addr_disp(s, tmp, s->ilen); - if (s->base.tb->flags & FLAG_MASK_32) { - tcg_gen_ori_i64(tmp, tmp, 0x80000000); - } - tcg_gen_deposit_i64(out, out, tmp, 0, 32); - tcg_temp_free_i64(tmp); -} - static TCGv_i64 psw_addr; static TCGv_i64 psw_mask; static TCGv_i64 gbea; @@ -336,9 +314,39 @@ static void return_low128(TCGv_i64 dest) tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl)); } =20 +static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) +{ + assert(s->pc_save !=3D -1); + if (TARGET_TB_PCREL) { + disp +=3D s->base.pc_next - s->pc_save; + tcg_gen_addi_i64(dest, psw_addr, disp); + } else { + tcg_gen_movi_i64(dest, s->base.pc_next + disp); + } +} + +static void pc_to_link_info(TCGv_i64 out, DisasContext *s) +{ + TCGv_i64 tmp; + + if (s->base.tb->flags & FLAG_MASK_64) { + gen_psw_addr_disp(s, out, s->ilen); + return; + } + + tmp =3D tcg_temp_new_i64(); + gen_psw_addr_disp(s, tmp, s->ilen); + if (s->base.tb->flags & FLAG_MASK_32) { + tcg_gen_ori_i64(tmp, tmp, 0x80000000); + } + tcg_gen_deposit_i64(out, out, tmp, 0, 32); + tcg_temp_free_i64(tmp); +} + static void update_psw_addr_disp(DisasContext *s, int64_t disp) { gen_psw_addr_disp(s, psw_addr, disp); + s->pc_save =3D s->base.pc_next + disp; } =20 static inline bool per_enabled(DisasContext *s) @@ -1172,6 +1180,7 @@ static DisasJumpType help_goto_indirect(DisasContext = *s, TCGv_i64 dest) { per_breaking_event(s); tcg_gen_mov_i64(psw_addr, dest); + s->pc_save =3D -1; per_branch_dest(s, psw_addr); return DISAS_PC_UPDATED; } @@ -1181,6 +1190,7 @@ static DisasJumpType help_branch(DisasContext *s, Dis= asCompare *c, { DisasJumpType ret; int64_t disp =3D (int64_t)imm * 2; + TCGv_i64 cdest_save =3D NULL; TCGLabel *lab; =20 /* Take care of the special cases first. */ @@ -1213,12 +1223,12 @@ static DisasJumpType help_branch(DisasContext *s, D= isasCompare *c, update_cc_op(s); =20 /* - * Store taken branch destination before the brcond. This - * avoids having to allocate a new local temp to hold it. - * We'll overwrite this in the not taken case anyway. + * Save taken branch destination across the brcond if required. */ - if (!is_imm) { - tcg_gen_mov_i64(psw_addr, cdest); + if (!is_imm && tcg_temp_is_normal_i64(cdest)) { + cdest_save =3D tcg_temp_ebb_new_i64(); + tcg_gen_mov_i64(cdest_save, cdest); + cdest =3D cdest_save; } =20 lab =3D gen_new_label(); @@ -1234,6 +1244,11 @@ static DisasJumpType help_branch(DisasContext *s, Di= sasCompare *c, per_breaking_event(s); if (is_imm) { gen_psw_addr_disp(s, psw_addr, disp); + } else { + tcg_gen_mov_i64(psw_addr, cdest); + } + if (cdest_save) { + tcg_temp_free_i64(cdest_save); } per_branch_dest(s, psw_addr); =20 @@ -1247,15 +1262,15 @@ static DisasJumpType help_branch(DisasContext *s, D= isasCompare *c, gen_set_label(lab); =20 /* Branch not taken. */ + gen_psw_addr_disp(s, psw_addr, s->ilen); if (use_goto_tb(s, s->base.pc_next + s->ilen)) { tcg_gen_goto_tb(1); - gen_psw_addr_disp(s, psw_addr, s->ilen); tcg_gen_exit_tb(s->base.tb, 1); } else { - gen_psw_addr_disp(s, psw_addr, s->ilen); tcg_gen_lookup_and_goto_ptr(); } =20 + s->pc_save =3D -1; ret =3D DISAS_NORETURN; =20 egress: @@ -6443,6 +6458,7 @@ static void s390x_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 + dc->pc_save =3D dc->base.pc_first; dc->cc_op =3D CC_OP_DYNAMIC; dc->ex_value =3D dc->base.tb->cs_base; dc->exit_to_mainloop =3D per_enabled(dc) || dc->ex_value; @@ -6455,9 +6471,13 @@ static void s390x_tr_tb_start(DisasContextBase *db, = CPUState *cs) static void s390x_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); + target_ulong pc_arg =3D dc->base.pc_next; =20 + if (TARGET_TB_PCREL) { + pc_arg &=3D ~TARGET_PAGE_MASK; + } /* Delay the set of ilen until we've read the insn. */ - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 0); + tcg_gen_insn_start(pc_arg, dc->cc_op, 0); dc->insn_start =3D tcg_last_op(); } =20 @@ -6548,7 +6568,11 @@ void restore_state_to_opc(CPUS390XState *env, Transl= ationBlock *tb, { int cc_op =3D data[1]; =20 - env->psw.addr =3D data[0]; + if (TARGET_TB_PCREL) { + env->psw.addr =3D (env->psw.addr & TARGET_PAGE_MASK) | data[0]; + } else { + env->psw.addr =3D data[0]; + } =20 /* Update the CC opcode if it is not already up-to-date. */ if ((cc_op !=3D CC_OP_DYNAMIC) && (cc_op !=3D CC_OP_STATIC)) { --=20 2.34.1