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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1662460723032100001 Content-Type: text/plain; charset="utf-8" A simple helper to retrieve the length of the current insn. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/translate.h | 5 +++++ target/arm/translate-vfp.c | 2 +- target/arm/translate.c | 5 ++--- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index af5d4a7086..90bf7c57fc 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -226,6 +226,11 @@ static inline void disas_set_insn_syndrome(DisasContex= t *s, uint32_t syn) s->insn_start =3D NULL; } =20 +static inline int curr_insn_len(DisasContext *s) +{ + return s->base.pc_next - s->pc_curr; +} + /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically= */ /* CPU state was modified dynamically; exit to main loop for interrupts. */ diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index bd5ae27d09..94cc1e4b77 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -242,7 +242,7 @@ static bool vfp_access_check_a(DisasContext *s, bool ig= nore_vfp_enabled) if (s->sme_trap_nonstreaming) { gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_smetrap(SME_ET_Streaming, - s->base.pc_next - s->pc_curr =3D=3D= 2)); + curr_insn_len(s) =3D=3D 2)); return false; } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 9474e4b44b..638a051281 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6660,7 +6660,7 @@ static ISSInfo make_issinfo(DisasContext *s, int rd, = bool p, bool w) /* ISS not valid if writeback */ if (p && !w) { ret =3D rd; - if (s->base.pc_next - s->pc_curr =3D=3D 2) { + if (curr_insn_len(s) =3D=3D 2) { ret |=3D ISSIs16Bit; } } else { @@ -9825,8 +9825,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) /* nothing more to generate */ break; case DISAS_WFI: - gen_helper_wfi(cpu_env, - tcg_constant_i32(dc->base.pc_next - dc->pc_curr= )); + gen_helper_wfi(cpu_env, tcg_constant_i32(curr_insn_len(dc))); /* * The helper doesn't necessarily throw an exception, but we * must go back to the main loop to check for interrupts anywa= y. --=20 2.34.1 From nobody Wed May 22 01:36:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1662459863127100001 Content-Type: text/plain; charset="utf-8" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.c | 40 ++++++++++++++++++++------------------ target/arm/translate.c | 10 ++++++---- 2 files changed, 27 insertions(+), 23 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b7787e7786..f7a13bddea 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -378,8 +378,10 @@ static inline bool use_goto_tb(DisasContext *s, uint64= _t dest) return translator_use_goto_tb(&s->base, dest); } =20 -static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) +static void gen_goto_tb(DisasContext *s, int n, int diff) { + uint64_t dest =3D s->pc_curr + diff; + if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(n); gen_a64_set_pc_im(dest); @@ -1362,7 +1364,7 @@ static inline AArch64DecodeFn *lookup_disas_fn(const = AArch64DecodeTable *table, */ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) { - uint64_t addr =3D s->pc_curr + sextract32(insn, 0, 26) * 4; + int diff =3D sextract32(insn, 0, 26) * 4; =20 if (insn & (1U << 31)) { /* BL Branch with link */ @@ -1371,7 +1373,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint3= 2_t insn) =20 /* B Branch / BL Branch with link */ reset_btype(s); - gen_goto_tb(s, 0, addr); + gen_goto_tb(s, 0, diff); } =20 /* Compare and branch (immediate) @@ -1383,14 +1385,14 @@ static void disas_uncond_b_imm(DisasContext *s, uin= t32_t insn) static void disas_comp_b_imm(DisasContext *s, uint32_t insn) { unsigned int sf, op, rt; - uint64_t addr; + int diff; TCGLabel *label_match; TCGv_i64 tcg_cmp; =20 sf =3D extract32(insn, 31, 1); op =3D extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ rt =3D extract32(insn, 0, 5); - addr =3D s->pc_curr + sextract32(insn, 5, 19) * 4; + diff =3D sextract32(insn, 5, 19) * 4; =20 tcg_cmp =3D read_cpu_reg(s, rt, sf); label_match =3D gen_new_label(); @@ -1399,9 +1401,9 @@ static void disas_comp_b_imm(DisasContext *s, uint32_= t insn) tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, label_match); =20 - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); gen_set_label(label_match); - gen_goto_tb(s, 1, addr); + gen_goto_tb(s, 1, diff); } =20 /* Test and branch (immediate) @@ -1413,13 +1415,13 @@ static void disas_comp_b_imm(DisasContext *s, uint3= 2_t insn) static void disas_test_b_imm(DisasContext *s, uint32_t insn) { unsigned int bit_pos, op, rt; - uint64_t addr; + int diff; TCGLabel *label_match; TCGv_i64 tcg_cmp; =20 bit_pos =3D (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); op =3D extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ - addr =3D s->pc_curr + sextract32(insn, 5, 14) * 4; + diff =3D sextract32(insn, 5, 14) * 4; rt =3D extract32(insn, 0, 5); =20 tcg_cmp =3D tcg_temp_new_i64(); @@ -1430,9 +1432,9 @@ static void disas_test_b_imm(DisasContext *s, uint32_= t insn) tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, label_match); tcg_temp_free_i64(tcg_cmp); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); gen_set_label(label_match); - gen_goto_tb(s, 1, addr); + gen_goto_tb(s, 1, diff); } =20 /* Conditional branch (immediate) @@ -1444,13 +1446,13 @@ static void disas_test_b_imm(DisasContext *s, uint3= 2_t insn) static void disas_cond_b_imm(DisasContext *s, uint32_t insn) { unsigned int cond; - uint64_t addr; + int diff; =20 if ((insn & (1 << 4)) || (insn & (1 << 24))) { unallocated_encoding(s); return; } - addr =3D s->pc_curr + sextract32(insn, 5, 19) * 4; + diff =3D sextract32(insn, 5, 19) * 4; cond =3D extract32(insn, 0, 4); =20 reset_btype(s); @@ -1458,12 +1460,12 @@ static void disas_cond_b_imm(DisasContext *s, uint3= 2_t insn) /* genuinely conditional branches */ TCGLabel *label_match =3D gen_new_label(); arm_gen_test_cc(cond, label_match); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); gen_set_label(label_match); - gen_goto_tb(s, 1, addr); + gen_goto_tb(s, 1, diff); } else { /* 0xe and 0xf are both "always" conditions */ - gen_goto_tb(s, 0, addr); + gen_goto_tb(s, 0, diff); } } =20 @@ -1637,7 +1639,7 @@ static void handle_sync(DisasContext *s, uint32_t ins= n, * any pending interrupts immediately. */ reset_btype(s); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); return; =20 case 7: /* SB */ @@ -1649,7 +1651,7 @@ static void handle_sync(DisasContext *s, uint32_t ins= n, * MB and end the TB instead. */ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); return; =20 default: @@ -14965,7 +14967,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) switch (dc->base.is_jmp) { case DISAS_NEXT: case DISAS_TOO_MANY: - gen_goto_tb(dc, 1, dc->base.pc_next); + gen_goto_tb(dc, 1, curr_insn_len(dc)); break; default: case DISAS_UPDATE_EXIT: diff --git a/target/arm/translate.c b/target/arm/translate.c index 638a051281..2b9a58b442 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2597,8 +2597,10 @@ static void gen_goto_ptr(void) * cpu_loop_exec. Any live exit_requests will be processed as we * enter the next TB. */ -static void gen_goto_tb(DisasContext *s, int n, target_ulong dest) +static void gen_goto_tb(DisasContext *s, int n, int diff) { + target_ulong dest =3D s->pc_curr + diff; + if (translator_use_goto_tb(&s->base, dest)) { tcg_gen_goto_tb(n); gen_set_pc_im(s, dest); @@ -2632,7 +2634,7 @@ static inline void gen_jmp_tb(DisasContext *s, uint32= _t dest, int tbno) * gen_jmp(); * on the second call to gen_jmp(). */ - gen_goto_tb(s, tbno, dest); + gen_goto_tb(s, tbno, dest - s->pc_curr); break; case DISAS_UPDATE_NOCHAIN: case DISAS_UPDATE_EXIT: @@ -9806,7 +9808,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) switch (dc->base.is_jmp) { case DISAS_NEXT: case DISAS_TOO_MANY: - gen_goto_tb(dc, 1, dc->base.pc_next); + gen_goto_tb(dc, 1, curr_insn_len(dc)); break; case DISAS_UPDATE_NOCHAIN: gen_set_pc_im(dc, dc->base.pc_next); @@ -9858,7 +9860,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) gen_set_pc_im(dc, dc->base.pc_next); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1662461293053100003 Content-Type: text/plain; charset="utf-8" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values by passing in pc difference. Signed-off-by: Richard Henderson --- target/arm/translate-a32.h | 2 +- target/arm/translate.h | 6 ++-- target/arm/translate-a64.c | 32 +++++++++--------- target/arm/translate-vfp.c | 2 +- target/arm/translate.c | 68 ++++++++++++++++++++------------------ 5 files changed, 56 insertions(+), 54 deletions(-) diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index 78a84c1414..09c8f467aa 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -40,7 +40,7 @@ void write_neon_element64(TCGv_i64 src, int reg, int ele,= MemOp memop); TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs); void gen_set_cpsr(TCGv_i32 var, uint32_t mask); void gen_set_condexec(DisasContext *s); -void gen_set_pc_im(DisasContext *s, target_ulong val); +void gen_update_pc(DisasContext *s, int diff); void gen_lookup_tb(DisasContext *s); long vfp_reg_offset(bool dp, unsigned reg); long neon_full_reg_offset(unsigned reg); diff --git a/target/arm/translate.h b/target/arm/translate.h index 90bf7c57fc..33b94a18bb 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -254,7 +254,7 @@ static inline int curr_insn_len(DisasContext *s) * For instructions which want an immediate exit to the main loop, as oppo= sed * to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, th= is * doesn't write the PC on exiting the translation loop so you need to ens= ure - * something (gen_a64_set_pc_im or runtime helper) has done so before we r= each + * something (gen_a64_update_pc or runtime helper) has done so before we r= each * return from cpu_tb_exec. */ #define DISAS_EXIT DISAS_TARGET_9 @@ -263,14 +263,14 @@ static inline int curr_insn_len(DisasContext *s) =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_a64_set_pc_im(uint64_t val); +void gen_a64_update_pc(DisasContext *s, int diff); extern const TranslatorOps aarch64_translator_ops; #else static inline void a64_translate_init(void) { } =20 -static inline void gen_a64_set_pc_im(uint64_t val) +static inline void gen_a64_update_pc(DisasContext *s, int diff) { } #endif diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f7a13bddea..640369ea43 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -148,9 +148,9 @@ static void reset_btype(DisasContext *s) } } =20 -void gen_a64_set_pc_im(uint64_t val) +void gen_a64_update_pc(DisasContext *s, int diff) { - tcg_gen_movi_i64(cpu_pc, val); + tcg_gen_movi_i64(cpu_pc, s->pc_curr + diff); } =20 /* @@ -342,14 +342,14 @@ static void gen_exception_internal(int excp) =20 static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int = excp) { - gen_a64_set_pc_im(pc); + gen_a64_update_pc(s, pc - s->pc_curr); gen_exception_internal(excp); s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome) { - gen_a64_set_pc_im(s->pc_curr); + gen_a64_update_pc(s, 0); gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome)); s->base.is_jmp =3D DISAS_NORETURN; } @@ -384,11 +384,11 @@ static void gen_goto_tb(DisasContext *s, int n, int d= iff) =20 if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(n); - gen_a64_set_pc_im(dest); + gen_a64_update_pc(s, diff); tcg_gen_exit_tb(s->base.tb, n); s->base.is_jmp =3D DISAS_NORETURN; } else { - gen_a64_set_pc_im(dest); + gen_a64_update_pc(s, diff); if (s->ss_active) { gen_step_complete_exception(s); } else { @@ -1960,7 +1960,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, uint32_t syndrome; =20 syndrome =3D syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isre= ad); - gen_a64_set_pc_im(s->pc_curr); + gen_a64_update_pc(s, 0); gen_helper_access_check_cp_reg(cpu_env, tcg_constant_ptr(ri), tcg_constant_i32(syndrome), @@ -1970,7 +1970,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, * The readfn or writefn might raise an exception; * synchronize the CPU state in case it does. */ - gen_a64_set_pc_im(s->pc_curr); + gen_a64_update_pc(s, 0); } =20 /* Handle special cases first */ @@ -2180,7 +2180,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) /* The pre HVC helper handles cases when HVC gets trapped * as an undefined insn by runtime configuration. */ - gen_a64_set_pc_im(s->pc_curr); + gen_a64_update_pc(s, 0); gen_helper_pre_hvc(cpu_env); gen_ss_advance(s); gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC, @@ -2191,7 +2191,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) unallocated_encoding(s); break; } - gen_a64_set_pc_im(s->pc_curr); + gen_a64_update_pc(s, 0); gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm1= 6))); gen_ss_advance(s); gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC, @@ -14954,7 +14954,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) */ switch (dc->base.is_jmp) { default: - gen_a64_set_pc_im(dc->base.pc_next); + gen_a64_update_pc(dc, curr_insn_len(dc)); /* fall through */ case DISAS_EXIT: case DISAS_JUMP: @@ -14971,13 +14971,13 @@ static void aarch64_tr_tb_stop(DisasContextBase *= dcbase, CPUState *cpu) break; default: case DISAS_UPDATE_EXIT: - gen_a64_set_pc_im(dc->base.pc_next); + gen_a64_update_pc(dc, curr_insn_len(dc)); /* fall through */ case DISAS_EXIT: tcg_gen_exit_tb(NULL, 0); break; case DISAS_UPDATE_NOCHAIN: - gen_a64_set_pc_im(dc->base.pc_next); + gen_a64_update_pc(dc, curr_insn_len(dc)); /* fall through */ case DISAS_JUMP: tcg_gen_lookup_and_goto_ptr(); @@ -14986,11 +14986,11 @@ static void aarch64_tr_tb_stop(DisasContextBase *= dcbase, CPUState *cpu) case DISAS_SWI: break; case DISAS_WFE: - gen_a64_set_pc_im(dc->base.pc_next); + gen_a64_update_pc(dc, curr_insn_len(dc)); gen_helper_wfe(cpu_env); break; case DISAS_YIELD: - gen_a64_set_pc_im(dc->base.pc_next); + gen_a64_update_pc(dc, curr_insn_len(dc)); gen_helper_yield(cpu_env); break; case DISAS_WFI: @@ -14998,7 +14998,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) * This is a special case because we don't want to just halt * the CPU if trying to debug across a WFI. */ - gen_a64_set_pc_im(dc->base.pc_next); + gen_a64_update_pc(dc, curr_insn_len(dc)); gen_helper_wfi(cpu_env, tcg_constant_i32(4)); /* * The helper doesn't necessarily throw an exception, but we diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 94cc1e4b77..070f465b17 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -856,7 +856,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_V= MRS *a) case ARM_VFP_FPSID: if (s->current_el =3D=3D 1) { gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); gen_helper_check_hcr_el2_trap(cpu_env, tcg_constant_i32(a->rt), tcg_constant_i32(a->reg)); diff --git a/target/arm/translate.c b/target/arm/translate.c index 2b9a58b442..92c52edb7b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -772,9 +772,9 @@ void gen_set_condexec(DisasContext *s) } } =20 -void gen_set_pc_im(DisasContext *s, target_ulong val) +void gen_update_pc(DisasContext *s, int diff) { - tcg_gen_movi_i32(cpu_R[15], val); + tcg_gen_movi_i32(cpu_R[15], s->pc_curr + diff); } =20 /* Set PC and Thumb state from var. var is marked as dead. */ @@ -866,7 +866,7 @@ static inline void gen_bxns(DisasContext *s, int rm) =20 /* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory * we need to sync state before calling it, but: - * - we don't need to do gen_set_pc_im() because the bxns helper will + * - we don't need to do gen_update_pc() because the bxns helper will * always set the PC itself * - we don't need to do gen_set_condexec() because BXNS is UNPREDICT= ABLE * unless it's outside an IT block or the last insn in an IT block, @@ -887,7 +887,7 @@ static inline void gen_blxns(DisasContext *s, int rm) * We do however need to set the PC, because the blxns helper reads it. * The blxns helper may throw an exception. */ - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); gen_helper_v7m_blxns(cpu_env, var); tcg_temp_free_i32(var); s->base.is_jmp =3D DISAS_EXIT; @@ -1055,7 +1055,7 @@ static inline void gen_hvc(DisasContext *s, int imm16) * as an undefined insn by runtime configuration (ie before * the insn really executes). */ - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); gen_helper_pre_hvc(cpu_env); /* Otherwise we will treat this as a real exception which * happens after execution of the insn. (The distinction matters @@ -1063,7 +1063,7 @@ static inline void gen_hvc(DisasContext *s, int imm16) * for single stepping.) */ s->svc_imm =3D imm16; - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp =3D DISAS_HVC; } =20 @@ -1072,16 +1072,16 @@ static inline void gen_smc(DisasContext *s) /* As with HVC, we may take an exception either before or after * the insn executes. */ - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa32_smc())); - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp =3D DISAS_SMC; } =20 static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int = excp) { gen_set_condexec(s); - gen_set_pc_im(s, pc); + gen_update_pc(s, pc - s->pc_curr); gen_exception_internal(excp); s->base.is_jmp =3D DISAS_NORETURN; } @@ -1107,10 +1107,10 @@ static void gen_exception_insn_el_v(DisasContext *s= , uint64_t pc, int excp, uint32_t syn, TCGv_i32 tcg_el) { if (s->aarch64) { - gen_a64_set_pc_im(pc); + gen_a64_update_pc(s, pc - s->pc_curr); } else { gen_set_condexec(s); - gen_set_pc_im(s, pc); + gen_update_pc(s, pc - s->pc_curr); } gen_exception_el_v(excp, syn, tcg_el); s->base.is_jmp =3D DISAS_NORETURN; @@ -1125,10 +1125,10 @@ void gen_exception_insn_el(DisasContext *s, uint64_= t pc, int excp, void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t s= yn) { if (s->aarch64) { - gen_a64_set_pc_im(pc); + gen_a64_update_pc(s, pc - s->pc_curr); } else { gen_set_condexec(s); - gen_set_pc_im(s, pc); + gen_update_pc(s, pc - s->pc_curr); } gen_exception(excp, syn); s->base.is_jmp =3D DISAS_NORETURN; @@ -1137,7 +1137,7 @@ void gen_exception_insn(DisasContext *s, uint64_t pc,= int excp, uint32_t syn) static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) { gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syn)); s->base.is_jmp =3D DISAS_NORETURN; } @@ -2603,10 +2603,10 @@ static void gen_goto_tb(DisasContext *s, int n, int= diff) =20 if (translator_use_goto_tb(&s->base, dest)) { tcg_gen_goto_tb(n); - gen_set_pc_im(s, dest); + gen_update_pc(s, diff); tcg_gen_exit_tb(s->base.tb, n); } else { - gen_set_pc_im(s, dest); + gen_update_pc(s, diff); gen_goto_ptr(); } s->base.is_jmp =3D DISAS_NORETURN; @@ -2615,9 +2615,11 @@ static void gen_goto_tb(DisasContext *s, int n, int = diff) /* Jump, specifying which TB number to use if we gen_goto_tb() */ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno) { + int diff =3D dest - s->pc_curr; + if (unlikely(s->ss_active)) { /* An indirect jump so that we still trigger the debug exception. = */ - gen_set_pc_im(s, dest); + gen_update_pc(s, diff); s->base.is_jmp =3D DISAS_JUMP; return; } @@ -2634,7 +2636,7 @@ static inline void gen_jmp_tb(DisasContext *s, uint32= _t dest, int tbno) * gen_jmp(); * on the second call to gen_jmp(). */ - gen_goto_tb(s, tbno, dest - s->pc_curr); + gen_goto_tb(s, tbno, diff); break; case DISAS_UPDATE_NOCHAIN: case DISAS_UPDATE_EXIT: @@ -2643,7 +2645,7 @@ static inline void gen_jmp_tb(DisasContext *s, uint32= _t dest, int tbno) * Avoid using goto_tb so we really do exit back to the main loop * and don't chain to another TB. */ - gen_set_pc_im(s, dest); + gen_update_pc(s, diff); gen_goto_ptr(); s->base.is_jmp =3D DISAS_NORETURN; break; @@ -2911,7 +2913,7 @@ static void gen_msr_banked(DisasContext *s, int r, in= t sysm, int rn) =20 /* Sync state because msr_banked() can raise exceptions */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); tcg_reg =3D load_reg(s, rn); gen_helper_msr_banked(cpu_env, tcg_reg, tcg_constant_i32(tgtmode), @@ -2931,7 +2933,7 @@ static void gen_mrs_banked(DisasContext *s, int r, in= t sysm, int rn) =20 /* Sync state because mrs_banked() can raise exceptions */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); tcg_reg =3D tcg_temp_new_i32(); gen_helper_mrs_banked(tcg_reg, cpu_env, tcg_constant_i32(tgtmode), @@ -4752,7 +4754,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, } =20 gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); gen_helper_access_check_cp_reg(cpu_env, tcg_constant_ptr(ri), tcg_constant_i32(syndrome), @@ -4763,7 +4765,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, * synchronize the CPU state in case it does. */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); } =20 /* Handle special cases first */ @@ -4777,7 +4779,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, unallocated_encoding(s); return; } - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp =3D DISAS_WFI; return; default: @@ -5164,7 +5166,7 @@ static void gen_srs(DisasContext *s, addr =3D tcg_temp_new_i32(); /* get_r13_banked() will raise an exception if called from System mode= */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); gen_helper_get_r13_banked(addr, cpu_env, tcg_constant_i32(mode)); switch (amode) { case 0: /* DA */ @@ -6233,7 +6235,7 @@ static bool trans_YIELD(DisasContext *s, arg_YIELD *a) * scheduling of other vCPUs. */ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp =3D DISAS_YIELD; } return true; @@ -6249,7 +6251,7 @@ static bool trans_WFE(DisasContext *s, arg_WFE *a) * implemented so we can't sleep like WFI does. */ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp =3D DISAS_WFE; } return true; @@ -6258,7 +6260,7 @@ static bool trans_WFE(DisasContext *s, arg_WFE *a) static bool trans_WFI(DisasContext *s, arg_WFI *a) { /* For WFI, halt the vCPU until an IRQ. */ - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp =3D DISAS_WFI; return true; } @@ -8773,7 +8775,7 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a) (a->imm =3D=3D semihost_imm)) { gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); } else { - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->svc_imm =3D a->imm; s->base.is_jmp =3D DISAS_SWI; } @@ -9787,7 +9789,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) case DISAS_TOO_MANY: case DISAS_UPDATE_EXIT: case DISAS_UPDATE_NOCHAIN: - gen_set_pc_im(dc, dc->base.pc_next); + gen_update_pc(dc, curr_insn_len(dc)); /* fall through */ default: /* FIXME: Single stepping a WFI insn will not halt the CPU. */ @@ -9811,13 +9813,13 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cpu) gen_goto_tb(dc, 1, curr_insn_len(dc)); break; case DISAS_UPDATE_NOCHAIN: - gen_set_pc_im(dc, dc->base.pc_next); + gen_update_pc(dc, curr_insn_len(dc)); /* fall through */ case DISAS_JUMP: gen_goto_ptr(); break; case DISAS_UPDATE_EXIT: - gen_set_pc_im(dc, dc->base.pc_next); + gen_update_pc(dc, curr_insn_len(dc)); /* fall through */ default: /* indicate that the hash table must be used to find the next = TB */ @@ -9857,7 +9859,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) gen_set_label(dc->condlabel); gen_set_condexec(dc); if (unlikely(dc->ss_active)) { - gen_set_pc_im(dc, dc->base.pc_next); + gen_update_pc(dc, curr_insn_len(dc)); gen_singlestep_exception(dc); } else { gen_goto_tb(dc, 1, curr_insn_len(dc)); --=20 2.34.1 From nobody Wed May 22 01:36:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Tue, 06 Sep 2022 03:05:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 4/9] target/arm: Change gen_exception_insn* to work on displacements Date: Tue, 6 Sep 2022 11:05:23 +0100 Message-Id: <20220906100528.343244-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220906100528.343244-1-richard.henderson@linaro.org> References: <20220906100528.343244-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1662461828001100001 Content-Type: text/plain; charset="utf-8" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson --- target/arm/translate.h | 4 ++-- target/arm/translate-a64.c | 28 +++++++++++-------------- target/arm/translate-m-nocp.c | 6 +++--- target/arm/translate-mve.c | 2 +- target/arm/translate-vfp.c | 6 +++--- target/arm/translate.c | 39 +++++++++++++++++------------------ 6 files changed, 40 insertions(+), 45 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 33b94a18bb..d42059aa1d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -281,9 +281,9 @@ void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); void arm_gen_test_cc(int cc, TCGLabel *label); MemOp pow2_align(unsigned i); void unallocated_encoding(DisasContext *s); -void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, +void gen_exception_insn_el(DisasContext *s, int pc_diff, int excp, uint32_t syn, uint32_t target_el); -void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t s= yn); +void gen_exception_insn(DisasContext *s, int pc_diff, int excp, uint32_t s= yn); =20 /* Return state of Alternate Half-precision flag, caller frees result */ static inline TCGv_i32 get_ahp_flag(void) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 640369ea43..17ea8b5650 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1163,7 +1163,7 @@ static bool fp_access_check_only(DisasContext *s) assert(!s->fp_access_checked); s->fp_access_checked =3D true; =20 - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_fp_access_trap(1, 0xe, false, 0), s->fp_excp_el); return false; @@ -1178,7 +1178,7 @@ static bool fp_access_check(DisasContext *s) return false; } if (s->sme_trap_nonstreaming && s->is_nonstreaming) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn(s, 0, EXCP_UDEF, syn_smetrap(SME_ET_Streaming, false)); return false; } @@ -1198,7 +1198,7 @@ bool sve_access_check(DisasContext *s) goto fail_exit; } } else if (s->sve_excp_el) { - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_sve_access_trap(), s->sve_excp_el); goto fail_exit; } @@ -1220,7 +1220,7 @@ bool sve_access_check(DisasContext *s) static bool sme_access_check(DisasContext *s) { if (s->sme_excp_el) { - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_smetrap(SME_ET_AccessTrap, false), s->sme_excp_el); return false; @@ -1250,12 +1250,12 @@ bool sme_enabled_check_with_svcr(DisasContext *s, u= nsigned req) return false; } if (FIELD_EX64(req, SVCR, SM) && !s->pstate_sm) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn(s, 0, EXCP_UDEF, syn_smetrap(SME_ET_NotStreaming, false)); return false; } if (FIELD_EX64(req, SVCR, ZA) && !s->pstate_za) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn(s, 0, EXCP_UDEF, syn_smetrap(SME_ET_InactiveZA, false)); return false; } @@ -1915,7 +1915,7 @@ static void gen_sysreg_undef(DisasContext *s, bool is= read, } else { syndrome =3D syn_uncategorized(); } - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome); + gen_exception_insn(s, 0, EXCP_UDEF, syndrome); } =20 /* MRS - move from system register @@ -2169,8 +2169,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) switch (op2_ll) { case 1: /* SVC= */ gen_ss_advance(s); - gen_exception_insn(s, s->base.pc_next, EXCP_SWI, - syn_aa64_svc(imm16)); + gen_exception_insn(s, 4, EXCP_SWI, syn_aa64_svc(imm16)); break; case 2: /* HVC= */ if (s->current_el =3D=3D 0) { @@ -2183,8 +2182,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) gen_a64_update_pc(s, 0); gen_helper_pre_hvc(cpu_env); gen_ss_advance(s); - gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC, - syn_aa64_hvc(imm16), 2); + gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(imm16), 2); break; case 3: /* SMC= */ if (s->current_el =3D=3D 0) { @@ -2194,8 +2192,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) gen_a64_update_pc(s, 0); gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm1= 6))); gen_ss_advance(s); - gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC, - syn_aa64_smc(imm16), 3); + gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(imm16), 3); break; default: unallocated_encoding(s); @@ -14843,7 +14840,7 @@ static void aarch64_tr_translate_insn(DisasContextB= ase *dcbase, CPUState *cpu) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate()); + gen_exception_insn(s, 0, EXCP_UDEF, syn_illegalstate()); return; } =20 @@ -14874,8 +14871,7 @@ static void aarch64_tr_translate_insn(DisasContextB= ase *dcbase, CPUState *cpu) if (s->btype !=3D 0 && s->guarded_page && !btype_destination_ok(insn, s->bt, s->btype)) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_btitrap(s->btype)); + gen_exception_insn(s, 0, EXCP_UDEF, syn_btitrap(s->btype)); return; } } else { diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c index 4029d7fdd4..694fae7e2e 100644 --- a/target/arm/translate-m-nocp.c +++ b/target/arm/translate-m-nocp.c @@ -143,7 +143,7 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM = *a) tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel); =20 if (s->fp_excp_el !=3D 0) { - gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + gen_exception_insn_el(s, 0, EXCP_NOCP, syn_uncategorized(), s->fp_excp_el); return true; } @@ -765,12 +765,12 @@ static bool trans_NOCP(DisasContext *s, arg_nocp *a) } =20 if (a->cp !=3D 10) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized()); + gen_exception_insn(s, 0, EXCP_NOCP, syn_uncategorized()); return true; } =20 if (s->fp_excp_el !=3D 0) { - gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + gen_exception_insn_el(s, 0, EXCP_NOCP, syn_uncategorized(), s->fp_excp_el); return true; } diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 0cf1b5ea4f..db7ea3f603 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -100,7 +100,7 @@ bool mve_eci_check(DisasContext *s) return true; default: /* Reserved value: INVSTATE UsageFault */ - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized= ()); + gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized()); return false; } } diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 070f465b17..5c5d58d2c6 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -230,7 +230,7 @@ static bool vfp_access_check_a(DisasContext *s, bool ig= nore_vfp_enabled) int coproc =3D arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa; uint32_t syn =3D syn_fp_access_trap(1, 0xe, false, coproc); =20 - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el= ); + gen_exception_insn_el(s, 0, EXCP_UDEF, syn, s->fp_excp_el); return false; } =20 @@ -240,7 +240,7 @@ static bool vfp_access_check_a(DisasContext *s, bool ig= nore_vfp_enabled) * appear to be any insns which touch VFP which are allowed. */ if (s->sme_trap_nonstreaming) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn(s, 0, EXCP_UDEF, syn_smetrap(SME_ET_Streaming, curr_insn_len(s) =3D=3D 2)); return false; @@ -272,7 +272,7 @@ bool vfp_access_check_m(DisasContext *s, bool skip_cont= ext_update) * the encoding space handled by the patterns in m-nocp.decode, * and for them we may need to raise NOCP here. */ - gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + gen_exception_insn_el(s, 0, EXCP_NOCP, syn_uncategorized(), s->fp_excp_el); return false; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 92c52edb7b..d441e31d3a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1103,32 +1103,33 @@ static void gen_exception(int excp, uint32_t syndro= me) tcg_constant_i32(syndrome)); } =20 -static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, +static void gen_exception_insn_el_v(DisasContext *s, int pc_diff, int excp, uint32_t syn, TCGv_i32 tcg_el) { if (s->aarch64) { - gen_a64_update_pc(s, pc - s->pc_curr); + gen_a64_update_pc(s, pc_diff); } else { gen_set_condexec(s); - gen_update_pc(s, pc - s->pc_curr); + gen_update_pc(s, pc_diff); } gen_exception_el_v(excp, syn, tcg_el); s->base.is_jmp =3D DISAS_NORETURN; } =20 -void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, +void gen_exception_insn_el(DisasContext *s, int pc_diff, int excp, uint32_t syn, uint32_t target_el) { - gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el)); + gen_exception_insn_el_v(s, pc_diff, excp, syn, + tcg_constant_i32(target_el)); } =20 -void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t s= yn) +void gen_exception_insn(DisasContext *s, int pc_diff, int excp, uint32_t s= yn) { if (s->aarch64) { - gen_a64_update_pc(s, pc - s->pc_curr); + gen_a64_update_pc(s, pc_diff); } else { gen_set_condexec(s); - gen_update_pc(s, pc - s->pc_curr); + gen_update_pc(s, pc_diff); } gen_exception(excp, syn); s->base.is_jmp =3D DISAS_NORETURN; @@ -1145,7 +1146,7 @@ static void gen_exception_bkpt_insn(DisasContext *s, = uint32_t syn) void unallocated_encoding(DisasContext *s) { /* Unallocated and reserved encodings are uncategorized */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized()); + gen_exception_insn(s, 0, EXCP_UDEF, syn_uncategorized()); } =20 /* Force a TB lookup after an instruction that changes the CPU state. */ @@ -2872,7 +2873,7 @@ static bool msr_banked_access_decode(DisasContext *s,= int r, int sysm, int rn, tcg_el =3D tcg_constant_i32(3); } =20 - gen_exception_insn_el_v(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn_el_v(s, 0, EXCP_UDEF, syn_uncategorized(), tcg_el); tcg_temp_free_i32(tcg_el); return false; @@ -2898,7 +2899,7 @@ static bool msr_banked_access_decode(DisasContext *s,= int r, int sysm, int rn, =20 undef: /* If we get here then some access check did not pass */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized()); + gen_exception_insn(s, 0, EXCP_UDEF, syn_uncategorized()); return false; } =20 @@ -5122,8 +5123,7 @@ static void gen_srs(DisasContext *s, * For the UNPREDICTABLE cases we choose to UNDEF. */ if (s->current_el =3D=3D 1 && !s->ns && mode =3D=3D ARM_CPU_MODE_MON) { - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, - syn_uncategorized(), 3); + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_uncategorized(), 3); return; } =20 @@ -8508,7 +8508,7 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a) * Do the check-and-raise-exception by hand. */ if (s->fp_excp_el) { - gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + gen_exception_insn_el(s, 0, EXCP_NOCP, syn_uncategorized(), s->fp_excp_el); return true; } @@ -8611,7 +8611,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a) tmp =3D load_cpu_field(v7m.ltpsize); tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc); tcg_temp_free_i32(tmp); - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized= ()); + gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized()); gen_set_label(skipexc); } =20 @@ -9081,7 +9081,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) * UsageFault exception. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized= ()); + gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized()); return; } =20 @@ -9090,7 +9090,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate()); + gen_exception_insn(s, 0, EXCP_UDEF, syn_illegalstate()); return; } =20 @@ -9655,7 +9655,7 @@ static void thumb_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF, syn_illegalstate()); + gen_exception_insn(dc, 0, EXCP_UDEF, syn_illegalstate()); return; } =20 @@ -9728,8 +9728,7 @@ static void thumb_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) */ tcg_remove_ops_after(dc->insn_eci_rewind); dc->condjmp =3D 0; - gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE, - syn_uncategorized()); + gen_exception_insn(dc, 0, EXCP_INVSTATE, syn_uncategorized()); } =20 arm_post_translate_insn(dc); --=20 2.34.1 From nobody Wed May 22 01:36:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1662460188; cv=none; d=zohomail.com; s=zohoarc; b=RQ57GyIydOj/kZjzQ4DIKDYFjtM/itOz8AOx8Z5ZOpPuNyzRbwIgyS3+ikAEUNzqWkdbfS6bNdbQoGPe4G4IvuceyWOtFYZK7JONjcE8h0orsEwcV3mgvUReLJt2QsOZS+lBZhB3e4u6YgsP+Clr4DaT598EU1ccqSzCDk6jdLk= ARC-Message-Signature: i=1; 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Tue, 06 Sep 2022 03:05:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 5/9] target/arm: Change gen_exception_internal to work on displacements Date: Tue, 6 Sep 2022 11:05:24 +0100 Message-Id: <20220906100528.343244-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220906100528.343244-1-richard.henderson@linaro.org> References: <20220906100528.343244-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1662460189008100001 Content-Type: text/plain; charset="utf-8" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/translate-a64.c | 6 +++--- target/arm/translate.c | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 17ea8b5650..9bb744fad3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -340,9 +340,9 @@ static void gen_exception_internal(int excp) gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp)); } =20 -static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int = excp) +static void gen_exception_internal_insn(DisasContext *s, int pc_diff, int = excp) { - gen_a64_update_pc(s, pc - s->pc_curr); + gen_a64_update_pc(s, pc_diff); gen_exception_internal(excp); s->base.is_jmp =3D DISAS_NORETURN; } @@ -2229,7 +2229,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) break; } #endif - gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); + gen_exception_internal_insn(s, 0, EXCP_SEMIHOST); } else { unallocated_encoding(s); } diff --git a/target/arm/translate.c b/target/arm/translate.c index d441e31d3a..63a41ed438 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1078,10 +1078,10 @@ static inline void gen_smc(DisasContext *s) s->base.is_jmp =3D DISAS_SMC; } =20 -static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int = excp) +static void gen_exception_internal_insn(DisasContext *s, int pc_diff, int = excp) { gen_set_condexec(s); - gen_update_pc(s, pc - s->pc_curr); + gen_update_pc(s, pc_diff); gen_exception_internal(excp); s->base.is_jmp =3D DISAS_NORETURN; } @@ -1175,7 +1175,7 @@ static inline void gen_hlt(DisasContext *s, int imm) s->current_el !=3D 0 && #endif (imm =3D=3D (s->thumb ? 0x3c : 0xf000))) { - gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); + gen_exception_internal_insn(s, 0, EXCP_SEMIHOST); return; } =20 @@ -6565,7 +6565,7 @@ static bool trans_BKPT(DisasContext *s, arg_BKPT *a) !IS_USER(s) && #endif (a->imm =3D=3D 0xab)) { - gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); + gen_exception_internal_insn(s, 0, EXCP_SEMIHOST); } else { gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); } @@ -8773,7 +8773,7 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a) !IS_USER(s) && #endif (a->imm =3D=3D semihost_imm)) { - gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); + gen_exception_internal_insn(s, 0, EXCP_SEMIHOST); } else { gen_update_pc(s, curr_insn_len(s)); s->svc_imm =3D a->imm; --=20 2.34.1 From nobody Wed May 22 01:36:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1662459535; cv=none; d=zohomail.com; s=zohoarc; b=hMxKUb4hdMXH7AP+FN4nTsh4cQmbWxb4NLjwiSO387SFUXlacaocOamESc5MA7wicf34g30twYCaRQkWYRzTqQsyhqiiyQpM4XdVtbnvJhHMPpYn5y+6EJxg2fkYAhhtK4mjrO3yn04/kMikTlK8j+KKbN1IgO2HVlhblBAIh9w= ARC-Message-Signature: i=1; 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Tue, 06 Sep 2022 03:05:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 6/9] target/arm: Change gen_jmp* to work on displacements Date: Tue, 6 Sep 2022 11:05:25 +0100 Message-Id: <20220906100528.343244-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220906100528.343244-1-richard.henderson@linaro.org> References: <20220906100528.343244-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1662459537589100001 Content-Type: text/plain; charset="utf-8" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson --- target/arm/translate.c | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 63a41ed438..4d13e365e2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -270,6 +270,12 @@ static uint32_t read_pc(DisasContext *s) return s->pc_curr + (s->thumb ? 4 : 8); } =20 +/* The pc_curr difference for an architectural jump. */ +static int jmp_diff(DisasContext *s, int diff) +{ + return diff + (s->thumb ? 4 : 8); +} + /* Set a variable to the value of a CPU register. */ void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) { @@ -2614,10 +2620,8 @@ static void gen_goto_tb(DisasContext *s, int n, int = diff) } =20 /* Jump, specifying which TB number to use if we gen_goto_tb() */ -static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno) +static void gen_jmp_tb(DisasContext *s, int diff, int tbno) { - int diff =3D dest - s->pc_curr; - if (unlikely(s->ss_active)) { /* An indirect jump so that we still trigger the debug exception. = */ gen_update_pc(s, diff); @@ -2659,9 +2663,9 @@ static inline void gen_jmp_tb(DisasContext *s, uint32= _t dest, int tbno) } } =20 -static inline void gen_jmp(DisasContext *s, uint32_t dest) +static inline void gen_jmp(DisasContext *s, int diff) { - gen_jmp_tb(s, dest, 0); + gen_jmp_tb(s, diff, 0); } =20 static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y) @@ -8331,7 +8335,7 @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a) =20 static bool trans_B(DisasContext *s, arg_i *a) { - gen_jmp(s, read_pc(s) + a->imm); + gen_jmp(s, jmp_diff(s, a->imm)); return true; } =20 @@ -8346,14 +8350,14 @@ static bool trans_B_cond_thumb(DisasContext *s, arg= _ci *a) return true; } arm_skip_unless(s, a->cond); - gen_jmp(s, read_pc(s) + a->imm); + gen_jmp(s, jmp_diff(s, a->imm)); return true; } =20 static bool trans_BL(DisasContext *s, arg_i *a) { tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); - gen_jmp(s, read_pc(s) + a->imm); + gen_jmp(s, jmp_diff(s, a->imm)); return true; } =20 @@ -8373,7 +8377,8 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) } tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); store_cpu_field_constant(!s->thumb, thumb); - gen_jmp(s, (read_pc(s) & ~3) + a->imm); + /* This difference computes a page offset so ok for TARGET_TB_PCREL. */ + gen_jmp(s, (read_pc(s) & ~3) - s->pc_curr + a->imm); return true; } =20 @@ -8534,10 +8539,10 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a) * when we take this upcoming exit from this TB, so gen_jmp_tb() i= s OK. */ } - gen_jmp_tb(s, s->base.pc_next, 1); + gen_jmp_tb(s, curr_insn_len(s), 1); =20 gen_set_label(nextlabel); - gen_jmp(s, read_pc(s) + a->imm); + gen_jmp(s, jmp_diff(s, a->imm)); return true; } =20 @@ -8617,7 +8622,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a) =20 if (a->f) { /* Loop-forever: just jump back to the loop start */ - gen_jmp(s, read_pc(s) - a->imm); + gen_jmp(s, jmp_diff(s, -a->imm)); return true; } =20 @@ -8648,7 +8653,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a) tcg_temp_free_i32(decr); } /* Jump back to the loop start */ - gen_jmp(s, read_pc(s) - a->imm); + gen_jmp(s, jmp_diff(s, -a->imm)); =20 gen_set_label(loopend); if (a->tp) { @@ -8656,7 +8661,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a) store_cpu_field(tcg_constant_i32(4), v7m.ltpsize); } /* End TB, continuing to following insn */ - gen_jmp_tb(s, s->base.pc_next, 1); + gen_jmp_tb(s, curr_insn_len(s), 1); return true; } =20 @@ -8755,7 +8760,7 @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a) tcg_gen_brcondi_i32(a->nz ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1662459072959100001 Content-Type: text/plain; charset="utf-8" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 41 +++++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9bb744fad3..7dd9b29dbf 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -148,9 +148,14 @@ static void reset_btype(DisasContext *s) } } =20 +static void gen_pc_plus_diff(DisasContext *s, TCGv_i64 dest, int diff) +{ + tcg_gen_movi_i64(dest, s->pc_curr + diff); +} + void gen_a64_update_pc(DisasContext *s, int diff) { - tcg_gen_movi_i64(cpu_pc, s->pc_curr + diff); + gen_pc_plus_diff(s, cpu_pc, diff); } =20 /* @@ -1368,7 +1373,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint3= 2_t insn) =20 if (insn & (1U << 31)) { /* BL Branch with link */ - tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); + gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s)); } =20 /* B Branch / BL Branch with link */ @@ -2319,11 +2324,17 @@ static void disas_uncond_b_reg(DisasContext *s, uin= t32_t insn) default: goto do_unallocated; } - gen_a64_set_pc(s, dst); /* BLR also needs to load return address */ if (opc =3D=3D 1) { - tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); + TCGv_i64 lr =3D cpu_reg(s, 30); + if (dst =3D=3D lr) { + TCGv_i64 tmp =3D new_tmp_a64(s); + tcg_gen_mov_i64(tmp, dst); + dst =3D tmp; + } + gen_pc_plus_diff(s, lr, curr_insn_len(s)); } + gen_a64_set_pc(s, dst); break; =20 case 8: /* BRAA */ @@ -2346,11 +2357,17 @@ static void disas_uncond_b_reg(DisasContext *s, uin= t32_t insn) } else { dst =3D cpu_reg(s, rn); } - gen_a64_set_pc(s, dst); /* BLRAA also needs to load return address */ if (opc =3D=3D 9) { - tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); + TCGv_i64 lr =3D cpu_reg(s, 30); + if (dst =3D=3D lr) { + TCGv_i64 tmp =3D new_tmp_a64(s); + tcg_gen_mov_i64(tmp, dst); + dst =3D tmp; + } + gen_pc_plus_diff(s, lr, curr_insn_len(s)); } + gen_a64_set_pc(s, dst); break; =20 case 4: /* ERET */ @@ -2918,7 +2935,8 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) =20 tcg_rt =3D cpu_reg(s, rt); =20 - clean_addr =3D tcg_constant_i64(s->pc_curr + imm); + clean_addr =3D new_tmp_a64(s); + gen_pc_plus_diff(s, clean_addr, imm); if (is_vector) { do_fp_ld(s, rt, clean_addr, size); } else { @@ -4262,23 +4280,22 @@ static void disas_ldst(DisasContext *s, uint32_t in= sn) static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) { unsigned int page, rd; - uint64_t base; - uint64_t offset; + int64_t offset; =20 page =3D extract32(insn, 31, 1); /* SignExtend(immhi:immlo) -> offset */ offset =3D sextract64(insn, 5, 19); offset =3D offset << 2 | extract32(insn, 29, 2); rd =3D extract32(insn, 0, 5); - base =3D s->pc_curr; =20 if (page) { /* ADRP (page based) */ - base &=3D ~0xfff; offset <<=3D 12; + /* The page offset is ok for TARGET_TB_PCREL. */ + offset -=3D s->pc_curr & 0xfff; } =20 - tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); + gen_pc_plus_diff(s, cpu_reg(s, rd), offset); } =20 /* --=20 2.34.1 From nobody Wed May 22 01:36:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1662460939605100001 Content-Type: text/plain; charset="utf-8" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/translate.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4d13e365e2..f01c8df60a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -276,11 +276,16 @@ static int jmp_diff(DisasContext *s, int diff) return diff + (s->thumb ? 4 : 8); } =20 +static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, int diff) +{ + tcg_gen_movi_i32(var, s->pc_curr + diff); +} + /* Set a variable to the value of a CPU register. */ void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) { if (reg =3D=3D 15) { - tcg_gen_movi_i32(var, read_pc(s)); + gen_pc_plus_diff(s, var, jmp_diff(s, 0)); } else { tcg_gen_mov_i32(var, cpu_R[reg]); } @@ -296,7 +301,8 @@ TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int = ofs) TCGv_i32 tmp =3D tcg_temp_new_i32(); =20 if (reg =3D=3D 15) { - tcg_gen_movi_i32(tmp, (read_pc(s) & ~3) + ofs); + /* This difference computes a page offset so ok for TARGET_TB_PCRE= L. */ + gen_pc_plus_diff(s, tmp, (read_pc(s) & ~3) - s->pc_curr + ofs); } else { tcg_gen_addi_i32(tmp, cpu_R[reg], ofs); } @@ -1158,7 +1164,7 @@ void unallocated_encoding(DisasContext *s) /* Force a TB lookup after an instruction that changes the CPU state. */ void gen_lookup_tb(DisasContext *s) { - tcg_gen_movi_i32(cpu_R[15], s->base.pc_next); + gen_pc_plus_diff(s, cpu_R[15], curr_insn_len(s)); s->base.is_jmp =3D DISAS_EXIT; } =20 @@ -6485,7 +6491,7 @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a) return false; } tmp =3D load_reg(s, a->rm); - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | s->thumb); gen_bx(s, tmp); return true; } @@ -8356,7 +8362,7 @@ static bool trans_B_cond_thumb(DisasContext *s, arg_c= i *a) =20 static bool trans_BL(DisasContext *s, arg_i *a) { - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | s->thumb); gen_jmp(s, jmp_diff(s, a->imm)); return true; } @@ -8375,7 +8381,7 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) if (s->thumb && (a->imm & 2)) { return false; } - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | s->thumb); store_cpu_field_constant(!s->thumb, thumb); /* This difference computes a page offset so ok for TARGET_TB_PCREL. */ gen_jmp(s, (read_pc(s) & ~3) - s->pc_curr + a->imm); @@ -8385,7 +8391,7 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) static bool trans_BL_BLX_prefix(DisasContext *s, arg_BL_BLX_prefix *a) { assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); - tcg_gen_movi_i32(cpu_R[14], read_pc(s) + (a->imm << 12)); + gen_pc_plus_diff(s, cpu_R[14], jmp_diff(s, a->imm << 12)); return true; } =20 @@ -8395,7 +8401,7 @@ static bool trans_BL_suffix(DisasContext *s, arg_BL_s= uffix *a) =20 assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); tcg_gen_addi_i32(tmp, cpu_R[14], (a->imm << 1) | 1); - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | 1); gen_bx(s, tmp); return true; } @@ -8411,7 +8417,7 @@ static bool trans_BLX_suffix(DisasContext *s, arg_BLX= _suffix *a) tmp =3D tcg_temp_new_i32(); tcg_gen_addi_i32(tmp, cpu_R[14], a->imm << 1); tcg_gen_andi_i32(tmp, tmp, 0xfffffffc); - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | 1); gen_bx(s, tmp); return true; } @@ -8734,10 +8740,11 @@ static bool op_tbranch(DisasContext *s, arg_tbranch= *a, bool half) tcg_gen_add_i32(addr, addr, tmp); =20 gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), half ? MO_UW : MO_UB); - tcg_temp_free_i32(addr); =20 tcg_gen_add_i32(tmp, tmp, tmp); - tcg_gen_addi_i32(tmp, tmp, read_pc(s)); + gen_pc_plus_diff(s, addr, jmp_diff(s, 0)); + tcg_gen_add_i32(tmp, tmp, addr); + tcg_temp_free_i32(addr); store_reg(s, 15, tmp); return true; } --=20 2.34.1 From nobody Wed May 22 01:36:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1662460175; cv=none; d=zohomail.com; s=zohoarc; b=SixYF4u7qhi/mEriCjVObVTvuLxmlYLnmVQUvpKEVY/wibkjmZGEFPx/RuVKr68Lx4oMVfrCYzTLraJtQn2BOFEAzB6uiRS7Sw+KCGJLAm+1cWu79dU0CHeZ9J2C0eRVoe1EfPWGPthYqWLgQIDkGssXoYzXZX9CTq7JHVwAApM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662460175; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1662460176896100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 ++ target/arm/translate.h | 6 ++++ target/arm/cpu.c | 23 +++++++------- target/arm/translate-a64.c | 37 ++++++++++++++++++----- target/arm/translate.c | 62 ++++++++++++++++++++++++++++++-------- 5 files changed, 100 insertions(+), 30 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 68ffb12427..ef62371d8f 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -34,4 +34,6 @@ =20 #define NB_MMU_MODES 15 =20 +#define TARGET_TB_PCREL 1 + #endif diff --git a/target/arm/translate.h b/target/arm/translate.h index d42059aa1d..7717ea3f45 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -12,6 +12,12 @@ typedef struct DisasContext { =20 /* The address of the current instruction being translated. */ target_ulong pc_curr; + /* + * For TARGET_TB_PCREL, the value relative to pc_curr against which + * offsets must be computed for cpu_pc. -1 if unknown due to jump. + */ + target_ulong pc_save; + target_ulong pc_cond_save; target_ulong page_start; uint32_t insn; /* Nonzero if this instruction has been conditionally skipped. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 047bf3f4ab..f5e74b6c3b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -64,17 +64,18 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - /* - * It's OK to look at env for the current mode here, because it's - * never possible for an AArch64 TB to chain to an AArch32 TB. - */ - if (is_a64(env)) { - env->pc =3D tb_pc(tb); - } else { - env->regs[15] =3D tb_pc(tb); + /* The program counter is always up to date with TARGET_TB_PCREL. */ + if (!TARGET_TB_PCREL) { + CPUARMState *env =3D cs->env_ptr; + /* + * It's OK to look at env for the current mode here, because it's + * never possible for an AArch64 TB to chain to an AArch32 TB. + */ + if (is_a64(env)) { + env->pc =3D tb_pc(tb); + } else { + env->regs[15] =3D tb_pc(tb); + } } } #endif /* CONFIG_TCG */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7dd9b29dbf..cd3e9bb3c0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -150,12 +150,18 @@ static void reset_btype(DisasContext *s) =20 static void gen_pc_plus_diff(DisasContext *s, TCGv_i64 dest, int diff) { - tcg_gen_movi_i64(dest, s->pc_curr + diff); + assert(s->pc_save !=3D -1); + if (TARGET_TB_PCREL) { + tcg_gen_addi_i64(dest, cpu_pc, (s->pc_curr - s->pc_save) + diff); + } else { + tcg_gen_movi_i64(dest, s->pc_curr + diff); + } } =20 void gen_a64_update_pc(DisasContext *s, int diff) { gen_pc_plus_diff(s, cpu_pc, diff); + s->pc_save =3D s->pc_curr + diff; } =20 /* @@ -209,6 +215,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 sr= c) * then loading an address into the PC will clear out any tag. */ gen_top_byte_ignore(s, cpu_pc, src, s->tbii); + s->pc_save =3D -1; } =20 /* @@ -347,16 +354,22 @@ static void gen_exception_internal(int excp) =20 static void gen_exception_internal_insn(DisasContext *s, int pc_diff, int = excp) { + target_ulong pc_save =3D s->pc_save; + gen_a64_update_pc(s, pc_diff); gen_exception_internal(excp); s->base.is_jmp =3D DISAS_NORETURN; + s->pc_save =3D pc_save; } =20 static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome) { + target_ulong pc_save =3D s->pc_save; + gen_a64_update_pc(s, 0); gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome)); s->base.is_jmp =3D DISAS_NORETURN; + s->pc_save =3D pc_save; } =20 static void gen_step_complete_exception(DisasContext *s) @@ -385,11 +398,16 @@ static inline bool use_goto_tb(DisasContext *s, uint6= 4_t dest) =20 static void gen_goto_tb(DisasContext *s, int n, int diff) { - uint64_t dest =3D s->pc_curr + diff; + target_ulong pc_save =3D s->pc_save; =20 - if (use_goto_tb(s, dest)) { - tcg_gen_goto_tb(n); - gen_a64_update_pc(s, diff); + if (use_goto_tb(s, s->pc_curr + diff)) { + if (TARGET_TB_PCREL) { + gen_a64_update_pc(s, diff); + tcg_gen_goto_tb(n); + } else { + tcg_gen_goto_tb(n); + gen_a64_update_pc(s, diff); + } tcg_gen_exit_tb(s->base.tb, n); s->base.is_jmp =3D DISAS_NORETURN; } else { @@ -401,6 +419,7 @@ static void gen_goto_tb(DisasContext *s, int n, int dif= f) s->base.is_jmp =3D DISAS_NORETURN; } } + s->pc_save =3D pc_save; } =20 static void init_tmp_a64_array(DisasContext *s) @@ -14717,7 +14736,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, =20 dc->isar =3D &arm_cpu->isar; dc->condjmp =3D 0; - + dc->pc_save =3D dc->base.pc_first; dc->aarch64 =3D true; dc->thumb =3D false; dc->sctlr_b =3D 0; @@ -14799,8 +14818,12 @@ static void aarch64_tr_tb_start(DisasContextBase *= db, CPUState *cpu) static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); + target_ulong pc_arg =3D dc->base.pc_next; =20 - tcg_gen_insn_start(dc->base.pc_next, 0, 0); + if (TARGET_TB_PCREL) { + pc_arg &=3D ~TARGET_PAGE_MASK; + } + tcg_gen_insn_start(pc_arg, 0, 0); dc->insn_start =3D tcg_last_op(); } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index f01c8df60a..a25ba48e87 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -164,6 +164,7 @@ void arm_gen_condlabel(DisasContext *s) if (!s->condjmp) { s->condlabel =3D gen_new_label(); s->condjmp =3D 1; + s->pc_cond_save =3D s->pc_save; } } =20 @@ -278,7 +279,12 @@ static int jmp_diff(DisasContext *s, int diff) =20 static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, int diff) { - tcg_gen_movi_i32(var, s->pc_curr + diff); + assert(s->pc_save !=3D -1); + if (TARGET_TB_PCREL) { + tcg_gen_addi_i32(var, cpu_R[15], (s->pc_curr - s->pc_save) + diff); + } else { + tcg_gen_movi_i32(var, s->pc_curr + diff); + } } =20 /* Set a variable to the value of a CPU register. */ @@ -321,6 +327,7 @@ void store_reg(DisasContext *s, int reg, TCGv_i32 var) */ tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3); s->base.is_jmp =3D DISAS_JUMP; + s->pc_save =3D -1; } else if (reg =3D=3D 13 && arm_dc_feature(s, ARM_FEATURE_M)) { /* For M-profile SP bits [1:0] are always zero */ tcg_gen_andi_i32(var, var, ~3); @@ -786,7 +793,8 @@ void gen_set_condexec(DisasContext *s) =20 void gen_update_pc(DisasContext *s, int diff) { - tcg_gen_movi_i32(cpu_R[15], s->pc_curr + diff); + gen_pc_plus_diff(s, cpu_R[15], diff); + s->pc_save =3D s->pc_curr + diff; } =20 /* Set PC and Thumb state from var. var is marked as dead. */ @@ -796,6 +804,7 @@ static inline void gen_bx(DisasContext *s, TCGv_i32 var) tcg_gen_andi_i32(cpu_R[15], var, ~1); tcg_gen_andi_i32(var, var, 1); store_cpu_field(var, thumb); + s->pc_save =3D -1; } =20 /* @@ -1118,6 +1127,8 @@ static void gen_exception(int excp, uint32_t syndrome) static void gen_exception_insn_el_v(DisasContext *s, int pc_diff, int excp, uint32_t syn, TCGv_i32 tcg_el) { + target_ulong pc_save =3D s->pc_save; + if (s->aarch64) { gen_a64_update_pc(s, pc_diff); } else { @@ -1126,6 +1137,7 @@ static void gen_exception_insn_el_v(DisasContext *s, = int pc_diff, int excp, } gen_exception_el_v(excp, syn, tcg_el); s->base.is_jmp =3D DISAS_NORETURN; + s->pc_save =3D pc_save; } =20 void gen_exception_insn_el(DisasContext *s, int pc_diff, int excp, @@ -1137,6 +1149,8 @@ void gen_exception_insn_el(DisasContext *s, int pc_di= ff, int excp, =20 void gen_exception_insn(DisasContext *s, int pc_diff, int excp, uint32_t s= yn) { + target_ulong pc_save =3D s->pc_save; + if (s->aarch64) { gen_a64_update_pc(s, pc_diff); } else { @@ -1145,6 +1159,7 @@ void gen_exception_insn(DisasContext *s, int pc_diff,= int excp, uint32_t syn) } gen_exception(excp, syn); s->base.is_jmp =3D DISAS_NORETURN; + s->pc_save =3D pc_save; } =20 static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) @@ -2612,11 +2627,14 @@ static void gen_goto_ptr(void) */ static void gen_goto_tb(DisasContext *s, int n, int diff) { - target_ulong dest =3D s->pc_curr + diff; - - if (translator_use_goto_tb(&s->base, dest)) { - tcg_gen_goto_tb(n); - gen_update_pc(s, diff); + if (translator_use_goto_tb(&s->base, s->pc_curr + diff)) { + if (TARGET_TB_PCREL) { + gen_update_pc(s, diff); + tcg_gen_goto_tb(n); + } else { + tcg_gen_goto_tb(n); + gen_update_pc(s, diff); + } tcg_gen_exit_tb(s->base.tb, n); } else { gen_update_pc(s, diff); @@ -2628,10 +2646,13 @@ static void gen_goto_tb(DisasContext *s, int n, int= diff) /* Jump, specifying which TB number to use if we gen_goto_tb() */ static void gen_jmp_tb(DisasContext *s, int diff, int tbno) { + target_ulong pc_save =3D s->pc_save; + if (unlikely(s->ss_active)) { /* An indirect jump so that we still trigger the debug exception. = */ gen_update_pc(s, diff); s->base.is_jmp =3D DISAS_JUMP; + s->pc_save =3D pc_save; return; } switch (s->base.is_jmp) { @@ -2667,6 +2688,7 @@ static void gen_jmp_tb(DisasContext *s, int diff, int= tbno) */ g_assert_not_reached(); } + s->pc_save =3D pc_save; } =20 static inline void gen_jmp(DisasContext *s, int diff) @@ -9333,7 +9355,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) =20 dc->isar =3D &cpu->isar; dc->condjmp =3D 0; - + dc->pc_save =3D dc->base.pc_first; dc->aarch64 =3D false; dc->thumb =3D EX_TBFLAG_AM32(tb_flags, THUMB); dc->be_data =3D EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; @@ -9488,13 +9510,17 @@ static void arm_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) * fields here. */ uint32_t condexec_bits; + target_ulong pc_arg =3D dc->base.pc_next; =20 + if (TARGET_TB_PCREL) { + pc_arg &=3D ~TARGET_PAGE_MASK; + } if (dc->eci) { condexec_bits =3D dc->eci << 4; } else { condexec_bits =3D (dc->condexec_cond << 4) | (dc->condexec_mask >>= 1); } - tcg_gen_insn_start(dc->base.pc_next, condexec_bits, 0); + tcg_gen_insn_start(pc_arg, condexec_bits, 0); dc->insn_start =3D tcg_last_op(); } =20 @@ -9537,7 +9563,10 @@ static bool arm_check_ss_active(DisasContext *dc) =20 static void arm_post_translate_insn(DisasContext *dc) { - if (dc->condjmp && !dc->base.is_jmp) { + if (dc->condjmp && dc->base.is_jmp =3D=3D DISAS_NEXT) { + if (dc->pc_save !=3D dc->pc_cond_save) { + gen_update_pc(dc, dc->pc_cond_save - dc->pc_save); + } gen_set_label(dc->condlabel); dc->condjmp =3D 0; } @@ -9867,6 +9896,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) =20 if (dc->condjmp) { /* "Condition failed" instruction codepath for the branch/trap ins= n */ + dc->pc_save =3D dc->pc_cond_save; gen_set_label(dc->condlabel); gen_set_condexec(dc); if (unlikely(dc->ss_active)) { @@ -9929,11 +9959,19 @@ void restore_state_to_opc(CPUARMState *env, Transla= tionBlock *tb, target_ulong *data) { if (is_a64(env)) { - env->pc =3D data[0]; + if (TARGET_TB_PCREL) { + env->pc =3D (env->pc & TARGET_PAGE_MASK) | data[0]; + } else { + env->pc =3D data[0]; + } env->condexec_bits =3D 0; env->exception.syndrome =3D data[2] << ARM_INSN_START_WORD2_SHIFT; } else { - env->regs[15] =3D data[0]; + if (TARGET_TB_PCREL) { + env->regs[15] =3D (env->regs[15] & TARGET_PAGE_MASK) | data[0]; + } else { + env->regs[15] =3D data[0]; + } env->condexec_bits =3D data[1]; env->exception.syndrome =3D data[2] << ARM_INSN_START_WORD2_SHIFT; } --=20 2.34.1