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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1662409574171100001 Content-Type: text/plain; charset="utf-8" This structure will shortly contain more than just data for accessing MMIO. Rename the 'addr' member to 'xlat_section' to more clearly indicate its purpose. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-defs.h | 22 ++++---- accel/tcg/cputlb.c | 102 +++++++++++++++++++------------------ target/arm/mte_helper.c | 14 ++--- target/arm/sve_helper.c | 4 +- target/arm/translate-a64.c | 2 +- 5 files changed, 73 insertions(+), 71 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index ba3cd32a1e..f70f54d850 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -108,6 +108,7 @@ typedef uint64_t target_ulong; # endif # endif =20 +/* Minimalized TLB entry for use by TCG fast path. */ typedef struct CPUTLBEntry { /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not @@ -131,14 +132,14 @@ typedef struct CPUTLBEntry { =20 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) !=3D (1 << CPU_TLB_ENTRY_BITS)); =20 -/* The IOTLB is not accessed directly inline by generated TCG code, - * so the CPUIOTLBEntry layout is not as critical as that of the - * CPUTLBEntry. (This is also why we don't want to combine the two - * structs into one.) +/* + * The full TLB entry, which is not accessed by generated TCG code, + * so the layout is not as critical as that of CPUTLBEntry. This is + * also why we don't want to combine the two structs. */ -typedef struct CPUIOTLBEntry { +typedef struct CPUTLBEntryFull { /* - * @addr contains: + * @xlat_section contains: * - in the lower TARGET_PAGE_BITS, a physical section number * - with the lower TARGET_PAGE_BITS masked off, an offset which * must be added to the virtual address to obtain: @@ -146,9 +147,9 @@ typedef struct CPUIOTLBEntry { * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) * + the offset within the target MemoryRegion (otherwise) */ - hwaddr addr; + hwaddr xlat_section; MemTxAttrs attrs; -} CPUIOTLBEntry; +} CPUTLBEntryFull; =20 /* * Data elements that are per MMU mode, minus the bits accessed by @@ -172,9 +173,8 @@ typedef struct CPUTLBDesc { size_t vindex; /* The tlb victim table, in two parts. */ CPUTLBEntry vtable[CPU_VTLB_SIZE]; - CPUIOTLBEntry viotlb[CPU_VTLB_SIZE]; - /* The iotlb. */ - CPUIOTLBEntry *iotlb; + CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE]; + CPUTLBEntryFull *fulltlb; } CPUTLBDesc; =20 /* diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 8fad2d9b83..4585d7c015 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -200,13 +200,13 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, C= PUTLBDescFast *fast, } =20 g_free(fast->table); - g_free(desc->iotlb); + g_free(desc->fulltlb); =20 tlb_window_reset(desc, now, 0); /* desc->n_used_entries is cleared by the caller */ fast->mask =3D (new_size - 1) << CPU_TLB_ENTRY_BITS; fast->table =3D g_try_new(CPUTLBEntry, new_size); - desc->iotlb =3D g_try_new(CPUIOTLBEntry, new_size); + desc->fulltlb =3D g_try_new(CPUTLBEntryFull, new_size); =20 /* * If the allocations fail, try smaller sizes. We just freed some @@ -215,7 +215,7 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPU= TLBDescFast *fast, * allocations to fail though, so we progressively reduce the allocati= on * size, aborting if we cannot even allocate the smallest TLB we suppo= rt. */ - while (fast->table =3D=3D NULL || desc->iotlb =3D=3D NULL) { + while (fast->table =3D=3D NULL || desc->fulltlb =3D=3D NULL) { if (new_size =3D=3D (1 << CPU_TLB_DYN_MIN_BITS)) { error_report("%s: %s", __func__, strerror(errno)); abort(); @@ -224,9 +224,9 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPU= TLBDescFast *fast, fast->mask =3D (new_size - 1) << CPU_TLB_ENTRY_BITS; =20 g_free(fast->table); - g_free(desc->iotlb); + g_free(desc->fulltlb); fast->table =3D g_try_new(CPUTLBEntry, new_size); - desc->iotlb =3D g_try_new(CPUIOTLBEntry, new_size); + desc->fulltlb =3D g_try_new(CPUTLBEntryFull, new_size); } } =20 @@ -258,7 +258,7 @@ static void tlb_mmu_init(CPUTLBDesc *desc, CPUTLBDescFa= st *fast, int64_t now) desc->n_used_entries =3D 0; fast->mask =3D (n_entries - 1) << CPU_TLB_ENTRY_BITS; fast->table =3D g_new(CPUTLBEntry, n_entries); - desc->iotlb =3D g_new(CPUIOTLBEntry, n_entries); + desc->fulltlb =3D g_new(CPUTLBEntryFull, n_entries); tlb_mmu_flush_locked(desc, fast); } =20 @@ -299,7 +299,7 @@ void tlb_destroy(CPUState *cpu) CPUTLBDescFast *fast =3D &env_tlb(env)->f[i]; =20 g_free(fast->table); - g_free(desc->iotlb); + g_free(desc->fulltlb); } } =20 @@ -1219,7 +1219,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, =20 /* Evict the old entry into the victim tlb. */ copy_tlb_helper_locked(tv, te); - desc->viotlb[vidx] =3D desc->iotlb[index]; + desc->vfulltlb[vidx] =3D desc->fulltlb[index]; tlb_n_used_entries_dec(env, mmu_idx); } =20 @@ -1236,8 +1236,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, * subtract here is that of the page base, and not the same as the * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). */ - desc->iotlb[index].addr =3D iotlb - vaddr_page; - desc->iotlb[index].attrs =3D attrs; + desc->fulltlb[index].xlat_section =3D iotlb - vaddr_page; + desc->fulltlb[index].attrs =3D attrs; =20 /* Now calculate the new entry */ tn.addend =3D addend - vaddr_page; @@ -1329,7 +1329,7 @@ static inline void cpu_transaction_failed(CPUState *c= pu, hwaddr physaddr, } } =20 -static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, +static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full, int mmu_idx, target_ulong addr, uintptr_t retaddr, MMUAccessType access_type, MemOp op) { @@ -1341,9 +1341,9 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBE= ntry *iotlbentry, bool locked =3D false; MemTxResult r; =20 - section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); + section =3D iotlb_to_section(cpu, full->xlat_section, full->attrs); mr =3D section->mr; - mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; + mr_offset =3D (full->xlat_section & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc =3D retaddr; if (!cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); @@ -1353,14 +1353,14 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTL= BEntry *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_read(mr, mr_offset, &val, op, iotlbentry-= >attrs); + r =3D memory_region_dispatch_read(mr, mr_offset, &val, op, full->attrs= ); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - section->offset_within_region; =20 cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), access= _type, - mmu_idx, iotlbentry->attrs, r, retaddr); + mmu_idx, full->attrs, r, retaddr); } if (locked) { qemu_mutex_unlock_iothread(); @@ -1370,8 +1370,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBE= ntry *iotlbentry, } =20 /* - * Save a potentially trashed IOTLB entry for later lookup by plugin. - * This is read by tlb_plugin_lookup if the iotlb entry doesn't match + * Save a potentially trashed CPUTLBEntryFull for later lookup by plugin. + * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match * because of the side effect of io_writex changing memory layout. */ static void save_iotlb_data(CPUState *cs, hwaddr addr, @@ -1385,7 +1385,7 @@ static void save_iotlb_data(CPUState *cs, hwaddr addr, #endif } =20 -static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, +static void io_writex(CPUArchState *env, CPUTLBEntryFull *full, int mmu_idx, uint64_t val, target_ulong addr, uintptr_t retaddr, MemOp op) { @@ -1396,9 +1396,9 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntr= y *iotlbentry, bool locked =3D false; MemTxResult r; =20 - section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); + section =3D iotlb_to_section(cpu, full->xlat_section, full->attrs); mr =3D section->mr; - mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; + mr_offset =3D (full->xlat_section & TARGET_PAGE_MASK) + addr; if (!cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); } @@ -1408,20 +1408,20 @@ static void io_writex(CPUArchState *env, CPUIOTLBEn= try *iotlbentry, * The memory_region_dispatch may trigger a flush/resize * so for plugins we save the iotlb_data just in case. */ - save_iotlb_data(cpu, iotlbentry->addr, section, mr_offset); + save_iotlb_data(cpu, full->xlat_section, section, mr_offset); =20 if (!qemu_mutex_iothread_locked()) { qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_write(mr, mr_offset, val, op, iotlbentry-= >attrs); + r =3D memory_region_dispatch_write(mr, mr_offset, val, op, full->attrs= ); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - section->offset_within_region; =20 cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), - MMU_DATA_STORE, mmu_idx, iotlbentry->attrs,= r, + MMU_DATA_STORE, mmu_idx, full->attrs, r, retaddr); } if (locked) { @@ -1468,9 +1468,10 @@ static bool victim_tlb_hit(CPUArchState *env, size_t= mmu_idx, size_t index, copy_tlb_helper_locked(vtlb, &tmptlb); qemu_spin_unlock(&env_tlb(env)->c.lock); =20 - CPUIOTLBEntry tmpio, *io =3D &env_tlb(env)->d[mmu_idx].iotlb[i= ndex]; - CPUIOTLBEntry *vio =3D &env_tlb(env)->d[mmu_idx].viotlb[vidx]; - tmpio =3D *io; *io =3D *vio; *vio =3D tmpio; + CPUTLBEntryFull *f1 =3D &env_tlb(env)->d[mmu_idx].fulltlb[inde= x]; + CPUTLBEntryFull *f2 =3D &env_tlb(env)->d[mmu_idx].vfulltlb[vid= x]; + CPUTLBEntryFull tmpf; + tmpf =3D *f1; *f1 =3D *f2; *f2 =3D tmpf; return true; } } @@ -1483,9 +1484,9 @@ static bool victim_tlb_hit(CPUArchState *env, size_t = mmu_idx, size_t index, (ADDR) & TARGET_PAGE_MASK) =20 static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size, - CPUIOTLBEntry *iotlbentry, uintptr_t retaddr) + CPUTLBEntryFull *full, uintptr_t retaddr) { - ram_addr_t ram_addr =3D mem_vaddr + iotlbentry->addr; + ram_addr_t ram_addr =3D mem_vaddr + full->xlat_section; =20 trace_memory_notdirty_write_access(mem_vaddr, ram_addr, size); =20 @@ -1578,9 +1579,9 @@ int probe_access_flags(CPUArchState *env, target_ulon= g addr, /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUIOTLBEntry *iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[inde= x]; + CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; =20 - notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr); + notdirty_write(env_cpu(env), addr, 1, full, retaddr); flags &=3D ~TLB_NOTDIRTY; } =20 @@ -1605,19 +1606,19 @@ void *probe_access(CPUArchState *env, target_ulong = addr, int size, =20 if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) { uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUIOTLBEntry *iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[inde= x]; + CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; =20 /* Handle watchpoints. */ if (flags & TLB_WATCHPOINT) { int wp_access =3D (access_type =3D=3D MMU_DATA_STORE ? BP_MEM_WRITE : BP_MEM_READ); cpu_check_watchpoint(env_cpu(env), addr, size, - iotlbentry->attrs, wp_access, retaddr); + full->attrs, wp_access, retaddr); } =20 /* Handle clean RAM pages. */ if (flags & TLB_NOTDIRTY) { - notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr); + notdirty_write(env_cpu(env), addr, 1, full, retaddr); } } =20 @@ -1674,7 +1675,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState = *env, target_ulong addr, * should have just filled the TLB. The one corner case is io_writex * which can cause TLB flushes and potential resizing of the TLBs * losing the information we need. In those cases we need to recover - * data from a copy of the iotlbentry. As long as this always occurs + * data from a copy of the CPUTLBEntryFull. As long as this always occurs * from the same thread (which a mem callback will be) this is safe. */ =20 @@ -1689,11 +1690,12 @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong = addr, int mmu_idx, if (likely(tlb_hit(tlb_addr, addr))) { /* We must have an iotlb entry for MMIO */ if (tlb_addr & TLB_MMIO) { - CPUIOTLBEntry *iotlbentry; - iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[index]; + CPUTLBEntryFull *full; + full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; data->is_io =3D true; - data->v.io.section =3D iotlb_to_section(cpu, iotlbentry->addr,= iotlbentry->attrs); - data->v.io.offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + = addr; + data->v.io.section =3D + iotlb_to_section(cpu, full->xlat_section, full->attrs); + data->v.io.offset =3D (full->xlat_section & TARGET_PAGE_MASK) = + addr; } else { data->is_io =3D false; data->v.ram.hostaddr =3D (void *)((uintptr_t)addr + tlbe->adde= nd); @@ -1801,7 +1803,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, =20 if (unlikely(tlb_addr & TLB_NOTDIRTY)) { notdirty_write(env_cpu(env), addr, size, - &env_tlb(env)->d[mmu_idx].iotlb[index], retaddr); + &env_tlb(env)->d[mmu_idx].fulltlb[index], retaddr); } =20 return hostaddr; @@ -1909,7 +1911,7 @@ load_helper(CPUArchState *env, target_ulong addr, Mem= OpIdx oi, =20 /* Handle anything that isn't just a straight memory access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - CPUIOTLBEntry *iotlbentry; + CPUTLBEntryFull *full; bool need_swap; =20 /* For anything that is unaligned, recurse through full_load. */ @@ -1917,20 +1919,20 @@ load_helper(CPUArchState *env, target_ulong addr, M= emOpIdx oi, goto do_unaligned_access; } =20 - iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[index]; + full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; =20 /* Handle watchpoints. */ if (unlikely(tlb_addr & TLB_WATCHPOINT)) { /* On watchpoint hit, this will longjmp out. */ cpu_check_watchpoint(env_cpu(env), addr, size, - iotlbentry->attrs, BP_MEM_READ, retaddr); + full->attrs, BP_MEM_READ, retaddr); } =20 need_swap =3D size > 1 && (tlb_addr & TLB_BSWAP); =20 /* Handle I/O access. */ if (likely(tlb_addr & TLB_MMIO)) { - return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, + return io_readx(env, full, mmu_idx, addr, retaddr, access_type, op ^ (need_swap * MO_BSWAP)); } =20 @@ -2245,12 +2247,12 @@ store_helper_unaligned(CPUArchState *env, target_ul= ong addr, uint64_t val, */ if (unlikely(tlb_addr & TLB_WATCHPOINT)) { cpu_check_watchpoint(env_cpu(env), addr, size - size2, - env_tlb(env)->d[mmu_idx].iotlb[index].attrs, + env_tlb(env)->d[mmu_idx].fulltlb[index].attrs, BP_MEM_WRITE, retaddr); } if (unlikely(tlb_addr2 & TLB_WATCHPOINT)) { cpu_check_watchpoint(env_cpu(env), page2, size2, - env_tlb(env)->d[mmu_idx].iotlb[index2].attrs, + env_tlb(env)->d[mmu_idx].fulltlb[index2].attr= s, BP_MEM_WRITE, retaddr); } =20 @@ -2314,7 +2316,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, =20 /* Handle anything that isn't just a straight memory access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - CPUIOTLBEntry *iotlbentry; + CPUTLBEntryFull *full; bool need_swap; =20 /* For anything that is unaligned, recurse through byte stores. */ @@ -2322,20 +2324,20 @@ store_helper(CPUArchState *env, target_ulong addr, = uint64_t val, goto do_unaligned_access; } =20 - iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[index]; + full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; =20 /* Handle watchpoints. */ if (unlikely(tlb_addr & TLB_WATCHPOINT)) { /* On watchpoint hit, this will longjmp out. */ cpu_check_watchpoint(env_cpu(env), addr, size, - iotlbentry->attrs, BP_MEM_WRITE, retaddr); + full->attrs, BP_MEM_WRITE, retaddr); } =20 need_swap =3D size > 1 && (tlb_addr & TLB_BSWAP); =20 /* Handle I/O access. */ if (tlb_addr & TLB_MMIO) { - io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, + io_writex(env, full, mmu_idx, val, addr, retaddr, op ^ (need_swap * MO_BSWAP)); return; } @@ -2347,7 +2349,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, =20 /* Handle clean RAM pages. */ if (tlb_addr & TLB_NOTDIRTY) { - notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr); + notdirty_write(env_cpu(env), addr, size, full, retaddr); } =20 haddr =3D (void *)((uintptr_t)addr + entry->addend); diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index d11a8c70d0..fdd23ab3f8 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -106,7 +106,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, return tags + index; #else uintptr_t index; - CPUIOTLBEntry *iotlbentry; + CPUTLBEntryFull *full; int in_page, flags; ram_addr_t ptr_ra; hwaddr ptr_paddr, tag_paddr, xlat; @@ -129,7 +129,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, assert(!(flags & TLB_INVALID_MASK)); =20 /* - * Find the iotlbentry for ptr. This *must* be present in the TLB + * Find the CPUTLBEntryFull for ptr. This *must* be present in the TLB * because we just found the mapping. * TODO: Perhaps there should be a cputlb helper that returns a * matching tlb entry + iotlb entry. @@ -144,10 +144,10 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, = int ptr_mmu_idx, g_assert(tlb_hit(comparator, ptr)); } # endif - iotlbentry =3D &env_tlb(env)->d[ptr_mmu_idx].iotlb[index]; + full =3D &env_tlb(env)->d[ptr_mmu_idx].fulltlb[index]; =20 /* If the virtual page MemAttr !=3D Tagged, access unchecked. */ - if (!arm_tlb_mte_tagged(&iotlbentry->attrs)) { + if (!arm_tlb_mte_tagged(&full->attrs)) { return NULL; } =20 @@ -181,7 +181,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, int wp =3D ptr_access =3D=3D MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_= WRITE; assert(ra !=3D 0); cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, - iotlbentry->attrs, wp, ra); + full->attrs, wp, ra); } =20 /* @@ -202,11 +202,11 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, = int ptr_mmu_idx, tag_paddr =3D ptr_paddr >> (LOG2_TAG_GRANULE + 1); =20 /* Look up the address in tag space. */ - tag_asi =3D iotlbentry->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; + tag_asi =3D full->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; tag_as =3D cpu_get_address_space(env_cpu(env), tag_asi); mr =3D address_space_translate(tag_as, tag_paddr, &xlat, NULL, tag_access =3D=3D MMU_DATA_STORE, - iotlbentry->attrs); + full->attrs); =20 /* * Note that @mr will never be NULL. If there is nothing in the addre= ss diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index d6f7ef94fe..9cae8fd352 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -5384,8 +5384,8 @@ bool sve_probe_page(SVEHostPage *info, bool nofault, = CPUARMState *env, g_assert(tlb_hit(comparator, addr)); # endif =20 - CPUIOTLBEntry *iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[inde= x]; - info->attrs =3D iotlbentry->attrs; + CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + info->attrs =3D full->attrs; } #endif =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 163df8c615..b7787e7786 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14634,7 +14634,7 @@ static bool is_guarded_page(CPUARMState *env, Disas= Context *s) * table entry even for that case. */ return (tlb_hit(entry->addr_code, addr) && - arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].iotlb[index].attrs)); + arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].fulltlb[index].attrs)= ); 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Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 1 - accel/tcg/cputlb.c | 7 +++---- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 500503da13..9e47184513 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -218,7 +218,6 @@ struct CPUWatchpoint { * the memory regions get moved around by io_writex. */ typedef struct SavedIOTLB { - hwaddr addr; MemoryRegionSection *section; hwaddr mr_offset; } SavedIOTLB; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 4585d7c015..03395e725d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1374,12 +1374,11 @@ static uint64_t io_readx(CPUArchState *env, CPUTLBE= ntryFull *full, * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match * because of the side effect of io_writex changing memory layout. */ -static void save_iotlb_data(CPUState *cs, hwaddr addr, - MemoryRegionSection *section, hwaddr mr_offset) +static void save_iotlb_data(CPUState *cs, MemoryRegionSection *section, + hwaddr mr_offset) { #ifdef CONFIG_PLUGIN SavedIOTLB *saved =3D &cs->saved_iotlb; - saved->addr =3D addr; saved->section =3D section; saved->mr_offset =3D mr_offset; #endif @@ -1408,7 +1407,7 @@ static void io_writex(CPUArchState *env, CPUTLBEntryF= ull *full, * The memory_region_dispatch may trigger a flush/resize * so for plugins we save the iotlb_data just in case. */ - save_iotlb_data(cpu, full->xlat_section, section, mr_offset); + save_iotlb_data(cpu, section, mr_offset); =20 if (!qemu_mutex_iothread_locked()) { qemu_mutex_lock_iothread(); --=20 2.34.1 From nobody Tue May 21 00:58:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1662409514; cv=none; d=zohomail.com; s=zohoarc; b=dy8jeYazJ+qkqx6CwR1g+JoZRQuxPcH4UZW7U4rfX/xoN2/VCzPxSgPZZtf1dLne1jvTOq1npa6n3yVbZ0JYoFubDUPlSu6KbLMUdBGarhWZviNYSbiRbM7RoOj8MDtG1tS+cX43VDfLThYZwGNe9ck2FEe7EWUiUBGGSX2AqkI= ARC-Message-Signature: i=1; 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Mon, 05 Sep 2022 13:23:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, qemu-arm@nongnu.org, pbonzini@redhat.com, David Hildenbrand Subject: [PATCH v3 3/6] accel/tcg: Suppress auto-invalidate in probe_access_internal Date: Mon, 5 Sep 2022 21:22:56 +0100 Message-Id: <20220905202259.189852-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220905202259.189852-1-richard.henderson@linaro.org> References: <20220905202259.189852-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1662409515780100002 Content-Type: text/plain; charset="utf-8" When PAGE_WRITE_INV is set when calling tlb_set_page, we immediately set TLB_INVALID_MASK in order to force tlb_fill to be called on the next lookup. Here in probe_access_internal, we have just called tlb_fill and eliminated true misses, thus the lookup must be valid. This allows us to remove a warning comment from s390x. There doesn't seem to be a reason to change the code though. Cc: David Hildenbrand Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- accel/tcg/cputlb.c | 10 +++++++++- target/s390x/tcg/mem_helper.c | 4 ---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 03395e725d..91f2b53142 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1535,6 +1535,7 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, } tlb_addr =3D tlb_read_ofs(entry, elt_ofs); =20 + flags =3D TLB_FLAGS_MASK; page_addr =3D addr & TARGET_PAGE_MASK; if (!tlb_hit_page(tlb_addr, page_addr)) { if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) { @@ -1550,10 +1551,17 @@ static int probe_access_internal(CPUArchState *env,= target_ulong addr, =20 /* TLB resize via tlb_fill may have moved the entry. */ entry =3D tlb_entry(env, mmu_idx, addr); + + /* + * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately, + * to force the next access through tlb_fill. We've just + * called tlb_fill, so we know that this entry *is* valid. + */ + flags &=3D ~TLB_INVALID_MASK; } tlb_addr =3D tlb_read_ofs(entry, elt_ofs); } - flags =3D tlb_addr & TLB_FLAGS_MASK; + flags &=3D tlb_addr; =20 /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) { diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index fc52aa128b..3758b9e688 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -148,10 +148,6 @@ static int s390_probe_access(CPUArchState *env, target= _ulong addr, int size, #else int flags; =20 - /* - * For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr= =3D=3DNULL - * to detect if there was an exception during tlb_fill(). - */ env->tlb_fill_exc =3D 0; flags =3D probe_access_flags(env, addr, access_type, mmu_idx, nonfault= , phost, ra); --=20 2.34.1 From nobody Tue May 21 00:58:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Mon, 05 Sep 2022 13:23:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, qemu-arm@nongnu.org, pbonzini@redhat.com Subject: [PATCH v3 4/6] accel/tcg: Introduce probe_access_full Date: Mon, 5 Sep 2022 21:22:57 +0100 Message-Id: <20220905202259.189852-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220905202259.189852-1-richard.henderson@linaro.org> References: <20220905202259.189852-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1662409801698100001 Content-Type: text/plain; charset="utf-8" Add an interface to return the CPUTLBEntryFull struct that goes with the lookup. The result is not intended to be valid across multiple lookups, so the user must use the results immediately. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/exec-all.h | 11 ++++++++++ accel/tcg/cputlb.c | 47 +++++++++++++++++++++++++---------------- 2 files changed, 40 insertions(+), 18 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index bcad607c4e..758cf6bcc7 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -434,6 +434,17 @@ int probe_access_flags(CPUArchState *env, target_ulong= addr, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr); =20 +#ifndef CONFIG_USER_ONLY +/** + * probe_access_full: + * Like probe_access_flags, except also return into @pfull. + */ +int probe_access_full(CPUArchState *env, target_ulong addr, + MMUAccessType access_type, int mmu_idx, + bool nonfault, void **phost, + CPUTLBEntryFull **pfull, uintptr_t retaddr); +#endif + #define CODE_GEN_ALIGN 16 /* must be >=3D of the size of a icach= e line */ =20 /* Estimated block size for TB allocation. */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 91f2b53142..62159549f6 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1512,7 +1512,8 @@ static void notdirty_write(CPUState *cpu, vaddr mem_v= addr, unsigned size, static int probe_access_internal(CPUArchState *env, target_ulong addr, int fault_size, MMUAccessType access_type, int mmu_idx, bool nonfault, - void **phost, uintptr_t retaddr) + void **phost, CPUTLBEntryFull **pfull, + uintptr_t retaddr) { uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); @@ -1546,10 +1547,12 @@ static int probe_access_internal(CPUArchState *env,= target_ulong addr, mmu_idx, nonfault, retaddr)) { /* Non-faulting page table read failed. */ *phost =3D NULL; + *pfull =3D NULL; return TLB_INVALID_MASK; } =20 /* TLB resize via tlb_fill may have moved the entry. */ + index =3D tlb_index(env, mmu_idx, addr); entry =3D tlb_entry(env, mmu_idx, addr); =20 /* @@ -1563,6 +1566,8 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, } flags &=3D tlb_addr; =20 + *pfull =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) { *phost =3D NULL; @@ -1574,37 +1579,44 @@ static int probe_access_internal(CPUArchState *env,= target_ulong addr, return flags; } =20 -int probe_access_flags(CPUArchState *env, target_ulong addr, - MMUAccessType access_type, int mmu_idx, - bool nonfault, void **phost, uintptr_t retaddr) +int probe_access_full(CPUArchState *env, target_ulong addr, + MMUAccessType access_type, int mmu_idx, + bool nonfault, void **phost, CPUTLBEntryFull **pfull, + uintptr_t retaddr) { - int flags; - - flags =3D probe_access_internal(env, addr, 0, access_type, mmu_idx, - nonfault, phost, retaddr); + int flags =3D probe_access_internal(env, addr, 0, access_type, mmu_idx, + nonfault, phost, pfull, retaddr); =20 /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; - - notdirty_write(env_cpu(env), addr, 1, full, retaddr); + notdirty_write(env_cpu(env), addr, 1, *pfull, retaddr); flags &=3D ~TLB_NOTDIRTY; } =20 return flags; } =20 +int probe_access_flags(CPUArchState *env, target_ulong addr, + MMUAccessType access_type, int mmu_idx, + bool nonfault, void **phost, uintptr_t retaddr) +{ + CPUTLBEntryFull *full; + + return probe_access_full(env, addr, access_type, mmu_idx, + nonfault, phost, &full, retaddr); +} + void *probe_access(CPUArchState *env, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retad= dr) { + CPUTLBEntryFull *full; void *host; int flags; =20 g_assert(-(addr | TARGET_PAGE_MASK) >=3D size); =20 flags =3D probe_access_internal(env, addr, size, access_type, mmu_idx, - false, &host, retaddr); + false, &host, &full, retaddr); =20 /* Per the interface, size =3D=3D 0 merely faults the access. */ if (size =3D=3D 0) { @@ -1612,9 +1624,6 @@ void *probe_access(CPUArchState *env, target_ulong ad= dr, int size, } =20 if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) { - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; - /* Handle watchpoints. */ if (flags & TLB_WATCHPOINT) { int wp_access =3D (access_type =3D=3D MMU_DATA_STORE @@ -1635,11 +1644,12 @@ void *probe_access(CPUArchState *env, target_ulong = addr, int size, void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, MMUAccessType access_type, int mmu_idx) { + CPUTLBEntryFull *full; void *host; int flags; =20 flags =3D probe_access_internal(env, addr, 0, access_type, - mmu_idx, true, &host, 0); + mmu_idx, true, &host, &full, 0); =20 /* No combination of flags are expected by the caller. */ return flags ? NULL : host; @@ -1658,10 +1668,11 @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr = addr, tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong ad= dr, void **hostp) { + CPUTLBEntryFull *full; void *p; =20 (void)probe_access_internal(env, addr, 1, MMU_INST_FETCH, - cpu_mmu_index(env, true), false, &p, 0); + cpu_mmu_index(env, true), false, &p, &full= , 0); if (p =3D=3D NULL) { return -1; } --=20 2.34.1 From nobody Tue May 21 00:58:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1662409747; cv=none; d=zohomail.com; s=zohoarc; b=a54D6+hLBMgLW5f59VK4Rf2pkWcZ8VxtQsX9XYWSB5XcTkjIBFWdiWzDWyjQfEuwdcPeQ9vziUDcnXYVdkHn6XaC3yBCbOuA+R96Zpmvu4hy8IjYBmCQfeNlq3lwYvSbl6c1UXiEV4L0sm8saEado7LqPxld+TSMSmsk8qYmBa4= ARC-Message-Signature: i=1; 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Mon, 05 Sep 2022 13:23:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, qemu-arm@nongnu.org, pbonzini@redhat.com Subject: [PATCH v3 5/6] accel/tcg: Introduce tlb_set_page_full Date: Mon, 5 Sep 2022 21:22:58 +0100 Message-Id: <20220905202259.189852-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220905202259.189852-1-richard.henderson@linaro.org> References: <20220905202259.189852-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1662409749388100001 Content-Type: text/plain; charset="utf-8" Now that we have collected all of the page data into CPUTLBEntryFull, provide an interface to record that all in one go, instead of using 4 arguments. This interface allows CPUTLBEntryFull to be extended without having to change the number of arguments. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-defs.h | 14 ++++++++++ include/exec/exec-all.h | 22 +++++++++++++++ accel/tcg/cputlb.c | 62 ++++++++++++++++++++++++++++------------- 3 files changed, 78 insertions(+), 20 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index f70f54d850..5e12cc1854 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -148,7 +148,21 @@ typedef struct CPUTLBEntryFull { * + the offset within the target MemoryRegion (otherwise) */ hwaddr xlat_section; + + /* + * @phys_addr contains the physical address in the address space + * given by cpu_asidx_from_attrs(cpu, @attrs). + */ + hwaddr phys_addr; + + /* @attrs contains the memory transaction attributes for the page. */ MemTxAttrs attrs; + + /* @prot contains the complete protections for the page. */ + uint8_t prot; + + /* @lg_page_size contains the log2 of the page size. */ + uint8_t lg_page_size; } CPUTLBEntryFull; =20 /* diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 758cf6bcc7..1a30c857f4 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -257,6 +257,28 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUStat= e *cpu, uint16_t idxmap, unsigned bits); =20 +/** + * tlb_set_page_full: + * @cpu: CPU context + * @mmu_idx: mmu index of the tlb to modify + * @vaddr: virtual address of the entry to add + * @full: the details of the tlb entry + * + * Add an entry to @cpu tlb index @mmu_idx. All of the fields of + * @full must be filled, except for xlat_section, and constitute + * the complete description of the translated page. + * + * This is generally called by the target tlb_fill function after + * having performed a successful page table walk to find the physical + * address and attributes for the translation. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; @full->ld_page_size is only + * used by tlb_flush_page. + */ +void tlb_set_page_full(CPUState *cpu, int mmu_idx, target_ulong vaddr, + CPUTLBEntryFull *full); + /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 62159549f6..3a3549ad4a 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1095,16 +1095,16 @@ static void tlb_add_large_page(CPUArchState *env, i= nt mmu_idx, env_tlb(env)->d[mmu_idx].large_page_mask =3D lp_mask; } =20 -/* Add a new TLB entry. At most one entry for a given virtual address +/* + * Add a new TLB entry. At most one entry for a given virtual address * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the * supplied size is only used by tlb_flush_page. * * Called from TCG-generated code, which is under an RCU read-side * critical section. */ -void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, - hwaddr paddr, MemTxAttrs attrs, int prot, - int mmu_idx, target_ulong size) +void tlb_set_page_full(CPUState *cpu, int mmu_idx, + target_ulong vaddr, CPUTLBEntryFull *full) { CPUArchState *env =3D cpu->env_ptr; CPUTLB *tlb =3D env_tlb(env); @@ -1117,35 +1117,36 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_= ulong vaddr, CPUTLBEntry *te, tn; hwaddr iotlb, xlat, sz, paddr_page; target_ulong vaddr_page; - int asidx =3D cpu_asidx_from_attrs(cpu, attrs); - int wp_flags; + int asidx, wp_flags, prot; bool is_ram, is_romd; =20 assert_cpu_is_self(cpu); =20 - if (size <=3D TARGET_PAGE_SIZE) { + if (full->lg_page_size <=3D TARGET_PAGE_BITS) { sz =3D TARGET_PAGE_SIZE; } else { - tlb_add_large_page(env, mmu_idx, vaddr, size); - sz =3D size; + sz =3D (hwaddr)1 << full->lg_page_size; + tlb_add_large_page(env, mmu_idx, vaddr, sz); } vaddr_page =3D vaddr & TARGET_PAGE_MASK; - paddr_page =3D paddr & TARGET_PAGE_MASK; + paddr_page =3D full->phys_addr & TARGET_PAGE_MASK; =20 + prot =3D full->prot; + asidx =3D cpu_asidx_from_attrs(cpu, full->attrs); section =3D address_space_translate_for_iotlb(cpu, asidx, paddr_page, - &xlat, &sz, attrs, &prot); + &xlat, &sz, full->attrs, &= prot); assert(sz >=3D TARGET_PAGE_SIZE); =20 tlb_debug("vaddr=3D" TARGET_FMT_lx " paddr=3D0x" TARGET_FMT_plx " prot=3D%x idx=3D%d\n", - vaddr, paddr, prot, mmu_idx); + vaddr, full->phys_addr, prot, mmu_idx); =20 address =3D vaddr_page; - if (size < TARGET_PAGE_SIZE) { + if (full->lg_page_size < TARGET_PAGE_BITS) { /* Repeat the MMU check and TLB fill on every access. */ address |=3D TLB_INVALID_MASK; } - if (attrs.byte_swap) { + if (full->attrs.byte_swap) { address |=3D TLB_BSWAP; } =20 @@ -1236,8 +1237,10 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_u= long vaddr, * subtract here is that of the page base, and not the same as the * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). */ + desc->fulltlb[index] =3D *full; desc->fulltlb[index].xlat_section =3D iotlb - vaddr_page; - desc->fulltlb[index].attrs =3D attrs; + desc->fulltlb[index].phys_addr =3D paddr_page; + desc->fulltlb[index].prot =3D prot; =20 /* Now calculate the new entry */ tn.addend =3D addend - vaddr_page; @@ -1272,15 +1275,34 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_= ulong vaddr, qemu_spin_unlock(&tlb->c.lock); } =20 -/* Add a new TLB entry, but without specifying the memory - * transaction attributes to be used. - */ +void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, + hwaddr paddr, MemTxAttrs attrs, int prot, + int mmu_idx, target_ulong size) +{ + CPUTLBEntryFull full =3D { + .phys_addr =3D paddr, + .attrs =3D attrs, + .prot =3D prot, + .lg_page_size =3D ctz64(size) + }; + + assert(is_power_of_2(size)); + tlb_set_page_full(cpu, mmu_idx, vaddr, &full); +} + void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size) { - tlb_set_page_with_attrs(cpu, vaddr, paddr, MEMTXATTRS_UNSPECIFIED, - prot, mmu_idx, size); + CPUTLBEntryFull full =3D { + .phys_addr =3D paddr, + .attrs =3D MEMTXATTRS_UNSPECIFIED, + .prot =3D prot, + .lg_page_size =3D ctz64(size) + }; + + assert(is_power_of_2(size)); + tlb_set_page_full(cpu, mmu_idx, vaddr, &full); } =20 /* --=20 2.34.1 From nobody Tue May 21 00:58:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1662409577; cv=none; d=zohomail.com; s=zohoarc; b=l3RmL5QIDyVymxH0rsKZIpK8iZrpA62ZhYqrLtoS79afqg3ynQ9CGBqoGWuSSZbl2BGc8Bkbyt+QbNQn9oMiz21xPP0Q5u5mpLFuq+50P+FOns/bj9T+3vJRrkbaIaI+zyXuAsXkohc/03BhaEsuDVTWxTgdGXkMBqK9zZpy5+g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662409577; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1662409577994100001 Content-Type: text/plain; charset="utf-8" Allow the target to cache items from the guest page tables. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-defs.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 5e12cc1854..67239b4e5e 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -163,6 +163,15 @@ typedef struct CPUTLBEntryFull { =20 /* @lg_page_size contains the log2 of the page size. */ uint8_t lg_page_size; + + /* + * Allow target-specific additions to this structure. + * This may be used to cache items from the guest cpu + * page tables for later use by the implementation. + */ +#ifdef TARGET_PAGE_ENTRY_EXTRA + TARGET_PAGE_ENTRY_EXTRA +#endif } CPUTLBEntryFull; =20 /* --=20 2.34.1