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Tsirkin" , Bernhard Beschow Subject: [PATCH 38/42] hw/isa/piix: Consolidate IRQ triggering Date: Thu, 1 Sep 2022 18:26:09 +0200 Message-Id: <20220901162613.6939-39-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=shentey@gmail.com; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1662052087894100001 Content-Type: text/plain; charset="utf-8" Speeds up PIIX4 which resolves an old TODO. Signed-off-by: Bernhard Beschow --- hw/isa/piix.c | 26 +++----------------------- 1 file changed, 3 insertions(+), 23 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 1d516de5cc..e413d7e792 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -83,27 +83,6 @@ static void piix_set_irq(void *opaque, int pirq, int lev= el) piix_set_irq_level(piix, pirq, level); } =20 -static void piix4_set_irq(void *opaque, int irq_num, int level) -{ - int i, pic_irq, pic_level; - PIIXState *s =3D opaque; - PCIBus *bus =3D pci_get_bus(&s->dev); - - /* now we change the pic irq level according to the piix irq mappings = */ - /* XXX: optimize */ - pic_irq =3D s->dev.config[PIIX_PIRQCA + irq_num]; - if (pic_irq < ISA_NUM_IRQS) { - /* The pic level is the logical OR of all the PCI irqs mapped to i= t. */ - pic_level =3D 0; - for (i =3D 0; i < PIIX_NUM_PIRQS; i++) { - if (pic_irq =3D=3D s->dev.config[PIIX_PIRQCA + i]) { - pic_level |=3D pci_bus_get_irq_level(bus, i); - } - } - qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); - } -} - /* * Return the global irq number corresponding to a given device irq * pin. We could also use the bus number to have a more precise mapping. @@ -275,7 +254,7 @@ static int piix4_post_load(void *opaque, int version_id) s->rcr =3D 0; } =20 - return 0; + return piix3_post_load(opaque, version_id); } =20 static int piix3_pre_save(void *opaque) @@ -585,7 +564,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) /* RTC */ s->rtc.irq =3D qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); =20 - pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s, + pci_bus_irqs(pci_bus, piix_set_irq, piix4_pci_slot_get_pirq, s, PIIX_NUM_PIRQS); } =20 @@ -603,6 +582,7 @@ static void piix4_class_init(ObjectClass *klass, void *= data) DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 + k->config_write =3D piix_write_config; k->realize =3D piix4_realize; k->vendor_id =3D PCI_VENDOR_ID_INTEL; k->device_id =3D PCI_DEVICE_ID_INTEL_82371AB_0; --=20 2.37.3