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Tsirkin" , Bernhard Beschow Subject: [PATCH 31/42] hw/isa/piix4: Rename reset control operations to match PIIX3 Date: Thu, 1 Sep 2022 18:26:02 +0200 Message-Id: <20220901162613.6939-32-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=shentey@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1662051476609100001 Content-Type: text/plain; charset="utf-8" Both implementations are the same and will be shared upon merging. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 95e4a9f3c1..e682370887 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -151,7 +151,7 @@ static const VMStateDescription vmstate_piix4 =3D { } }; =20 -static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, +static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { PIIXState *s =3D opaque; @@ -164,16 +164,16 @@ static void piix4_rcr_write(void *opaque, hwaddr addr= , uint64_t val, s->rcr =3D val & 2; /* keep System Reset type only */ } =20 -static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) +static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned int len) { PIIXState *s =3D opaque; =20 return s->rcr; } =20 -static const MemoryRegionOps piix4_rcr_ops =3D { - .read =3D piix4_rcr_read, - .write =3D piix4_rcr_write, +static const MemoryRegionOps rcr_ops =3D { + .read =3D rcr_read, + .write =3D rcr_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .impl =3D { .min_access_size =3D 1, @@ -193,7 +193,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } =20 - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, "reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &s->rcr_mem, 1); --=20 2.37.3