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Tsirkin" , Bernhard Beschow Subject: [PATCH 27/42] hw/isa/piix4: Allow board to provide PCI interrupt routes Date: Thu, 1 Sep 2022 18:25:58 +0200 Message-Id: <20220901162613.6939-28-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=shentey@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1662050777109100001 PIIX3 initializes the PIRQx route control registers to the default values as described in the 82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4) April 1997 manual. PIIX4, however, initializes the routes according to the Malta=E2=84=A2 User=E2=80=99s Manual, ch 6.6, which are IRQs 10 and 11.= In order to allow the reset methods to be consolidated, allow board code to specify the routes. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/isa/piix4.c | 14 ++++++++++---- hw/mips/malta.c | 4 ++++ 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index ed9eca715f..763c98b565 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -57,6 +57,8 @@ struct PIIX4State { MemoryRegion rcr_mem; uint8_t rcr; =20 + uint8_t pci_irq_reset_mappings[PIIX_NUM_PIRQS]; + bool has_acpi; bool has_usb; bool smm_enabled; @@ -122,10 +124,10 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0x4c] =3D 0x4d; pci_conf[0x4e] =3D 0x03; pci_conf[0x4f] =3D 0x00; - pci_conf[0x60] =3D 0x0a; // PCI A -> IRQ 10 - pci_conf[0x61] =3D 0x0a; // PCI B -> IRQ 10 - pci_conf[0x62] =3D 0x0b; // PCI C -> IRQ 11 - pci_conf[0x63] =3D 0x0b; // PCI D -> IRQ 11 + pci_conf[PIIX_PIRQCA] =3D d->pci_irq_reset_mappings[0]; + pci_conf[PIIX_PIRQCB] =3D d->pci_irq_reset_mappings[1]; + pci_conf[PIIX_PIRQCC] =3D d->pci_irq_reset_mappings[2]; + pci_conf[PIIX_PIRQCD] =3D d->pci_irq_reset_mappings[3]; pci_conf[0x69] =3D 0x02; pci_conf[0x70] =3D 0x80; pci_conf[0x76] =3D 0x0c; @@ -299,6 +301,10 @@ static void piix4_init(Object *obj) =20 static Property piix4_props[] =3D { DEFINE_PROP_UINT32("smb_io_base", PIIX4State, smb_io_base, 0), + DEFINE_PROP_UINT8("pirqa", PIIX4State, pci_irq_reset_mappings[0], 0x80= ), + DEFINE_PROP_UINT8("pirqb", PIIX4State, pci_irq_reset_mappings[1], 0x80= ), + DEFINE_PROP_UINT8("pirqc", PIIX4State, pci_irq_reset_mappings[2], 0x80= ), + DEFINE_PROP_UINT8("pirqd", PIIX4State, pci_irq_reset_mappings[3], 0x80= ), DEFINE_PROP_BOOL("has-acpi", PIIX4State, has_acpi, true), DEFINE_PROP_BOOL("has-usb", PIIX4State, has_usb, true), DEFINE_PROP_BOOL("smm-enabled", PIIX4State, smm_enabled, false), diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 6339b0d66c..44b6b14f3d 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1403,6 +1403,10 @@ void mips_malta_init(MachineState *machine) piix4 =3D pci_new_multifunction(PCI_DEVFN(10, 0), true, TYPE_PIIX4_PCI_DEVICE); qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100); + qdev_prop_set_uint8(DEVICE(piix4), "pirqa", 10); + qdev_prop_set_uint8(DEVICE(piix4), "pirqb", 10); + qdev_prop_set_uint8(DEVICE(piix4), "pirqc", 11); + qdev_prop_set_uint8(DEVICE(piix4), "pirqd", 11); pci_realize_and_unref(piix4, pci_bus, &error_fatal); isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); =20 --=20 2.37.3