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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <f4bug@amsat.org>
Subject: [PULL 1/4] target/avr: Support probe argument to tlb_fill
Date: Thu, 1 Sep 2022 07:51:48 +0100
Message-Id: <20220901065210.117081-3-richard.henderson@linaro.org>
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While there are no target-specific nonfaulting probes,
generic code may grow some uses at some point.
Note that the attrs argument was incorrect -- it should have
been MEMTXATTRS_UNSPECIFIED. Just use the simpler interface.
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/avr/helper.c | 46 ++++++++++++++++++++++++++++-----------------
1 file changed, 29 insertions(+), 17 deletions(-)
diff --git a/target/avr/helper.c b/target/avr/helper.c
index db76452f9a..82284f8997 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -102,38 +102,50 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, in=
t size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
- int prot =3D 0;
- MemTxAttrs attrs =3D {};
+ int prot, page_size =3D TARGET_PAGE_SIZE;
uint32_t paddr;
=20
address &=3D TARGET_PAGE_MASK;
=20
if (mmu_idx =3D=3D MMU_CODE_IDX) {
- /* access to code in flash */
+ /* Access to code in flash. */
paddr =3D OFFSET_CODE + address;
prot =3D PAGE_READ | PAGE_EXEC;
- if (paddr + TARGET_PAGE_SIZE > OFFSET_DATA) {
+ if (paddr >=3D OFFSET_DATA) {
+ /*
+ * This should not be possible via any architectural operation=
s.
+ * There is certainly not an exception that we can deliver.
+ * Accept probing that might come from generic code.
+ */
+ if (probe) {
+ return false;
+ }
error_report("execution left flash memory");
abort();
}
- } else if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS)=
{
- /*
- * access to CPU registers, exit and rebuilt this TB to use full a=
ccess
- * incase it touches specially handled registers like SREG or SP
- */
- AVRCPU *cpu =3D AVR_CPU(cs);
- CPUAVRState *env =3D &cpu->env;
- env->fullacc =3D 1;
- cpu_loop_exit_restore(cs, retaddr);
} else {
- /* access to memory. nothing special */
+ /* Access to memory. */
paddr =3D OFFSET_DATA + address;
prot =3D PAGE_READ | PAGE_WRITE;
+ if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
+ /*
+ * Access to CPU registers, exit and rebuilt this TB to use
+ * full access in case it touches specially handled registers
+ * like SREG or SP. For probing, set page_size =3D 1, in order
+ * to force tlb_fill to be called for the next access.
+ */
+ if (probe) {
+ page_size =3D 1;
+ } else {
+ AVRCPU *cpu =3D AVR_CPU(cs);
+ CPUAVRState *env =3D &cpu->env;
+ env->fullacc =3D 1;
+ cpu_loop_exit_restore(cs, retaddr);
+ }
+ }
}
=20
- tlb_set_page_with_attrs(cs, address, paddr, attrs, prot,
- mmu_idx, TARGET_PAGE_SIZE);
-
+ tlb_set_page(cs, address, paddr, prot, mmu_idx, page_size);
return true;
}
=20
--=20
2.34.1