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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1662011555635100004 While there are no target-specific nonfaulting probes, generic code may grow some uses at some point. Note that the attrs argument was incorrect -- it should have been MEMTXATTRS_UNSPECIFIED. Just use the simpler interface. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/avr/helper.c | 46 ++++++++++++++++++++++++++++----------------- 1 file changed, 29 insertions(+), 17 deletions(-) diff --git a/target/avr/helper.c b/target/avr/helper.c index db76452f9a..82284f8997 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -102,38 +102,50 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - int prot =3D 0; - MemTxAttrs attrs =3D {}; + int prot, page_size =3D TARGET_PAGE_SIZE; uint32_t paddr; =20 address &=3D TARGET_PAGE_MASK; =20 if (mmu_idx =3D=3D MMU_CODE_IDX) { - /* access to code in flash */ + /* Access to code in flash. */ paddr =3D OFFSET_CODE + address; prot =3D PAGE_READ | PAGE_EXEC; - if (paddr + TARGET_PAGE_SIZE > OFFSET_DATA) { + if (paddr >=3D OFFSET_DATA) { + /* + * This should not be possible via any architectural operation= s. + * There is certainly not an exception that we can deliver. + * Accept probing that might come from generic code. + */ + if (probe) { + return false; + } error_report("execution left flash memory"); abort(); } - } else if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS)= { - /* - * access to CPU registers, exit and rebuilt this TB to use full a= ccess - * incase it touches specially handled registers like SREG or SP - */ - AVRCPU *cpu =3D AVR_CPU(cs); - CPUAVRState *env =3D &cpu->env; - env->fullacc =3D 1; - cpu_loop_exit_restore(cs, retaddr); } else { - /* access to memory. nothing special */ + /* Access to memory. */ paddr =3D OFFSET_DATA + address; prot =3D PAGE_READ | PAGE_WRITE; + if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { + /* + * Access to CPU registers, exit and rebuilt this TB to use + * full access in case it touches specially handled registers + * like SREG or SP. For probing, set page_size =3D 1, in order + * to force tlb_fill to be called for the next access. + */ + if (probe) { + page_size =3D 1; + } else { + AVRCPU *cpu =3D AVR_CPU(cs); + CPUAVRState *env =3D &cpu->env; + env->fullacc =3D 1; + cpu_loop_exit_restore(cs, retaddr); + } + } } =20 - tlb_set_page_with_attrs(cs, address, paddr, attrs, prot, - mmu_idx, TARGET_PAGE_SIZE); - + tlb_set_page(cs, address, paddr, prot, mmu_idx, page_size); return true; } =20 --=20 2.34.1