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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2a; envelope-from=danielhb413@gmail.com; helo=mail-oa1-x2a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1661975080516100001 From: C=C3=A9dric Le Goater Drop the use of ppc4xx_init() and duplicate a bit of code related to clocks in the SoC realize routine. We will clean that up in the following patches. ppc_dcr_init() simply allocates default DCR handlers for the CPU. Maybe this could be done in model initializer of the CPU families needing it. Reviewed-by: Daniel Henrique Barboza Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: BALATON Zoltan Message-Id: <20220809153904.485018-8-clg@kaod.org> Signed-off-by: Daniel Henrique Barboza --- hw/ppc/ppc405.h | 2 +- hw/ppc/ppc405_boards.c | 2 +- hw/ppc/ppc405_uc.c | 40 ++++++++++++++++++++++++++++++---------- hw/ppc/ppc4xx_devs.c | 32 -------------------------------- include/hw/ppc/ppc4xx.h | 5 ----- 5 files changed, 32 insertions(+), 49 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index dc862bc861..8cc76cc8b3 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -79,7 +79,7 @@ struct Ppc405SoCState { hwaddr ram_size; =20 uint32_t sysclk; - PowerPCCPU *cpu; + PowerPCCPU cpu; DeviceState *uic; }; =20 diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index b93e85b5d9..3677793adc 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -313,7 +313,7 @@ static void ppc405_init(MachineState *machine) =20 /* Load ELF kernel and rootfs.cpio */ } else if (kernel_filename && !machine->firmware) { - boot_from_kernel(machine, ppc405->soc.cpu); + boot_from_kernel(machine, &ppc405->soc.cpu); } } =20 diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index c05ab60436..14a525b2eb 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1432,22 +1432,41 @@ static void ppc405ep_cpc_init (CPUPPCState *env, cl= k_setup_t clk_setup[8], #endif } =20 +static void ppc405_soc_instance_init(Object *obj) +{ + Ppc405SoCState *s =3D PPC405_SOC(obj); + + object_initialize_child(obj, "cpu", &s->cpu, + POWERPC_CPU_TYPE_NAME("405ep")); +} + +static void ppc405_reset(void *opaque) +{ + cpu_reset(CPU(opaque)); +} + static void ppc405_soc_realize(DeviceState *dev, Error **errp) { Ppc405SoCState *s =3D PPC405_SOC(dev); - clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; + clk_setup_t clk_setup[PPC405EP_CLK_NB]; qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; CPUPPCState *env; =20 memset(clk_setup, 0, sizeof(clk_setup)); =20 /* init CPUs */ - s->cpu =3D ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"), - &clk_setup[PPC405EP_CPU_CLK], - &tlb_clk_setup, s->sysclk); - env =3D &s->cpu->env; - clk_setup[PPC405EP_CPU_CLK].cb =3D tlb_clk_setup.cb; - clk_setup[PPC405EP_CPU_CLK].opaque =3D tlb_clk_setup.opaque; + if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) { + return; + } + qemu_register_reset(ppc405_reset, &s->cpu); + + env =3D &s->cpu.env; + + clk_setup[PPC405EP_CPU_CLK].cb =3D + ppc_40x_timers_init(env, s->sysclk, PPC_INTERRUPT_PIT); + clk_setup[PPC405EP_CPU_CLK].opaque =3D env; + + ppc_dcr_init(env, NULL, NULL); =20 /* CPU control */ ppc405ep_cpc_init(env, clk_setup, s->sysclk); @@ -1464,16 +1483,16 @@ static void ppc405_soc_realize(DeviceState *dev, Er= ror **errp) /* Universal interrupt controller */ s->uic =3D qdev_new(TYPE_PPC_UIC); =20 - object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(s->cpu), + object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(&s->cpu), &error_fatal); if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) { return; } =20 sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT, - qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_INT)); + qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT)= ); sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT, - qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_CINT)= ); + qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT= )); =20 /* SDRAM controller */ /* XXX 405EP has no ECC interrupt */ @@ -1563,6 +1582,7 @@ static const TypeInfo ppc405_types[] =3D { .name =3D TYPE_PPC405_SOC, .parent =3D TYPE_DEVICE, .instance_size =3D sizeof(Ppc405SoCState), + .instance_init =3D ppc405_soc_instance_init, .class_init =3D ppc405_soc_class_init, } }; diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 737c0896b4..069b511951 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -37,38 +37,6 @@ #include "qapi/error.h" #include "trace.h" =20 -static void ppc4xx_reset(void *opaque) -{ - PowerPCCPU *cpu =3D opaque; - - cpu_reset(CPU(cpu)); -} - -/*************************************************************************= ****/ -/* Generic PowerPC 4xx processor instantiation */ -PowerPCCPU *ppc4xx_init(const char *cpu_type, - clk_setup_t *cpu_clk, clk_setup_t *tb_clk, - uint32_t sysclk) -{ - PowerPCCPU *cpu; - CPUPPCState *env; - - /* init CPUs */ - cpu =3D POWERPC_CPU(cpu_create(cpu_type)); - env =3D &cpu->env; - - cpu_clk->cb =3D NULL; /* We don't care about CPU clock frequency chang= es */ - cpu_clk->opaque =3D env; - /* Set time-base frequency to sysclk */ - tb_clk->cb =3D ppc_40x_timers_init(env, sysclk, PPC_INTERRUPT_PIT); - tb_clk->opaque =3D env; - ppc_dcr_init(env, NULL, NULL); - /* Register qemu callbacks */ - qemu_register_reset(ppc4xx_reset, cpu); - - return cpu; -} - /*************************************************************************= ****/ /* SDRAM controller */ typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index 980f964b5a..591e2421a3 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -28,11 +28,6 @@ #include "hw/ppc/ppc.h" #include "exec/memory.h" =20 -/* PowerPC 4xx core initialization */ -PowerPCCPU *ppc4xx_init(const char *cpu_model, - clk_setup_t *cpu_clk, clk_setup_t *tb_clk, - uint32_t sysclk); - void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, MemoryRegion ram_memories[], hwaddr ram_bases[], hwaddr ram_sizes[], --=20 2.37.2