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Tsirkin" , Sergio Lopez , Gerd Hoffmann Subject: [PATCH 2/2] [RfC] expose host-phys-bits to guest Date: Wed, 31 Aug 2022 14:50:59 +0200 Message-Id: <20220831125059.170032-3-kraxel@redhat.com> In-Reply-To: <20220831125059.170032-1-kraxel@redhat.com> References: <20220831125059.170032-1-kraxel@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.85 on 10.11.54.8 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=kraxel@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1661950404983100001 Content-Type: text/plain; charset="utf-8" Move "host-phys-bits" property from cpu->host_phys_bits to cpu->env.features[FEAT_KVM_HINTS] (KVM_HINTS_HOST_PHYS_BITS). This has the effect that the guest can see whenever host-phys-bits is turned on or not and act accordingly. Current mode of operation for firmware is to be conservative with address space usage because is impossible to figure how much is actually available. This patch allows the firmware to use the full physical address space available (with host-phys-bits=3Don). Signed-off-by: Gerd Hoffmann --- target/i386/cpu.h | 3 --- hw/i386/microvm.c | 6 +++++- target/i386/cpu.c | 3 +-- target/i386/host-cpu.c | 4 +++- target/i386/kvm/kvm.c | 1 + 5 files changed, 10 insertions(+), 7 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 82004b65b944..b9c6d3d9cac6 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1898,9 +1898,6 @@ struct ArchCPU { /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ bool fill_mtrr_mask; =20 - /* if true override the phys_bits value with a value read from the hos= t */ - bool host_phys_bits; - /* if set, limit maximum value for phys_bits when host_phys_bits is tr= ue */ uint8_t host_phys_bits_limit; =20 diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 7fe8cce03e92..edb1d4cbcbc1 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -54,6 +54,8 @@ #include "kvm/kvm_i386.h" #include "hw/xen/start_info.h" =20 +#include "standard-headers/asm-x86/kvm_para.h" + #define MICROVM_QBOOT_FILENAME "qboot.rom" #define MICROVM_BIOS_FILENAME "bios-microvm.bin" =20 @@ -424,7 +426,9 @@ static void microvm_device_pre_plug_cb(HotplugHandler *= hotplug_dev, { X86CPU *cpu =3D X86_CPU(dev); =20 - cpu->host_phys_bits =3D true; /* need reliable phys-bits */ + /* need reliable phys-bits */ + cpu->env.features[FEAT_KVM_HINTS] |=3D (1 << KVM_HINTS_HOST_PHYS_BITS); + x86_cpu_pre_plug(hotplug_dev, dev, errp); } =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1db1278a599b..d60f4498a3c3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -778,7 +778,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { [FEAT_KVM_HINTS] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { - "kvm-hint-dedicated", NULL, NULL, NULL, + "kvm-hint-dedicated", "host-phys-bits", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, @@ -7016,7 +7016,6 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), - DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit= , 0), DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, diff --git a/target/i386/host-cpu.c b/target/i386/host-cpu.c index 10f8aba86e53..30e9dd9f66f1 100644 --- a/target/i386/host-cpu.c +++ b/target/i386/host-cpu.c @@ -13,6 +13,8 @@ #include "qapi/error.h" #include "sysemu/sysemu.h" =20 +#include "standard-headers/asm-x86/kvm_para.h" + /* Note: Only safe for use on x86(-64) hosts */ static uint32_t host_cpu_phys_bits(void) { @@ -68,7 +70,7 @@ static uint32_t host_cpu_adjust_phys_bits(X86CPU *cpu) warned =3D true; } =20 - if (cpu->host_phys_bits) { + if (cpu->env.features[FEAT_KVM_HINTS] & (1 << KVM_HINTS_HOST_PHYS_BITS= )) { /* The user asked for us to use the host physical bits */ phys_bits =3D host_phys_bits; if (cpu->host_phys_bits_limit && diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index f148a6d52fa4..182a70c98d35 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -459,6 +459,7 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint= 32_t function, } } else if (function =3D=3D KVM_CPUID_FEATURES && reg =3D=3D R_EDX) { ret |=3D 1U << KVM_HINTS_REALTIME; + ret |=3D 1U << KVM_HINTS_HOST_PHYS_BITS; } =20 return ret; --=20 2.37.2