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[217.94.215.31]) by smtp.gmail.com with ESMTPSA id 6-20020a170906310600b0073c10031dc9sm6449583ejx.80.2022.08.31.03.01.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Aug 2022 03:01:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=I6LPJZUvTPv4BSyUK+1MUo2I6TDAef6EvKzOqmCgYAk=; b=YGNWllmJgZffUoYl652TgA6Z8aGkGVgFYkAq3XDBpX3hfqwBWqhk3vpfJoLZpVZUNq TT3B7FC4Zjjco6cItiA8JLXVA/e80GwKWHB16BUTgi5Wb2ybMUgd7jJ/j1wQCbPMdOzn M4DaW1xxG6Y7ImpEgZ6DtE4KLyuyTun7xOYtUMn7GKim0ws0smhuAcwxf43DKgIhqbhO ALtNc+e6KGXviGGMMRBK9JrLhpk4O6A7UOfKR4wccTqwUzXdsB0DFcHD147mg1nvhE6M OnakrCFG2SUrXBbgR5V4lhtp/xa3vVD0XQ/RXN3z5x9QxtkmC6DBXNFHbFtye3Kc1tPe Dcsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=I6LPJZUvTPv4BSyUK+1MUo2I6TDAef6EvKzOqmCgYAk=; b=1F6sb4cn/c8l548OTP+3JhIN6R8eexY2FYZl+RZkq2aP098T8Kk+IXCOAlgmjZQYaA wFmNH67xsEZ0wSqcGXIJ70dwt0nfXmlFYy/7adncxDdTz1lNCbwd/gYGLW1zDKYq577k M/bMJM8g5Fp2NvodoB9mYyldXy/gltdkL4SXWjAbUxdK4g0hK4i3lyyRgcOOjBMqR604 vSk4aZYy752nnFyTQLqpiDnYjWGMz0VWrDpozAWuMUXnM5uICQ/0WXwqDOegMa7N/chY ScNzaI+n2vv6gFBDWAMnGM1AkmdZwSK25TwZ1PCi7+ygFi9qD/XGCmhpWjn8R2Zg4Y/j auRQ== X-Gm-Message-State: ACgBeo2wAK6AotOK28swVV2kS+zaZWljXtyLoSD1Z6zQHMrzDxesMB4L lJm3REzpPB5yOLoBdCf5pbx/8ojSmZU= X-Google-Smtp-Source: AA6agR6Ep7QxLRaKNpzh8Da48p2gg5klf69WkAXwbQEIq7KkPikpiAqFULV+5D4cobUC4/650qV0lQ== X-Received: by 2002:a17:906:9bf3:b0:741:6900:61a5 with SMTP id de51-20020a1709069bf300b00741690061a5mr11050768ejc.286.1661940112122; Wed, 31 Aug 2022 03:01:52 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , BALATON Zoltan , Jiaxun Yang , Bernhard Beschow Subject: [PATCH v3 01/10] hw/isa/vt82c686: Resolve chip-specific realize methods Date: Wed, 31 Aug 2022 11:59:05 +0200 Message-Id: <20220831095914.2041-2-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220831095914.2041-1-shentey@gmail.com> References: <20220831095914.2041-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=shentey@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1661940252751100001 Content-Type: text/plain; charset="utf-8" The object creation now happens in chip-specific init methods which allows the realize methods to be consolidated into one method. Shifting the logic into the init methods has the addidional advantage that the parent object's init methods are called implicitly - like constructors in object-oriented languages. Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 8f656251b8..0217c98fe4 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -544,7 +544,7 @@ struct ViaISAState { qemu_irq cpu_intr; qemu_irq *isa_irqs; ISABus *isa_bus; - ViaSuperIOState *via_sio; + ViaSuperIOState via_sio; }; =20 static const VMStateDescription vmstate_via =3D { @@ -602,6 +602,11 @@ static void via_isa_realize(PCIDevice *d, Error **errp) d->wmask[i] =3D 0; } } + + /* Super I/O */ + if (!qdev_realize(DEVICE(&s->via_sio), BUS(s->isa_bus), errp)) { + return; + } } =20 /* TYPE_VT82C686B_ISA */ @@ -615,7 +620,7 @@ static void vt82c686b_write_config(PCIDevice *d, uint32= _t addr, pci_default_write_config(d, addr, val, len); if (addr =3D=3D 0x85) { /* BIT(1): enable or disable superio config io ports */ - via_superio_io_enable(s->via_sio, val & BIT(1)); + via_superio_io_enable(&s->via_sio, val & BIT(1)); } } =20 @@ -639,13 +644,11 @@ static void vt82c686b_isa_reset(DeviceState *dev) pci_conf[0x77] =3D 0x10; /* GPIO Control 1/2/3/4 */ } =20 -static void vt82c686b_realize(PCIDevice *d, Error **errp) +static void vt82c686b_init(Object *obj) { - ViaISAState *s =3D VIA_ISA(d); + ViaISAState *s =3D VIA_ISA(obj); =20 - via_isa_realize(d, errp); - s->via_sio =3D VIA_SUPERIO(isa_create_simple(s->isa_bus, - TYPE_VT82C686B_SUPERIO)); + object_initialize_child(obj, "sio", &s->via_sio, TYPE_VT82C686B_SUPERI= O); } =20 static void vt82c686b_class_init(ObjectClass *klass, void *data) @@ -653,7 +656,7 @@ static void vt82c686b_class_init(ObjectClass *klass, vo= id *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 - k->realize =3D vt82c686b_realize; + k->realize =3D via_isa_realize; k->config_write =3D vt82c686b_write_config; k->vendor_id =3D PCI_VENDOR_ID_VIA; k->device_id =3D PCI_DEVICE_ID_VIA_82C686B_ISA; @@ -670,6 +673,7 @@ static const TypeInfo vt82c686b_isa_info =3D { .name =3D TYPE_VT82C686B_ISA, .parent =3D TYPE_VIA_ISA, .instance_size =3D sizeof(ViaISAState), + .instance_init =3D vt82c686b_init, .class_init =3D vt82c686b_class_init, }; =20 @@ -684,7 +688,7 @@ static void vt8231_write_config(PCIDevice *d, uint32_t = addr, pci_default_write_config(d, addr, val, len); if (addr =3D=3D 0x50) { /* BIT(2): enable or disable superio config io ports */ - via_superio_io_enable(s->via_sio, val & BIT(2)); + via_superio_io_enable(&s->via_sio, val & BIT(2)); } } =20 @@ -703,13 +707,11 @@ static void vt8231_isa_reset(DeviceState *dev) pci_conf[0x6b] =3D 0x01; /* Fast IR I/O Base */ } =20 -static void vt8231_realize(PCIDevice *d, Error **errp) +static void vt8231_init(Object *obj) { - ViaISAState *s =3D VIA_ISA(d); + ViaISAState *s =3D VIA_ISA(obj); =20 - via_isa_realize(d, errp); - s->via_sio =3D VIA_SUPERIO(isa_create_simple(s->isa_bus, - TYPE_VT8231_SUPERIO)); + object_initialize_child(obj, "sio", &s->via_sio, TYPE_VT8231_SUPERIO); } =20 static void vt8231_class_init(ObjectClass *klass, void *data) @@ -717,7 +719,7 @@ static void vt8231_class_init(ObjectClass *klass, void = *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 - k->realize =3D vt8231_realize; + k->realize =3D via_isa_realize; k->config_write =3D vt8231_write_config; k->vendor_id =3D PCI_VENDOR_ID_VIA; k->device_id =3D PCI_DEVICE_ID_VIA_8231_ISA; @@ -734,6 +736,7 @@ static const TypeInfo vt8231_isa_info =3D { .name =3D TYPE_VT8231_ISA, .parent =3D TYPE_VIA_ISA, .instance_size =3D sizeof(ViaISAState), + .instance_init =3D vt8231_init, .class_init =3D vt8231_class_init, }; =20 --=20 2.37.3