From nobody Mon Feb 9 16:19:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1661507957; cv=none; d=zohomail.com; s=zohoarc; b=h2gKAdbqXVpjE8rEcLWKnpW2MZl74bPh+/1AKO50uBVl/yRKAvVXFZ8TThV2TAfzogj48BlFZ3A5ISyLBjKXMaVAvJB1np221O+quOAO5Oqy2iX2QeMGUfy4Ci2UZhbQFJIXMiC+ttIklrg1xKMn8zgeIKlR1kxFD3uFTfdBVhg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661507957; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QM34CbWUGNk1z+dp1bR4Y53NkWRvnStCRWy4YeqOuYg=; b=bhmdySzvOillB+Ddxyo6N5PMwmrI5SVyxoRxPv8BLeAZtLJGWdlwQkxG7Me67qhzzHzWSd0ZzWjKZFjYVL+zByJXzwGBvUBz2+drHhGGdohWdcepL4D3A0TJ1ilmOMqss0tAVLeiG4fbWygoeIdwqcOsPdwu7bN/vqGxjP/C46g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661507957361382.2806563213411; Fri, 26 Aug 2022 02:59:17 -0700 (PDT) Received: from localhost ([::1]:41348 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oRW7Q-0006mb-C5 for importer@patchew.org; Fri, 26 Aug 2022 05:59:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60310) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oRW5i-0004Ne-Aq for qemu-devel@nongnu.org; Fri, 26 Aug 2022 05:57:30 -0400 Received: from mga09.intel.com ([134.134.136.24]:31251) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oRW5g-0006Yc-4U for qemu-devel@nongnu.org; Fri, 26 Aug 2022 05:57:29 -0400 Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2022 02:57:26 -0700 Received: from xuling-b360m-d3h.sh.intel.com ([10.239.82.110]) by orsmga008.jf.intel.com with ESMTP; 26 Aug 2022 02:57:24 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661507848; x=1693043848; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HUq4vRWTTE31MAsDgzpf3+j/IZnxJdlhKxhcw3NSspg=; b=VVx7/9eF4u5ZuQJsCDG0a+dBT9JFxpV/VLz5ZBUsAd5+znY9LJPJbw9+ hOvbn0dyKz9bVKELD/4aG/Dnb960ocKsodrvmoYr5BfEQYxtLdonioSDR a/xUaHfgJFihmIE0rgYsPSF5LJs2ULuVmI9ik2pPGpgJ//ie8gbSFuSti S7bdlXRfoA7nhPcv/361Wz/cuTRR/fM+CjJt0W3l0lg+dMDiYcKWj/m6h VIOxIw57tEY0Pc9+Xika1Jn+YLSEvdXgGOQjRONz1H0PwLNT1IBWgESDF 26JUEnqEQhdewdVEZTbILTXG3peNiyxdr3hYE+MzB+YmUOV1s/APNL4tc w==; X-IronPort-AV: E=McAfee;i="6500,9779,10450"; a="295250434" X-IronPort-AV: E=Sophos;i="5.93,265,1654585200"; d="scan'208";a="295250434" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,265,1654585200"; d="scan'208";a="639999927" From: ling xu To: qemu-devel@nongnu.org Cc: quintela@redhat.com, dgilbert@redhat.com, ling xu , Zhou Zhao , Jun Jin Subject: [PATCH v6 1/2] Update AVX512 support for xbzrle_encode_buffer Date: Fri, 26 Aug 2022 17:57:18 +0800 Message-Id: <20220826095719.2887535-2-ling1.xu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220826095719.2887535-1-ling1.xu@intel.com> References: <20220826095719.2887535-1-ling1.xu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.24; envelope-from=ling1.xu@intel.com; helo=mga09.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1661507957908100001 Content-Type: text/plain; charset="utf-8" This commit updates code of avx512 support for xbzrle_encode_buffer function to accelerate xbzrle encoding speed. Runtime check of avx512 support and benchmark for this feature are added. Compared with C version of xbzrle_encode_buffer function, avx512 version can achieve 50%-70% performance improvement on benchmarking. In addition, if dirty data is randomly located in 4K page, the avx512 version can achieve almost 140% performance gain. Signed-off-by: ling xu Co-authored-by: Zhou Zhao Co-authored-by: Jun Jin Reviewed-by: Juan Quintela --- meson.build | 16 ++++++ meson_options.txt | 2 + migration/ram.c | 34 +++++++++++-- migration/xbzrle.c | 124 +++++++++++++++++++++++++++++++++++++++++++++ migration/xbzrle.h | 4 ++ 5 files changed, 177 insertions(+), 3 deletions(-) diff --git a/meson.build b/meson.build index 20fddbd707..5d4b82d7f3 100644 --- a/meson.build +++ b/meson.build @@ -2264,6 +2264,22 @@ config_host_data.set('CONFIG_AVX512F_OPT', get_optio= n('avx512f') \ int main(int argc, char *argv[]) { return bar(argv[0]); } '''), error_message: 'AVX512F not available').allowed()) =20 +config_host_data.set('CONFIG_AVX512BW_OPT', get_option('avx512bw') \ + .require(have_cpuid_h, error_message: 'cpuid.h not available, cannot ena= ble AVX512BW') \ + .require(cc.links(''' + #pragma GCC push_options + #pragma GCC target("avx512bw") + #include + #include + static int bar(void *a) { + + __m512i *x =3D a; + __m512i res=3D _mm512_abs_epi8(*x); + return res[1]; + } + int main(int argc, char *argv[]) { return bar(argv[0]); } + '''), error_message: 'AVX512BW not available').allowed()) + have_pvrdma =3D get_option('pvrdma') \ .require(rdma.found(), error_message: 'PVRDMA requires OpenFabrics libra= ries') \ .require(cc.compiles(gnu_source_prefix + ''' diff --git a/meson_options.txt b/meson_options.txt index e58e158396..07194bf680 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -104,6 +104,8 @@ option('avx2', type: 'feature', value: 'auto', description: 'AVX2 optimizations') option('avx512f', type: 'feature', value: 'disabled', description: 'AVX512F optimizations') +option('avx512bw', type: 'feature', value: 'auto', + description: 'AVX512BW optimizations') option('keyring', type: 'feature', value: 'auto', description: 'Linux keyring support') =20 diff --git a/migration/ram.c b/migration/ram.c index dc1de9ddbc..ff4c15c9c3 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -83,6 +83,34 @@ /* 0x80 is reserved in migration.h start with 0x100 next */ #define RAM_SAVE_FLAG_COMPRESS_PAGE 0x100 =20 +int (*xbzrle_encode_buffer_func)(uint8_t *, uint8_t *, int, + uint8_t *, int) =3D xbzrle_encode_buffer; +#if defined(CONFIG_AVX512BW_OPT) +#include "qemu/cpuid.h" +static void __attribute__((constructor)) init_cpu_flag(void) +{ + unsigned max =3D __get_cpuid_max(0, NULL); + int a, b, c, d; + if (max >=3D 1) { + __cpuid(1, a, b, c, d); + /* We must check that AVX is not just available, but usable. */ + if ((c & bit_OSXSAVE) && (c & bit_AVX) && max >=3D 7) { + int bv; + __asm("xgetbv" : "=3Da"(bv), "=3Dd"(d) : "c"(0)); + __cpuid_count(7, 0, a, b, c, d); + /* 0xe6: + * XCR0[7:5] =3D 111b (OPMASK state, upper 256-bit of ZMM0-ZMM= 15 + * and ZMM16-ZMM31 state are enabled by OS) + * XCR0[2:1] =3D 11b (XMM state and YMM state are enabled by O= S) + */ + if ((bv & 0xe6) =3D=3D 0xe6 && (b & bit_AVX512BW)) { + xbzrle_encode_buffer_func =3D xbzrle_encode_buffer_avx512; + } + } + } +} +#endif + XBZRLECacheStats xbzrle_counters; =20 /* struct contains XBZRLE cache and a static page @@ -802,9 +830,9 @@ static int save_xbzrle_page(RAMState *rs, uint8_t **cur= rent_data, memcpy(XBZRLE.current_buf, *current_data, TARGET_PAGE_SIZE); =20 /* XBZRLE encoding (if there is no overflow) */ - encoded_len =3D xbzrle_encode_buffer(prev_cached_page, XBZRLE.current_= buf, - TARGET_PAGE_SIZE, XBZRLE.encoded_bu= f, - TARGET_PAGE_SIZE); + encoded_len =3D xbzrle_encode_buffer_func(prev_cached_page, XBZRLE.cur= rent_buf, + TARGET_PAGE_SIZE, XBZRLE.encod= ed_buf, + TARGET_PAGE_SIZE); =20 /* * Update the cache contents, so that it corresponds to the data diff --git a/migration/xbzrle.c b/migration/xbzrle.c index 1ba482ded9..05366e86c0 100644 --- a/migration/xbzrle.c +++ b/migration/xbzrle.c @@ -174,3 +174,127 @@ int xbzrle_decode_buffer(uint8_t *src, int slen, uint= 8_t *dst, int dlen) =20 return d; } + +#if defined(CONFIG_AVX512BW_OPT) +#pragma GCC push_options +#pragma GCC target("avx512bw") +#include +int xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t *new_buf, int sl= en, + uint8_t *dst, int dlen) +{ + uint32_t zrun_len =3D 0, nzrun_len =3D 0; + int d =3D 0, i =3D 0, num =3D 0; + uint8_t *nzrun_start =3D NULL; + /* add 1 to include residual part in main loop */ + uint32_t count512s =3D (slen >> 6) + 1; + /* countResidual is tail of data, i.e., countResidual =3D slen % 64 */ + uint32_t count_residual =3D slen & 0b111111; + bool never_same =3D true; + uint64_t mask_residual =3D 1; + mask_residual <<=3D count_residual; + mask_residual -=3D 1; + __m512i r =3D _mm512_set1_epi32(0); + + while (count512s) { + if (d + 2 > dlen) { + return -1; + } + + int bytes_to_check =3D 64; + uint64_t mask =3D 0xffffffffffffffff; + if (count512s =3D=3D 1) { + bytes_to_check =3D count_residual; + mask =3D mask_residual; + } + __m512i old_data =3D _mm512_mask_loadu_epi8(r, + mask, old_buf + i); + __m512i new_data =3D _mm512_mask_loadu_epi8(r, + mask, new_buf + i); + uint64_t comp =3D _mm512_cmpeq_epi8_mask(old_data, new_data); + count512s--; + + bool is_same =3D (comp & 0x1); + while (bytes_to_check) { + if (is_same) { + if (nzrun_len) { + d +=3D uleb128_encode_small(dst + d, nzrun_len); + if (d + nzrun_len > dlen) { + return -1; + } + nzrun_start =3D new_buf + i - nzrun_len; + memcpy(dst + d, nzrun_start, nzrun_len); + d +=3D nzrun_len; + nzrun_len =3D 0; + } + /* 64 data at a time for speed */ + if (count512s && (comp =3D=3D 0xffffffffffffffff)) { + i +=3D 64; + zrun_len +=3D 64; + break; + } + never_same =3D false; + num =3D __builtin_ctzll(~comp); + num =3D (num < bytes_to_check) ? num : bytes_to_check; + zrun_len +=3D num; + bytes_to_check -=3D num; + comp >>=3D num; + i +=3D num; + if (bytes_to_check) { + /* still has different data after same data */ + d +=3D uleb128_encode_small(dst + d, zrun_len); + zrun_len =3D 0; + } else { + break; + } + } + if (never_same || zrun_len) { + /* + * never_same only acts if + * data begins with diff in first count512s + */ + d +=3D uleb128_encode_small(dst + d, zrun_len); + zrun_len =3D 0; + never_same =3D false; + } + /* has diff, 64 data at a time for speed */ + if ((bytes_to_check =3D=3D 64) && (comp =3D=3D 0x0)) { + i +=3D 64; + nzrun_len +=3D 64; + break; + } + num =3D __builtin_ctzll(comp); + num =3D (num < bytes_to_check) ? num : bytes_to_check; + nzrun_len +=3D num; + bytes_to_check -=3D num; + comp >>=3D num; + i +=3D num; + if (bytes_to_check) { + /* mask like 111000 */ + d +=3D uleb128_encode_small(dst + d, nzrun_len); + /* overflow */ + if (d + nzrun_len > dlen) { + return -1; + } + nzrun_start =3D new_buf + i - nzrun_len; + memcpy(dst + d, nzrun_start, nzrun_len); + d +=3D nzrun_len; + nzrun_len =3D 0; + is_same =3D true; + } + } + } + + if (nzrun_len !=3D 0) { + d +=3D uleb128_encode_small(dst + d, nzrun_len); + /* overflow */ + if (d + nzrun_len > dlen) { + return -1; + } + nzrun_start =3D new_buf + i - nzrun_len; + memcpy(dst + d, nzrun_start, nzrun_len); + d +=3D nzrun_len; + } + return d; +} +#pragma GCC pop_options +#endif diff --git a/migration/xbzrle.h b/migration/xbzrle.h index a0db507b9c..6feb49160a 100644 --- a/migration/xbzrle.h +++ b/migration/xbzrle.h @@ -18,4 +18,8 @@ int xbzrle_encode_buffer(uint8_t *old_buf, uint8_t *new_b= uf, int slen, uint8_t *dst, int dlen); =20 int xbzrle_decode_buffer(uint8_t *src, int slen, uint8_t *dst, int dlen); +#if defined(CONFIG_AVX512BW_OPT) +int xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t *new_buf, int sl= en, + uint8_t *dst, int dlen); +#endif #endif --=20 2.25.1