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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661212598982100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/i386/cpu-param.h | 1 + target/i386/tcg/tcg-cpu.c | 8 ++-- target/i386/tcg/translate.c | 86 ++++++++++++++++++++++++++++++------- 3 files changed, 77 insertions(+), 18 deletions(-) diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index 9740bd7abd..51a3f153bf 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -24,5 +24,6 @@ #endif #define TARGET_PAGE_BITS 12 #define NB_MMU_MODES 3 +#define TARGET_TB_PCREL 1 =20 #endif diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 76989a5a9d..74333247c5 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -49,9 +49,11 @@ static void x86_cpu_exec_exit(CPUState *cs) static void x86_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - X86CPU *cpu =3D X86_CPU(cs); - - cpu->env.eip =3D tb_pc(tb) - tb->cs_base; + /* The instruction pointer is always up to date with TARGET_TB_PCREL. = */ + if (!TARGET_TB_PCREL) { + CPUX86State *env =3D cs->env_ptr; + env->eip =3D tb_pc(tb) - tb->cs_base; + } } =20 #ifndef CONFIG_USER_ONLY diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 6192a3e30e..5e252f26b2 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -64,6 +64,7 @@ =20 /* global register indexes */ static TCGv cpu_cc_dst, cpu_cc_src, cpu_cc_src2; +static TCGv cpu_eip; static TCGv_i32 cpu_cc_op; static TCGv cpu_regs[CPU_NB_REGS]; static TCGv cpu_seg_base[6]; @@ -77,6 +78,7 @@ typedef struct DisasContext { =20 target_ulong pc; /* pc =3D eip + cs_base */ target_ulong cs_base; /* base of CS segment */ + target_ulong pc_save; =20 MemOp aflag; MemOp dflag; @@ -481,7 +483,7 @@ static void gen_add_A0_im(DisasContext *s, int val) =20 static inline void gen_op_jmp_v(TCGv dest) { - tcg_gen_st_tl(dest, cpu_env, offsetof(CPUX86State, eip)); + tcg_gen_mov_tl(cpu_eip, dest); } =20 static inline @@ -516,24 +518,36 @@ static inline void gen_op_st_rm_T0_A0(DisasContext *s= , int idx, int d) } } =20 -static TCGv gen_eip_cur(DisasContext *s) +static void gen_jmp_im(DisasContext *s, target_ulong eip) { - return tcg_constant_tl(s->base.pc_next - s->cs_base); -} - -static void gen_jmp_im(DisasContext *s, target_ulong pc) -{ - gen_op_jmp_v(tcg_constant_tl(pc)); + if (TARGET_TB_PCREL) { + target_ulong eip_save =3D s->pc_save - s->cs_base; + tcg_gen_addi_tl(cpu_eip, cpu_eip, eip - eip_save); + } else { + tcg_gen_movi_tl(cpu_eip, eip); + } } =20 static void gen_update_eip_cur(DisasContext *s) { gen_jmp_im(s, s->base.pc_next - s->cs_base); + s->pc_save =3D s->base.pc_next; } =20 static void gen_update_eip_next(DisasContext *s) { gen_jmp_im(s, s->pc - s->cs_base); + s->pc_save =3D s->pc; +} + +static TCGv gen_eip_cur(DisasContext *s) +{ + if (TARGET_TB_PCREL) { + gen_update_eip_cur(s); + return cpu_eip; + } else { + return tcg_constant_tl(s->base.pc_next - s->cs_base); + } } =20 static int cur_insn_len(DisasContext *s) @@ -548,12 +562,25 @@ static TCGv_i32 cur_insn_len_i32(DisasContext *s) =20 static TCGv_i32 eip_next_i32(DisasContext *s) { - return tcg_constant_i32(s->pc - s->cs_base); + if (TARGET_TB_PCREL) { + TCGv_i32 ret =3D tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(ret, cpu_eip); + tcg_gen_addi_i32(ret, ret, s->pc - s->pc_save); + return ret; + } else { + return tcg_constant_i32(s->pc - s->cs_base); + } } =20 static TCGv eip_next_tl(DisasContext *s) { - return tcg_constant_tl(s->pc - s->cs_base); + if (TARGET_TB_PCREL) { + TCGv ret =3D tcg_temp_new(); + tcg_gen_addi_tl(ret, cpu_eip, s->pc - s->pc_save); + return ret; + } else { + return tcg_constant_tl(s->pc - s->cs_base); + } } =20 /* Compute SEG:REG into A0. SEG is selected from the override segment @@ -2252,7 +2279,12 @@ static TCGv gen_lea_modrm_1(DisasContext *s, Address= Parts a) ea =3D cpu_regs[a.base]; } if (!ea) { - tcg_gen_movi_tl(s->A0, a.disp); + if (TARGET_TB_PCREL && a.base =3D=3D -2) { + /* With cpu_eip ~=3D pc_save, the expression is pc-relative. */ + tcg_gen_addi_tl(s->A0, cpu_eip, a.disp - s->pc_save); + } else { + tcg_gen_movi_tl(s->A0, a.disp); + } ea =3D s->A0; } else if (a.disp !=3D 0) { tcg_gen_addi_tl(s->A0, ea, a.disp); @@ -2366,8 +2398,13 @@ static void gen_goto_tb(DisasContext *s, int tb_num,= target_ulong eip) =20 if (translator_use_goto_tb(&s->base, pc)) { /* jump to same page: we can use a direct jump */ - tcg_gen_goto_tb(tb_num); - gen_jmp_im(s, eip); + if (TARGET_TB_PCREL) { + gen_jmp_im(s, eip); + tcg_gen_goto_tb(tb_num); + } else { + tcg_gen_goto_tb(tb_num); + gen_jmp_im(s, eip); + } tcg_gen_exit_tb(s->base.tb, tb_num); s->base.is_jmp =3D DISAS_NORETURN; } else { @@ -8458,6 +8495,13 @@ void tcg_x86_init(void) [R_EDI] =3D "edi", [R_EBP] =3D "ebp", [R_ESP] =3D "esp", +#endif + }; + static const char eip_name[] =3D { +#ifdef TARGET_X86_64 + "rip" +#else + "eip" #endif }; static const char seg_base_names[6][8] =3D { @@ -8484,6 +8528,7 @@ void tcg_x86_init(void) "cc_src"); cpu_cc_src2 =3D tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_s= rc2), "cc_src2"); + cpu_eip =3D tcg_global_mem_new(cpu_env, offsetof(CPUX86State, eip), ei= p_name); =20 for (i =3D 0; i < CPU_NB_REGS; ++i) { cpu_regs[i] =3D tcg_global_mem_new(cpu_env, @@ -8520,6 +8565,7 @@ static void i386_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cpu) int iopl =3D (flags >> IOPL_SHIFT) & 3; =20 dc->cs_base =3D dc->base.tb->cs_base; + dc->pc_save =3D dc->base.pc_next; dc->flags =3D flags; #ifndef CONFIG_USER_ONLY dc->cpl =3D cpl; @@ -8583,9 +8629,14 @@ static void i386_tr_tb_start(DisasContextBase *db, C= PUState *cpu) static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); + target_ulong pc_arg =3D dc->base.pc_next; =20 dc->prev_insn_end =3D tcg_last_op(); - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); + if (TARGET_TB_PCREL) { + pc_arg -=3D dc->cs_base; + pc_arg &=3D ~TARGET_PAGE_MASK; + } + tcg_gen_insn_start(pc_arg, dc->cc_op); } =20 static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) @@ -8686,7 +8737,12 @@ void restore_state_to_opc(CPUX86State *env, Translat= ionBlock *tb, target_ulong *data) { int cc_op =3D data[1]; - env->eip =3D data[0] - tb->cs_base; + + if (TARGET_TB_PCREL) { + env->eip =3D (env->eip & TARGET_PAGE_MASK) | data[0]; + } else { + env->eip =3D data[0] - tb->cs_base; + } if (cc_op !=3D CC_OP_DYNAMIC) { env->cc_op =3D cc_op; } --=20 2.34.1