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([2602:47:d49d:ec01:c3f1:b74f:5edd:63af]) by smtp.gmail.com with ESMTPSA id 82-20020a621555000000b0053655af14easm5133124pfv.45.2022.08.22.16.33.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 16:33:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc; bh=+OJB/KgYLATLASrlEThWGbrHHghDFAhGZdOzeh5O3nA=; b=xLtk26nh/DujLrPeyWNtLD4Nd3B5S7lGt8a2bX8GLDqctGEfJRW2+3hvlpLNj4UFh4 gq7Lqp1x9P+Sk8s5iGwFmzDltytaUklPL9t4HM1WHr56Tn4ODYkrgGleZ1aCDuYovZK3 6Sg5hnBUMtvlgUBxGjqIc+NXQ5kJPJXiuo2VGg28K8bJ+pN6wHNIJQVT4iEDgMoWUhNu k2YHKR1jDR9gSTJAHWn+2XdtUci6hlHYcxErpJlAz/EW7oGj4qDw6N+ToxNMxGyeeMpG 1ybBFjoIOQER61nR4q2EQLrwsN6EUEw0zVqhF6HFqgBz4JaOFkESHQiRZ3opjDSl6oJ0 DIig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc; bh=+OJB/KgYLATLASrlEThWGbrHHghDFAhGZdOzeh5O3nA=; b=pEXf1iSvqaMGuXRiYTR+0Q1CLkaI15wFUyarm7G23676jBMNOXKC7ySwYEmEPy43hK mhAKRwMtgRkU0JfctLuwTLK8H4rFBz1h4sp691i3rfznMfdsWtJeOrq6gi+uUYnP3U6I kXUwJMgpSE0pL/dnVAdm7sxq9pAOqN8lHEByCNnE7Huv+rnPxJQi9sOwkdg9u8Vbkd/x NbbcLGYBWzA4bXJO2ZcimSMVOtmflC3dbdzHy7Z6Hm6dxT6jhul5JdacoByt5SVTSUHk b2Vb1l2ulvnFGt4JlTOy3Lv3I4nRTas1iqER9LNif5oUMtrLtw0ypJK/l5fWdrD9nmMk Lw9Q== X-Gm-Message-State: ACgBeo10PDWzirgyE8Wxzpv5p4OIWygm16oj8pMitzvJnPVNtzjpVQfr 9k8tsDNWXWeddSEUoKHOAz/XqgOk/Wp2yQ== X-Google-Smtp-Source: AA6agR4Jx5gdywYpBcakG3AzkBZuSgkl/yA7h6uGFdaPoRY+/1EM2s7cXuvPymZ3HJi+E8LeXKwywg== X-Received: by 2002:a65:6048:0:b0:412:73c7:cca9 with SMTP id a8-20020a656048000000b0041273c7cca9mr19112568pgp.257.1661211212591; Mon, 22 Aug 2022 16:33:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 10/22] target/i386: Create cur_insn_len, cur_insn_len_i32 Date: Mon, 22 Aug 2022 16:33:06 -0700 Message-Id: <20220822233318.1728621-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822233318.1728621-1-richard.henderson@linaro.org> References: <20220822233318.1728621-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661212492430100001 Content-Type: text/plain; charset="utf-8" Create common routines for computing the length of the insn. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 1dc3ff67ae..ee8e87a617 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -530,6 +530,16 @@ static void gen_update_eip_next(DisasContext *s) gen_jmp_im(s, s->pc - s->cs_base); } =20 +static int cur_insn_len(DisasContext *s) +{ + return s->pc - s->base.pc_next; +} + +static TCGv_i32 cur_insn_len_i32(DisasContext *s) +{ + return tcg_constant_i32(cur_insn_len(s)); +} + /* Compute SEG:REG into A0. SEG is selected from the override segment (OVR_SEG) and the default segment (DEF_SEG). OVR_SEG may be -1 to indicate no override. */ @@ -712,9 +722,6 @@ static bool gen_check_io(DisasContext *s, MemOp ot, TCG= v_i32 port, gen_helper_check_io(cpu_env, port, tcg_constant_i32(1 << ot)); } if (GUEST(s)) { - target_ulong cur_eip =3D s->base.pc_next - s->cs_base; - target_ulong next_eip =3D s->pc - s->cs_base; - gen_update_cc_op(s); gen_update_eip_cur(s); if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { @@ -723,7 +730,7 @@ static bool gen_check_io(DisasContext *s, MemOp ot, TCG= v_i32 port, svm_flags |=3D 1 << (SVM_IOIO_SIZE_SHIFT + ot); gen_helper_svm_check_io(cpu_env, port, tcg_constant_i32(svm_flags), - tcg_constant_i32(next_eip - cur_eip)); + cur_insn_len_i32(s)); } return true; #endif @@ -2028,7 +2035,7 @@ static uint64_t advance_pc(CPUX86State *env, DisasCon= text *s, int num_bytes) } =20 s->pc +=3D num_bytes; - if (unlikely(s->pc - s->base.pc_next > X86_MAX_INSN_LENGTH)) { + if (unlikely(cur_insn_len(s) > X86_MAX_INSN_LENGTH)) { /* If the instruction's 16th byte is on a different page than the = 1st, a * page fault on the second page wins over the general protection = fault * caused by the instruction being too long. @@ -2622,7 +2629,7 @@ static void gen_interrupt(DisasContext *s, int intno) gen_update_cc_op(s); gen_update_eip_cur(s); gen_helper_raise_interrupt(cpu_env, tcg_constant_i32(intno), - tcg_constant_i32(s->pc - s->base.pc_next)); + cur_insn_len_i32(s)); s->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -7166,7 +7173,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (prefixes & PREFIX_REPZ) { gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_pause(cpu_env, tcg_const_i32(s->pc - s->base.pc_nex= t)); + gen_helper_pause(cpu_env, cur_insn_len_i32(s)); s->base.is_jmp =3D DISAS_NORETURN; } break; @@ -7192,7 +7199,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_into(cpu_env, tcg_const_i32(s->pc - s->base.pc_next)); + gen_helper_into(cpu_env, cur_insn_len_i32(s)); break; #ifdef WANT_ICEBP case 0xf1: /* icebp (undocumented, exits to external debugger) */ @@ -7351,7 +7358,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) /* XXX: is it usable in real mode ? */ gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_syscall(cpu_env, tcg_const_i32(s->pc - s->base.pc_next)= ); + gen_helper_syscall(cpu_env, cur_insn_len_i32(s)); /* TF handling for the syscall insn is different. The TF bit is c= hecked after the syscall insn completes. This allows #DB to not be generated after one has entered CPL0 if TF is set in FMASK. */ @@ -7383,7 +7390,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (check_cpl0(s)) { gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - s->base.pc_next)= ); + gen_helper_hlt(cpu_env, cur_insn_len_i32(s)); s->base.is_jmp =3D DISAS_NORETURN; } break; @@ -7492,7 +7499,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - s->base.pc_nex= t)); + gen_helper_mwait(cpu_env, cur_insn_len_i32(s)); s->base.is_jmp =3D DISAS_NORETURN; break; =20 @@ -7568,7 +7575,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_update_cc_op(s); gen_update_eip_cur(s); gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1), - tcg_const_i32(s->pc - s->base.pc_next)); + cur_insn_len_i32(s)); tcg_gen_exit_tb(NULL, 0); s->base.is_jmp =3D DISAS_NORETURN; break; --=20 2.34.1