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([2602:47:d49d:ec01:c3f1:b74f:5edd:63af]) by smtp.gmail.com with ESMTPSA id k17-20020aa79731000000b0052d3899f8c2sm3809112pfg.4.2022.08.22.16.23.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 16:23:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=8mcpoGyicxvO86RBsxLMjT2beQqB3D9uTqe6maslzKo=; b=OJU+Ggx0BJawEPHqLVlm/fs4h6nJypZdAIlSfgKR3OCi0AzQ93LhVDaRfwHtMO6sWN fy1sXLZu+wV2QbqDzkA43BD1TzNUy2p0xwbOqkgdFam3NZXqUlDOuPaodgn4xshpH2Dt UReEl6dLFffYcL++T07UkdKpsn7M+7GAm/6rI0K7MOw/MB55jJU0BkcIU1U86BUa+RQM 94JEg9qSRbmSo9p5++lnICwokoF+iG5dkszy7W59Wi5MTV5+dDBOguWFKVRo4JB/TrqP ozZNnIX8wwpZJi68WLtkzZrMhJ8ZBvM7uNUpMjOJ/h36KOWnooG2j3SZS0RB5VBZhosn MPKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=8mcpoGyicxvO86RBsxLMjT2beQqB3D9uTqe6maslzKo=; b=BmO78VhuSJZ6pKP9kxiizKQs5LpeQW8DqIUD1YpK/0PvMV+1NeAihEMfQ0kxynnnFk 7XnIOiJJ0EZFoZ5nRCDeuXq2tmuzaSn0EAZqHhQYJngilyjEAvDahNUMk9Ex3pQP8jpF 9+4o3Hn7+BtFplSmy40cWEkb8vV7GwIjHfXsH07E6Q1cdTLFRHU9lr9uipXcOMmffPc3 OaUL9f4Yqa3HLaN/p656GkDqySzctE1733yiApcuHXrxSVmqCTRa6mgRV3DJsI5Iwf/R nZh93DlRA2Rl6VZlaNBFdirSpdfwfHfRO/Gl08/C8MUIriuijbqOtSl477YpCHWcekHa R5TQ== X-Gm-Message-State: ACgBeo266Rj6TAh94J4mnOLoZyo861BEsssc4HWsmFR1l1VvQIDuc3Z0 2SvecUF39tAL7zeAkXisX0wwAJx9vwuceA== X-Google-Smtp-Source: AA6agR5U8vUSAmYLhiBkgTCAFlD3zQBhoxKtbI8rrcCEjCxadqkQ/JCI0XYq0Wg8tKwXp7yyQ351+A== X-Received: by 2002:a17:902:ed92:b0:172:a334:acbb with SMTP id e18-20020a170902ed9200b00172a334acbbmr22171627plj.58.1661210630747; Mon, 22 Aug 2022 16:23:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 10/17] target/arm: Change gen_goto_tb to work on displacements Date: Mon, 22 Aug 2022 16:23:31 -0700 Message-Id: <20220822232338.1727934-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822232338.1727934-1-richard.henderson@linaro.org> References: <20220822232338.1727934-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661211121511100001 Content-Type: text/plain; charset="utf-8" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 40 ++++++++++++++++++++------------------ target/arm/translate.c | 10 ++++++---- 2 files changed, 27 insertions(+), 23 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 163df8c615..695ccd0723 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -378,8 +378,10 @@ static inline bool use_goto_tb(DisasContext *s, uint64= _t dest) return translator_use_goto_tb(&s->base, dest); } =20 -static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) +static void gen_goto_tb(DisasContext *s, int n, int diff) { + uint64_t dest =3D s->pc_curr + diff; + if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(n); gen_a64_set_pc_im(dest); @@ -1362,7 +1364,7 @@ static inline AArch64DecodeFn *lookup_disas_fn(const = AArch64DecodeTable *table, */ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) { - uint64_t addr =3D s->pc_curr + sextract32(insn, 0, 26) * 4; + int diff =3D sextract32(insn, 0, 26) * 4; =20 if (insn & (1U << 31)) { /* BL Branch with link */ @@ -1371,7 +1373,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint3= 2_t insn) =20 /* B Branch / BL Branch with link */ reset_btype(s); - gen_goto_tb(s, 0, addr); + gen_goto_tb(s, 0, diff); } =20 /* Compare and branch (immediate) @@ -1383,14 +1385,14 @@ static void disas_uncond_b_imm(DisasContext *s, uin= t32_t insn) static void disas_comp_b_imm(DisasContext *s, uint32_t insn) { unsigned int sf, op, rt; - uint64_t addr; + int diff; TCGLabel *label_match; TCGv_i64 tcg_cmp; =20 sf =3D extract32(insn, 31, 1); op =3D extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ rt =3D extract32(insn, 0, 5); - addr =3D s->pc_curr + sextract32(insn, 5, 19) * 4; + diff =3D sextract32(insn, 5, 19) * 4; =20 tcg_cmp =3D read_cpu_reg(s, rt, sf); label_match =3D gen_new_label(); @@ -1399,9 +1401,9 @@ static void disas_comp_b_imm(DisasContext *s, uint32_= t insn) tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, label_match); =20 - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); gen_set_label(label_match); - gen_goto_tb(s, 1, addr); + gen_goto_tb(s, 1, diff); } =20 /* Test and branch (immediate) @@ -1413,13 +1415,13 @@ static void disas_comp_b_imm(DisasContext *s, uint3= 2_t insn) static void disas_test_b_imm(DisasContext *s, uint32_t insn) { unsigned int bit_pos, op, rt; - uint64_t addr; + int diff; TCGLabel *label_match; TCGv_i64 tcg_cmp; =20 bit_pos =3D (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); op =3D extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ - addr =3D s->pc_curr + sextract32(insn, 5, 14) * 4; + diff =3D sextract32(insn, 5, 14) * 4; rt =3D extract32(insn, 0, 5); =20 tcg_cmp =3D tcg_temp_new_i64(); @@ -1430,9 +1432,9 @@ static void disas_test_b_imm(DisasContext *s, uint32_= t insn) tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, label_match); tcg_temp_free_i64(tcg_cmp); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); gen_set_label(label_match); - gen_goto_tb(s, 1, addr); + gen_goto_tb(s, 1, diff); } =20 /* Conditional branch (immediate) @@ -1444,13 +1446,13 @@ static void disas_test_b_imm(DisasContext *s, uint3= 2_t insn) static void disas_cond_b_imm(DisasContext *s, uint32_t insn) { unsigned int cond; - uint64_t addr; + int diff; =20 if ((insn & (1 << 4)) || (insn & (1 << 24))) { unallocated_encoding(s); return; } - addr =3D s->pc_curr + sextract32(insn, 5, 19) * 4; + diff =3D sextract32(insn, 5, 19) * 4; cond =3D extract32(insn, 0, 4); =20 reset_btype(s); @@ -1458,12 +1460,12 @@ static void disas_cond_b_imm(DisasContext *s, uint3= 2_t insn) /* genuinely conditional branches */ TCGLabel *label_match =3D gen_new_label(); arm_gen_test_cc(cond, label_match); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); gen_set_label(label_match); - gen_goto_tb(s, 1, addr); + gen_goto_tb(s, 1, diff); } else { /* 0xe and 0xf are both "always" conditions */ - gen_goto_tb(s, 0, addr); + gen_goto_tb(s, 0, diff); } } =20 @@ -1637,7 +1639,7 @@ static void handle_sync(DisasContext *s, uint32_t ins= n, * any pending interrupts immediately. */ reset_btype(s); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); return; =20 case 7: /* SB */ @@ -1649,7 +1651,7 @@ static void handle_sync(DisasContext *s, uint32_t ins= n, * MB and end the TB instead. */ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); return; =20 default: @@ -14965,7 +14967,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) switch (dc->base.is_jmp) { case DISAS_NEXT: case DISAS_TOO_MANY: - gen_goto_tb(dc, 1, dc->base.pc_next); + gen_goto_tb(dc, 1, curr_insn_len(dc)); break; default: case DISAS_UPDATE_EXIT: diff --git a/target/arm/translate.c b/target/arm/translate.c index 638a051281..2b9a58b442 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2597,8 +2597,10 @@ static void gen_goto_ptr(void) * cpu_loop_exec. Any live exit_requests will be processed as we * enter the next TB. */ -static void gen_goto_tb(DisasContext *s, int n, target_ulong dest) +static void gen_goto_tb(DisasContext *s, int n, int diff) { + target_ulong dest =3D s->pc_curr + diff; + if (translator_use_goto_tb(&s->base, dest)) { tcg_gen_goto_tb(n); gen_set_pc_im(s, dest); @@ -2632,7 +2634,7 @@ static inline void gen_jmp_tb(DisasContext *s, uint32= _t dest, int tbno) * gen_jmp(); * on the second call to gen_jmp(). */ - gen_goto_tb(s, tbno, dest); + gen_goto_tb(s, tbno, dest - s->pc_curr); break; case DISAS_UPDATE_NOCHAIN: case DISAS_UPDATE_EXIT: @@ -9806,7 +9808,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) switch (dc->base.is_jmp) { case DISAS_NEXT: case DISAS_TOO_MANY: - gen_goto_tb(dc, 1, dc->base.pc_next); + gen_goto_tb(dc, 1, curr_insn_len(dc)); break; case DISAS_UPDATE_NOCHAIN: gen_set_pc_im(dc, dc->base.pc_next); @@ -9858,7 +9860,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) gen_set_pc_im(dc, dc->base.pc_next); gen_singlestep_exception(dc); } else { - gen_goto_tb(dc, 1, dc->base.pc_next); + gen_goto_tb(dc, 1, curr_insn_len(dc)); } } } --=20 2.34.1